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Nicolas Pitre <nico@cam.org> tighten error checking in bulk_write
[openocd.git] / src / flash / mx3_nand.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "mx3_nand.h"
39
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %d is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%x)";
46 static const char invalid_command_sequense_err_msg[] =
47 "invalid command sequence in %s";
48 static const char get_status_register_err_msg[] = "can't get NAND status";
49 static uint32_t in_sram_address;
50 unsigned char sign_of_sequental_byte_read;
51
52 static int test_iomux_settings (target_t * target, uint32_t value,
53 uint32_t mask, const char *text);
54 static int initialize_nf_controller (struct nand_device_s *device);
55 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
56 static int get_next_halfword_from_sram_buffer (target_t * target,
57 uint16_t * value);
58 static int poll_for_complete_op (target_t * target, const char *text);
59 static int validate_target_state (struct nand_device_s *device);
60 static int do_data_output (struct nand_device_s *device);
61
62 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
63 char *cmd, char **args, int argc,
64 struct nand_device_s *device);
65 static int imx31_init (struct nand_device_s *device);
66 static int imx31_read_data (struct nand_device_s *device, void *data);
67 static int imx31_write_data (struct nand_device_s *device, uint16_t data);
68 static int imx31_nand_ready (struct nand_device_s *device, int timeout);
69 static int imx31_register_commands (struct command_context_s *cmd_ctx);
70 static int imx31_reset (struct nand_device_s *device);
71 static int imx31_command (struct nand_device_s *device, uint8_t command);
72 static int imx31_address (struct nand_device_s *device, uint8_t address);
73 static int imx31_controller_ready (struct nand_device_s *device, int tout);
74 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
75 uint8_t * data, uint32_t data_size, uint8_t * oob,
76 uint32_t oob_size);
77 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
78 uint8_t * data, uint32_t data_size, uint8_t * oob,
79 uint32_t oob_size);
80
81 nand_flash_controller_t imx31_nand_flash_controller = {
82 .name = "imx31",
83 .nand_device_command = imx31_nand_device_command,
84 .register_commands = imx31_register_commands,
85 .init = imx31_init,
86 .reset = imx31_reset,
87 .command = imx31_command,
88 .address = imx31_address,
89 .write_data = imx31_write_data,
90 .read_data = imx31_read_data,
91 .write_page = imx31_write_page,
92 .read_page = imx31_read_page,
93 .controller_ready = imx31_controller_ready,
94 .nand_ready = imx31_nand_ready,
95 };
96
97 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
98 char *cmd, char **args, int argc,
99 struct nand_device_s *device)
100 {
101 mx3_nf_controller_t *mx3_nf_info;
102 mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
103 if (mx3_nf_info == NULL)
104 {
105 LOG_ERROR ("no memory for nand controller");
106 return ERROR_FAIL;
107 }
108
109 device->controller_priv = mx3_nf_info;
110
111 mx3_nf_info->target = get_target (args[1]);
112 if (mx3_nf_info->target == NULL)
113 {
114 LOG_ERROR ("target '%s' not defined", args[1]);
115 return ERROR_FAIL;
116 }
117 if (argc < 3)
118 {
119 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
120 return ERROR_FAIL;
121 }
122 /*
123 * check hwecc requirements
124 */
125 {
126 int hwecc_needed;
127 hwecc_needed = strcmp (args[2], "hwecc");
128 if (hwecc_needed == 0)
129 {
130 mx3_nf_info->flags.hw_ecc_enabled = 1;
131 }
132 else
133 {
134 mx3_nf_info->flags.hw_ecc_enabled = 0;
135 }
136 }
137
138 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
139 mx3_nf_info->fin = MX3_NF_FIN_NONE;
140 mx3_nf_info->flags.target_little_endian =
141 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
142 /*
143 * testing host endianess
144 */
145 {
146 int x = 1;
147 if (*(char *) &x == 1)
148 {
149 mx3_nf_info->flags.host_little_endian = 1;
150 }
151 else
152 {
153 mx3_nf_info->flags.host_little_endian = 0;
154 }
155 }
156 return ERROR_OK;
157 }
158
159 static int imx31_init (struct nand_device_s *device)
160 {
161 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
162 target_t *target = mx3_nf_info->target;
163
164 {
165 /*
166 * validate target state
167 */
168 int validate_target_result;
169 validate_target_result = validate_target_state (device);
170 if (validate_target_result != ERROR_OK)
171 {
172 return validate_target_result;
173 }
174 }
175
176 {
177 uint16_t buffsize_register_content;
178 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
179 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
180 }
181
182 {
183 uint32_t pcsr_register_content;
184 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
185 if (!device->bus_width)
186 {
187 device->bus_width =
188 (pcsr_register_content & 0x80000000) ? 16 : 8;
189 }
190 else
191 {
192 pcsr_register_content |=
193 ((device->bus_width == 16) ? 0x80000000 : 0x00000000);
194 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
195 }
196
197 if (!device->page_size)
198 {
199 device->page_size =
200 (pcsr_register_content & 0x40000000) ? 2048 : 512;
201 }
202 else
203 {
204 pcsr_register_content |=
205 ((device->page_size == 2048) ? 0x40000000 : 0x00000000);
206 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
207 }
208 if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048))
209 {
210 LOG_ERROR
211 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
212 }
213 }
214
215 {
216 uint32_t cgr_register_content;
217 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
218 if (!(cgr_register_content & 0x00000300))
219 {
220 LOG_ERROR ("clock gating to EMI disabled");
221 return ERROR_FAIL;
222 }
223 }
224
225 {
226 uint32_t gpr_register_content;
227 target_read_u32 (target, MX3_GPR, &gpr_register_content);
228 if (gpr_register_content & 0x00000060)
229 {
230 LOG_ERROR ("pins mode overrided by GPR");
231 return ERROR_FAIL;
232 }
233 }
234
235 {
236 /*
237 * testing IOMUX settings; must be in "functional-mode output and
238 * functional-mode input" mode
239 */
240 uint8_t test_iomux;
241 test_iomux = ERROR_OK;
242 test_iomux |=
243 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
244 test_iomux |=
245 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
246 test_iomux |=
247 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
248 if (device->bus_width == 16)
249 {
250 test_iomux |=
251 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
252 "d8,d9,d10");
253 test_iomux |=
254 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
255 "d11,d12,d13,d14");
256 test_iomux |=
257 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
258 }
259 test_iomux |=
260 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
261 "nfwp,nfce,nfrb");
262 test_iomux |=
263 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
264 "nfwe,nfre,nfale,nfcle");
265 if (test_iomux != ERROR_OK)
266 {
267 return ERROR_FAIL;
268 }
269 }
270
271 initialize_nf_controller (device);
272
273 {
274 int retval;
275 uint16_t nand_status_content;
276 retval = ERROR_OK;
277 retval |= imx31_command (device, NAND_CMD_STATUS);
278 retval |= imx31_address (device, 0x00);
279 retval |= do_data_output (device);
280 if (retval != ERROR_OK)
281 {
282 LOG_ERROR (get_status_register_err_msg);
283 return ERROR_FAIL;
284 }
285 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
286 if (!(nand_status_content & 0x0080))
287 {
288 /*
289 * is host-big-endian correctly ??
290 */
291 LOG_INFO ("NAND read-only");
292 mx3_nf_info->flags.nand_readonly = 1;
293 }
294 else
295 {
296 mx3_nf_info->flags.nand_readonly = 0;
297 }
298 }
299 return ERROR_OK;
300 }
301
302 static int imx31_read_data (struct nand_device_s *device, void *data)
303 {
304 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
305 target_t *target = mx3_nf_info->target;
306 {
307 /*
308 * validate target state
309 */
310 int validate_target_result;
311 validate_target_result = validate_target_state (device);
312 if (validate_target_result != ERROR_OK)
313 {
314 return validate_target_result;
315 }
316 }
317
318 {
319 /*
320 * get data from nand chip
321 */
322 int try_data_output_from_nand_chip;
323 try_data_output_from_nand_chip = do_data_output (device);
324 if (try_data_output_from_nand_chip != ERROR_OK)
325 {
326 return try_data_output_from_nand_chip;
327 }
328 }
329
330 if (device->bus_width == 16)
331 {
332 get_next_halfword_from_sram_buffer (target, data);
333 }
334 else
335 {
336 get_next_byte_from_sram_buffer (target, data);
337 }
338
339 return ERROR_OK;
340 }
341
342 static int imx31_write_data (struct nand_device_s *device, uint16_t data)
343 {
344 LOG_ERROR ("write_data() not implemented");
345 return ERROR_NAND_OPERATION_FAILED;
346 }
347
348 static int imx31_nand_ready (struct nand_device_s *device, int timeout)
349 {
350 return imx31_controller_ready (device, timeout);
351 }
352
353 static int imx31_register_commands (struct command_context_s *cmd_ctx)
354 {
355 return ERROR_OK;
356 }
357
358 static int imx31_reset (struct nand_device_s *device)
359 {
360 /*
361 * validate target state
362 */
363 int validate_target_result;
364 validate_target_result = validate_target_state (device);
365 if (validate_target_result != ERROR_OK)
366 {
367 return validate_target_result;
368 }
369 initialize_nf_controller (device);
370 return ERROR_OK;
371 }
372
373 static int imx31_command (struct nand_device_s *device, uint8_t command)
374 {
375 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
376 target_t *target = mx3_nf_info->target;
377 {
378 /*
379 * validate target state
380 */
381 int validate_target_result;
382 validate_target_result = validate_target_state (device);
383 if (validate_target_result != ERROR_OK)
384 {
385 return validate_target_result;
386 }
387 }
388
389 switch (command)
390 {
391 case NAND_CMD_READOOB:
392 command = NAND_CMD_READ0;
393 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
394 * data_read() and
395 * read_block_data() to
396 * spare area in SRAM
397 * buffer */
398 break;
399 case NAND_CMD_READ1:
400 command = NAND_CMD_READ0;
401 /*
402 * offset == one half of page size
403 */
404 in_sram_address =
405 MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1);
406 default:
407 in_sram_address = MX3_NF_MAIN_BUFFER0;
408 }
409
410 target_write_u16 (target, MX3_NF_FCMD, command);
411 /*
412 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
413 */
414 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
415 {
416 int poll_result;
417 poll_result = poll_for_complete_op (target, "command");
418 if (poll_result != ERROR_OK)
419 {
420 return poll_result;
421 }
422 }
423 /*
424 * reset cursor to begin of the buffer
425 */
426 sign_of_sequental_byte_read = 0;
427 switch (command)
428 {
429 case NAND_CMD_READID:
430 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
431 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
432 break;
433 case NAND_CMD_STATUS:
434 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
435 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
436 break;
437 case NAND_CMD_READ0:
438 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
439 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
440 break;
441 case NAND_CMD_SEQIN:
442 LOG_ERROR ("aaa");
443 return ERROR_FAIL;
444 break;
445 default:
446 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
447 }
448 return ERROR_OK;
449 }
450
451 static int imx31_address (struct nand_device_s *device, uint8_t address)
452 {
453 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
454 target_t *target = mx3_nf_info->target;
455 {
456 /*
457 * validate target state
458 */
459 int validate_target_result;
460 validate_target_result = validate_target_state (device);
461 if (validate_target_result != ERROR_OK)
462 {
463 return validate_target_result;
464 }
465 }
466
467 target_write_u16 (target, MX3_NF_FADDR, address);
468 /*
469 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
470 */
471 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
472 {
473 int poll_result;
474 poll_result = poll_for_complete_op (target, "address");
475 if (poll_result != ERROR_OK)
476 {
477 return poll_result;
478 }
479 }
480 return ERROR_OK;
481 }
482
483 static int imx31_controller_ready (struct nand_device_s *device, int tout)
484 {
485 uint16_t poll_complete_status;
486 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
487 target_t *target = mx3_nf_info->target;
488
489 {
490 /*
491 * validate target state
492 */
493 int validate_target_result;
494 validate_target_result = validate_target_state (device);
495 if (validate_target_result != ERROR_OK)
496 {
497 return validate_target_result;
498 }
499 }
500
501 do
502 {
503 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
504 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
505 {
506 return tout;
507 }
508 alive_sleep (1);
509 }
510 while (tout-- > 0);
511 return tout;
512 }
513
514 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
515 uint8_t * data, uint32_t data_size, uint8_t * oob,
516 uint32_t oob_size)
517 {
518 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
519 target_t *target = mx3_nf_info->target;
520
521 if (data_size % 2)
522 {
523 LOG_ERROR (data_block_size_err_msg, data_size);
524 return ERROR_NAND_OPERATION_FAILED;
525 }
526 if (oob_size % 2)
527 {
528 LOG_ERROR (data_block_size_err_msg, oob_size);
529 return ERROR_NAND_OPERATION_FAILED;
530 }
531 if (!data)
532 {
533 LOG_ERROR ("nothing to program");
534 return ERROR_NAND_OPERATION_FAILED;
535 }
536 {
537 /*
538 * validate target state
539 */
540 int retval;
541 retval = validate_target_state (device);
542 if (retval != ERROR_OK)
543 {
544 return retval;
545 }
546 }
547 {
548 int retval = ERROR_OK;
549 retval |= imx31_command (device, NAND_CMD_SEQIN);
550 retval |= imx31_address (device, 0x00);
551 retval |= imx31_address (device, page & 0xff);
552 retval |= imx31_address (device, (page >> 8) & 0xff);
553 if (device->address_cycles >= 4)
554 {
555 retval |= imx31_address (device, (page >> 16) & 0xff);
556 if (device->address_cycles >= 5)
557 {
558 retval |= imx31_address (device, (page >> 24) & 0xff);
559 }
560 }
561 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
562 if (oob)
563 {
564 if (mx3_nf_info->flags.hw_ecc_enabled)
565 {
566 /*
567 * part of spare block will be overrided by hardware
568 * ECC generator
569 */
570 LOG_DEBUG
571 ("part of spare block will be overrided by hardware ECC generator");
572 }
573 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
574 oob);
575 }
576 /*
577 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
578 */
579 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
580 {
581 int poll_result;
582 poll_result = poll_for_complete_op (target, "data input");
583 if (poll_result != ERROR_OK)
584 {
585 return poll_result;
586 }
587 }
588 retval |= imx31_command (device, NAND_CMD_PAGEPROG);
589 if (retval != ERROR_OK)
590 {
591 return retval;
592 }
593
594 /*
595 * check status register
596 */
597 {
598 uint16_t nand_status_content;
599 retval = ERROR_OK;
600 retval |= imx31_command (device, NAND_CMD_STATUS);
601 retval |= imx31_address (device, 0x00);
602 retval |= do_data_output (device);
603 if (retval != ERROR_OK)
604 {
605 LOG_ERROR (get_status_register_err_msg);
606 return retval;
607 }
608 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
609 if (nand_status_content & 0x0001)
610 {
611 /*
612 * is host-big-endian correctly ??
613 */
614 return ERROR_NAND_OPERATION_FAILED;
615 }
616 }
617 }
618 return ERROR_OK;
619 }
620
621 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
622 uint8_t * data, uint32_t data_size, uint8_t * oob,
623 uint32_t oob_size)
624 {
625 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
626 target_t *target = mx3_nf_info->target;
627
628 if (data_size % 2)
629 {
630 LOG_ERROR (data_block_size_err_msg, data_size);
631 return ERROR_NAND_OPERATION_FAILED;
632 }
633 if (oob_size % 2)
634 {
635 LOG_ERROR (data_block_size_err_msg, oob_size);
636 return ERROR_NAND_OPERATION_FAILED;
637 }
638
639 {
640 /*
641 * validate target state
642 */
643 int retval;
644 retval = validate_target_state (device);
645 if (retval != ERROR_OK)
646 {
647 return retval;
648 }
649 }
650 {
651 int retval = ERROR_OK;
652 retval |= imx31_command (device, NAND_CMD_READ0);
653 retval |= imx31_address (device, 0x00);
654 retval |= imx31_address (device, page & 0xff);
655 retval |= imx31_address (device, (page >> 8) & 0xff);
656 if (device->address_cycles >= 4)
657 {
658 retval |= imx31_address (device, (page >> 16) & 0xff);
659 if (device->address_cycles >= 5)
660 {
661 retval |= imx31_address (device, (page >> 24) & 0xff);
662 retval |= imx31_command (device, NAND_CMD_READSTART);
663 }
664 }
665 retval |= do_data_output (device);
666 if (retval != ERROR_OK)
667 {
668 return retval;
669 }
670
671 if (data)
672 {
673 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
674 data);
675 }
676 if (oob)
677 {
678 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
679 oob);
680 }
681 }
682 return ERROR_OK;
683 }
684
685 static int test_iomux_settings (target_t * target, uint32_t address,
686 uint32_t mask, const char *text)
687 {
688 uint32_t register_content;
689 target_read_u32 (target, address, &register_content);
690 if ((register_content & mask) != (0x12121212 & mask))
691 {
692 LOG_ERROR ("IOMUX for {%s} is bad", text);
693 return ERROR_FAIL;
694 }
695 return ERROR_OK;
696 }
697
698 static int initialize_nf_controller (struct nand_device_s *device)
699 {
700 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
701 target_t *target = mx3_nf_info->target;
702 /*
703 * resets NAND flash controller in zero time ? I dont know.
704 */
705 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
706 {
707 uint16_t work_mode;
708 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
709 if (target->endianness == TARGET_BIG_ENDIAN)
710 {
711 work_mode |= MX3_NF_BIT_BE_EN;
712 }
713 if (mx3_nf_info->flags.hw_ecc_enabled)
714 {
715 work_mode |= MX3_NF_BIT_ECC_EN;
716 }
717 target_write_u16 (target, MX3_NF_CFG1, work_mode);
718 }
719 /*
720 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
721 */
722 target_write_u16 (target, MX3_NF_BUFCFG, 2);
723 {
724 uint16_t temp;
725 target_read_u16 (target, MX3_NF_FWP, &temp);
726 if ((temp & 0x0007) == 1)
727 {
728 LOG_ERROR ("NAND flash is tight-locked, reset needed");
729 return ERROR_FAIL;
730 }
731
732 }
733 /*
734 * unlock NAND flash for write
735 */
736 target_write_u16 (target, MX3_NF_FWP, 4);
737 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
738 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
739 /*
740 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
741 */
742 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
743 /*
744 * address of SRAM buffer
745 */
746 in_sram_address = MX3_NF_MAIN_BUFFER0;
747 sign_of_sequental_byte_read = 0;
748 return ERROR_OK;
749 }
750
751 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
752 {
753 static uint8_t even_byte = 0;
754 /*
755 * host-big_endian ??
756 */
757 if (sign_of_sequental_byte_read == 0)
758 {
759 even_byte = 0;
760 }
761 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
762 {
763 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
764 *value = 0;
765 sign_of_sequental_byte_read = 0;
766 even_byte = 0;
767 return ERROR_NAND_OPERATION_FAILED;
768 }
769 else
770 {
771 uint16_t temp;
772 target_read_u16 (target, in_sram_address, &temp);
773 if (even_byte)
774 {
775 *value = temp >> 8;
776 even_byte = 0;
777 in_sram_address += 2;
778 }
779 else
780 {
781 *value = temp & 0xff;
782 even_byte = 1;
783 }
784 }
785 sign_of_sequental_byte_read = 1;
786 return ERROR_OK;
787 }
788
789 static int get_next_halfword_from_sram_buffer (target_t * target,
790 uint16_t * value)
791 {
792 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
793 {
794 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
795 *value = 0;
796 return ERROR_NAND_OPERATION_FAILED;
797 }
798 else
799 {
800 target_read_u16 (target, in_sram_address, value);
801 in_sram_address += 2;
802 }
803 return ERROR_OK;
804 }
805
806 static int poll_for_complete_op (target_t * target, const char *text)
807 {
808 uint16_t poll_complete_status;
809 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
810 {
811 usleep (25);
812 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
813 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
814 {
815 break;
816 }
817 }
818 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
819 {
820 LOG_ERROR ("%s sending timeout", text);
821 return ERROR_NAND_OPERATION_FAILED;
822 }
823 return ERROR_OK;
824 }
825
826 static int validate_target_state (struct nand_device_s *device)
827 {
828 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
829 target_t *target = mx3_nf_info->target;
830
831 if (target->state != TARGET_HALTED)
832 {
833 LOG_ERROR (target_not_halted_err_msg);
834 return ERROR_NAND_OPERATION_FAILED;
835 }
836
837 if (mx3_nf_info->flags.target_little_endian !=
838 (target->endianness == TARGET_LITTLE_ENDIAN))
839 {
840 /*
841 * endianness changed after NAND controller probed
842 */
843 return ERROR_NAND_OPERATION_FAILED;
844 }
845 return ERROR_OK;
846 }
847
848 static int do_data_output (struct nand_device_s *device)
849 {
850 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
851 target_t *target = mx3_nf_info->target;
852 switch (mx3_nf_info->fin)
853 {
854 case MX3_NF_FIN_DATAOUT:
855 /*
856 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
857 */
858 target_write_u16 (target, MX3_NF_CFG2,
859 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
860 optype));
861 {
862 int poll_result;
863 poll_result = poll_for_complete_op (target, "data output");
864 if (poll_result != ERROR_OK)
865 {
866 return poll_result;
867 }
868 }
869 mx3_nf_info->fin = MX3_NF_FIN_NONE;
870 /*
871 * ECC stuff
872 */
873 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
874 && mx3_nf_info->flags.hw_ecc_enabled)
875 {
876 uint16_t ecc_status;
877 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
878 switch (ecc_status & 0x000c)
879 {
880 case 1 << 2:
881 LOG_DEBUG
882 ("main area readed with 1 (correctable) error");
883 break;
884 case 2 << 2:
885 LOG_DEBUG
886 ("main area readed with more than 1 (incorrectable) error");
887 return ERROR_NAND_OPERATION_FAILED;
888 break;
889 }
890 switch (ecc_status & 0x0003)
891 {
892 case 1:
893 LOG_DEBUG
894 ("spare area readed with 1 (correctable) error");
895 break;
896 case 2:
897 LOG_DEBUG
898 ("main area readed with more than 1 (incorrectable) error");
899 return ERROR_NAND_OPERATION_FAILED;
900 break;
901 }
902 }
903 break;
904 case MX3_NF_FIN_NONE:
905 break;
906 }
907 return ERROR_OK;
908 }
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