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split jim_jtag_command into multiple handlers
[openocd.git] / src / flash / mx3_nand.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "mx3_nand.h"
39
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %" PRId32 " is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
46 static const char get_status_register_err_msg[] = "can't get NAND status";
47 static uint32_t in_sram_address;
48 unsigned char sign_of_sequental_byte_read;
49
50 static int test_iomux_settings (struct target * target, uint32_t value,
51 uint32_t mask, const char *text);
52 static int initialize_nf_controller (struct nand_device *nand);
53 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
54 static int get_next_halfword_from_sram_buffer (struct target * target,
55 uint16_t * value);
56 static int poll_for_complete_op (struct target * target, const char *text);
57 static int validate_target_state (struct nand_device *nand);
58 static int do_data_output (struct nand_device *nand);
59
60 static int imx31_command (struct nand_device *nand, uint8_t command);
61 static int imx31_address (struct nand_device *nand, uint8_t address);
62 static int imx31_controller_ready (struct nand_device *nand, int tout);
63
64 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
65 {
66 struct mx3_nf_controller *mx3_nf_info;
67 mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
68 if (mx3_nf_info == NULL)
69 {
70 LOG_ERROR ("no memory for nand controller");
71 return ERROR_FAIL;
72 }
73
74 nand->controller_priv = mx3_nf_info;
75
76 mx3_nf_info->target = get_target (CMD_ARGV[1]);
77 if (mx3_nf_info->target == NULL)
78 {
79 LOG_ERROR ("target '%s' not defined", CMD_ARGV[1]);
80 return ERROR_FAIL;
81 }
82 if (CMD_ARGC < 3)
83 {
84 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
85 return ERROR_FAIL;
86 }
87 /*
88 * check hwecc requirements
89 */
90 {
91 int hwecc_needed;
92 hwecc_needed = strcmp (CMD_ARGV[2], "hwecc");
93 if (hwecc_needed == 0)
94 {
95 mx3_nf_info->flags.hw_ecc_enabled = 1;
96 }
97 else
98 {
99 mx3_nf_info->flags.hw_ecc_enabled = 0;
100 }
101 }
102
103 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
104 mx3_nf_info->fin = MX3_NF_FIN_NONE;
105 mx3_nf_info->flags.target_little_endian =
106 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
107 /*
108 * testing host endianess
109 */
110 {
111 int x = 1;
112 if (*(char *) &x == 1)
113 {
114 mx3_nf_info->flags.host_little_endian = 1;
115 }
116 else
117 {
118 mx3_nf_info->flags.host_little_endian = 0;
119 }
120 }
121 return ERROR_OK;
122 }
123
124 static int imx31_init (struct nand_device *nand)
125 {
126 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
127 struct target *target = mx3_nf_info->target;
128
129 {
130 /*
131 * validate target state
132 */
133 int validate_target_result;
134 validate_target_result = validate_target_state(nand);
135 if (validate_target_result != ERROR_OK)
136 {
137 return validate_target_result;
138 }
139 }
140
141 {
142 uint16_t buffsize_register_content;
143 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
144 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
145 }
146
147 {
148 uint32_t pcsr_register_content;
149 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
150 if (!nand->bus_width)
151 {
152 nand->bus_width =
153 (pcsr_register_content & 0x80000000) ? 16 : 8;
154 }
155 else
156 {
157 pcsr_register_content |=
158 ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
159 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
160 }
161
162 if (!nand->page_size)
163 {
164 nand->page_size =
165 (pcsr_register_content & 0x40000000) ? 2048 : 512;
166 }
167 else
168 {
169 pcsr_register_content |=
170 ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
171 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
172 }
173 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
174 {
175 LOG_ERROR
176 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
177 }
178 }
179
180 {
181 uint32_t cgr_register_content;
182 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
183 if (!(cgr_register_content & 0x00000300))
184 {
185 LOG_ERROR ("clock gating to EMI disabled");
186 return ERROR_FAIL;
187 }
188 }
189
190 {
191 uint32_t gpr_register_content;
192 target_read_u32 (target, MX3_GPR, &gpr_register_content);
193 if (gpr_register_content & 0x00000060)
194 {
195 LOG_ERROR ("pins mode overrided by GPR");
196 return ERROR_FAIL;
197 }
198 }
199
200 {
201 /*
202 * testing IOMUX settings; must be in "functional-mode output and
203 * functional-mode input" mode
204 */
205 int test_iomux;
206 test_iomux = ERROR_OK;
207 test_iomux |=
208 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
209 test_iomux |=
210 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
211 test_iomux |=
212 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
213 if (nand->bus_width == 16)
214 {
215 test_iomux |=
216 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
217 "d8,d9,d10");
218 test_iomux |=
219 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
220 "d11,d12,d13,d14");
221 test_iomux |=
222 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
223 }
224 test_iomux |=
225 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
226 "nfwp,nfce,nfrb");
227 test_iomux |=
228 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
229 "nfwe,nfre,nfale,nfcle");
230 if (test_iomux != ERROR_OK)
231 {
232 return ERROR_FAIL;
233 }
234 }
235
236 initialize_nf_controller (nand);
237
238 {
239 int retval;
240 uint16_t nand_status_content;
241 retval = ERROR_OK;
242 retval |= imx31_command (nand, NAND_CMD_STATUS);
243 retval |= imx31_address (nand, 0x00);
244 retval |= do_data_output (nand);
245 if (retval != ERROR_OK)
246 {
247 LOG_ERROR (get_status_register_err_msg);
248 return ERROR_FAIL;
249 }
250 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
251 if (!(nand_status_content & 0x0080))
252 {
253 /*
254 * is host-big-endian correctly ??
255 */
256 LOG_INFO ("NAND read-only");
257 mx3_nf_info->flags.nand_readonly = 1;
258 }
259 else
260 {
261 mx3_nf_info->flags.nand_readonly = 0;
262 }
263 }
264 return ERROR_OK;
265 }
266
267 static int imx31_read_data (struct nand_device *nand, void *data)
268 {
269 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
270 struct target *target = mx3_nf_info->target;
271 {
272 /*
273 * validate target state
274 */
275 int validate_target_result;
276 validate_target_result = validate_target_state (nand);
277 if (validate_target_result != ERROR_OK)
278 {
279 return validate_target_result;
280 }
281 }
282
283 {
284 /*
285 * get data from nand chip
286 */
287 int try_data_output_from_nand_chip;
288 try_data_output_from_nand_chip = do_data_output (nand);
289 if (try_data_output_from_nand_chip != ERROR_OK)
290 {
291 return try_data_output_from_nand_chip;
292 }
293 }
294
295 if (nand->bus_width == 16)
296 {
297 get_next_halfword_from_sram_buffer (target, data);
298 }
299 else
300 {
301 get_next_byte_from_sram_buffer (target, data);
302 }
303
304 return ERROR_OK;
305 }
306
307 static int imx31_write_data (struct nand_device *nand, uint16_t data)
308 {
309 LOG_ERROR ("write_data() not implemented");
310 return ERROR_NAND_OPERATION_FAILED;
311 }
312
313 static int imx31_nand_ready (struct nand_device *nand, int timeout)
314 {
315 return imx31_controller_ready (nand, timeout);
316 }
317
318 static int imx31_reset (struct nand_device *nand)
319 {
320 /*
321 * validate target state
322 */
323 int validate_target_result;
324 validate_target_result = validate_target_state (nand);
325 if (validate_target_result != ERROR_OK)
326 {
327 return validate_target_result;
328 }
329 initialize_nf_controller (nand);
330 return ERROR_OK;
331 }
332
333 static int imx31_command (struct nand_device *nand, uint8_t command)
334 {
335 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
336 struct target *target = mx3_nf_info->target;
337 {
338 /*
339 * validate target state
340 */
341 int validate_target_result;
342 validate_target_result = validate_target_state (nand);
343 if (validate_target_result != ERROR_OK)
344 {
345 return validate_target_result;
346 }
347 }
348
349 switch (command)
350 {
351 case NAND_CMD_READOOB:
352 command = NAND_CMD_READ0;
353 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
354 * data_read() and
355 * read_block_data() to
356 * spare area in SRAM
357 * buffer */
358 break;
359 case NAND_CMD_READ1:
360 command = NAND_CMD_READ0;
361 /*
362 * offset == one half of page size
363 */
364 in_sram_address =
365 MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
366 default:
367 in_sram_address = MX3_NF_MAIN_BUFFER0;
368 }
369
370 target_write_u16 (target, MX3_NF_FCMD, command);
371 /*
372 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
373 */
374 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
375 {
376 int poll_result;
377 poll_result = poll_for_complete_op (target, "command");
378 if (poll_result != ERROR_OK)
379 {
380 return poll_result;
381 }
382 }
383 /*
384 * reset cursor to begin of the buffer
385 */
386 sign_of_sequental_byte_read = 0;
387 switch (command)
388 {
389 case NAND_CMD_READID:
390 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
391 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
392 break;
393 case NAND_CMD_STATUS:
394 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
395 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
396 break;
397 case NAND_CMD_READ0:
398 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
399 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
400 break;
401 default:
402 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
403 }
404 return ERROR_OK;
405 }
406
407 static int imx31_address (struct nand_device *nand, uint8_t address)
408 {
409 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
410 struct target *target = mx3_nf_info->target;
411 {
412 /*
413 * validate target state
414 */
415 int validate_target_result;
416 validate_target_result = validate_target_state (nand);
417 if (validate_target_result != ERROR_OK)
418 {
419 return validate_target_result;
420 }
421 }
422
423 target_write_u16 (target, MX3_NF_FADDR, address);
424 /*
425 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
426 */
427 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
428 {
429 int poll_result;
430 poll_result = poll_for_complete_op (target, "address");
431 if (poll_result != ERROR_OK)
432 {
433 return poll_result;
434 }
435 }
436 return ERROR_OK;
437 }
438
439 static int imx31_controller_ready (struct nand_device *nand, int tout)
440 {
441 uint16_t poll_complete_status;
442 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
443 struct target *target = mx3_nf_info->target;
444
445 {
446 /*
447 * validate target state
448 */
449 int validate_target_result;
450 validate_target_result = validate_target_state (nand);
451 if (validate_target_result != ERROR_OK)
452 {
453 return validate_target_result;
454 }
455 }
456
457 do
458 {
459 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
460 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
461 {
462 return tout;
463 }
464 alive_sleep (1);
465 }
466 while (tout-- > 0);
467 return tout;
468 }
469
470 static int imx31_write_page (struct nand_device *nand, uint32_t page,
471 uint8_t * data, uint32_t data_size, uint8_t * oob,
472 uint32_t oob_size)
473 {
474 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
475 struct target *target = mx3_nf_info->target;
476
477 if (data_size % 2)
478 {
479 LOG_ERROR (data_block_size_err_msg, data_size);
480 return ERROR_NAND_OPERATION_FAILED;
481 }
482 if (oob_size % 2)
483 {
484 LOG_ERROR (data_block_size_err_msg, oob_size);
485 return ERROR_NAND_OPERATION_FAILED;
486 }
487 if (!data)
488 {
489 LOG_ERROR ("nothing to program");
490 return ERROR_NAND_OPERATION_FAILED;
491 }
492 {
493 /*
494 * validate target state
495 */
496 int retval;
497 retval = validate_target_state (nand);
498 if (retval != ERROR_OK)
499 {
500 return retval;
501 }
502 }
503 {
504 int retval = ERROR_OK;
505 retval |= imx31_command(nand, NAND_CMD_SEQIN);
506 retval |= imx31_address(nand, 0x00);
507 retval |= imx31_address(nand, page & 0xff);
508 retval |= imx31_address(nand, (page >> 8) & 0xff);
509 if (nand->address_cycles >= 4)
510 {
511 retval |= imx31_address (nand, (page >> 16) & 0xff);
512 if (nand->address_cycles >= 5)
513 {
514 retval |= imx31_address (nand, (page >> 24) & 0xff);
515 }
516 }
517 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
518 if (oob)
519 {
520 if (mx3_nf_info->flags.hw_ecc_enabled)
521 {
522 /*
523 * part of spare block will be overrided by hardware
524 * ECC generator
525 */
526 LOG_DEBUG
527 ("part of spare block will be overrided by hardware ECC generator");
528 }
529 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
530 oob);
531 }
532 /*
533 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
534 */
535 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
536 {
537 int poll_result;
538 poll_result = poll_for_complete_op (target, "data input");
539 if (poll_result != ERROR_OK)
540 {
541 return poll_result;
542 }
543 }
544 retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
545 if (retval != ERROR_OK)
546 {
547 return retval;
548 }
549
550 /*
551 * check status register
552 */
553 {
554 uint16_t nand_status_content;
555 retval = ERROR_OK;
556 retval |= imx31_command(nand, NAND_CMD_STATUS);
557 retval |= imx31_address(nand, 0x00);
558 retval |= do_data_output(nand);
559 if (retval != ERROR_OK)
560 {
561 LOG_ERROR (get_status_register_err_msg);
562 return retval;
563 }
564 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
565 if (nand_status_content & 0x0001)
566 {
567 /*
568 * is host-big-endian correctly ??
569 */
570 return ERROR_NAND_OPERATION_FAILED;
571 }
572 }
573 }
574 return ERROR_OK;
575 }
576
577 static int imx31_read_page (struct nand_device *nand, uint32_t page,
578 uint8_t * data, uint32_t data_size, uint8_t * oob,
579 uint32_t oob_size)
580 {
581 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
582 struct target *target = mx3_nf_info->target;
583
584 if (data_size % 2)
585 {
586 LOG_ERROR (data_block_size_err_msg, data_size);
587 return ERROR_NAND_OPERATION_FAILED;
588 }
589 if (oob_size % 2)
590 {
591 LOG_ERROR (data_block_size_err_msg, oob_size);
592 return ERROR_NAND_OPERATION_FAILED;
593 }
594
595 {
596 /*
597 * validate target state
598 */
599 int retval;
600 retval = validate_target_state(nand);
601 if (retval != ERROR_OK)
602 {
603 return retval;
604 }
605 }
606 {
607 int retval = ERROR_OK;
608 retval |= imx31_command(nand, NAND_CMD_READ0);
609 retval |= imx31_address(nand, 0x00);
610 retval |= imx31_address(nand, page & 0xff);
611 retval |= imx31_address(nand, (page >> 8) & 0xff);
612 if (nand->address_cycles >= 4)
613 {
614 retval |= imx31_address(nand, (page >> 16) & 0xff);
615 if (nand->address_cycles >= 5)
616 {
617 retval |= imx31_address(nand, (page >> 24) & 0xff);
618 retval |= imx31_command(nand, NAND_CMD_READSTART);
619 }
620 }
621 retval |= do_data_output (nand);
622 if (retval != ERROR_OK)
623 {
624 return retval;
625 }
626
627 if (data)
628 {
629 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
630 data);
631 }
632 if (oob)
633 {
634 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
635 oob);
636 }
637 }
638 return ERROR_OK;
639 }
640
641 static int test_iomux_settings (struct target * target, uint32_t address,
642 uint32_t mask, const char *text)
643 {
644 uint32_t register_content;
645 target_read_u32 (target, address, &register_content);
646 if ((register_content & mask) != (0x12121212 & mask))
647 {
648 LOG_ERROR ("IOMUX for {%s} is bad", text);
649 return ERROR_FAIL;
650 }
651 return ERROR_OK;
652 }
653
654 static int initialize_nf_controller (struct nand_device *nand)
655 {
656 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
657 struct target *target = mx3_nf_info->target;
658 /*
659 * resets NAND flash controller in zero time ? I dont know.
660 */
661 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
662 {
663 uint16_t work_mode;
664 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
665 if (target->endianness == TARGET_BIG_ENDIAN)
666 {
667 work_mode |= MX3_NF_BIT_BE_EN;
668 }
669 if (mx3_nf_info->flags.hw_ecc_enabled)
670 {
671 work_mode |= MX3_NF_BIT_ECC_EN;
672 }
673 target_write_u16 (target, MX3_NF_CFG1, work_mode);
674 }
675 /*
676 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
677 */
678 target_write_u16 (target, MX3_NF_BUFCFG, 2);
679 {
680 uint16_t temp;
681 target_read_u16 (target, MX3_NF_FWP, &temp);
682 if ((temp & 0x0007) == 1)
683 {
684 LOG_ERROR ("NAND flash is tight-locked, reset needed");
685 return ERROR_FAIL;
686 }
687
688 }
689 /*
690 * unlock NAND flash for write
691 */
692 target_write_u16 (target, MX3_NF_FWP, 4);
693 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
694 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
695 /*
696 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
697 */
698 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
699 /*
700 * address of SRAM buffer
701 */
702 in_sram_address = MX3_NF_MAIN_BUFFER0;
703 sign_of_sequental_byte_read = 0;
704 return ERROR_OK;
705 }
706
707 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
708 {
709 static uint8_t even_byte = 0;
710 /*
711 * host-big_endian ??
712 */
713 if (sign_of_sequental_byte_read == 0)
714 {
715 even_byte = 0;
716 }
717 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
718 {
719 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
720 *value = 0;
721 sign_of_sequental_byte_read = 0;
722 even_byte = 0;
723 return ERROR_NAND_OPERATION_FAILED;
724 }
725 else
726 {
727 uint16_t temp;
728 target_read_u16 (target, in_sram_address, &temp);
729 if (even_byte)
730 {
731 *value = temp >> 8;
732 even_byte = 0;
733 in_sram_address += 2;
734 }
735 else
736 {
737 *value = temp & 0xff;
738 even_byte = 1;
739 }
740 }
741 sign_of_sequental_byte_read = 1;
742 return ERROR_OK;
743 }
744
745 static int get_next_halfword_from_sram_buffer (struct target * target,
746 uint16_t * value)
747 {
748 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
749 {
750 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
751 *value = 0;
752 return ERROR_NAND_OPERATION_FAILED;
753 }
754 else
755 {
756 target_read_u16 (target, in_sram_address, value);
757 in_sram_address += 2;
758 }
759 return ERROR_OK;
760 }
761
762 static int poll_for_complete_op (struct target * target, const char *text)
763 {
764 uint16_t poll_complete_status;
765 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
766 {
767 usleep (25);
768 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
769 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
770 {
771 break;
772 }
773 }
774 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
775 {
776 LOG_ERROR ("%s sending timeout", text);
777 return ERROR_NAND_OPERATION_FAILED;
778 }
779 return ERROR_OK;
780 }
781
782 static int validate_target_state (struct nand_device *nand)
783 {
784 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
785 struct target *target = mx3_nf_info->target;
786
787 if (target->state != TARGET_HALTED)
788 {
789 LOG_ERROR (target_not_halted_err_msg);
790 return ERROR_NAND_OPERATION_FAILED;
791 }
792
793 if (mx3_nf_info->flags.target_little_endian !=
794 (target->endianness == TARGET_LITTLE_ENDIAN))
795 {
796 /*
797 * endianness changed after NAND controller probed
798 */
799 return ERROR_NAND_OPERATION_FAILED;
800 }
801 return ERROR_OK;
802 }
803
804 static int do_data_output (struct nand_device *nand)
805 {
806 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
807 struct target *target = mx3_nf_info->target;
808 switch (mx3_nf_info->fin)
809 {
810 case MX3_NF_FIN_DATAOUT:
811 /*
812 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
813 */
814 target_write_u16 (target, MX3_NF_CFG2,
815 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
816 optype));
817 {
818 int poll_result;
819 poll_result = poll_for_complete_op (target, "data output");
820 if (poll_result != ERROR_OK)
821 {
822 return poll_result;
823 }
824 }
825 mx3_nf_info->fin = MX3_NF_FIN_NONE;
826 /*
827 * ECC stuff
828 */
829 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
830 && mx3_nf_info->flags.hw_ecc_enabled)
831 {
832 uint16_t ecc_status;
833 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
834 switch (ecc_status & 0x000c)
835 {
836 case 1 << 2:
837 LOG_DEBUG
838 ("main area readed with 1 (correctable) error");
839 break;
840 case 2 << 2:
841 LOG_DEBUG
842 ("main area readed with more than 1 (incorrectable) error");
843 return ERROR_NAND_OPERATION_FAILED;
844 break;
845 }
846 switch (ecc_status & 0x0003)
847 {
848 case 1:
849 LOG_DEBUG
850 ("spare area readed with 1 (correctable) error");
851 break;
852 case 2:
853 LOG_DEBUG
854 ("main area readed with more than 1 (incorrectable) error");
855 return ERROR_NAND_OPERATION_FAILED;
856 break;
857 }
858 }
859 break;
860 case MX3_NF_FIN_NONE:
861 break;
862 }
863 return ERROR_OK;
864 }
865
866 struct nand_flash_controller imx31_nand_flash_controller = {
867 .name = "imx31",
868 .nand_device_command = &imx31_nand_device_command,
869 .init = &imx31_init,
870 .reset = &imx31_reset,
871 .command = &imx31_command,
872 .address = &imx31_address,
873 .write_data = &imx31_write_data,
874 .read_data = &imx31_read_data,
875 .write_page = &imx31_write_page,
876 .read_page = &imx31_read_page,
877 .controller_ready = &imx31_controller_ready,
878 .nand_ready = &imx31_nand_ready,
879 };
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