flash/nor: use command_print() in command "flash banks"
[openocd.git] / src / flash / mflash.h
1 /***************************************************************************
2 * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17
18 #ifndef OPENOCD_FLASH_MFLASH_H
19 #define OPENOCD_FLASH_MFLASH_H
20
21 struct command_context;
22
23 typedef unsigned long mg_io_uint32;
24 typedef unsigned short mg_io_uint16;
25 typedef unsigned char mg_io_uint8;
26
27 struct mflash_gpio_num {
28 char port[2];
29 signed short num;
30 };
31
32 struct mflash_gpio_drv {
33 const char *name;
34 int (*set_gpio_to_output)(struct mflash_gpio_num gpio);
35 int (*set_gpio_output_val)(struct mflash_gpio_num gpio, uint8_t val);
36 };
37
38 typedef struct _mg_io_type_drv_info {
39
40 mg_io_uint16 general_configuration; /* 00 */
41 mg_io_uint16 number_of_cylinders; /* 01 */
42 mg_io_uint16 reserved1; /* 02 */
43 mg_io_uint16 number_of_heads; /* 03 */
44 mg_io_uint16 unformatted_bytes_per_track; /* 04 */
45 mg_io_uint16 unformatted_bytes_per_sector; /* 05 */
46 mg_io_uint16 sectors_per_track; /* 06 */
47 mg_io_uint16 vendor_unique1[3]; /* 07/08/09 */
48
49 mg_io_uint8 serial_number[20]; /* 10~19 */
50
51 mg_io_uint16 buffer_type; /* 20 */
52 mg_io_uint16 buffer_sector_size; /* 21 */
53 mg_io_uint16 number_of_ecc_bytes; /* 22 */
54
55 mg_io_uint8 firmware_revision[8]; /* 23~26 */
56 mg_io_uint8 model_number[40]; /* 27 */
57
58 mg_io_uint8 maximum_block_transfer; /* 47 low byte */
59 mg_io_uint8 vendor_unique2; /* 47 high byte */
60 mg_io_uint16 dword_io; /* 48 */
61
62 mg_io_uint16 capabilities; /* 49 */
63 mg_io_uint16 reserved2; /* 50 */
64
65 mg_io_uint8 vendor_unique3; /* 51 low byte */
66 mg_io_uint8 pio_cycle_timing_mode; /* 51 high byte */
67 mg_io_uint8 vendor_unique4; /* 52 low byte */
68 mg_io_uint8 dma_cycle_timing_mode; /* 52 high byte */
69 mg_io_uint16 translation_fields_valid; /* 53 (low bit) */
70 mg_io_uint16 number_of_current_cylinders; /* 54 */
71 mg_io_uint16 number_of_current_heads; /* 55 */
72 mg_io_uint16 current_sectors_per_track; /* 56 */
73 mg_io_uint16 current_sector_capacity_lo; /* 57 & 58 */
74 mg_io_uint16 current_sector_capacity_hi; /* 57 & 58 */
75 mg_io_uint8 multi_sector_count; /* 59 low */
76 mg_io_uint8 multi_sector_setting_valid; /* 59 high (low bit) */
77
78 mg_io_uint16 total_user_addressable_sectors_lo; /* 60 & 61 */
79 mg_io_uint16 total_user_addressable_sectors_hi; /* 60 & 61 */
80
81 mg_io_uint8 single_dma_modes_supported; /* 62 low byte */
82 mg_io_uint8 single_dma_transfer_active; /* 62 high byte */
83 mg_io_uint8 multi_dma_modes_supported; /* 63 low byte */
84 mg_io_uint8 multi_dma_transfer_active; /* 63 high byte */
85 mg_io_uint16 adv_pio_mode;
86 mg_io_uint16 min_dma_cyc;
87 mg_io_uint16 recommend_dma_cyc;
88 mg_io_uint16 min_pio_cyc_no_iordy;
89 mg_io_uint16 min_pio_cyc_with_iordy;
90 mg_io_uint8 reserved3[22];
91 mg_io_uint16 major_ver_num;
92 mg_io_uint16 minor_ver_num;
93 mg_io_uint16 feature_cmd_set_suprt0;
94 mg_io_uint16 feature_cmd_set_suprt1;
95 mg_io_uint16 feature_cmd_set_suprt2;
96 mg_io_uint16 feature_cmd_set_en0;
97 mg_io_uint16 feature_cmd_set_en1;
98 mg_io_uint16 feature_cmd_set_en2;
99 mg_io_uint16 reserved4;
100 mg_io_uint16 req_time_for_security_er_done;
101 mg_io_uint16 req_time_for_enhan_security_er_done;
102 mg_io_uint16 adv_pwr_mgm_lvl_val;
103 mg_io_uint16 reserved5;
104 mg_io_uint16 re_of_hw_rst;
105 mg_io_uint8 reserved6[68];
106 mg_io_uint16 security_stas;
107 mg_io_uint8 vendor_uniq_bytes[62];
108 mg_io_uint16 cfa_pwr_mode;
109 mg_io_uint8 reserved7[186];
110
111 mg_io_uint16 scts_per_secure_data_unit;
112 mg_io_uint16 integrity_word;
113
114 } mg_io_type_drv_info;
115
116 typedef struct _mg_pll_t {
117 unsigned int lock_cyc;
118 unsigned short feedback_div; /* 9bit divider */
119 unsigned char input_div; /* 5bit divider */
120 unsigned char output_div; /* 2bit divider */
121 } mg_pll_t;
122
123 struct mg_drv_info {
124 mg_io_type_drv_info drv_id;
125 uint32_t tot_sects;
126 };
127
128 struct mflash_bank {
129 uint32_t base;
130
131 struct mflash_gpio_num rst_pin;
132
133 struct mflash_gpio_drv *gpio_drv;
134 struct target *target;
135 struct mg_drv_info *drv_info;
136 };
137
138 int mflash_register_commands(struct command_context *cmd_ctx);
139
140 #define MG_MFLASH_SECTOR_SIZE (0x200) /* 512Bytes = 2^9 */
141 #define MG_MFLASH_SECTOR_SIZE_MASK (0x200-1)
142 #define MG_MFLASH_SECTOR_SIZE_SHIFT (9)
143
144 #define MG_BUFFER_OFFSET 0x8000
145 #define MG_REG_OFFSET 0xC000
146 #define MG_REG_FEATURE 0x2 /* write case */
147 #define MG_REG_ERROR 0x2 /* read case */
148 #define MG_REG_SECT_CNT 0x4
149 #define MG_REG_SECT_NUM 0x6
150 #define MG_REG_CYL_LOW 0x8
151 #define MG_REG_CYL_HIGH 0xA
152 #define MG_REG_DRV_HEAD 0xC
153 #define MG_REG_COMMAND 0xE /* write case */
154 #define MG_REG_STATUS 0xE /* read case */
155 #define MG_REG_DRV_CTRL 0x10
156 #define MG_REG_BURST_CTRL 0x12
157
158 #define MG_OEM_DISK_WAIT_TIME_LONG 15000 /* msec */
159 #define MG_OEM_DISK_WAIT_TIME_NORMAL 3000 /* msec */
160 #define MG_OEM_DISK_WAIT_TIME_SHORT 1000 /* msec */
161
162 #define MG_PLL_CLK_OUT 66000000.0 /* 66Mhz */
163 #define MG_PLL_MAX_FEEDBACKDIV_VAL 512
164 #define MG_PLL_MAX_INPUTDIV_VAL 32
165 #define MG_PLL_MAX_OUTPUTDIV_VAL 4
166
167 #define MG_PLL_STD_INPUTCLK 12000000.0 /* 12Mhz */
168 #define MG_PLL_STD_LOCKCYCLE 10000
169
170 #define MG_UNLOCK_OTP_AREA 0xFF
171
172 #define MG_FILEIO_CHUNK 1048576
173
174 #define ERROR_MG_IO (-1600)
175 #define ERROR_MG_TIMEOUT (-1601)
176 #define ERROR_MG_INVALID_PLL (-1603)
177 #define ERROR_MG_INTERFACE (-1604)
178 #define ERROR_MG_INVALID_OSC (-1605)
179 #define ERROR_MG_UNSUPPORTED_SOC (-1606)
180
181 typedef enum _mg_io_type_wait {
182
183 mg_io_wait_bsy = 1,
184 mg_io_wait_not_bsy = 2,
185 mg_io_wait_rdy = 3,
186 mg_io_wait_drq = 4, /* wait for data request */
187 mg_io_wait_drq_noerr = 5, /* wait for DRQ but ignore the error status bit */
188 mg_io_wait_rdy_noerr = 6 /* wait for ready, but ignore error status bit */
189
190 } mg_io_type_wait;
191
192 /*= "Status Register" bit masks. */
193 typedef enum _mg_io_type_rbit_status {
194
195 mg_io_rbit_status_error = 0x01, /* error bit in status register */
196 mg_io_rbit_status_corrected_error = 0x04, /* corrected error in status register */
197 mg_io_rbit_status_data_req = 0x08, /* data request bit in status register */
198 mg_io_rbit_status_seek_done = 0x10, /* DSC - Drive Seek Complete */
199 mg_io_rbit_status_write_fault = 0x20, /* DWF - Drive Write Fault */
200 mg_io_rbit_status_ready = 0x40,
201 mg_io_rbit_status_busy = 0x80
202
203 } mg_io_type_rbit_status;
204
205 /*= "Error Register" bit masks. */
206 typedef enum _mg_io_type_rbit_error {
207
208 mg_io_rbit_err_general = 0x01,
209 mg_io_rbit_err_aborted = 0x04,
210 mg_io_rbit_err_bad_sect_num = 0x10,
211 mg_io_rbit_err_uncorrectable = 0x40,
212 mg_io_rbit_err_bad_block = 0x80
213
214 } mg_io_type_rbit_error;
215
216 /* = "Device Control Register" bit. */
217 typedef enum _mg_io_type_rbit_devc {
218
219 mg_io_rbit_devc_intr = 0x02, /* interrupt enable bit (1:disable, 0:enable) */
220 mg_io_rbit_devc_srst = 0x04 /* softwrae reset bit (1:assert, 0:de-assert) */
221
222 } mg_io_type_rbit_devc;
223
224 /* "Drive Select/Head Register" values. */
225 typedef enum _mg_io_type_rval_dev {
226
227 mg_io_rval_dev_must_be_on = 0x80, /* These 1 bits are always on */
228 mg_io_rval_dev_drv_master = (0x00 | mg_io_rval_dev_must_be_on), /* Master */
229 mg_io_rval_dev_drv_slave0 = (0x10 | mg_io_rval_dev_must_be_on), /* Slave0 */
230 mg_io_rval_dev_drv_slave1 = (0x20 | mg_io_rval_dev_must_be_on), /* Slave1 */
231 mg_io_rval_dev_drv_slave2 = (0x30 | mg_io_rval_dev_must_be_on), /* Slave2 */
232 mg_io_rval_dev_lba_mode = (0x40 | mg_io_rval_dev_must_be_on)
233
234 } mg_io_type_rval_dev;
235
236 typedef enum _mg_io_type_cmd {
237 mg_io_cmd_read = 0x20,
238 mg_io_cmd_write = 0x30,
239
240 mg_io_cmd_setmul = 0xC6,
241 mg_io_cmd_readmul = 0xC4,
242 mg_io_cmd_writemul = 0xC5,
243
244 mg_io_cmd_idle = 0x97, /* 0xE3 */
245 mg_io_cmd_idle_immediate = 0x95, /* 0xE1 */
246
247 mg_io_cmd_setsleep = 0x99, /* 0xE6 */
248 mg_io_cmd_stdby = 0x96, /* 0xE2 */
249 mg_io_cmd_stdby_immediate = 0x94, /* 0xE0 */
250
251 mg_io_cmd_identify = 0xEC,
252 mg_io_cmd_set_feature = 0xEF,
253
254 mg_io_cmd_confirm_write = 0x3C,
255 mg_io_cmd_confirm_read = 0x40,
256 mg_io_cmd_wakeup = 0xC3
257
258 } mg_io_type_cmd;
259
260 typedef enum _mg_feature_id {
261 mg_feature_id_transmode = 0x3
262 } mg_feature_id;
263
264 typedef enum _mg_feature_val {
265 mg_feature_val_trans_default = 0x0,
266 mg_feature_val_trans_vcmd = 0x3,
267 mg_feature_val_trand_vcmds = 0x2
268 } mg_feature_val;
269
270 typedef enum _mg_vcmd {
271 mg_vcmd_update_xipinfo = 0xFA, /* FWPATCH commmand through IOM I/O */
272 mg_vcmd_verify_fwpatch = 0xFB, /* FWPATCH commmand through IOM I/O */
273 mg_vcmd_update_stgdrvinfo = 0xFC, /* IOM identificatin info program command */
274 mg_vcmd_prep_fwpatch = 0xFD, /* FWPATCH commmand through IOM I/O */
275 mg_vcmd_exe_fwpatch = 0xFE, /* FWPATCH commmand through IOM I/O */
276 mg_vcmd_wr_pll = 0x8B,
277 mg_vcmd_purge_nand = 0x8C, /* Only for Seagle */
278 mg_vcmd_lock_otp = 0x8D,
279 mg_vcmd_rd_otp = 0x8E,
280 mg_vcmd_wr_otp = 0x8F
281 } mg_vcmd;
282
283 typedef enum _mg_opmode {
284 mg_op_mode_xip = 1, /* TRUE XIP */
285 mg_op_mode_snd = 2, /* BOOT + Storage */
286 mg_op_mode_stg = 0 /* Only Storage */
287 } mg_opmode;
288
289 #endif /* OPENOCD_FLASH_MFLASH_H */