1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
41 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
42 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
43 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
44 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
45 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
46 int cfi_probe(struct flash_bank_s
*bank
);
47 int cfi_auto_probe(struct flash_bank_s
*bank
);
48 int cfi_erase_check(struct flash_bank_s
*bank
);
49 int cfi_protect_check(struct flash_bank_s
*bank
);
50 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
52 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 #define CFI_MAX_BUS_WIDTH 4
55 #define CFI_MAX_CHIP_WIDTH 4
57 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
58 #define CFI_MAX_INTEL_CODESIZE 256
60 flash_driver_t cfi_flash
=
63 .register_commands
= cfi_register_commands
,
64 .flash_bank_command
= cfi_flash_bank_command
,
66 .protect
= cfi_protect
,
69 .auto_probe
= cfi_auto_probe
,
70 .erase_check
= cfi_erase_check
,
71 .protect_check
= cfi_protect_check
,
75 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
77 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
78 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
81 /* CFI fixups foward declarations */
82 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
83 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
84 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
86 /* fixup after identifying JEDEC manufactuer and ID */
87 cfi_fixup_t cfi_jedec_fixups
[] = {
88 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
91 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
92 {CFI_MFR_SST
, 0x2780, cfi_fixup_non_cfi
, NULL
},
93 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
94 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
95 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
96 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
100 /* fixup after reading cmdset 0002 primary query table */
101 cfi_fixup_t cfi_0002_fixups
[] = {
102 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
103 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
104 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
105 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
106 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
107 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
108 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
112 /* fixup after reading cmdset 0001 primary query table */
113 cfi_fixup_t cfi_0001_fixups
[] = {
117 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
119 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
122 for (f
= fixups
; f
->fixup
; f
++)
124 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
125 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
127 f
->fixup(bank
, f
->param
);
132 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
133 __inline__ u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
135 /* while the sector list isn't built, only accesses to sector 0 work */
137 return bank
->base
+ offset
* bank
->bus_width
;
142 ERROR("BUG: sector list not yet built");
145 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
150 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
154 /* clear whole buffer, to ensure bits that exceed the bus_width
157 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
160 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
162 for (i
= bank
->bus_width
; i
> 0; i
--)
164 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
169 for (i
= 1; i
<= bank
->bus_width
; i
++)
171 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
176 /* read unsigned 8-bit value from the bank
177 * flash banks are expected to be made of similar chips
178 * the query result should be the same for all
180 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
182 target_t
*target
= bank
->target
;
183 u8 data
[CFI_MAX_BUS_WIDTH
];
185 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
187 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
190 return data
[bank
->bus_width
- 1];
193 /* read unsigned 8-bit value from the bank
194 * in case of a bank made of multiple chips,
195 * the individual values are ORed
197 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
199 target_t
*target
= bank
->target
;
200 u8 data
[CFI_MAX_BUS_WIDTH
];
203 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
205 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
207 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
215 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
216 value
|= data
[bank
->bus_width
- 1 - i
];
222 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
224 target_t
*target
= bank
->target
;
225 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
227 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
229 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
230 return data
[0] | data
[bank
->bus_width
] << 8;
232 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
235 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
237 target_t
*target
= bank
->target
;
238 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
240 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
242 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
243 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
245 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
246 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
249 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
251 target_t
*target
= bank
->target
;
254 if (target
->state
!= TARGET_HALTED
)
256 ERROR("BUG: attempted to clear status register while target wasn't halted");
260 cfi_command(bank
, 0x50, command
);
261 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
264 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
268 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
270 DEBUG("status: 0x%x", status
);
274 /* mask out bit 0 (reserved) */
275 status
= status
& 0xfe;
277 DEBUG("status: 0x%x", status
);
279 if ((status
& 0x80) != 0x80)
281 ERROR("timeout while waiting for WSM to become ready");
283 else if (status
!= 0x80)
285 ERROR("status register: 0x%x", status
);
287 ERROR("Block Lock-Bit Detected, Operation Abort");
289 ERROR("Program suspended");
291 ERROR("Low Programming Voltage Detected, Operation Aborted");
293 ERROR("Program Error / Error in Setting Lock-Bit");
295 ERROR("Error in Block Erasure or Clear Lock-Bits");
297 ERROR("Block Erase Suspended");
299 cfi_intel_clear_status_register(bank
);
305 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
307 u8 status
, oldstatus
;
309 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
312 status
= cfi_get_u8(bank
, 0, 0x0);
313 if ((status
^ oldstatus
) & 0x40) {
315 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
316 status
= cfi_get_u8(bank
, 0, 0x0);
317 if ((status
^ oldstatus
) & 0x40) {
318 ERROR("dq5 timeout, status: 0x%x", status
);
319 return(ERROR_FLASH_OPERATION_FAILED
);
321 DEBUG("status: 0x%x", status
);
326 DEBUG("status: 0x%x", status
);
332 } while (timeout
-- > 0);
334 ERROR("timeout, status: 0x%x", status
);
336 return(ERROR_FLASH_BUSY
);
339 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
341 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
342 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
343 target_t
*target
= bank
->target
;
346 cfi_info
->pri_ext
= pri_ext
;
348 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
349 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
350 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
352 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
354 cfi_command(bank
, 0xf0, command
);
355 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
356 cfi_command(bank
, 0xff, command
);
357 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
358 return ERROR_FLASH_BANK_INVALID
;
361 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
362 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
364 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
366 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
367 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
368 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
370 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
372 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
373 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
375 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
376 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
377 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
379 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
380 if (pri_ext
->num_protection_fields
!= 1)
382 WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
385 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
386 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
387 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
389 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
394 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
396 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
397 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
398 target_t
*target
= bank
->target
;
401 cfi_info
->pri_ext
= pri_ext
;
403 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
404 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
405 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
407 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
409 cfi_command(bank
, 0xf0, command
);
410 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
411 return ERROR_FLASH_BANK_INVALID
;
414 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
415 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
417 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
419 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
420 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
421 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
422 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
423 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
424 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
425 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
426 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
427 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
428 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
429 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
431 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
432 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
434 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
435 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
437 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
440 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
441 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
442 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
444 DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
446 /* default values for implementation specific workarounds */
447 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
448 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
449 pri_ext
->_reversed_geometry
= 0;
454 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
456 cfi_atmel_pri_ext_t atmel_pri_ext
;
457 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
458 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
459 target_t
*target
= bank
->target
;
462 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
463 * but a different primary extended query table.
464 * We read the atmel table, and prepare a valid AMD/Spansion query table.
467 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
469 cfi_info
->pri_ext
= pri_ext
;
471 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
472 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
473 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
475 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
477 cfi_command(bank
, 0xf0, command
);
478 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
479 return ERROR_FLASH_BANK_INVALID
;
482 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
483 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
484 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
486 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
487 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
489 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
491 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
492 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
494 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
495 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
496 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
497 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
499 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
500 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
502 if (atmel_pri_ext
.features
& 0x02)
503 pri_ext
->EraseSuspend
= 2;
505 if (atmel_pri_ext
.bottom_boot
)
506 pri_ext
->TopBottom
= 2;
508 pri_ext
->TopBottom
= 3;
510 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
511 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
516 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
518 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
520 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
522 return cfi_read_atmel_pri_ext(bank
);
526 return cfi_read_spansion_pri_ext(bank
);
530 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
533 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
534 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
536 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
540 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
541 pri_ext
->pri
[1], pri_ext
->pri
[2],
542 pri_ext
->major_version
, pri_ext
->minor_version
);
546 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
547 (pri_ext
->SiliconRevision
) >> 2,
548 (pri_ext
->SiliconRevision
) & 0x03);
552 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
553 pri_ext
->EraseSuspend
,
558 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
559 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
560 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
565 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
568 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
569 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
571 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
575 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
579 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
583 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
584 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
585 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
589 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
594 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
596 /*command_t *cfi_cmd = */
597 register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
599 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
600 "print part id of cfi flash bank <num>");
605 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
607 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
609 cfi_flash_bank_t
*cfi_info
;
614 WARNING("incomplete flash_bank cfi configuration");
615 return ERROR_FLASH_BANK_INVALID
;
618 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
619 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
621 ERROR("chip and bus width have to specified in bytes");
622 return ERROR_FLASH_BANK_INVALID
;
625 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
626 cfi_info
->probed
= 0;
627 bank
->driver_priv
= cfi_info
;
629 cfi_info
->write_algorithm
= NULL
;
630 cfi_info
->erase_check_algorithm
= NULL
;
632 cfi_info
->x16_as_x8
= 0;
633 cfi_info
->jedec_probe
= 0;
634 cfi_info
->not_cfi
= 0;
636 for (i
= 6; i
< argc
; i
++)
638 if (strcmp(args
[i
], "x16_as_x8") == 0)
640 cfi_info
->x16_as_x8
= 1;
642 else if (strcmp(args
[i
], "jedec_probe") == 0)
644 cfi_info
->jedec_probe
= 1;
648 cfi_info
->write_algorithm
= NULL
;
650 /* bank wasn't probed yet */
651 cfi_info
->qry
[0] = -1;
656 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
658 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
659 target_t
*target
= bank
->target
;
663 cfi_intel_clear_status_register(bank
);
665 for (i
= first
; i
<= last
; i
++)
667 cfi_command(bank
, 0x20, command
);
668 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
670 cfi_command(bank
, 0xd0, command
);
671 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
673 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
674 bank
->sectors
[i
].is_erased
= 1;
677 cfi_command(bank
, 0xff, command
);
678 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
680 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
681 return ERROR_FLASH_OPERATION_FAILED
;
685 cfi_command(bank
, 0xff, command
);
686 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
691 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
693 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
694 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
695 target_t
*target
= bank
->target
;
699 for (i
= first
; i
<= last
; i
++)
701 cfi_command(bank
, 0xaa, command
);
702 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
704 cfi_command(bank
, 0x55, command
);
705 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
707 cfi_command(bank
, 0x80, command
);
708 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
710 cfi_command(bank
, 0xaa, command
);
711 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
713 cfi_command(bank
, 0x55, command
);
714 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
716 cfi_command(bank
, 0x30, command
);
717 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
719 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
720 bank
->sectors
[i
].is_erased
= 1;
723 cfi_command(bank
, 0xf0, command
);
724 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
726 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
727 return ERROR_FLASH_OPERATION_FAILED
;
731 cfi_command(bank
, 0xf0, command
);
732 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
737 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
739 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
741 if (bank
->target
->state
!= TARGET_HALTED
)
743 return ERROR_TARGET_NOT_HALTED
;
746 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
748 return ERROR_FLASH_SECTOR_INVALID
;
751 if (cfi_info
->qry
[0] != 'Q')
752 return ERROR_FLASH_BANK_NOT_PROBED
;
754 switch(cfi_info
->pri_id
)
758 return cfi_intel_erase(bank
, first
, last
);
761 return cfi_spansion_erase(bank
, first
, last
);
764 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
771 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
773 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
774 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
775 target_t
*target
= bank
->target
;
780 /* if the device supports neither legacy lock/unlock (bit 3) nor
781 * instant individual block locking (bit 5).
783 if (!(pri_ext
->feature_support
& 0x28))
784 return ERROR_FLASH_OPERATION_FAILED
;
786 cfi_intel_clear_status_register(bank
);
788 for (i
= first
; i
<= last
; i
++)
790 cfi_command(bank
, 0x60, command
);
791 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
792 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
795 cfi_command(bank
, 0x01, command
);
796 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
797 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
798 bank
->sectors
[i
].is_protected
= 1;
802 cfi_command(bank
, 0xd0, command
);
803 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
804 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
805 bank
->sectors
[i
].is_protected
= 0;
808 /* instant individual block locking doesn't require reading of the status register */
809 if (!(pri_ext
->feature_support
& 0x20))
811 /* Clear lock bits operation may take up to 1.4s */
812 cfi_intel_wait_status_busy(bank
, 1400);
817 /* read block lock bit, to verify status */
818 cfi_command(bank
, 0x90, command
);
819 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
820 block_status
= cfi_get_u8(bank
, i
, 0x2);
822 if ((block_status
& 0x1) != set
)
824 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
825 cfi_command(bank
, 0x70, command
);
826 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
827 cfi_intel_wait_status_busy(bank
, 10);
830 return ERROR_FLASH_OPERATION_FAILED
;
840 /* if the device doesn't support individual block lock bits set/clear,
841 * all blocks have been unlocked in parallel, so we set those that should be protected
843 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
845 for (i
= 0; i
< bank
->num_sectors
; i
++)
847 if (bank
->sectors
[i
].is_protected
== 1)
849 cfi_intel_clear_status_register(bank
);
851 cfi_command(bank
, 0x60, command
);
852 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
854 cfi_command(bank
, 0x01, command
);
855 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
857 cfi_intel_wait_status_busy(bank
, 100);
862 cfi_command(bank
, 0xff, command
);
863 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
868 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
870 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
872 if (bank
->target
->state
!= TARGET_HALTED
)
874 return ERROR_TARGET_NOT_HALTED
;
877 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
879 return ERROR_FLASH_SECTOR_INVALID
;
882 if (cfi_info
->qry
[0] != 'Q')
883 return ERROR_FLASH_BANK_NOT_PROBED
;
885 switch(cfi_info
->pri_id
)
889 cfi_intel_protect(bank
, set
, first
, last
);
892 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
899 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
900 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
902 /* target_t *target = bank->target; */
907 * The data to flash must not be changed in endian! We write a bytestrem in
908 * target byte order already. Only the control and status byte lane of the flash
909 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
910 * word (data seems to be in the upper or lower byte lane for u16 accesses).
914 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
918 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
919 word
[i
] = word
[i
+ 1];
920 word
[bank
->bus_width
- 1] = byte
;
926 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
927 word
[i
] = word
[i
- 1];
933 /* Convert code image to target endian */
934 /* FIXME create general block conversion fcts in target.c?) */ static
935 void cfi_fix_code_endian(target_t
*target
, u32
*dest
, const u32
*src
, u32 count
)
938 for (i
=0; i
< count
; i
++)
940 target_buffer_set_u32(target
, (u8
*)dest
, *src
);
946 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
948 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
949 target_t
*target
= bank
->target
;
950 reg_param_t reg_params
[7];
951 armv4_5_algorithm_t armv4_5_info
;
952 working_area_t
*source
;
953 u32 buffer_size
= 32768;
954 u8 write_command_buf
[CFI_MAX_BUS_WIDTH
];
955 u8 busy_pattern_buf
[CFI_MAX_BUS_WIDTH
];
956 u8 error_pattern_buf
[CFI_MAX_BUS_WIDTH
];
957 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
959 /* algorithm register usage:
960 * r0: source address (in RAM)
961 * r1: target address (in Flash)
963 * r3: flash write command
964 * r4: status byte (returned to host)
965 * r5: busy test pattern
966 * r6: error test pattern
969 static const u32 word_32_code
[] = {
970 0xe4904004, /* loop: ldr r4, [r0], #4 */
971 0xe5813000, /* str r3, [r1] */
972 0xe5814000, /* str r4, [r1] */
973 0xe5914000, /* busy: ldr r4, [r1] */
974 0xe0047005, /* and r7, r4, r5 */
975 0xe1570005, /* cmp r7, r5 */
976 0x1afffffb, /* bne busy */
977 0xe1140006, /* tst r4, r6 */
978 0x1a000003, /* bne done */
979 0xe2522001, /* subs r2, r2, #1 */
980 0x0a000001, /* beq done */
981 0xe2811004, /* add r1, r1 #4 */
982 0xeafffff2, /* b loop */
983 0xeafffffe /* done: b -2 */
986 static const u32 word_16_code
[] = {
987 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
988 0xe1c130b0, /* strh r3, [r1] */
989 0xe1c140b0, /* strh r4, [r1] */
990 0xe1d140b0, /* busy ldrh r4, [r1] */
991 0xe0047005, /* and r7, r4, r5 */
992 0xe1570005, /* cmp r7, r5 */
993 0x1afffffb, /* bne busy */
994 0xe1140006, /* tst r4, r6 */
995 0x1a000003, /* bne done */
996 0xe2522001, /* subs r2, r2, #1 */
997 0x0a000001, /* beq done */
998 0xe2811002, /* add r1, r1 #2 */
999 0xeafffff2, /* b loop */
1000 0xeafffffe /* done: b -2 */
1003 static const u32 word_8_code
[] = {
1004 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1005 0xe5c13000, /* strb r3, [r1] */
1006 0xe5c14000, /* strb r4, [r1] */
1007 0xe5d14000, /* busy ldrb r4, [r1] */
1008 0xe0047005, /* and r7, r4, r5 */
1009 0xe1570005, /* cmp r7, r5 */
1010 0x1afffffb, /* bne busy */
1011 0xe1140006, /* tst r4, r6 */
1012 0x1a000003, /* bne done */
1013 0xe2522001, /* subs r2, r2, #1 */
1014 0x0a000001, /* beq done */
1015 0xe2811001, /* add r1, r1 #1 */
1016 0xeafffff2, /* b loop */
1017 0xeafffffe /* done: b -2 */
1019 u32 target_code
[CFI_MAX_INTEL_CODESIZE
];
1020 const u32
*target_code_src
;
1021 int target_code_size
;
1022 int retval
= ERROR_OK
;
1025 cfi_intel_clear_status_register(bank
);
1027 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1028 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1029 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1031 /* If we are setting up the write_algorith, we need target_code_src */
1032 /* if not we only need target_code_size. */
1034 /* However, we don't want to create multiple code paths, so we */
1035 /* do the unecessary evaluation of target_code_src, which the */
1036 /* compiler will probably nicely optimize away if not needed */
1038 /* prepare algorithm code for target endian */
1039 switch (bank
->bus_width
)
1042 target_code_src
= word_8_code
;
1043 target_code_size
= sizeof(word_8_code
);
1046 target_code_src
= word_16_code
;
1047 target_code_size
= sizeof(word_16_code
);
1050 target_code_src
= word_32_code
;
1051 target_code_size
= sizeof(word_32_code
);
1054 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1055 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1058 /* flash write code */
1059 if (!cfi_info
->write_algorithm
)
1061 if ( target_code_size
> sizeof(target_code
) )
1063 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1064 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1066 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
);
1068 /* Get memory for block write handler */
1069 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1070 if (retval
!= ERROR_OK
)
1072 WARNING("No working area available, can't do block memory writes");
1073 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1076 /* write algorithm code to working area */
1077 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, (u8
*)target_code
);
1078 if (retval
!= ERROR_OK
)
1080 ERROR("Unable to write block write code to target");
1085 /* Get a workspace buffer for the data to flash starting with 32k size.
1086 Half size until buffer would be smaller 256 Bytem then fail back */
1087 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1088 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1091 if (buffer_size
<= 256)
1093 WARNING("no large enough working area available, can't do block memory writes");
1094 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1099 /* setup algo registers */
1100 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1101 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1102 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1103 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1104 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1105 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1106 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1108 /* prepare command and status register patterns */
1109 cfi_command(bank
, 0x40, write_command_buf
);
1110 cfi_command(bank
, 0x80, busy_pattern_buf
);
1111 cfi_command(bank
, 0x7e, error_pattern_buf
);
1113 switch (bank
->bus_width
)
1116 write_command_val
= write_command_buf
[0];
1117 busy_pattern_val
= busy_pattern_buf
[0];
1118 error_pattern_val
= error_pattern_buf
[0];
1121 write_command_val
= target_buffer_get_u16(target
, write_command_buf
);
1122 busy_pattern_val
= target_buffer_get_u16(target
, busy_pattern_buf
);
1123 error_pattern_val
= target_buffer_get_u16(target
, error_pattern_buf
);
1126 write_command_val
= target_buffer_get_u32(target
, write_command_buf
);
1127 busy_pattern_val
= target_buffer_get_u32(target
, busy_pattern_buf
);
1128 error_pattern_val
= target_buffer_get_u32(target
, error_pattern_buf
);
1131 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1132 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1136 INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1138 /* Programming main loop */
1141 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1144 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1146 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1147 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1148 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1150 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1151 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1152 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1154 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1156 /* Execute algorithm, assume breakpoint for last instruction */
1157 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1158 cfi_info
->write_algorithm
->address
,
1159 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1160 10000, /* 10s should be enough for max. 32k of data */
1163 /* On failure try a fall back to direct word writes */
1164 if (retval
!= ERROR_OK
)
1166 cfi_intel_clear_status_register(bank
);
1167 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1168 retval
= ERROR_FLASH_OPERATION_FAILED
;
1169 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1170 /* FIXME To allow fall back or recovery, we must save the actual status
1171 somewhere, so that a higher level code can start recovery. */
1175 /* Check return value from algo code */
1176 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1179 /* read status register (outputs debug inforation) */
1180 cfi_intel_wait_status_busy(bank
, 100);
1181 cfi_intel_clear_status_register(bank
);
1182 retval
= ERROR_FLASH_OPERATION_FAILED
;
1186 buffer
+= thisrun_count
;
1187 address
+= thisrun_count
;
1188 count
-= thisrun_count
;
1191 /* free up resources */
1194 target_free_working_area(target
, source
);
1196 if (cfi_info
->write_algorithm
)
1198 target_free_working_area(target
, cfi_info
->write_algorithm
);
1199 cfi_info
->write_algorithm
= NULL
;
1202 destroy_reg_param(®_params
[0]);
1203 destroy_reg_param(®_params
[1]);
1204 destroy_reg_param(®_params
[2]);
1205 destroy_reg_param(®_params
[3]);
1206 destroy_reg_param(®_params
[4]);
1207 destroy_reg_param(®_params
[5]);
1208 destroy_reg_param(®_params
[6]);
1213 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1215 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1216 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1217 target_t
*target
= bank
->target
;
1218 reg_param_t reg_params
[10];
1219 armv4_5_algorithm_t armv4_5_info
;
1220 working_area_t
*source
;
1221 u32 buffer_size
= 32768;
1222 u8 write_command
[CFI_MAX_BUS_WIDTH
];
1226 int exit_code
= ERROR_OK
;
1228 /* input parameters - */
1229 /* R0 = source address */
1230 /* R1 = destination address */
1231 /* R2 = number of writes */
1232 /* R3 = flash write command */
1233 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1234 /* output parameters - */
1235 /* R5 = 0x80 ok 0x00 bad */
1236 /* temp registers - */
1237 /* R6 = value read from flash to test status */
1238 /* R7 = holding register */
1239 /* unlock registers - */
1240 /* R8 = unlock1_addr */
1241 /* R9 = unlock1_cmd */
1242 /* R10 = unlock2_addr */
1243 /* R11 = unlock2_cmd */
1245 u32 word_32_code
[] = {
1246 /* 00008100 <sp_32_code>: */
1247 0xe4905004, /* ldr r5, [r0], #4 */
1248 0xe5889000, /* str r9, [r8] */
1249 0xe58ab000, /* str r11, [r10] */
1250 0xe5883000, /* str r3, [r8] */
1251 0xe5815000, /* str r5, [r1] */
1252 0xe1a00000, /* nop */
1254 /* 00008110 <sp_32_busy>: */
1255 0xe5916000, /* ldr r6, [r1] */
1256 0xe0257006, /* eor r7, r5, r6 */
1257 0xe0147007, /* ands r7, r4, r7 */
1258 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1259 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1260 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1261 0xe5916000, /* ldr r6, [r1] */
1262 0xe0257006, /* eor r7, r5, r6 */
1263 0xe0147007, /* ands r7, r4, r7 */
1264 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1265 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1266 0x1a000004, /* bne 8154 <sp_32_done> */
1268 /* 00008140 <sp_32_cont>: */
1269 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1270 0x03a05080, /* moveq r5, #128 ; 0x80 */
1271 0x0a000001, /* beq 8154 <sp_32_done> */
1272 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1273 0xeaffffe8, /* b 8100 <sp_32_code> */
1275 /* 00008154 <sp_32_done>: */
1276 0xeafffffe /* b 8154 <sp_32_done> */
1279 u32 word_16_code
[] = {
1280 /* 00008158 <sp_16_code>: */
1281 0xe0d050b2, /* ldrh r5, [r0], #2 */
1282 0xe1c890b0, /* strh r9, [r8] */
1283 0xe1cab0b0, /* strh r11, [r10] */
1284 0xe1c830b0, /* strh r3, [r8] */
1285 0xe1c150b0, /* strh r5, [r1] */
1286 0xe1a00000, /* nop (mov r0,r0) */
1288 /* 00008168 <sp_16_busy>: */
1289 0xe1d160b0, /* ldrh r6, [r1] */
1290 0xe0257006, /* eor r7, r5, r6 */
1291 0xe0147007, /* ands r7, r4, r7 */
1292 0x0a000007, /* beq 8198 <sp_16_cont> */
1293 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1294 0x0afffff9, /* beq 8168 <sp_16_busy> */
1295 0xe1d160b0, /* ldrh r6, [r1] */
1296 0xe0257006, /* eor r7, r5, r6 */
1297 0xe0147007, /* ands r7, r4, r7 */
1298 0x0a000001, /* beq 8198 <sp_16_cont> */
1299 0xe3a05000, /* mov r5, #0 ; 0x0 */
1300 0x1a000004, /* bne 81ac <sp_16_done> */
1302 /* 00008198 <sp_16_cont>: */
1303 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1304 0x03a05080, /* moveq r5, #128 ; 0x80 */
1305 0x0a000001, /* beq 81ac <sp_16_done> */
1306 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1307 0xeaffffe8, /* b 8158 <sp_16_code> */
1309 /* 000081ac <sp_16_done>: */
1310 0xeafffffe /* b 81ac <sp_16_done> */
1313 u32 word_8_code
[] = {
1314 /* 000081b0 <sp_16_code_end>: */
1315 0xe4d05001, /* ldrb r5, [r0], #1 */
1316 0xe5c89000, /* strb r9, [r8] */
1317 0xe5cab000, /* strb r11, [r10] */
1318 0xe5c83000, /* strb r3, [r8] */
1319 0xe5c15000, /* strb r5, [r1] */
1320 0xe1a00000, /* nop (mov r0,r0) */
1322 /* 000081c0 <sp_8_busy>: */
1323 0xe5d16000, /* ldrb r6, [r1] */
1324 0xe0257006, /* eor r7, r5, r6 */
1325 0xe0147007, /* ands r7, r4, r7 */
1326 0x0a000007, /* beq 81f0 <sp_8_cont> */
1327 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1328 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1329 0xe5d16000, /* ldrb r6, [r1] */
1330 0xe0257006, /* eor r7, r5, r6 */
1331 0xe0147007, /* ands r7, r4, r7 */
1332 0x0a000001, /* beq 81f0 <sp_8_cont> */
1333 0xe3a05000, /* mov r5, #0 ; 0x0 */
1334 0x1a000004, /* bne 8204 <sp_8_done> */
1336 /* 000081f0 <sp_8_cont>: */
1337 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1338 0x03a05080, /* moveq r5, #128 ; 0x80 */
1339 0x0a000001, /* beq 8204 <sp_8_done> */
1340 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1341 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1343 /* 00008204 <sp_8_done>: */
1344 0xeafffffe /* b 8204 <sp_8_done> */
1347 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1348 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1349 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1351 /* flash write code */
1352 if (!cfi_info
->write_algorithm
)
1356 /* convert bus-width dependent algorithm code to correct endiannes */
1357 if (bank
->bus_width
== 1)
1359 code_p
= malloc(24 * 4);
1361 for (i
= 0; i
< 24; i
++)
1362 target_buffer_set_u32(target
, code_p
+ (i
*4), word_8_code
[i
]);
1364 else if (bank
->bus_width
== 2)
1366 code_p
= malloc(24 * 4);
1368 for (i
= 0; i
< 24; i
++)
1369 target_buffer_set_u32(target
, code_p
+ (i
*4), word_16_code
[i
]);
1371 else if (bank
->bus_width
== 4)
1373 code_p
= malloc(24 * 4);
1375 for (i
= 0; i
< 24; i
++)
1376 target_buffer_set_u32(target
, code_p
+ (i
*4), word_32_code
[i
]);
1380 return ERROR_FLASH_OPERATION_FAILED
;
1383 /* allocate working area */
1384 retval
=target_alloc_working_area(target
, 24 * 4,
1385 &cfi_info
->write_algorithm
);
1386 if (retval
!= ERROR_OK
)
1391 /* write algorithm code to working area */
1392 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 24 * 4, code_p
);
1397 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1400 if (buffer_size
<= 256)
1402 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1403 if (cfi_info
->write_algorithm
)
1404 target_free_working_area(target
, cfi_info
->write_algorithm
);
1406 WARNING("not enough working area available, can't do block memory writes");
1407 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1411 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1412 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1413 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1414 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1415 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1416 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1417 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1418 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1419 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1420 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1424 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1426 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1428 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1429 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1430 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1431 cfi_command(bank
, 0xA0, write_command
);
1432 buf_set_u32(reg_params
[3].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1433 cfi_command(bank
, 0x80, write_command
);
1434 buf_set_u32(reg_params
[4].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1435 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1436 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaa);
1437 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1438 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55);
1440 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1441 cfi_info
->write_algorithm
->address
,
1442 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1443 10000, &armv4_5_info
);
1445 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1447 if ((retval
!= ERROR_OK
) || status
!= 0x80)
1449 DEBUG("status: 0x%x", status
);
1450 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1454 buffer
+= thisrun_count
;
1455 address
+= thisrun_count
;
1456 count
-= thisrun_count
;
1459 target_free_working_area(target
, source
);
1461 destroy_reg_param(®_params
[0]);
1462 destroy_reg_param(®_params
[1]);
1463 destroy_reg_param(®_params
[2]);
1464 destroy_reg_param(®_params
[3]);
1465 destroy_reg_param(®_params
[4]);
1466 destroy_reg_param(®_params
[5]);
1467 destroy_reg_param(®_params
[6]);
1468 destroy_reg_param(®_params
[7]);
1469 destroy_reg_param(®_params
[8]);
1470 destroy_reg_param(®_params
[9]);
1475 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1477 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1478 target_t
*target
= bank
->target
;
1481 cfi_intel_clear_status_register(bank
);
1482 cfi_command(bank
, 0x40, command
);
1483 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1485 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1487 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1489 cfi_command(bank
, 0xff, command
);
1490 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1492 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1493 return ERROR_FLASH_OPERATION_FAILED
;
1499 int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1501 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1502 target_t
*target
= bank
->target
;
1505 /* Calculate buffer size and boundary mask */
1506 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1507 u32 buffermask
= buffersize
-1;
1510 /* Check for valid range */
1511 if (address
& buffermask
)
1513 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1514 return ERROR_FLASH_OPERATION_FAILED
;
1516 switch(bank
->chip_width
)
1518 case 4 : bufferwsize
= buffersize
/ 4; break;
1519 case 2 : bufferwsize
= buffersize
/ 2; break;
1520 case 1 : bufferwsize
= buffersize
; break;
1522 ERROR("Unsupported chip width %d", bank
->chip_width
);
1523 return ERROR_FLASH_OPERATION_FAILED
;
1526 /* Check for valid size */
1527 if (wordcount
> bufferwsize
)
1529 ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1530 return ERROR_FLASH_OPERATION_FAILED
;
1533 /* Write to flash buffer */
1534 cfi_intel_clear_status_register(bank
);
1536 /* Initiate buffer operation _*/
1537 cfi_command(bank
, 0xE8, command
);
1538 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1539 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1541 cfi_command(bank
, 0xff, command
);
1542 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1544 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1545 return ERROR_FLASH_OPERATION_FAILED
;
1548 /* Write buffer wordcount-1 and data words */
1549 cfi_command(bank
, bufferwsize
-1, command
);
1550 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1552 target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
);
1554 /* Commit write operation */
1555 cfi_command(bank
, 0xd0, command
);
1556 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1557 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1559 cfi_command(bank
, 0xff, command
);
1560 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1562 ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1563 return ERROR_FLASH_OPERATION_FAILED
;
1569 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1571 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1572 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1573 target_t
*target
= bank
->target
;
1576 cfi_command(bank
, 0xaa, command
);
1577 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1579 cfi_command(bank
, 0x55, command
);
1580 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
1582 cfi_command(bank
, 0xa0, command
);
1583 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1585 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1587 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1589 cfi_command(bank
, 0xf0, command
);
1590 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1592 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1593 return ERROR_FLASH_OPERATION_FAILED
;
1599 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1601 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1603 switch(cfi_info
->pri_id
)
1607 return cfi_intel_write_word(bank
, word
, address
);
1610 return cfi_spansion_write_word(bank
, word
, address
);
1613 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1617 return ERROR_FLASH_OPERATION_FAILED
;
1620 int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1622 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1624 switch(cfi_info
->pri_id
)
1628 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1631 /* return cfi_spansion_write_words(bank, word, address); */
1632 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info
->pri_id
);
1635 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1639 return ERROR_FLASH_OPERATION_FAILED
;
1642 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1644 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1645 target_t
*target
= bank
->target
;
1646 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1647 u32 write_p
, copy_p
;
1648 int align
; /* number of unaligned bytes */
1649 int blk_count
; /* number of bus_width bytes for block copy */
1650 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1654 if (bank
->target
->state
!= TARGET_HALTED
)
1655 return ERROR_TARGET_NOT_HALTED
;
1657 if (offset
+ count
> bank
->size
)
1658 return ERROR_FLASH_DST_OUT_OF_BANK
;
1660 if (cfi_info
->qry
[0] != 'Q')
1661 return ERROR_FLASH_BANK_NOT_PROBED
;
1663 /* start at the first byte of the first word (bus_width size) */
1664 write_p
= address
& ~(bank
->bus_width
- 1);
1665 if ((align
= address
- write_p
) != 0)
1667 INFO("Fixup %d unaligned head bytes", align
);
1669 for (i
= 0; i
< bank
->bus_width
; i
++)
1670 current_word
[i
] = 0;
1673 /* copy bytes before the first write address */
1674 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1677 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1678 cfi_add_byte(bank
, current_word
, byte
);
1681 /* add bytes from the buffer */
1682 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1684 cfi_add_byte(bank
, current_word
, *buffer
++);
1689 /* if the buffer is already finished, copy bytes after the last write address */
1690 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1693 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1694 cfi_add_byte(bank
, current_word
, byte
);
1697 retval
= cfi_write_word(bank
, current_word
, write_p
);
1698 if (retval
!= ERROR_OK
)
1703 /* handle blocks of bus_size aligned bytes */
1704 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1705 switch(cfi_info
->pri_id
)
1707 /* try block writes (fails without working area) */
1710 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1713 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1716 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1717 retval
= ERROR_FLASH_OPERATION_FAILED
;
1720 if (retval
== ERROR_OK
)
1722 /* Increment pointers and decrease count on succesful block write */
1723 buffer
+= blk_count
;
1724 write_p
+= blk_count
;
1729 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1731 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1732 u32 buffermask
= buffersize
-1;
1735 switch(bank
->chip_width
)
1737 case 4 : bufferwsize
= buffersize
/ 4; break;
1738 case 2 : bufferwsize
= buffersize
/ 2; break;
1739 case 1 : bufferwsize
= buffersize
; break;
1741 ERROR("Unsupported chip width %d", bank
->chip_width
);
1742 return ERROR_FLASH_OPERATION_FAILED
;
1745 /* fall back to memory writes */
1746 while (count
> bank
->bus_width
)
1748 if ((write_p
& 0xff) == 0)
1750 INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1753 /* NB! this is broken for spansion! */
1754 if ((count
> bufferwsize
) && !(write_p
& buffermask
))
1756 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1757 if (retval
!= ERROR_OK
)
1760 buffer
+= buffersize
;
1761 write_p
+= buffersize
;
1762 count
-= buffersize
;
1767 for (i
= 0; i
< bank
->bus_width
; i
++)
1768 current_word
[i
] = 0;
1770 for (i
= 0; i
< bank
->bus_width
; i
++)
1772 cfi_add_byte(bank
, current_word
, *buffer
++);
1775 retval
= cfi_write_word(bank
, current_word
, write_p
);
1776 if (retval
!= ERROR_OK
)
1779 write_p
+= bank
->bus_width
;
1780 count
-= bank
->bus_width
;
1788 /* return to read array mode, so we can read from flash again for padding */
1789 cfi_command(bank
, 0xf0, current_word
);
1790 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1791 cfi_command(bank
, 0xff, current_word
);
1792 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1794 /* handle unaligned tail bytes */
1797 INFO("Fixup %d unaligned tail bytes", count
);
1800 for (i
= 0; i
< bank
->bus_width
; i
++)
1801 current_word
[i
] = 0;
1803 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1805 cfi_add_byte(bank
, current_word
, *buffer
++);
1808 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1811 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1812 cfi_add_byte(bank
, current_word
, byte
);
1814 retval
= cfi_write_word(bank
, current_word
, write_p
);
1815 if (retval
!= ERROR_OK
)
1819 /* return to read array mode */
1820 cfi_command(bank
, 0xf0, current_word
);
1821 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1822 cfi_command(bank
, 0xff, current_word
);
1823 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1828 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
1830 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1831 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1833 pri_ext
->_reversed_geometry
= 1;
1836 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
1839 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1840 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1842 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
1844 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1846 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
1848 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
1851 swap
= cfi_info
->erase_region_info
[i
];
1852 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
1853 cfi_info
->erase_region_info
[j
] = swap
;
1858 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
1860 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1861 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1862 cfi_unlock_addresses_t
*unlock_addresses
= param
;
1864 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
1865 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
1868 int cfi_probe(struct flash_bank_s
*bank
)
1870 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1871 target_t
*target
= bank
->target
;
1873 int num_sectors
= 0;
1877 u32 unlock1
= 0x555;
1878 u32 unlock2
= 0x2aa;
1880 if (bank
->target
->state
!= TARGET_HALTED
)
1882 return ERROR_TARGET_NOT_HALTED
;
1885 cfi_info
->probed
= 0;
1887 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1888 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1890 if (cfi_info
->jedec_probe
)
1896 /* switch to read identifier codes mode ("AUTOSELECT") */
1897 cfi_command(bank
, 0xaa, command
);
1898 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1899 cfi_command(bank
, 0x55, command
);
1900 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
);
1901 cfi_command(bank
, 0x90, command
);
1902 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1904 if (bank
->chip_width
== 1)
1906 u8 manufacturer
, device_id
;
1907 target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
);
1908 target_read_u8(target
, bank
->base
+ 0x1, &device_id
);
1909 cfi_info
->manufacturer
= manufacturer
;
1910 cfi_info
->device_id
= device_id
;
1912 else if (bank
->chip_width
== 2)
1914 target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
);
1915 target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
);
1918 /* switch back to read array mode */
1919 cfi_command(bank
, 0xf0, command
);
1920 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1921 cfi_command(bank
, 0xff, command
);
1922 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1924 cfi_fixup(bank
, cfi_jedec_fixups
);
1926 /* query only if this is a CFI compatible flash,
1927 * otherwise the relevant info has already been filled in
1929 if (cfi_info
->not_cfi
== 0)
1931 /* enter CFI query mode
1932 * according to JEDEC Standard No. 68.01,
1933 * a single bus sequence with address = 0x55, data = 0x98 should put
1934 * the device into CFI query mode.
1936 * SST flashes clearly violate this, and we will consider them incompatbile for now
1938 cfi_command(bank
, 0x98, command
);
1939 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1941 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
1942 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
1943 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
1945 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
1947 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
1949 cfi_command(bank
, 0xf0, command
);
1950 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1951 cfi_command(bank
, 0xff, command
);
1952 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1953 return ERROR_FLASH_BANK_INVALID
;
1956 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
1957 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
1958 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
1959 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
1961 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
1963 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
1964 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
1965 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
1966 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
1967 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
1968 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
1969 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
1970 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
1971 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
1972 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
1973 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
1974 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
1976 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1977 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
1978 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
1979 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
1980 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
1981 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
1982 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
1983 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
1984 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
1985 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
1986 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
1988 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
1989 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
1990 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
1991 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
1993 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
1995 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
1997 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
2000 if (cfi_info
->num_erase_regions
)
2002 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2003 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2005 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2006 DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2011 cfi_info
->erase_region_info
= NULL
;
2014 /* We need to read the primary algorithm extended query table before calculating
2015 * the sector layout to be able to apply fixups
2017 switch(cfi_info
->pri_id
)
2019 /* Intel command set (standard and extended) */
2022 cfi_read_intel_pri_ext(bank
);
2024 /* AMD/Spansion, Atmel, ... command set */
2026 cfi_read_0002_pri_ext(bank
);
2029 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2033 /* return to read array mode
2034 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2036 cfi_command(bank
, 0xf0, command
);
2037 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2038 cfi_command(bank
, 0xff, command
);
2039 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2042 /* apply fixups depending on the primary command set */
2043 switch(cfi_info
->pri_id
)
2045 /* Intel command set (standard and extended) */
2048 cfi_fixup(bank
, cfi_0001_fixups
);
2050 /* AMD/Spansion, Atmel, ... command set */
2052 cfi_fixup(bank
, cfi_0002_fixups
);
2055 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2059 if (cfi_info
->num_erase_regions
== 0)
2061 /* a device might have only one erase block, spanning the whole device */
2062 bank
->num_sectors
= 1;
2063 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2065 bank
->sectors
[sector
].offset
= 0x0;
2066 bank
->sectors
[sector
].size
= bank
->size
;
2067 bank
->sectors
[sector
].is_erased
= -1;
2068 bank
->sectors
[sector
].is_protected
= -1;
2072 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2074 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2077 bank
->num_sectors
= num_sectors
;
2078 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2080 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2083 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2085 bank
->sectors
[sector
].offset
= offset
;
2086 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2087 offset
+= bank
->sectors
[sector
].size
;
2088 bank
->sectors
[sector
].is_erased
= -1;
2089 bank
->sectors
[sector
].is_protected
= -1;
2095 cfi_info
->probed
= 1;
2100 int cfi_auto_probe(struct flash_bank_s
*bank
)
2102 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2103 if (cfi_info
->probed
)
2105 return cfi_probe(bank
);
2108 int cfi_erase_check(struct flash_bank_s
*bank
)
2110 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2111 target_t
*target
= bank
->target
;
2115 if (bank
->target
->state
!= TARGET_HALTED
)
2117 return ERROR_TARGET_NOT_HALTED
;
2120 if (!cfi_info
->erase_check_algorithm
)
2122 u32 erase_check_code
[] =
2124 0xe4d03001, /* ldrb r3, [r0], #1 */
2125 0xe0022003, /* and r2, r2, r3 */
2126 0xe2511001, /* subs r1, r1, #1 */
2127 0x1afffffb, /* b -4 */
2128 0xeafffffe /* b 0 */
2131 /* make sure we have a working area */
2132 if (target_alloc_working_area(target
, 20, &cfi_info
->erase_check_algorithm
) != ERROR_OK
)
2134 WARNING("no working area available, falling back to slow memory reads");
2138 u8 erase_check_code_buf
[5 * 4];
2140 for (i
= 0; i
< 5; i
++)
2141 target_buffer_set_u32(target
, erase_check_code_buf
+ (i
*4), erase_check_code
[i
]);
2143 /* write algorithm code to working area */
2144 target
->type
->write_memory(target
, cfi_info
->erase_check_algorithm
->address
, 4, 5, erase_check_code_buf
);
2148 if (!cfi_info
->erase_check_algorithm
)
2150 u32
*buffer
= malloc(4096);
2152 for (i
= 0; i
< bank
->num_sectors
; i
++)
2154 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2155 u32 size
= bank
->sectors
[i
].size
;
2156 u32 check
= 0xffffffffU
;
2161 u32 thisrun_size
= (size
> 4096) ? 4096 : size
;
2164 target
->type
->read_memory(target
, address
, 4, thisrun_size
/ 4, (u8
*)buffer
);
2166 for (j
= 0; j
< thisrun_size
/ 4; j
++)
2169 if (check
!= 0xffffffff)
2175 size
-= thisrun_size
;
2176 address
+= thisrun_size
;
2179 bank
->sectors
[i
].is_erased
= erased
;
2186 for (i
= 0; i
< bank
->num_sectors
; i
++)
2188 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2189 u32 size
= bank
->sectors
[i
].size
;
2191 reg_param_t reg_params
[3];
2192 armv4_5_algorithm_t armv4_5_info
;
2194 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2195 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2196 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2198 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2199 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2201 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2202 buf_set_u32(reg_params
[1].value
, 0, 32, size
);
2204 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2205 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2207 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, cfi_info
->erase_check_algorithm
->address
, cfi_info
->erase_check_algorithm
->address
+ 0x10, 10000, &armv4_5_info
)) != ERROR_OK
)
2208 return ERROR_FLASH_OPERATION_FAILED
;
2210 if (buf_get_u32(reg_params
[2].value
, 0, 32) == 0xff)
2211 bank
->sectors
[i
].is_erased
= 1;
2213 bank
->sectors
[i
].is_erased
= 0;
2215 destroy_reg_param(®_params
[0]);
2216 destroy_reg_param(®_params
[1]);
2217 destroy_reg_param(®_params
[2]);
2224 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2226 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2227 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2228 target_t
*target
= bank
->target
;
2229 u8 command
[CFI_MAX_BUS_WIDTH
];
2232 /* check if block lock bits are supported on this device */
2233 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2234 return ERROR_FLASH_OPERATION_FAILED
;
2236 cfi_command(bank
, 0x90, command
);
2237 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
2239 for (i
= 0; i
< bank
->num_sectors
; i
++)
2241 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2243 if (block_status
& 1)
2244 bank
->sectors
[i
].is_protected
= 1;
2246 bank
->sectors
[i
].is_protected
= 0;
2249 cfi_command(bank
, 0xff, command
);
2250 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2255 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2257 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2258 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2259 target_t
*target
= bank
->target
;
2263 cfi_command(bank
, 0xaa, command
);
2264 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2266 cfi_command(bank
, 0x55, command
);
2267 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
2269 cfi_command(bank
, 0x90, command
);
2270 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2272 for (i
= 0; i
< bank
->num_sectors
; i
++)
2274 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2276 if (block_status
& 1)
2277 bank
->sectors
[i
].is_protected
= 1;
2279 bank
->sectors
[i
].is_protected
= 0;
2282 cfi_command(bank
, 0xf0, command
);
2283 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2288 int cfi_protect_check(struct flash_bank_s
*bank
)
2290 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2292 if (bank
->target
->state
!= TARGET_HALTED
)
2294 return ERROR_TARGET_NOT_HALTED
;
2297 if (cfi_info
->qry
[0] != 'Q')
2298 return ERROR_FLASH_BANK_NOT_PROBED
;
2300 switch(cfi_info
->pri_id
)
2304 return cfi_intel_protect_check(bank
);
2307 return cfi_spansion_protect_check(bank
);
2310 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2317 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2320 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2322 if (cfi_info
->qry
[0] == (char)-1)
2324 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2328 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2330 buf_size
-= printed
;
2332 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2333 cfi_info
->manufacturer
, cfi_info
->device_id
);
2335 buf_size
-= printed
;
2337 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2339 buf_size
-= printed
;
2341 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2342 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2343 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2344 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2346 buf_size
-= printed
;
2348 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2349 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2351 buf_size
-= printed
;
2353 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2354 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2355 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2356 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2358 buf_size
-= printed
;
2360 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, cfi_info
->max_buf_write_size
);
2362 buf_size
-= printed
;
2364 switch(cfi_info
->pri_id
)
2368 cfi_intel_info(bank
, buf
, buf_size
);
2371 cfi_spansion_info(bank
, buf
, buf_size
);
2374 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
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