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deb9cfe0c7da5a7dd9666576190141e32b5051f6
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28
29 #include "flash.h"
30 #include "target.h"
31 #include "log.h"
32 #include "armv4_5.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
35 #include "types.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39 #include <unistd.h>
40
41 int cfi_register_commands(struct command_context_s *cmd_ctx);
42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int cfi_probe(struct flash_bank_s *bank);
47 int cfi_auto_probe(struct flash_bank_s *bank);
48 int cfi_protect_check(struct flash_bank_s *bank);
49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
55
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
58
59 flash_driver_t cfi_flash =
60 {
61 .name = "cfi",
62 .register_commands = cfi_register_commands,
63 .flash_bank_command = cfi_flash_bank_command,
64 .erase = cfi_erase,
65 .protect = cfi_protect,
66 .write = cfi_write,
67 .probe = cfi_probe,
68 .auto_probe = cfi_auto_probe,
69 .erase_check = default_flash_blank_check,
70 .protect_check = cfi_protect_check,
71 .info = cfi_info
72 };
73
74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
75 {
76 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
77 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
78 };
79
80 /* CFI fixups foward declarations */
81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
84
85 /* fixup after identifying JEDEC manufactuer and ID */
86 cfi_fixup_t cfi_jedec_fixups[] = {
87 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
88 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
94 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
95 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
96 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
97 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_non_cfi, NULL},
98 {CFI_MFR_MX, 0x225b, cfi_fixup_non_cfi, NULL},
99 {CFI_MFR_AMD, 0x225b, cfi_fixup_non_cfi, NULL},
100 {0, 0, NULL, NULL}
101 };
102
103 /* fixup after reading cmdset 0002 primary query table */
104 cfi_fixup_t cfi_0002_fixups[] = {
105 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
106 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
107 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
108 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
109 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
110 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
111 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
112 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
113 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
114 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
115 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
116 {0, 0, NULL, NULL}
117 };
118
119 /* fixup after reading cmdset 0001 primary query table */
120 cfi_fixup_t cfi_0001_fixups[] = {
121 {0, 0, NULL, NULL}
122 };
123
124 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
125 {
126 cfi_flash_bank_t *cfi_info = bank->driver_priv;
127 cfi_fixup_t *f;
128
129 for (f = fixups; f->fixup; f++)
130 {
131 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
132 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
133 {
134 f->fixup(bank, f->param);
135 }
136 }
137 }
138
139 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
140 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
141 {
142 /* while the sector list isn't built, only accesses to sector 0 work */
143 if (sector == 0)
144 return bank->base + offset * bank->bus_width;
145 else
146 {
147 if (!bank->sectors)
148 {
149 LOG_ERROR("BUG: sector list not yet built");
150 exit(-1);
151 }
152 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
153 }
154
155 }
156
157 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
158 {
159 int i;
160
161 /* clear whole buffer, to ensure bits that exceed the bus_width
162 * are set to zero
163 */
164 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
165 cmd_buf[i] = 0;
166
167 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
168 {
169 for (i = bank->bus_width; i > 0; i--)
170 {
171 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
172 }
173 }
174 else
175 {
176 for (i = 1; i <= bank->bus_width; i++)
177 {
178 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
179 }
180 }
181 }
182
183 /* read unsigned 8-bit value from the bank
184 * flash banks are expected to be made of similar chips
185 * the query result should be the same for all
186 */
187 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
188 {
189 target_t *target = bank->target;
190 u8 data[CFI_MAX_BUS_WIDTH];
191
192 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
193
194 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
195 return data[0];
196 else
197 return data[bank->bus_width - 1];
198 }
199
200 /* read unsigned 8-bit value from the bank
201 * in case of a bank made of multiple chips,
202 * the individual values are ORed
203 */
204 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
205 {
206 target_t *target = bank->target;
207 u8 data[CFI_MAX_BUS_WIDTH];
208 int i;
209
210 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
211
212 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
213 {
214 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
215 data[0] |= data[i];
216
217 return data[0];
218 }
219 else
220 {
221 u8 value = 0;
222 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
223 value |= data[bank->bus_width - 1 - i];
224
225 return value;
226 }
227 }
228
229 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
230 {
231 target_t *target = bank->target;
232 u8 data[CFI_MAX_BUS_WIDTH * 2];
233
234 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
235
236 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
237 return data[0] | data[bank->bus_width] << 8;
238 else
239 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
240 }
241
242 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
243 {
244 target_t *target = bank->target;
245 u8 data[CFI_MAX_BUS_WIDTH * 4];
246
247 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
248
249 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
250 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
251 else
252 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
253 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
254 }
255
256 void cfi_intel_clear_status_register(flash_bank_t *bank)
257 {
258 target_t *target = bank->target;
259 u8 command[8];
260
261 if (target->state != TARGET_HALTED)
262 {
263 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
264 exit(-1);
265 }
266
267 cfi_command(bank, 0x50, command);
268 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
269 }
270
271 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
272 {
273 u8 status;
274
275 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
276 {
277 LOG_DEBUG("status: 0x%x", status);
278 alive_sleep(1);
279 }
280
281 /* mask out bit 0 (reserved) */
282 status = status & 0xfe;
283
284 LOG_DEBUG("status: 0x%x", status);
285
286 if ((status & 0x80) != 0x80)
287 {
288 LOG_ERROR("timeout while waiting for WSM to become ready");
289 }
290 else if (status != 0x80)
291 {
292 LOG_ERROR("status register: 0x%x", status);
293 if (status & 0x2)
294 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
295 if (status & 0x4)
296 LOG_ERROR("Program suspended");
297 if (status & 0x8)
298 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
299 if (status & 0x10)
300 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
301 if (status & 0x20)
302 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
303 if (status & 0x40)
304 LOG_ERROR("Block Erase Suspended");
305
306 cfi_intel_clear_status_register(bank);
307 }
308
309 return status;
310 }
311
312 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
313 {
314 u8 status, oldstatus;
315
316 oldstatus = cfi_get_u8(bank, 0, 0x0);
317
318 do {
319 status = cfi_get_u8(bank, 0, 0x0);
320 if ((status ^ oldstatus) & 0x40) {
321 if (status & 0x20) {
322 oldstatus = cfi_get_u8(bank, 0, 0x0);
323 status = cfi_get_u8(bank, 0, 0x0);
324 if ((status ^ oldstatus) & 0x40) {
325 LOG_ERROR("dq5 timeout, status: 0x%x", status);
326 return(ERROR_FLASH_OPERATION_FAILED);
327 } else {
328 LOG_DEBUG("status: 0x%x", status);
329 return(ERROR_OK);
330 }
331 }
332 } else {
333 LOG_DEBUG("status: 0x%x", status);
334 return(ERROR_OK);
335 }
336
337 oldstatus = status;
338 alive_sleep(1);
339 } while (timeout-- > 0);
340
341 LOG_ERROR("timeout, status: 0x%x", status);
342
343 return(ERROR_FLASH_BUSY);
344 }
345
346 int cfi_read_intel_pri_ext(flash_bank_t *bank)
347 {
348 int retval;
349 cfi_flash_bank_t *cfi_info = bank->driver_priv;
350 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
351 target_t *target = bank->target;
352 u8 command[8];
353
354 cfi_info->pri_ext = pri_ext;
355
356 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
357 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
358 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
359
360 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
361 {
362 cfi_command(bank, 0xf0, command);
363 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
364 {
365 return retval;
366 }
367 cfi_command(bank, 0xff, command);
368 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
369 {
370 return retval;
371 }
372 LOG_ERROR("Could not read bank flash bank information");
373 return ERROR_FLASH_BANK_INVALID;
374 }
375
376 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
377 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
378
379 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
380
381 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
382 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
383 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
384
385 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
386
387 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
388 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
389
390 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
391 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
392 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
393
394 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
395 if (pri_ext->num_protection_fields != 1)
396 {
397 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
398 }
399
400 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
401 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
402 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
403
404 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
405
406 return ERROR_OK;
407 }
408
409 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
410 {
411 int retval;
412 cfi_flash_bank_t *cfi_info = bank->driver_priv;
413 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
414 target_t *target = bank->target;
415 u8 command[8];
416
417 cfi_info->pri_ext = pri_ext;
418
419 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
420 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
421 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
422
423 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
424 {
425 cfi_command(bank, 0xf0, command);
426 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
427 {
428 return retval;
429 }
430 LOG_ERROR("Could not read spansion bank information");
431 return ERROR_FLASH_BANK_INVALID;
432 }
433
434 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
435 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
436
437 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
438
439 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
440 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
441 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
442 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
443 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
444 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
445 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
446 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
447 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
448 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
449 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
450
451 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
452 pri_ext->EraseSuspend, pri_ext->BlkProt);
453
454 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
455 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
456
457 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
458
459
460 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
461 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
462 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
463
464 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
465
466 /* default values for implementation specific workarounds */
467 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
468 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
469 pri_ext->_reversed_geometry = 0;
470
471 return ERROR_OK;
472 }
473
474 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
475 {
476 int retval;
477 cfi_atmel_pri_ext_t atmel_pri_ext;
478 cfi_flash_bank_t *cfi_info = bank->driver_priv;
479 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
480 target_t *target = bank->target;
481 u8 command[8];
482
483 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
484 * but a different primary extended query table.
485 * We read the atmel table, and prepare a valid AMD/Spansion query table.
486 */
487
488 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
489
490 cfi_info->pri_ext = pri_ext;
491
492 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
493 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
494 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
495
496 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
497 {
498 cfi_command(bank, 0xf0, command);
499 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
500 {
501 return retval;
502 }
503 LOG_ERROR("Could not read atmel bank information");
504 return ERROR_FLASH_BANK_INVALID;
505 }
506
507 pri_ext->pri[0] = atmel_pri_ext.pri[0];
508 pri_ext->pri[1] = atmel_pri_ext.pri[1];
509 pri_ext->pri[2] = atmel_pri_ext.pri[2];
510
511 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
512 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
513
514 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
515
516 pri_ext->major_version = atmel_pri_ext.major_version;
517 pri_ext->minor_version = atmel_pri_ext.minor_version;
518
519 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
520 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
521 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
522 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
523
524 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
525 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
526
527 if (atmel_pri_ext.features & 0x02)
528 pri_ext->EraseSuspend = 2;
529
530 if (atmel_pri_ext.bottom_boot)
531 pri_ext->TopBottom = 2;
532 else
533 pri_ext->TopBottom = 3;
534
535 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
536 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
537
538 return ERROR_OK;
539 }
540
541 int cfi_read_0002_pri_ext(flash_bank_t *bank)
542 {
543 cfi_flash_bank_t *cfi_info = bank->driver_priv;
544
545 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
546 {
547 return cfi_read_atmel_pri_ext(bank);
548 }
549 else
550 {
551 return cfi_read_spansion_pri_ext(bank);
552 }
553 }
554
555 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
556 {
557 int printed;
558 cfi_flash_bank_t *cfi_info = bank->driver_priv;
559 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
560
561 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
562 buf += printed;
563 buf_size -= printed;
564
565 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
566 pri_ext->pri[1], pri_ext->pri[2],
567 pri_ext->major_version, pri_ext->minor_version);
568 buf += printed;
569 buf_size -= printed;
570
571 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
572 (pri_ext->SiliconRevision) >> 2,
573 (pri_ext->SiliconRevision) & 0x03);
574 buf += printed;
575 buf_size -= printed;
576
577 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
578 pri_ext->EraseSuspend,
579 pri_ext->BlkProt);
580 buf += printed;
581 buf_size -= printed;
582
583 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
584 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
585 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
586
587 return ERROR_OK;
588 }
589
590 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
591 {
592 int printed;
593 cfi_flash_bank_t *cfi_info = bank->driver_priv;
594 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
595
596 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
597 buf += printed;
598 buf_size -= printed;
599
600 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
601 buf += printed;
602 buf_size -= printed;
603
604 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
605 buf += printed;
606 buf_size -= printed;
607
608 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
609 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
610 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
611 buf += printed;
612 buf_size -= printed;
613
614 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
615
616 return ERROR_OK;
617 }
618
619 int cfi_register_commands(struct command_context_s *cmd_ctx)
620 {
621 /*command_t *cfi_cmd = */
622 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
623 /*
624 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
625 "print part id of cfi flash bank <num>");
626 */
627 return ERROR_OK;
628 }
629
630 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
631 */
632 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
633 {
634 cfi_flash_bank_t *cfi_info;
635 int i;
636
637 if (argc < 6)
638 {
639 LOG_WARNING("incomplete flash_bank cfi configuration");
640 return ERROR_FLASH_BANK_INVALID;
641 }
642
643 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
644 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
645 {
646 LOG_ERROR("chip and bus width have to specified in bytes");
647 return ERROR_FLASH_BANK_INVALID;
648 }
649
650 cfi_info = malloc(sizeof(cfi_flash_bank_t));
651 cfi_info->probed = 0;
652 bank->driver_priv = cfi_info;
653
654 cfi_info->write_algorithm = NULL;
655
656 cfi_info->x16_as_x8 = 0;
657 cfi_info->jedec_probe = 0;
658 cfi_info->not_cfi = 0;
659
660 for (i = 6; i < argc; i++)
661 {
662 if (strcmp(args[i], "x16_as_x8") == 0)
663 {
664 cfi_info->x16_as_x8 = 1;
665 }
666 else if (strcmp(args[i], "jedec_probe") == 0)
667 {
668 cfi_info->jedec_probe = 1;
669 }
670 }
671
672 cfi_info->write_algorithm = NULL;
673
674 /* bank wasn't probed yet */
675 cfi_info->qry[0] = -1;
676
677 return ERROR_OK;
678 }
679
680 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
681 {
682 int retval;
683 cfi_flash_bank_t *cfi_info = bank->driver_priv;
684 target_t *target = bank->target;
685 u8 command[8];
686 int i;
687
688 cfi_intel_clear_status_register(bank);
689
690 for (i = first; i <= last; i++)
691 {
692 cfi_command(bank, 0x20, command);
693 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
694 {
695 return retval;
696 }
697
698 cfi_command(bank, 0xd0, command);
699 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
700 {
701 return retval;
702 }
703
704 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
705 bank->sectors[i].is_erased = 1;
706 else
707 {
708 cfi_command(bank, 0xff, command);
709 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
710 {
711 return retval;
712 }
713
714 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
715 return ERROR_FLASH_OPERATION_FAILED;
716 }
717 }
718
719 cfi_command(bank, 0xff, command);
720 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
721
722 }
723
724 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
725 {
726 int retval;
727 cfi_flash_bank_t *cfi_info = bank->driver_priv;
728 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
729 target_t *target = bank->target;
730 u8 command[8];
731 int i;
732
733 for (i = first; i <= last; i++)
734 {
735 cfi_command(bank, 0xaa, command);
736 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
737 {
738 return retval;
739 }
740
741 cfi_command(bank, 0x55, command);
742 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
743 {
744 return retval;
745 }
746
747 cfi_command(bank, 0x80, command);
748 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
749 {
750 return retval;
751 }
752
753 cfi_command(bank, 0xaa, command);
754 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
755 {
756 return retval;
757 }
758
759 cfi_command(bank, 0x55, command);
760 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
761 {
762 return retval;
763 }
764
765 cfi_command(bank, 0x30, command);
766 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
767 {
768 return retval;
769 }
770
771 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
772 bank->sectors[i].is_erased = 1;
773 else
774 {
775 cfi_command(bank, 0xf0, command);
776 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
777 {
778 return retval;
779 }
780
781 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
782 return ERROR_FLASH_OPERATION_FAILED;
783 }
784 }
785
786 cfi_command(bank, 0xf0, command);
787 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
788 }
789
790 int cfi_erase(struct flash_bank_s *bank, int first, int last)
791 {
792 cfi_flash_bank_t *cfi_info = bank->driver_priv;
793
794 if (bank->target->state != TARGET_HALTED)
795 {
796 LOG_ERROR("Target not halted");
797 return ERROR_TARGET_NOT_HALTED;
798 }
799
800 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
801 {
802 return ERROR_FLASH_SECTOR_INVALID;
803 }
804
805 if (cfi_info->qry[0] != 'Q')
806 return ERROR_FLASH_BANK_NOT_PROBED;
807
808 switch(cfi_info->pri_id)
809 {
810 case 1:
811 case 3:
812 return cfi_intel_erase(bank, first, last);
813 break;
814 case 2:
815 return cfi_spansion_erase(bank, first, last);
816 break;
817 default:
818 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
819 break;
820 }
821
822 return ERROR_OK;
823 }
824
825 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
826 {
827 int retval;
828 cfi_flash_bank_t *cfi_info = bank->driver_priv;
829 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
830 target_t *target = bank->target;
831 u8 command[8];
832 int retry = 0;
833 int i;
834
835 /* if the device supports neither legacy lock/unlock (bit 3) nor
836 * instant individual block locking (bit 5).
837 */
838 if (!(pri_ext->feature_support & 0x28))
839 return ERROR_FLASH_OPERATION_FAILED;
840
841 cfi_intel_clear_status_register(bank);
842
843 for (i = first; i <= last; i++)
844 {
845 cfi_command(bank, 0x60, command);
846 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
847 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
848 {
849 return retval;
850 }
851 if (set)
852 {
853 cfi_command(bank, 0x01, command);
854 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
855 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
856 {
857 return retval;
858 }
859 bank->sectors[i].is_protected = 1;
860 }
861 else
862 {
863 cfi_command(bank, 0xd0, command);
864 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
865 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
866 {
867 return retval;
868 }
869 bank->sectors[i].is_protected = 0;
870 }
871
872 /* instant individual block locking doesn't require reading of the status register */
873 if (!(pri_ext->feature_support & 0x20))
874 {
875 /* Clear lock bits operation may take up to 1.4s */
876 cfi_intel_wait_status_busy(bank, 1400);
877 }
878 else
879 {
880 u8 block_status;
881 /* read block lock bit, to verify status */
882 cfi_command(bank, 0x90, command);
883 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
884 {
885 return retval;
886 }
887 block_status = cfi_get_u8(bank, i, 0x2);
888
889 if ((block_status & 0x1) != set)
890 {
891 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
892 cfi_command(bank, 0x70, command);
893 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
894 {
895 return retval;
896 }
897 cfi_intel_wait_status_busy(bank, 10);
898
899 if (retry > 10)
900 return ERROR_FLASH_OPERATION_FAILED;
901 else
902 {
903 i--;
904 retry++;
905 }
906 }
907 }
908 }
909
910 /* if the device doesn't support individual block lock bits set/clear,
911 * all blocks have been unlocked in parallel, so we set those that should be protected
912 */
913 if ((!set) && (!(pri_ext->feature_support & 0x20)))
914 {
915 for (i = 0; i < bank->num_sectors; i++)
916 {
917 if (bank->sectors[i].is_protected == 1)
918 {
919 cfi_intel_clear_status_register(bank);
920
921 cfi_command(bank, 0x60, command);
922 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
923 {
924 return retval;
925 }
926
927 cfi_command(bank, 0x01, command);
928 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
929 {
930 return retval;
931 }
932
933 cfi_intel_wait_status_busy(bank, 100);
934 }
935 }
936 }
937
938 cfi_command(bank, 0xff, command);
939 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
940 }
941
942 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
943 {
944 cfi_flash_bank_t *cfi_info = bank->driver_priv;
945
946 if (bank->target->state != TARGET_HALTED)
947 {
948 LOG_ERROR("Target not halted");
949 return ERROR_TARGET_NOT_HALTED;
950 }
951
952 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
953 {
954 return ERROR_FLASH_SECTOR_INVALID;
955 }
956
957 if (cfi_info->qry[0] != 'Q')
958 return ERROR_FLASH_BANK_NOT_PROBED;
959
960 switch(cfi_info->pri_id)
961 {
962 case 1:
963 case 3:
964 cfi_intel_protect(bank, set, first, last);
965 break;
966 default:
967 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
968 break;
969 }
970
971 return ERROR_OK;
972 }
973
974 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
975 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
976 {
977 /* target_t *target = bank->target; */
978
979 int i;
980
981 /* NOTE:
982 * The data to flash must not be changed in endian! We write a bytestrem in
983 * target byte order already. Only the control and status byte lane of the flash
984 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
985 * word (data seems to be in the upper or lower byte lane for u16 accesses).
986 */
987
988 #if 0
989 if (target->endianness == TARGET_LITTLE_ENDIAN)
990 {
991 #endif
992 /* shift bytes */
993 for (i = 0; i < bank->bus_width - 1; i++)
994 word[i] = word[i + 1];
995 word[bank->bus_width - 1] = byte;
996 #if 0
997 }
998 else
999 {
1000 /* shift bytes */
1001 for (i = bank->bus_width - 1; i > 0; i--)
1002 word[i] = word[i - 1];
1003 word[0] = byte;
1004 }
1005 #endif
1006 }
1007
1008 /* Convert code image to target endian */
1009 /* FIXME create general block conversion fcts in target.c?) */
1010 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
1011 {
1012 u32 i;
1013 for (i=0; i< count; i++)
1014 {
1015 target_buffer_set_u32(target, dest, *src);
1016 dest+=4;
1017 src++;
1018 }
1019 }
1020
1021 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1022 {
1023 target_t *target = bank->target;
1024
1025 u8 buf[CFI_MAX_BUS_WIDTH];
1026 cfi_command(bank, cmd, buf);
1027 switch (bank->bus_width)
1028 {
1029 case 1 :
1030 return buf[0];
1031 break;
1032 case 2 :
1033 return target_buffer_get_u16(target, buf);
1034 break;
1035 case 4 :
1036 return target_buffer_get_u32(target, buf);
1037 break;
1038 default :
1039 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1040 return 0;
1041 }
1042 }
1043
1044 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1045 {
1046 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1047 target_t *target = bank->target;
1048 reg_param_t reg_params[7];
1049 armv4_5_algorithm_t armv4_5_info;
1050 working_area_t *source;
1051 u32 buffer_size = 32768;
1052 u32 write_command_val, busy_pattern_val, error_pattern_val;
1053
1054 /* algorithm register usage:
1055 * r0: source address (in RAM)
1056 * r1: target address (in Flash)
1057 * r2: count
1058 * r3: flash write command
1059 * r4: status byte (returned to host)
1060 * r5: busy test pattern
1061 * r6: error test pattern
1062 */
1063
1064 static const u32 word_32_code[] = {
1065 0xe4904004, /* loop: ldr r4, [r0], #4 */
1066 0xe5813000, /* str r3, [r1] */
1067 0xe5814000, /* str r4, [r1] */
1068 0xe5914000, /* busy: ldr r4, [r1] */
1069 0xe0047005, /* and r7, r4, r5 */
1070 0xe1570005, /* cmp r7, r5 */
1071 0x1afffffb, /* bne busy */
1072 0xe1140006, /* tst r4, r6 */
1073 0x1a000003, /* bne done */
1074 0xe2522001, /* subs r2, r2, #1 */
1075 0x0a000001, /* beq done */
1076 0xe2811004, /* add r1, r1 #4 */
1077 0xeafffff2, /* b loop */
1078 0xeafffffe /* done: b -2 */
1079 };
1080
1081 static const u32 word_16_code[] = {
1082 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1083 0xe1c130b0, /* strh r3, [r1] */
1084 0xe1c140b0, /* strh r4, [r1] */
1085 0xe1d140b0, /* busy ldrh r4, [r1] */
1086 0xe0047005, /* and r7, r4, r5 */
1087 0xe1570005, /* cmp r7, r5 */
1088 0x1afffffb, /* bne busy */
1089 0xe1140006, /* tst r4, r6 */
1090 0x1a000003, /* bne done */
1091 0xe2522001, /* subs r2, r2, #1 */
1092 0x0a000001, /* beq done */
1093 0xe2811002, /* add r1, r1 #2 */
1094 0xeafffff2, /* b loop */
1095 0xeafffffe /* done: b -2 */
1096 };
1097
1098 static const u32 word_8_code[] = {
1099 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1100 0xe5c13000, /* strb r3, [r1] */
1101 0xe5c14000, /* strb r4, [r1] */
1102 0xe5d14000, /* busy ldrb r4, [r1] */
1103 0xe0047005, /* and r7, r4, r5 */
1104 0xe1570005, /* cmp r7, r5 */
1105 0x1afffffb, /* bne busy */
1106 0xe1140006, /* tst r4, r6 */
1107 0x1a000003, /* bne done */
1108 0xe2522001, /* subs r2, r2, #1 */
1109 0x0a000001, /* beq done */
1110 0xe2811001, /* add r1, r1 #1 */
1111 0xeafffff2, /* b loop */
1112 0xeafffffe /* done: b -2 */
1113 };
1114 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1115 const u32 *target_code_src;
1116 int target_code_size;
1117 int retval = ERROR_OK;
1118
1119
1120 cfi_intel_clear_status_register(bank);
1121
1122 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1123 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1124 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1125
1126 /* If we are setting up the write_algorith, we need target_code_src */
1127 /* if not we only need target_code_size. */
1128 /* */
1129 /* However, we don't want to create multiple code paths, so we */
1130 /* do the unecessary evaluation of target_code_src, which the */
1131 /* compiler will probably nicely optimize away if not needed */
1132
1133 /* prepare algorithm code for target endian */
1134 switch (bank->bus_width)
1135 {
1136 case 1 :
1137 target_code_src = word_8_code;
1138 target_code_size = sizeof(word_8_code);
1139 break;
1140 case 2 :
1141 target_code_src = word_16_code;
1142 target_code_size = sizeof(word_16_code);
1143 break;
1144 case 4 :
1145 target_code_src = word_32_code;
1146 target_code_size = sizeof(word_32_code);
1147 break;
1148 default:
1149 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1151 }
1152
1153 /* flash write code */
1154 if (!cfi_info->write_algorithm)
1155 {
1156 if ( target_code_size > sizeof(target_code) )
1157 {
1158 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1159 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1160 }
1161 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1162
1163 /* Get memory for block write handler */
1164 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1165 if (retval != ERROR_OK)
1166 {
1167 LOG_WARNING("No working area available, can't do block memory writes");
1168 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1169 };
1170
1171 /* write algorithm code to working area */
1172 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1173 if (retval != ERROR_OK)
1174 {
1175 LOG_ERROR("Unable to write block write code to target");
1176 goto cleanup;
1177 }
1178 }
1179
1180 /* Get a workspace buffer for the data to flash starting with 32k size.
1181 Half size until buffer would be smaller 256 Bytem then fail back */
1182 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1183 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1184 {
1185 buffer_size /= 2;
1186 if (buffer_size <= 256)
1187 {
1188 LOG_WARNING("no large enough working area available, can't do block memory writes");
1189 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1190 goto cleanup;
1191 }
1192 };
1193
1194 /* setup algo registers */
1195 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1196 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1197 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1198 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1199 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1200 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1201 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1202
1203 /* prepare command and status register patterns */
1204 write_command_val = cfi_command_val(bank, 0x40);
1205 busy_pattern_val = cfi_command_val(bank, 0x80);
1206 error_pattern_val = cfi_command_val(bank, 0x7e);
1207
1208 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1209
1210 /* Programming main loop */
1211 while (count > 0)
1212 {
1213 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1214 u32 wsm_error;
1215
1216 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1217 {
1218 goto cleanup;
1219 }
1220
1221 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1222 buf_set_u32(reg_params[1].value, 0, 32, address);
1223 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1224
1225 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1226 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1227 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1228
1229 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1230
1231 /* Execute algorithm, assume breakpoint for last instruction */
1232 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1233 cfi_info->write_algorithm->address,
1234 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1235 10000, /* 10s should be enough for max. 32k of data */
1236 &armv4_5_info);
1237
1238 /* On failure try a fall back to direct word writes */
1239 if (retval != ERROR_OK)
1240 {
1241 cfi_intel_clear_status_register(bank);
1242 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1243 retval = ERROR_FLASH_OPERATION_FAILED;
1244 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1245 /* FIXME To allow fall back or recovery, we must save the actual status
1246 somewhere, so that a higher level code can start recovery. */
1247 goto cleanup;
1248 }
1249
1250 /* Check return value from algo code */
1251 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1252 if (wsm_error)
1253 {
1254 /* read status register (outputs debug inforation) */
1255 cfi_intel_wait_status_busy(bank, 100);
1256 cfi_intel_clear_status_register(bank);
1257 retval = ERROR_FLASH_OPERATION_FAILED;
1258 goto cleanup;
1259 }
1260
1261 buffer += thisrun_count;
1262 address += thisrun_count;
1263 count -= thisrun_count;
1264 }
1265
1266 /* free up resources */
1267 cleanup:
1268 if (source)
1269 target_free_working_area(target, source);
1270
1271 if (cfi_info->write_algorithm)
1272 {
1273 target_free_working_area(target, cfi_info->write_algorithm);
1274 cfi_info->write_algorithm = NULL;
1275 }
1276
1277 destroy_reg_param(&reg_params[0]);
1278 destroy_reg_param(&reg_params[1]);
1279 destroy_reg_param(&reg_params[2]);
1280 destroy_reg_param(&reg_params[3]);
1281 destroy_reg_param(&reg_params[4]);
1282 destroy_reg_param(&reg_params[5]);
1283 destroy_reg_param(&reg_params[6]);
1284
1285 return retval;
1286 }
1287
1288 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1289 {
1290 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1291 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1292 target_t *target = bank->target;
1293 reg_param_t reg_params[10];
1294 armv4_5_algorithm_t armv4_5_info;
1295 working_area_t *source;
1296 u32 buffer_size = 32768;
1297 u32 status;
1298 int retval, retvaltemp;
1299 int exit_code = ERROR_OK;
1300
1301 /* input parameters - */
1302 /* R0 = source address */
1303 /* R1 = destination address */
1304 /* R2 = number of writes */
1305 /* R3 = flash write command */
1306 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1307 /* output parameters - */
1308 /* R5 = 0x80 ok 0x00 bad */
1309 /* temp registers - */
1310 /* R6 = value read from flash to test status */
1311 /* R7 = holding register */
1312 /* unlock registers - */
1313 /* R8 = unlock1_addr */
1314 /* R9 = unlock1_cmd */
1315 /* R10 = unlock2_addr */
1316 /* R11 = unlock2_cmd */
1317
1318 static const u32 word_32_code[] = {
1319 /* 00008100 <sp_32_code>: */
1320 0xe4905004, /* ldr r5, [r0], #4 */
1321 0xe5889000, /* str r9, [r8] */
1322 0xe58ab000, /* str r11, [r10] */
1323 0xe5883000, /* str r3, [r8] */
1324 0xe5815000, /* str r5, [r1] */
1325 0xe1a00000, /* nop */
1326 /* */
1327 /* 00008110 <sp_32_busy>: */
1328 0xe5916000, /* ldr r6, [r1] */
1329 0xe0257006, /* eor r7, r5, r6 */
1330 0xe0147007, /* ands r7, r4, r7 */
1331 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1332 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1333 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1334 0xe5916000, /* ldr r6, [r1] */
1335 0xe0257006, /* eor r7, r5, r6 */
1336 0xe0147007, /* ands r7, r4, r7 */
1337 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1338 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1339 0x1a000004, /* bne 8154 <sp_32_done> */
1340 /* */
1341 /* 00008140 <sp_32_cont>: */
1342 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1343 0x03a05080, /* moveq r5, #128 ; 0x80 */
1344 0x0a000001, /* beq 8154 <sp_32_done> */
1345 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1346 0xeaffffe8, /* b 8100 <sp_32_code> */
1347 /* */
1348 /* 00008154 <sp_32_done>: */
1349 0xeafffffe /* b 8154 <sp_32_done> */
1350 };
1351
1352 static const u32 word_16_code[] = {
1353 /* 00008158 <sp_16_code>: */
1354 0xe0d050b2, /* ldrh r5, [r0], #2 */
1355 0xe1c890b0, /* strh r9, [r8] */
1356 0xe1cab0b0, /* strh r11, [r10] */
1357 0xe1c830b0, /* strh r3, [r8] */
1358 0xe1c150b0, /* strh r5, [r1] */
1359 0xe1a00000, /* nop (mov r0,r0) */
1360 /* */
1361 /* 00008168 <sp_16_busy>: */
1362 0xe1d160b0, /* ldrh r6, [r1] */
1363 0xe0257006, /* eor r7, r5, r6 */
1364 0xe0147007, /* ands r7, r4, r7 */
1365 0x0a000007, /* beq 8198 <sp_16_cont> */
1366 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1367 0x0afffff9, /* beq 8168 <sp_16_busy> */
1368 0xe1d160b0, /* ldrh r6, [r1] */
1369 0xe0257006, /* eor r7, r5, r6 */
1370 0xe0147007, /* ands r7, r4, r7 */
1371 0x0a000001, /* beq 8198 <sp_16_cont> */
1372 0xe3a05000, /* mov r5, #0 ; 0x0 */
1373 0x1a000004, /* bne 81ac <sp_16_done> */
1374 /* */
1375 /* 00008198 <sp_16_cont>: */
1376 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1377 0x03a05080, /* moveq r5, #128 ; 0x80 */
1378 0x0a000001, /* beq 81ac <sp_16_done> */
1379 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1380 0xeaffffe8, /* b 8158 <sp_16_code> */
1381 /* */
1382 /* 000081ac <sp_16_done>: */
1383 0xeafffffe /* b 81ac <sp_16_done> */
1384 };
1385
1386 static const u32 word_8_code[] = {
1387 /* 000081b0 <sp_16_code_end>: */
1388 0xe4d05001, /* ldrb r5, [r0], #1 */
1389 0xe5c89000, /* strb r9, [r8] */
1390 0xe5cab000, /* strb r11, [r10] */
1391 0xe5c83000, /* strb r3, [r8] */
1392 0xe5c15000, /* strb r5, [r1] */
1393 0xe1a00000, /* nop (mov r0,r0) */
1394 /* */
1395 /* 000081c0 <sp_8_busy>: */
1396 0xe5d16000, /* ldrb r6, [r1] */
1397 0xe0257006, /* eor r7, r5, r6 */
1398 0xe0147007, /* ands r7, r4, r7 */
1399 0x0a000007, /* beq 81f0 <sp_8_cont> */
1400 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1401 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1402 0xe5d16000, /* ldrb r6, [r1] */
1403 0xe0257006, /* eor r7, r5, r6 */
1404 0xe0147007, /* ands r7, r4, r7 */
1405 0x0a000001, /* beq 81f0 <sp_8_cont> */
1406 0xe3a05000, /* mov r5, #0 ; 0x0 */
1407 0x1a000004, /* bne 8204 <sp_8_done> */
1408 /* */
1409 /* 000081f0 <sp_8_cont>: */
1410 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1411 0x03a05080, /* moveq r5, #128 ; 0x80 */
1412 0x0a000001, /* beq 8204 <sp_8_done> */
1413 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1414 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1415 /* */
1416 /* 00008204 <sp_8_done>: */
1417 0xeafffffe /* b 8204 <sp_8_done> */
1418 };
1419
1420 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1421 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1422 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1423
1424 /* flash write code */
1425 if (!cfi_info->write_algorithm)
1426 {
1427 u8 *target_code;
1428 int target_code_size;
1429 const u32 *src;
1430
1431 /* convert bus-width dependent algorithm code to correct endiannes */
1432 switch (bank->bus_width)
1433 {
1434 case 1:
1435 src = word_8_code;
1436 target_code_size = sizeof(word_8_code);
1437 break;
1438 case 2:
1439 src = word_16_code;
1440 target_code_size = sizeof(word_16_code);
1441 break;
1442 case 4:
1443 src = word_32_code;
1444 target_code_size = sizeof(word_32_code);
1445 break;
1446 default:
1447 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1448 return ERROR_FLASH_OPERATION_FAILED;
1449 }
1450 target_code = malloc(target_code_size);
1451 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1452
1453 /* allocate working area */
1454 retval=target_alloc_working_area(target, target_code_size,
1455 &cfi_info->write_algorithm);
1456 if (retval != ERROR_OK)
1457 {
1458 free(target_code);
1459 return retval;
1460 }
1461
1462 /* write algorithm code to working area */
1463 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1464 target_code_size, target_code)) != ERROR_OK)
1465 {
1466 free(target_code);
1467 return retval;
1468 }
1469
1470 free(target_code);
1471 }
1472 /* the following code still assumes target code is fixed 24*4 bytes */
1473
1474 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1475 {
1476 buffer_size /= 2;
1477 if (buffer_size <= 256)
1478 {
1479 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1480 if (cfi_info->write_algorithm)
1481 target_free_working_area(target, cfi_info->write_algorithm);
1482
1483 LOG_WARNING("not enough working area available, can't do block memory writes");
1484 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1485 }
1486 };
1487
1488 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1489 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1490 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1491 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1492 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1493 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1494 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1495 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1496 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1497 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1498
1499 while (count > 0)
1500 {
1501 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1502
1503 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1504
1505 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1506 buf_set_u32(reg_params[1].value, 0, 32, address);
1507 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1508 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1509 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1510 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1511 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1512 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1513 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1514
1515 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1516 cfi_info->write_algorithm->address,
1517 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1518 10000, &armv4_5_info);
1519
1520 status = buf_get_u32(reg_params[5].value, 0, 32);
1521
1522 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1523 {
1524 LOG_DEBUG("status: 0x%x", status);
1525 exit_code = ERROR_FLASH_OPERATION_FAILED;
1526 break;
1527 }
1528
1529 buffer += thisrun_count;
1530 address += thisrun_count;
1531 count -= thisrun_count;
1532 }
1533
1534 target_free_working_area(target, source);
1535
1536 destroy_reg_param(&reg_params[0]);
1537 destroy_reg_param(&reg_params[1]);
1538 destroy_reg_param(&reg_params[2]);
1539 destroy_reg_param(&reg_params[3]);
1540 destroy_reg_param(&reg_params[4]);
1541 destroy_reg_param(&reg_params[5]);
1542 destroy_reg_param(&reg_params[6]);
1543 destroy_reg_param(&reg_params[7]);
1544 destroy_reg_param(&reg_params[8]);
1545 destroy_reg_param(&reg_params[9]);
1546
1547 return exit_code;
1548 }
1549
1550 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1551 {
1552 int retval;
1553 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1554 target_t *target = bank->target;
1555 u8 command[8];
1556
1557 cfi_intel_clear_status_register(bank);
1558 cfi_command(bank, 0x40, command);
1559 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1560 {
1561 return retval;
1562 }
1563
1564 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1565 {
1566 return retval;
1567 }
1568
1569 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1570 {
1571 cfi_command(bank, 0xff, command);
1572 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1573 {
1574 return retval;
1575 }
1576
1577 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1578 return ERROR_FLASH_OPERATION_FAILED;
1579 }
1580
1581 return ERROR_OK;
1582 }
1583
1584 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1585 {
1586 int retval;
1587 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1588 target_t *target = bank->target;
1589 u8 command[8];
1590
1591 /* Calculate buffer size and boundary mask */
1592 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1593 u32 buffermask = buffersize-1;
1594 u32 bufferwsize;
1595
1596 /* Check for valid range */
1597 if (address & buffermask)
1598 {
1599 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1600 return ERROR_FLASH_OPERATION_FAILED;
1601 }
1602 switch(bank->chip_width)
1603 {
1604 case 4 : bufferwsize = buffersize / 4; break;
1605 case 2 : bufferwsize = buffersize / 2; break;
1606 case 1 : bufferwsize = buffersize; break;
1607 default:
1608 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1609 return ERROR_FLASH_OPERATION_FAILED;
1610 }
1611
1612 bufferwsize/=(bank->bus_width / bank->chip_width);
1613
1614
1615 /* Check for valid size */
1616 if (wordcount > bufferwsize)
1617 {
1618 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1619 return ERROR_FLASH_OPERATION_FAILED;
1620 }
1621
1622 /* Write to flash buffer */
1623 cfi_intel_clear_status_register(bank);
1624
1625 /* Initiate buffer operation _*/
1626 cfi_command(bank, 0xE8, command);
1627 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1628 {
1629 return retval;
1630 }
1631 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1632 {
1633 cfi_command(bank, 0xff, command);
1634 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1635 {
1636 return retval;
1637 }
1638
1639 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1640 return ERROR_FLASH_OPERATION_FAILED;
1641 }
1642
1643 /* Write buffer wordcount-1 and data words */
1644 cfi_command(bank, bufferwsize-1, command);
1645 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1646 {
1647 return retval;
1648 }
1649
1650 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1651 {
1652 return retval;
1653 }
1654
1655 /* Commit write operation */
1656 cfi_command(bank, 0xd0, command);
1657 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1658 {
1659 return retval;
1660 }
1661 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1662 {
1663 cfi_command(bank, 0xff, command);
1664 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1665 {
1666 return retval;
1667 }
1668
1669 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1670 return ERROR_FLASH_OPERATION_FAILED;
1671 }
1672
1673 return ERROR_OK;
1674 }
1675
1676 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1677 {
1678 int retval;
1679 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1680 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1681 target_t *target = bank->target;
1682 u8 command[8];
1683
1684 cfi_command(bank, 0xaa, command);
1685 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1686 {
1687 return retval;
1688 }
1689
1690 cfi_command(bank, 0x55, command);
1691 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1692 {
1693 return retval;
1694 }
1695
1696 cfi_command(bank, 0xa0, command);
1697 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1698 {
1699 return retval;
1700 }
1701
1702 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1703 {
1704 return retval;
1705 }
1706
1707 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1708 {
1709 cfi_command(bank, 0xf0, command);
1710 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1711 {
1712 return retval;
1713 }
1714
1715 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1716 return ERROR_FLASH_OPERATION_FAILED;
1717 }
1718
1719 return ERROR_OK;
1720 }
1721
1722 int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1723 {
1724 int retval;
1725 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1726 target_t *target = bank->target;
1727 u8 command[8];
1728 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1729
1730 /* Calculate buffer size and boundary mask */
1731 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1732 u32 buffermask = buffersize-1;
1733 u32 bufferwsize;
1734
1735 /* Check for valid range */
1736 if (address & buffermask)
1737 {
1738 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1739 return ERROR_FLASH_OPERATION_FAILED;
1740 }
1741 switch(bank->chip_width)
1742 {
1743 case 4 : bufferwsize = buffersize / 4; break;
1744 case 2 : bufferwsize = buffersize / 2; break;
1745 case 1 : bufferwsize = buffersize; break;
1746 default:
1747 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1748 return ERROR_FLASH_OPERATION_FAILED;
1749 }
1750
1751 bufferwsize/=(bank->bus_width / bank->chip_width);
1752
1753 /* Check for valid size */
1754 if (wordcount > bufferwsize)
1755 {
1756 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1757 return ERROR_FLASH_OPERATION_FAILED;
1758 }
1759
1760 // Unlock
1761 cfi_command(bank, 0xaa, command);
1762 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1763 {
1764 return retval;
1765 }
1766
1767 cfi_command(bank, 0x55, command);
1768 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1769 {
1770 return retval;
1771 }
1772
1773 // Buffer load command
1774 cfi_command(bank, 0x25, command);
1775 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1776 {
1777 return retval;
1778 }
1779
1780 /* Write buffer wordcount-1 and data words */
1781 cfi_command(bank, bufferwsize-1, command);
1782 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1783 {
1784 return retval;
1785 }
1786
1787 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1788 {
1789 return retval;
1790 }
1791
1792 /* Commit write operation */
1793 cfi_command(bank, 0x29, command);
1794 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1795 {
1796 return retval;
1797 }
1798
1799 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1800 {
1801 cfi_command(bank, 0xf0, command);
1802 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1803 {
1804 return retval;
1805 }
1806
1807 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1808 return ERROR_FLASH_OPERATION_FAILED;
1809 }
1810
1811 return ERROR_OK;
1812 }
1813
1814 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1815 {
1816 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1817
1818 switch(cfi_info->pri_id)
1819 {
1820 case 1:
1821 case 3:
1822 return cfi_intel_write_word(bank, word, address);
1823 break;
1824 case 2:
1825 return cfi_spansion_write_word(bank, word, address);
1826 break;
1827 default:
1828 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1829 break;
1830 }
1831
1832 return ERROR_FLASH_OPERATION_FAILED;
1833 }
1834
1835 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1836 {
1837 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1838
1839 switch(cfi_info->pri_id)
1840 {
1841 case 1:
1842 case 3:
1843 return cfi_intel_write_words(bank, word, wordcount, address);
1844 break;
1845 case 2:
1846 return cfi_spansion_write_words(bank, word, wordcount, address);
1847 break;
1848 default:
1849 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1850 break;
1851 }
1852
1853 return ERROR_FLASH_OPERATION_FAILED;
1854 }
1855
1856 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1857 {
1858 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1859 target_t *target = bank->target;
1860 u32 address = bank->base + offset; /* address of first byte to be programmed */
1861 u32 write_p, copy_p;
1862 int align; /* number of unaligned bytes */
1863 int blk_count; /* number of bus_width bytes for block copy */
1864 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1865 int i;
1866 int retval;
1867
1868 if (bank->target->state != TARGET_HALTED)
1869 {
1870 LOG_ERROR("Target not halted");
1871 return ERROR_TARGET_NOT_HALTED;
1872 }
1873
1874 if (offset + count > bank->size)
1875 return ERROR_FLASH_DST_OUT_OF_BANK;
1876
1877 if (cfi_info->qry[0] != 'Q')
1878 return ERROR_FLASH_BANK_NOT_PROBED;
1879
1880 /* start at the first byte of the first word (bus_width size) */
1881 write_p = address & ~(bank->bus_width - 1);
1882 if ((align = address - write_p) != 0)
1883 {
1884 LOG_INFO("Fixup %d unaligned head bytes", align );
1885
1886 for (i = 0; i < bank->bus_width; i++)
1887 current_word[i] = 0;
1888 copy_p = write_p;
1889
1890 /* copy bytes before the first write address */
1891 for (i = 0; i < align; ++i, ++copy_p)
1892 {
1893 u8 byte;
1894 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1895 {
1896 return retval;
1897 }
1898 cfi_add_byte(bank, current_word, byte);
1899 }
1900
1901 /* add bytes from the buffer */
1902 for (; (i < bank->bus_width) && (count > 0); i++)
1903 {
1904 cfi_add_byte(bank, current_word, *buffer++);
1905 count--;
1906 copy_p++;
1907 }
1908
1909 /* if the buffer is already finished, copy bytes after the last write address */
1910 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1911 {
1912 u8 byte;
1913 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1914 {
1915 return retval;
1916 }
1917 cfi_add_byte(bank, current_word, byte);
1918 }
1919
1920 retval = cfi_write_word(bank, current_word, write_p);
1921 if (retval != ERROR_OK)
1922 return retval;
1923 write_p = copy_p;
1924 }
1925
1926 /* handle blocks of bus_size aligned bytes */
1927 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1928 switch(cfi_info->pri_id)
1929 {
1930 /* try block writes (fails without working area) */
1931 case 1:
1932 case 3:
1933 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1934 break;
1935 case 2:
1936 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1937 break;
1938 default:
1939 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1940 retval = ERROR_FLASH_OPERATION_FAILED;
1941 break;
1942 }
1943 if (retval == ERROR_OK)
1944 {
1945 /* Increment pointers and decrease count on succesful block write */
1946 buffer += blk_count;
1947 write_p += blk_count;
1948 count -= blk_count;
1949 }
1950 else
1951 {
1952 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1953 {
1954 //adjust buffersize for chip width
1955 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1956 u32 buffermask = buffersize-1;
1957 u32 bufferwsize;
1958
1959 switch(bank->chip_width)
1960 {
1961 case 4 : bufferwsize = buffersize / 4; break;
1962 case 2 : bufferwsize = buffersize / 2; break;
1963 case 1 : bufferwsize = buffersize; break;
1964 default:
1965 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1966 return ERROR_FLASH_OPERATION_FAILED;
1967 }
1968
1969 bufferwsize/=(bank->bus_width / bank->chip_width);
1970
1971 /* fall back to memory writes */
1972 while (count >= bank->bus_width)
1973 {
1974 int fallback;
1975 if ((write_p & 0xff) == 0)
1976 {
1977 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1978 }
1979 fallback = 1;
1980 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1981 {
1982 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1983 if (retval == ERROR_OK)
1984 {
1985 buffer += buffersize;
1986 write_p += buffersize;
1987 count -= buffersize;
1988 fallback=0;
1989 }
1990 }
1991 /* try the slow way? */
1992 if (fallback)
1993 {
1994 for (i = 0; i < bank->bus_width; i++)
1995 current_word[i] = 0;
1996
1997 for (i = 0; i < bank->bus_width; i++)
1998 {
1999 cfi_add_byte(bank, current_word, *buffer++);
2000 }
2001
2002 retval = cfi_write_word(bank, current_word, write_p);
2003 if (retval != ERROR_OK)
2004 return retval;
2005
2006 write_p += bank->bus_width;
2007 count -= bank->bus_width;
2008 }
2009 }
2010 }
2011 else
2012 return retval;
2013 }
2014
2015 /* return to read array mode, so we can read from flash again for padding */
2016 cfi_command(bank, 0xf0, current_word);
2017 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2018 {
2019 return retval;
2020 }
2021 cfi_command(bank, 0xff, current_word);
2022 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2023 {
2024 return retval;
2025 }
2026
2027 /* handle unaligned tail bytes */
2028 if (count > 0)
2029 {
2030 LOG_INFO("Fixup %d unaligned tail bytes", count );
2031
2032 copy_p = write_p;
2033 for (i = 0; i < bank->bus_width; i++)
2034 current_word[i] = 0;
2035
2036 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2037 {
2038 cfi_add_byte(bank, current_word, *buffer++);
2039 count--;
2040 }
2041 for (; i < bank->bus_width; ++i, ++copy_p)
2042 {
2043 u8 byte;
2044 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2045 {
2046 return retval;
2047 }
2048 cfi_add_byte(bank, current_word, byte);
2049 }
2050 retval = cfi_write_word(bank, current_word, write_p);
2051 if (retval != ERROR_OK)
2052 return retval;
2053 }
2054
2055 /* return to read array mode */
2056 cfi_command(bank, 0xf0, current_word);
2057 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2058 {
2059 return retval;
2060 }
2061 cfi_command(bank, 0xff, current_word);
2062 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2063 }
2064
2065 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2066 {
2067 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2068 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2069
2070 pri_ext->_reversed_geometry = 1;
2071 }
2072
2073 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2074 {
2075 int i;
2076 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2077 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2078
2079 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2080 {
2081 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2082
2083 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2084 {
2085 int j = (cfi_info->num_erase_regions - 1) - i;
2086 u32 swap;
2087
2088 swap = cfi_info->erase_region_info[i];
2089 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2090 cfi_info->erase_region_info[j] = swap;
2091 }
2092 }
2093 }
2094
2095 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2096 {
2097 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2098 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2099 cfi_unlock_addresses_t *unlock_addresses = param;
2100
2101 pri_ext->_unlock1 = unlock_addresses->unlock1;
2102 pri_ext->_unlock2 = unlock_addresses->unlock2;
2103 }
2104
2105 int cfi_probe(struct flash_bank_s *bank)
2106 {
2107 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2108 target_t *target = bank->target;
2109 u8 command[8];
2110 int num_sectors = 0;
2111 int i;
2112 int sector = 0;
2113 u32 offset = 0;
2114 u32 unlock1 = 0x555;
2115 u32 unlock2 = 0x2aa;
2116 int retval;
2117
2118 if (bank->target->state != TARGET_HALTED)
2119 {
2120 LOG_ERROR("Target not halted");
2121 return ERROR_TARGET_NOT_HALTED;
2122 }
2123
2124 cfi_info->probed = 0;
2125
2126 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2127 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2128 */
2129 if (cfi_info->jedec_probe)
2130 {
2131 unlock1 = 0x5555;
2132 unlock2 = 0x2aaa;
2133 }
2134
2135 /* switch to read identifier codes mode ("AUTOSELECT") */
2136 cfi_command(bank, 0xaa, command);
2137 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2138 {
2139 return retval;
2140 }
2141 cfi_command(bank, 0x55, command);
2142 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2143 {
2144 return retval;
2145 }
2146 cfi_command(bank, 0x90, command);
2147 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2148 {
2149 return retval;
2150 }
2151
2152 if (bank->chip_width == 1)
2153 {
2154 u8 manufacturer, device_id;
2155 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
2156 {
2157 return retval;
2158 }
2159 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
2160 {
2161 return retval;
2162 }
2163 cfi_info->manufacturer = manufacturer;
2164 cfi_info->device_id = device_id;
2165 }
2166 else if (bank->chip_width == 2)
2167 {
2168 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2169 {
2170 return retval;
2171 }
2172 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2173 {
2174 return retval;
2175 }
2176 }
2177
2178 /* switch back to read array mode */
2179 cfi_command(bank, 0xf0, command);
2180 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2181 {
2182 return retval;
2183 }
2184 cfi_command(bank, 0xff, command);
2185 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2186 {
2187 return retval;
2188 }
2189
2190 cfi_fixup(bank, cfi_jedec_fixups);
2191
2192 /* query only if this is a CFI compatible flash,
2193 * otherwise the relevant info has already been filled in
2194 */
2195 if (cfi_info->not_cfi == 0)
2196 {
2197 /* enter CFI query mode
2198 * according to JEDEC Standard No. 68.01,
2199 * a single bus sequence with address = 0x55, data = 0x98 should put
2200 * the device into CFI query mode.
2201 *
2202 * SST flashes clearly violate this, and we will consider them incompatbile for now
2203 */
2204 cfi_command(bank, 0x98, command);
2205 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2206 {
2207 return retval;
2208 }
2209
2210 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2211 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2212 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2213
2214 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2215
2216 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2217 {
2218 cfi_command(bank, 0xf0, command);
2219 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2220 {
2221 return retval;
2222 }
2223 cfi_command(bank, 0xff, command);
2224 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2225 {
2226 return retval;
2227 }
2228 LOG_ERROR("Could not probe bank");
2229 return ERROR_FLASH_BANK_INVALID;
2230 }
2231
2232 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2233 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2234 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2235 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2236
2237 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2238
2239 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2240 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2241 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2242 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2243 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2244 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2245 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2246 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2247 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2248 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2249 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2250 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2251
2252 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2253 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2254 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2255 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2256 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2257 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2258 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2259 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2260 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2261 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2262 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2263
2264 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
2265 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2266 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2267 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2268
2269 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2270
2271 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
2272 {
2273 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
2274 }
2275
2276 if (cfi_info->num_erase_regions)
2277 {
2278 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2279 for (i = 0; i < cfi_info->num_erase_regions; i++)
2280 {
2281 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2282 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2283 }
2284 }
2285 else
2286 {
2287 cfi_info->erase_region_info = NULL;
2288 }
2289
2290 /* We need to read the primary algorithm extended query table before calculating
2291 * the sector layout to be able to apply fixups
2292 */
2293 switch(cfi_info->pri_id)
2294 {
2295 /* Intel command set (standard and extended) */
2296 case 0x0001:
2297 case 0x0003:
2298 cfi_read_intel_pri_ext(bank);
2299 break;
2300 /* AMD/Spansion, Atmel, ... command set */
2301 case 0x0002:
2302 cfi_read_0002_pri_ext(bank);
2303 break;
2304 default:
2305 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2306 break;
2307 }
2308
2309 /* return to read array mode
2310 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2311 */
2312 cfi_command(bank, 0xf0, command);
2313 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2314 {
2315 return retval;
2316 }
2317 cfi_command(bank, 0xff, command);
2318 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2319 {
2320 return retval;
2321 }
2322 }
2323
2324 /* apply fixups depending on the primary command set */
2325 switch(cfi_info->pri_id)
2326 {
2327 /* Intel command set (standard and extended) */
2328 case 0x0001:
2329 case 0x0003:
2330 cfi_fixup(bank, cfi_0001_fixups);
2331 break;
2332 /* AMD/Spansion, Atmel, ... command set */
2333 case 0x0002:
2334 cfi_fixup(bank, cfi_0002_fixups);
2335 break;
2336 default:
2337 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2338 break;
2339 }
2340
2341 if (cfi_info->num_erase_regions == 0)
2342 {
2343 /* a device might have only one erase block, spanning the whole device */
2344 bank->num_sectors = 1;
2345 bank->sectors = malloc(sizeof(flash_sector_t));
2346
2347 bank->sectors[sector].offset = 0x0;
2348 bank->sectors[sector].size = bank->size;
2349 bank->sectors[sector].is_erased = -1;
2350 bank->sectors[sector].is_protected = -1;
2351 }
2352 else
2353 {
2354 for (i = 0; i < cfi_info->num_erase_regions; i++)
2355 {
2356 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2357 }
2358
2359 bank->num_sectors = num_sectors;
2360 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2361
2362 for (i = 0; i < cfi_info->num_erase_regions; i++)
2363 {
2364 int j;
2365 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2366 {
2367 bank->sectors[sector].offset = offset;
2368 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2369 offset += bank->sectors[sector].size;
2370 bank->sectors[sector].is_erased = -1;
2371 bank->sectors[sector].is_protected = -1;
2372 sector++;
2373 }
2374 }
2375 }
2376
2377 cfi_info->probed = 1;
2378
2379 return ERROR_OK;
2380 }
2381
2382 int cfi_auto_probe(struct flash_bank_s *bank)
2383 {
2384 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2385 if (cfi_info->probed)
2386 return ERROR_OK;
2387 return cfi_probe(bank);
2388 }
2389
2390
2391 int cfi_intel_protect_check(struct flash_bank_s *bank)
2392 {
2393 int retval;
2394 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2395 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2396 target_t *target = bank->target;
2397 u8 command[CFI_MAX_BUS_WIDTH];
2398 int i;
2399
2400 /* check if block lock bits are supported on this device */
2401 if (!(pri_ext->blk_status_reg_mask & 0x1))
2402 return ERROR_FLASH_OPERATION_FAILED;
2403
2404 cfi_command(bank, 0x90, command);
2405 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2406 {
2407 return retval;
2408 }
2409
2410 for (i = 0; i < bank->num_sectors; i++)
2411 {
2412 u8 block_status = cfi_get_u8(bank, i, 0x2);
2413
2414 if (block_status & 1)
2415 bank->sectors[i].is_protected = 1;
2416 else
2417 bank->sectors[i].is_protected = 0;
2418 }
2419
2420 cfi_command(bank, 0xff, command);
2421 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2422 }
2423
2424 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2425 {
2426 int retval;
2427 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2428 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2429 target_t *target = bank->target;
2430 u8 command[8];
2431 int i;
2432
2433 cfi_command(bank, 0xaa, command);
2434 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2435 {
2436 return retval;
2437 }
2438
2439 cfi_command(bank, 0x55, command);
2440 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2441 {
2442 return retval;
2443 }
2444
2445 cfi_command(bank, 0x90, command);
2446 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2447 {
2448 return retval;
2449 }
2450
2451 for (i = 0; i < bank->num_sectors; i++)
2452 {
2453 u8 block_status = cfi_get_u8(bank, i, 0x2);
2454
2455 if (block_status & 1)
2456 bank->sectors[i].is_protected = 1;
2457 else
2458 bank->sectors[i].is_protected = 0;
2459 }
2460
2461 cfi_command(bank, 0xf0, command);
2462 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2463 }
2464
2465 int cfi_protect_check(struct flash_bank_s *bank)
2466 {
2467 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2468
2469 if (bank->target->state != TARGET_HALTED)
2470 {
2471 LOG_ERROR("Target not halted");
2472 return ERROR_TARGET_NOT_HALTED;
2473 }
2474
2475 if (cfi_info->qry[0] != 'Q')
2476 return ERROR_FLASH_BANK_NOT_PROBED;
2477
2478 switch(cfi_info->pri_id)
2479 {
2480 case 1:
2481 case 3:
2482 return cfi_intel_protect_check(bank);
2483 break;
2484 case 2:
2485 return cfi_spansion_protect_check(bank);
2486 break;
2487 default:
2488 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2489 break;
2490 }
2491
2492 return ERROR_OK;
2493 }
2494
2495 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2496 {
2497 int printed;
2498 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2499
2500 if (cfi_info->qry[0] == (char)-1)
2501 {
2502 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2503 return ERROR_OK;
2504 }
2505
2506 if (cfi_info->not_cfi == 0)
2507 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2508 else
2509 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2510 buf += printed;
2511 buf_size -= printed;
2512
2513 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2514 cfi_info->manufacturer, cfi_info->device_id);
2515 buf += printed;
2516 buf_size -= printed;
2517
2518 if (cfi_info->not_cfi == 0)
2519 {
2520 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2521 buf += printed;
2522 buf_size -= printed;
2523
2524 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2525 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2526 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2527 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2528 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2529 buf += printed;
2530 buf_size -= printed;
2531
2532 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2533 1 << cfi_info->word_write_timeout_typ,
2534 1 << cfi_info->buf_write_timeout_typ,
2535 1 << cfi_info->block_erase_timeout_typ,
2536 1 << cfi_info->chip_erase_timeout_typ);
2537 buf += printed;
2538 buf_size -= printed;
2539
2540 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2541 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2542 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2543 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2544 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2545 buf += printed;
2546 buf_size -= printed;
2547
2548 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2549 1 << cfi_info->dev_size,
2550 cfi_info->interface_desc,
2551 1 << cfi_info->max_buf_write_size);
2552 buf += printed;
2553 buf_size -= printed;
2554
2555 switch(cfi_info->pri_id)
2556 {
2557 case 1:
2558 case 3:
2559 cfi_intel_info(bank, buf, buf_size);
2560 break;
2561 case 2:
2562 cfi_spansion_info(bank, buf, buf_size);
2563 break;
2564 default:
2565 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2566 break;
2567 }
2568 }
2569
2570 return ERROR_OK;
2571 }
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