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[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28 #include "armv4_5.h"
29 #include "binarybuffer.h"
30 #include "algorithm.h"
31
32
33 #define CFI_MAX_BUS_WIDTH 4
34 #define CFI_MAX_CHIP_WIDTH 4
35
36 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
37 #define CFI_MAX_INTEL_CODESIZE 256
38
39 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
40 {
41 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
42 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
43 };
44
45 /* CFI fixups foward declarations */
46 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
47 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
48 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
49
50 /* fixup after reading cmdset 0002 primary query table */
51 static const struct cfi_fixup cfi_0002_fixups[] = {
52 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
53 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
54 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
55 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
58 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
60 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
63 {0, 0, NULL, NULL}
64 };
65
66 /* fixup after reading cmdset 0001 primary query table */
67 static const struct cfi_fixup cfi_0001_fixups[] = {
68 {0, 0, NULL, NULL}
69 };
70
71 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
72 {
73 struct cfi_flash_bank *cfi_info = bank->driver_priv;
74 const struct cfi_fixup *f;
75
76 for (f = fixups; f->fixup; f++)
77 {
78 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
79 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
80 {
81 f->fixup(bank, f->param);
82 }
83 }
84 }
85
86 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
87 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
88 {
89 struct cfi_flash_bank *cfi_info = bank->driver_priv;
90
91 if (cfi_info->x16_as_x8) offset *= 2;
92
93 /* while the sector list isn't built, only accesses to sector 0 work */
94 if (sector == 0)
95 return bank->base + offset * bank->bus_width;
96 else
97 {
98 if (!bank->sectors)
99 {
100 LOG_ERROR("BUG: sector list not yet built");
101 exit(-1);
102 }
103 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
104 }
105
106 }
107
108 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
109 {
110 int i;
111
112 /* clear whole buffer, to ensure bits that exceed the bus_width
113 * are set to zero
114 */
115 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
116 cmd_buf[i] = 0;
117
118 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
119 {
120 for (i = bank->bus_width; i > 0; i--)
121 {
122 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
123 }
124 }
125 else
126 {
127 for (i = 1; i <= bank->bus_width; i++)
128 {
129 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
130 }
131 }
132 }
133
134 /* read unsigned 8-bit value from the bank
135 * flash banks are expected to be made of similar chips
136 * the query result should be the same for all
137 */
138 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
139 {
140 struct target *target = bank->target;
141 uint8_t data[CFI_MAX_BUS_WIDTH];
142
143 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
144
145 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
146 return data[0];
147 else
148 return data[bank->bus_width - 1];
149 }
150
151 /* read unsigned 8-bit value from the bank
152 * in case of a bank made of multiple chips,
153 * the individual values are ORed
154 */
155 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
156 {
157 struct target *target = bank->target;
158 uint8_t data[CFI_MAX_BUS_WIDTH];
159 int i;
160
161 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
162
163 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
164 {
165 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
166 data[0] |= data[i];
167
168 return data[0];
169 }
170 else
171 {
172 uint8_t value = 0;
173 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
174 value |= data[bank->bus_width - 1 - i];
175
176 return value;
177 }
178 }
179
180 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
181 {
182 struct target *target = bank->target;
183 struct cfi_flash_bank *cfi_info = bank->driver_priv;
184 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
185
186 if (cfi_info->x16_as_x8)
187 {
188 uint8_t i;
189 for (i = 0;i < 2;i++)
190 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
191 &data[i*bank->bus_width]);
192 }
193 else
194 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
195
196 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
197 return data[0] | data[bank->bus_width] << 8;
198 else
199 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
200 }
201
202 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
203 {
204 struct target *target = bank->target;
205 struct cfi_flash_bank *cfi_info = bank->driver_priv;
206 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
207
208 if (cfi_info->x16_as_x8)
209 {
210 uint8_t i;
211 for (i = 0;i < 4;i++)
212 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
213 &data[i*bank->bus_width]);
214 }
215 else
216 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
217
218 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
219 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
220 else
221 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
222 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
223 }
224
225 static void cfi_intel_clear_status_register(struct flash_bank *bank)
226 {
227 struct target *target = bank->target;
228 uint8_t command[8];
229
230 if (target->state != TARGET_HALTED)
231 {
232 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
233 exit(-1);
234 }
235
236 cfi_command(bank, 0x50, command);
237 target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
238 }
239
240 uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
241 {
242 uint8_t status;
243
244 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
245 {
246 LOG_DEBUG("status: 0x%x", status);
247 alive_sleep(1);
248 }
249
250 /* mask out bit 0 (reserved) */
251 status = status & 0xfe;
252
253 LOG_DEBUG("status: 0x%x", status);
254
255 if ((status & 0x80) != 0x80)
256 {
257 LOG_ERROR("timeout while waiting for WSM to become ready");
258 }
259 else if (status != 0x80)
260 {
261 LOG_ERROR("status register: 0x%x", status);
262 if (status & 0x2)
263 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
264 if (status & 0x4)
265 LOG_ERROR("Program suspended");
266 if (status & 0x8)
267 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
268 if (status & 0x10)
269 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
270 if (status & 0x20)
271 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
272 if (status & 0x40)
273 LOG_ERROR("Block Erase Suspended");
274
275 cfi_intel_clear_status_register(bank);
276 }
277
278 return status;
279 }
280
281 int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
282 {
283 uint8_t status, oldstatus;
284 struct cfi_flash_bank *cfi_info = bank->driver_priv;
285
286 oldstatus = cfi_get_u8(bank, 0, 0x0);
287
288 do {
289 status = cfi_get_u8(bank, 0, 0x0);
290 if ((status ^ oldstatus) & 0x40) {
291 if (status & cfi_info->status_poll_mask & 0x20) {
292 oldstatus = cfi_get_u8(bank, 0, 0x0);
293 status = cfi_get_u8(bank, 0, 0x0);
294 if ((status ^ oldstatus) & 0x40) {
295 LOG_ERROR("dq5 timeout, status: 0x%x", status);
296 return(ERROR_FLASH_OPERATION_FAILED);
297 } else {
298 LOG_DEBUG("status: 0x%x", status);
299 return(ERROR_OK);
300 }
301 }
302 } else { /* no toggle: finished, OK */
303 LOG_DEBUG("status: 0x%x", status);
304 return(ERROR_OK);
305 }
306
307 oldstatus = status;
308 alive_sleep(1);
309 } while (timeout-- > 0);
310
311 LOG_ERROR("timeout, status: 0x%x", status);
312
313 return(ERROR_FLASH_BUSY);
314 }
315
316 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
317 {
318 int retval;
319 struct cfi_flash_bank *cfi_info = bank->driver_priv;
320 struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
321 struct target *target = bank->target;
322 uint8_t command[8];
323
324 cfi_info->pri_ext = pri_ext;
325
326 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
327 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
328 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
329
330 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
331 {
332 cfi_command(bank, 0xf0, command);
333 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
334 {
335 return retval;
336 }
337 cfi_command(bank, 0xff, command);
338 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
339 {
340 return retval;
341 }
342 LOG_ERROR("Could not read bank flash bank information");
343 return ERROR_FLASH_BANK_INVALID;
344 }
345
346 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
347 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
348
349 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
350
351 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
352 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
353 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
354
355 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
356 pri_ext->feature_support,
357 pri_ext->suspend_cmd_support,
358 pri_ext->blk_status_reg_mask);
359
360 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
361 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
362
363 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
364 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
365 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
366
367 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
368 if (pri_ext->num_protection_fields != 1)
369 {
370 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
371 }
372
373 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
374 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
375 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
376
377 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
378
379 return ERROR_OK;
380 }
381
382 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
383 {
384 int retval;
385 struct cfi_flash_bank *cfi_info = bank->driver_priv;
386 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
387 struct target *target = bank->target;
388 uint8_t command[8];
389
390 cfi_info->pri_ext = pri_ext;
391
392 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
393 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
394 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
395
396 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
397 {
398 cfi_command(bank, 0xf0, command);
399 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
400 {
401 return retval;
402 }
403 LOG_ERROR("Could not read spansion bank information");
404 return ERROR_FLASH_BANK_INVALID;
405 }
406
407 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
408 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
409
410 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
411
412 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
413 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
414 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
415 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
416 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
417 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
418 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
419 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
420 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
421 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
422 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
423
424 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
425 pri_ext->EraseSuspend, pri_ext->BlkProt);
426
427 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
428 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
429
430 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
431
432
433 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
434 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
435 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
436
437 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
438
439 /* default values for implementation specific workarounds */
440 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
441 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
442 pri_ext->_reversed_geometry = 0;
443
444 return ERROR_OK;
445 }
446
447 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
448 {
449 int retval;
450 struct cfi_atmel_pri_ext atmel_pri_ext;
451 struct cfi_flash_bank *cfi_info = bank->driver_priv;
452 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
453 struct target *target = bank->target;
454 uint8_t command[8];
455
456 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
457 * but a different primary extended query table.
458 * We read the atmel table, and prepare a valid AMD/Spansion query table.
459 */
460
461 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
462
463 cfi_info->pri_ext = pri_ext;
464
465 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
466 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
467 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
468
469 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
470 {
471 cfi_command(bank, 0xf0, command);
472 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
473 {
474 return retval;
475 }
476 LOG_ERROR("Could not read atmel bank information");
477 return ERROR_FLASH_BANK_INVALID;
478 }
479
480 pri_ext->pri[0] = atmel_pri_ext.pri[0];
481 pri_ext->pri[1] = atmel_pri_ext.pri[1];
482 pri_ext->pri[2] = atmel_pri_ext.pri[2];
483
484 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
485 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
486
487 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
488
489 pri_ext->major_version = atmel_pri_ext.major_version;
490 pri_ext->minor_version = atmel_pri_ext.minor_version;
491
492 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
493 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
494 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
495 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
496
497 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
498 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
499
500 if (atmel_pri_ext.features & 0x02)
501 pri_ext->EraseSuspend = 2;
502
503 if (atmel_pri_ext.bottom_boot)
504 pri_ext->TopBottom = 2;
505 else
506 pri_ext->TopBottom = 3;
507
508 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
509 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
510
511 return ERROR_OK;
512 }
513
514 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
515 {
516 struct cfi_flash_bank *cfi_info = bank->driver_priv;
517
518 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
519 {
520 return cfi_read_atmel_pri_ext(bank);
521 }
522 else
523 {
524 return cfi_read_spansion_pri_ext(bank);
525 }
526 }
527
528 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
529 {
530 int printed;
531 struct cfi_flash_bank *cfi_info = bank->driver_priv;
532 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
533
534 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
535 buf += printed;
536 buf_size -= printed;
537
538 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
539 pri_ext->pri[1], pri_ext->pri[2],
540 pri_ext->major_version, pri_ext->minor_version);
541 buf += printed;
542 buf_size -= printed;
543
544 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
545 (pri_ext->SiliconRevision) >> 2,
546 (pri_ext->SiliconRevision) & 0x03);
547 buf += printed;
548 buf_size -= printed;
549
550 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
551 pri_ext->EraseSuspend,
552 pri_ext->BlkProt);
553 buf += printed;
554 buf_size -= printed;
555
556 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
557 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
558 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
559
560 return ERROR_OK;
561 }
562
563 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
564 {
565 int printed;
566 struct cfi_flash_bank *cfi_info = bank->driver_priv;
567 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
568
569 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
570 buf += printed;
571 buf_size -= printed;
572
573 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
574 buf += printed;
575 buf_size -= printed;
576
577 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
578 buf += printed;
579 buf_size -= printed;
580
581 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
582 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
583 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
584 buf += printed;
585 buf_size -= printed;
586
587 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
588
589 return ERROR_OK;
590 }
591
592 static int cfi_register_commands(struct command_context *cmd_ctx)
593 {
594 return ERROR_OK;
595 }
596
597 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
598 */
599 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
600 {
601 struct cfi_flash_bank *cfi_info;
602
603 if (CMD_ARGC < 6)
604 {
605 LOG_WARNING("incomplete flash_bank cfi configuration");
606 return ERROR_FLASH_BANK_INVALID;
607 }
608
609 uint16_t chip_width, bus_width;
610 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], bus_width);
611 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[4], chip_width);
612
613 if ((chip_width > CFI_MAX_CHIP_WIDTH)
614 || (bus_width > CFI_MAX_BUS_WIDTH))
615 {
616 LOG_ERROR("chip and bus width have to specified in bytes");
617 return ERROR_FLASH_BANK_INVALID;
618 }
619
620 cfi_info = malloc(sizeof(struct cfi_flash_bank));
621 cfi_info->probed = 0;
622 bank->driver_priv = cfi_info;
623
624 cfi_info->write_algorithm = NULL;
625
626 cfi_info->x16_as_x8 = 0;
627 cfi_info->jedec_probe = 0;
628 cfi_info->not_cfi = 0;
629
630 for (unsigned i = 6; i < CMD_ARGC; i++)
631 {
632 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
633 {
634 cfi_info->x16_as_x8 = 1;
635 }
636 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
637 {
638 cfi_info->jedec_probe = 1;
639 }
640 }
641
642 cfi_info->write_algorithm = NULL;
643
644 /* bank wasn't probed yet */
645 cfi_info->qry[0] = -1;
646
647 return ERROR_OK;
648 }
649
650 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
651 {
652 int retval;
653 struct cfi_flash_bank *cfi_info = bank->driver_priv;
654 struct target *target = bank->target;
655 uint8_t command[8];
656 int i;
657
658 cfi_intel_clear_status_register(bank);
659
660 for (i = first; i <= last; i++)
661 {
662 cfi_command(bank, 0x20, command);
663 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
664 {
665 return retval;
666 }
667
668 cfi_command(bank, 0xd0, command);
669 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
670 {
671 return retval;
672 }
673
674 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
675 bank->sectors[i].is_erased = 1;
676 else
677 {
678 cfi_command(bank, 0xff, command);
679 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
680 {
681 return retval;
682 }
683
684 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
685 return ERROR_FLASH_OPERATION_FAILED;
686 }
687 }
688
689 cfi_command(bank, 0xff, command);
690 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
691
692 }
693
694 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
695 {
696 int retval;
697 struct cfi_flash_bank *cfi_info = bank->driver_priv;
698 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
699 struct target *target = bank->target;
700 uint8_t command[8];
701 int i;
702
703 for (i = first; i <= last; i++)
704 {
705 cfi_command(bank, 0xaa, command);
706 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
707 {
708 return retval;
709 }
710
711 cfi_command(bank, 0x55, command);
712 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
713 {
714 return retval;
715 }
716
717 cfi_command(bank, 0x80, command);
718 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
719 {
720 return retval;
721 }
722
723 cfi_command(bank, 0xaa, command);
724 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
725 {
726 return retval;
727 }
728
729 cfi_command(bank, 0x55, command);
730 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
731 {
732 return retval;
733 }
734
735 cfi_command(bank, 0x30, command);
736 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
737 {
738 return retval;
739 }
740
741 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
742 bank->sectors[i].is_erased = 1;
743 else
744 {
745 cfi_command(bank, 0xf0, command);
746 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
747 {
748 return retval;
749 }
750
751 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
752 return ERROR_FLASH_OPERATION_FAILED;
753 }
754 }
755
756 cfi_command(bank, 0xf0, command);
757 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
758 }
759
760 static int cfi_erase(struct flash_bank *bank, int first, int last)
761 {
762 struct cfi_flash_bank *cfi_info = bank->driver_priv;
763
764 if (bank->target->state != TARGET_HALTED)
765 {
766 LOG_ERROR("Target not halted");
767 return ERROR_TARGET_NOT_HALTED;
768 }
769
770 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
771 {
772 return ERROR_FLASH_SECTOR_INVALID;
773 }
774
775 if (cfi_info->qry[0] != 'Q')
776 return ERROR_FLASH_BANK_NOT_PROBED;
777
778 switch (cfi_info->pri_id)
779 {
780 case 1:
781 case 3:
782 return cfi_intel_erase(bank, first, last);
783 break;
784 case 2:
785 return cfi_spansion_erase(bank, first, last);
786 break;
787 default:
788 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
789 break;
790 }
791
792 return ERROR_OK;
793 }
794
795 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
796 {
797 int retval;
798 struct cfi_flash_bank *cfi_info = bank->driver_priv;
799 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
800 struct target *target = bank->target;
801 uint8_t command[8];
802 int retry = 0;
803 int i;
804
805 /* if the device supports neither legacy lock/unlock (bit 3) nor
806 * instant individual block locking (bit 5).
807 */
808 if (!(pri_ext->feature_support & 0x28))
809 return ERROR_FLASH_OPERATION_FAILED;
810
811 cfi_intel_clear_status_register(bank);
812
813 for (i = first; i <= last; i++)
814 {
815 cfi_command(bank, 0x60, command);
816 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
817 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
818 {
819 return retval;
820 }
821 if (set)
822 {
823 cfi_command(bank, 0x01, command);
824 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
825 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
826 {
827 return retval;
828 }
829 bank->sectors[i].is_protected = 1;
830 }
831 else
832 {
833 cfi_command(bank, 0xd0, command);
834 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
835 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
836 {
837 return retval;
838 }
839 bank->sectors[i].is_protected = 0;
840 }
841
842 /* instant individual block locking doesn't require reading of the status register */
843 if (!(pri_ext->feature_support & 0x20))
844 {
845 /* Clear lock bits operation may take up to 1.4s */
846 cfi_intel_wait_status_busy(bank, 1400);
847 }
848 else
849 {
850 uint8_t block_status;
851 /* read block lock bit, to verify status */
852 cfi_command(bank, 0x90, command);
853 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
854 {
855 return retval;
856 }
857 block_status = cfi_get_u8(bank, i, 0x2);
858
859 if ((block_status & 0x1) != set)
860 {
861 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
862 cfi_command(bank, 0x70, command);
863 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
864 {
865 return retval;
866 }
867 cfi_intel_wait_status_busy(bank, 10);
868
869 if (retry > 10)
870 return ERROR_FLASH_OPERATION_FAILED;
871 else
872 {
873 i--;
874 retry++;
875 }
876 }
877 }
878 }
879
880 /* if the device doesn't support individual block lock bits set/clear,
881 * all blocks have been unlocked in parallel, so we set those that should be protected
882 */
883 if ((!set) && (!(pri_ext->feature_support & 0x20)))
884 {
885 for (i = 0; i < bank->num_sectors; i++)
886 {
887 if (bank->sectors[i].is_protected == 1)
888 {
889 cfi_intel_clear_status_register(bank);
890
891 cfi_command(bank, 0x60, command);
892 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
893 {
894 return retval;
895 }
896
897 cfi_command(bank, 0x01, command);
898 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
899 {
900 return retval;
901 }
902
903 cfi_intel_wait_status_busy(bank, 100);
904 }
905 }
906 }
907
908 cfi_command(bank, 0xff, command);
909 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
910 }
911
912 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
913 {
914 struct cfi_flash_bank *cfi_info = bank->driver_priv;
915
916 if (bank->target->state != TARGET_HALTED)
917 {
918 LOG_ERROR("Target not halted");
919 return ERROR_TARGET_NOT_HALTED;
920 }
921
922 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
923 {
924 return ERROR_FLASH_SECTOR_INVALID;
925 }
926
927 if (cfi_info->qry[0] != 'Q')
928 return ERROR_FLASH_BANK_NOT_PROBED;
929
930 switch (cfi_info->pri_id)
931 {
932 case 1:
933 case 3:
934 cfi_intel_protect(bank, set, first, last);
935 break;
936 default:
937 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
938 break;
939 }
940
941 return ERROR_OK;
942 }
943
944 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
945 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
946 {
947 /* struct target *target = bank->target; */
948
949 int i;
950
951 /* NOTE:
952 * The data to flash must not be changed in endian! We write a bytestrem in
953 * target byte order already. Only the control and status byte lane of the flash
954 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
955 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
956 */
957
958 #if 0
959 if (target->endianness == TARGET_LITTLE_ENDIAN)
960 {
961 #endif
962 /* shift bytes */
963 for (i = 0; i < bank->bus_width - 1; i++)
964 word[i] = word[i + 1];
965 word[bank->bus_width - 1] = byte;
966 #if 0
967 }
968 else
969 {
970 /* shift bytes */
971 for (i = bank->bus_width - 1; i > 0; i--)
972 word[i] = word[i - 1];
973 word[0] = byte;
974 }
975 #endif
976 }
977
978 /* Convert code image to target endian */
979 /* FIXME create general block conversion fcts in target.c?) */
980 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
981 {
982 uint32_t i;
983 for (i = 0; i< count; i++)
984 {
985 target_buffer_set_u32(target, dest, *src);
986 dest += 4;
987 src++;
988 }
989 }
990
991 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
992 {
993 struct target *target = bank->target;
994
995 uint8_t buf[CFI_MAX_BUS_WIDTH];
996 cfi_command(bank, cmd, buf);
997 switch (bank->bus_width)
998 {
999 case 1 :
1000 return buf[0];
1001 break;
1002 case 2 :
1003 return target_buffer_get_u16(target, buf);
1004 break;
1005 case 4 :
1006 return target_buffer_get_u32(target, buf);
1007 break;
1008 default :
1009 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1010 return 0;
1011 }
1012 }
1013
1014 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1015 {
1016 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1017 struct target *target = bank->target;
1018 struct reg_param reg_params[7];
1019 struct armv4_5_algorithm armv4_5_info;
1020 struct working_area *source;
1021 uint32_t buffer_size = 32768;
1022 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1023
1024 /* algorithm register usage:
1025 * r0: source address (in RAM)
1026 * r1: target address (in Flash)
1027 * r2: count
1028 * r3: flash write command
1029 * r4: status byte (returned to host)
1030 * r5: busy test pattern
1031 * r6: error test pattern
1032 */
1033
1034 static const uint32_t word_32_code[] = {
1035 0xe4904004, /* loop: ldr r4, [r0], #4 */
1036 0xe5813000, /* str r3, [r1] */
1037 0xe5814000, /* str r4, [r1] */
1038 0xe5914000, /* busy: ldr r4, [r1] */
1039 0xe0047005, /* and r7, r4, r5 */
1040 0xe1570005, /* cmp r7, r5 */
1041 0x1afffffb, /* bne busy */
1042 0xe1140006, /* tst r4, r6 */
1043 0x1a000003, /* bne done */
1044 0xe2522001, /* subs r2, r2, #1 */
1045 0x0a000001, /* beq done */
1046 0xe2811004, /* add r1, r1 #4 */
1047 0xeafffff2, /* b loop */
1048 0xeafffffe /* done: b -2 */
1049 };
1050
1051 static const uint32_t word_16_code[] = {
1052 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1053 0xe1c130b0, /* strh r3, [r1] */
1054 0xe1c140b0, /* strh r4, [r1] */
1055 0xe1d140b0, /* busy ldrh r4, [r1] */
1056 0xe0047005, /* and r7, r4, r5 */
1057 0xe1570005, /* cmp r7, r5 */
1058 0x1afffffb, /* bne busy */
1059 0xe1140006, /* tst r4, r6 */
1060 0x1a000003, /* bne done */
1061 0xe2522001, /* subs r2, r2, #1 */
1062 0x0a000001, /* beq done */
1063 0xe2811002, /* add r1, r1 #2 */
1064 0xeafffff2, /* b loop */
1065 0xeafffffe /* done: b -2 */
1066 };
1067
1068 static const uint32_t word_8_code[] = {
1069 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1070 0xe5c13000, /* strb r3, [r1] */
1071 0xe5c14000, /* strb r4, [r1] */
1072 0xe5d14000, /* busy ldrb r4, [r1] */
1073 0xe0047005, /* and r7, r4, r5 */
1074 0xe1570005, /* cmp r7, r5 */
1075 0x1afffffb, /* bne busy */
1076 0xe1140006, /* tst r4, r6 */
1077 0x1a000003, /* bne done */
1078 0xe2522001, /* subs r2, r2, #1 */
1079 0x0a000001, /* beq done */
1080 0xe2811001, /* add r1, r1 #1 */
1081 0xeafffff2, /* b loop */
1082 0xeafffffe /* done: b -2 */
1083 };
1084 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1085 const uint32_t *target_code_src;
1086 uint32_t target_code_size;
1087 int retval = ERROR_OK;
1088
1089
1090 cfi_intel_clear_status_register(bank);
1091
1092 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1093 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1094 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1095
1096 /* If we are setting up the write_algorith, we need target_code_src */
1097 /* if not we only need target_code_size. */
1098
1099 /* However, we don't want to create multiple code paths, so we */
1100 /* do the unecessary evaluation of target_code_src, which the */
1101 /* compiler will probably nicely optimize away if not needed */
1102
1103 /* prepare algorithm code for target endian */
1104 switch (bank->bus_width)
1105 {
1106 case 1 :
1107 target_code_src = word_8_code;
1108 target_code_size = sizeof(word_8_code);
1109 break;
1110 case 2 :
1111 target_code_src = word_16_code;
1112 target_code_size = sizeof(word_16_code);
1113 break;
1114 case 4 :
1115 target_code_src = word_32_code;
1116 target_code_size = sizeof(word_32_code);
1117 break;
1118 default:
1119 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1120 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1121 }
1122
1123 /* flash write code */
1124 if (!cfi_info->write_algorithm)
1125 {
1126 if (target_code_size > sizeof(target_code))
1127 {
1128 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1129 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1130 }
1131 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1132
1133 /* Get memory for block write handler */
1134 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1135 if (retval != ERROR_OK)
1136 {
1137 LOG_WARNING("No working area available, can't do block memory writes");
1138 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1139 };
1140
1141 /* write algorithm code to working area */
1142 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1143 if (retval != ERROR_OK)
1144 {
1145 LOG_ERROR("Unable to write block write code to target");
1146 goto cleanup;
1147 }
1148 }
1149
1150 /* Get a workspace buffer for the data to flash starting with 32k size.
1151 Half size until buffer would be smaller 256 Bytem then fail back */
1152 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1153 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1154 {
1155 buffer_size /= 2;
1156 if (buffer_size <= 256)
1157 {
1158 LOG_WARNING("no large enough working area available, can't do block memory writes");
1159 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1160 goto cleanup;
1161 }
1162 };
1163
1164 /* setup algo registers */
1165 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1166 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1167 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1168 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1169 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1170 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1171 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1172
1173 /* prepare command and status register patterns */
1174 write_command_val = cfi_command_val(bank, 0x40);
1175 busy_pattern_val = cfi_command_val(bank, 0x80);
1176 error_pattern_val = cfi_command_val(bank, 0x7e);
1177
1178 LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1179
1180 /* Programming main loop */
1181 while (count > 0)
1182 {
1183 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1184 uint32_t wsm_error;
1185
1186 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1187 {
1188 goto cleanup;
1189 }
1190
1191 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1192 buf_set_u32(reg_params[1].value, 0, 32, address);
1193 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1194
1195 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1196 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1197 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1198
1199 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1200
1201 /* Execute algorithm, assume breakpoint for last instruction */
1202 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1203 cfi_info->write_algorithm->address,
1204 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1205 10000, /* 10s should be enough for max. 32k of data */
1206 &armv4_5_info);
1207
1208 /* On failure try a fall back to direct word writes */
1209 if (retval != ERROR_OK)
1210 {
1211 cfi_intel_clear_status_register(bank);
1212 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1213 retval = ERROR_FLASH_OPERATION_FAILED;
1214 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1215 /* FIXME To allow fall back or recovery, we must save the actual status
1216 somewhere, so that a higher level code can start recovery. */
1217 goto cleanup;
1218 }
1219
1220 /* Check return value from algo code */
1221 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1222 if (wsm_error)
1223 {
1224 /* read status register (outputs debug inforation) */
1225 cfi_intel_wait_status_busy(bank, 100);
1226 cfi_intel_clear_status_register(bank);
1227 retval = ERROR_FLASH_OPERATION_FAILED;
1228 goto cleanup;
1229 }
1230
1231 buffer += thisrun_count;
1232 address += thisrun_count;
1233 count -= thisrun_count;
1234 }
1235
1236 /* free up resources */
1237 cleanup:
1238 if (source)
1239 target_free_working_area(target, source);
1240
1241 if (cfi_info->write_algorithm)
1242 {
1243 target_free_working_area(target, cfi_info->write_algorithm);
1244 cfi_info->write_algorithm = NULL;
1245 }
1246
1247 destroy_reg_param(&reg_params[0]);
1248 destroy_reg_param(&reg_params[1]);
1249 destroy_reg_param(&reg_params[2]);
1250 destroy_reg_param(&reg_params[3]);
1251 destroy_reg_param(&reg_params[4]);
1252 destroy_reg_param(&reg_params[5]);
1253 destroy_reg_param(&reg_params[6]);
1254
1255 return retval;
1256 }
1257
1258 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1259 {
1260 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1261 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1262 struct target *target = bank->target;
1263 struct reg_param reg_params[10];
1264 struct armv4_5_algorithm armv4_5_info;
1265 struct working_area *source;
1266 uint32_t buffer_size = 32768;
1267 uint32_t status;
1268 int retval, retvaltemp;
1269 int exit_code = ERROR_OK;
1270
1271 /* input parameters - */
1272 /* R0 = source address */
1273 /* R1 = destination address */
1274 /* R2 = number of writes */
1275 /* R3 = flash write command */
1276 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1277 /* output parameters - */
1278 /* R5 = 0x80 ok 0x00 bad */
1279 /* temp registers - */
1280 /* R6 = value read from flash to test status */
1281 /* R7 = holding register */
1282 /* unlock registers - */
1283 /* R8 = unlock1_addr */
1284 /* R9 = unlock1_cmd */
1285 /* R10 = unlock2_addr */
1286 /* R11 = unlock2_cmd */
1287
1288 static const uint32_t word_32_code[] = {
1289 /* 00008100 <sp_32_code>: */
1290 0xe4905004, /* ldr r5, [r0], #4 */
1291 0xe5889000, /* str r9, [r8] */
1292 0xe58ab000, /* str r11, [r10] */
1293 0xe5883000, /* str r3, [r8] */
1294 0xe5815000, /* str r5, [r1] */
1295 0xe1a00000, /* nop */
1296 /* */
1297 /* 00008110 <sp_32_busy>: */
1298 0xe5916000, /* ldr r6, [r1] */
1299 0xe0257006, /* eor r7, r5, r6 */
1300 0xe0147007, /* ands r7, r4, r7 */
1301 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1302 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1303 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1304 0xe5916000, /* ldr r6, [r1] */
1305 0xe0257006, /* eor r7, r5, r6 */
1306 0xe0147007, /* ands r7, r4, r7 */
1307 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1308 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1309 0x1a000004, /* bne 8154 <sp_32_done> */
1310 /* */
1311 /* 00008140 <sp_32_cont>: */
1312 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1313 0x03a05080, /* moveq r5, #128 ; 0x80 */
1314 0x0a000001, /* beq 8154 <sp_32_done> */
1315 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1316 0xeaffffe8, /* b 8100 <sp_32_code> */
1317 /* */
1318 /* 00008154 <sp_32_done>: */
1319 0xeafffffe /* b 8154 <sp_32_done> */
1320 };
1321
1322 static const uint32_t word_16_code[] = {
1323 /* 00008158 <sp_16_code>: */
1324 0xe0d050b2, /* ldrh r5, [r0], #2 */
1325 0xe1c890b0, /* strh r9, [r8] */
1326 0xe1cab0b0, /* strh r11, [r10] */
1327 0xe1c830b0, /* strh r3, [r8] */
1328 0xe1c150b0, /* strh r5, [r1] */
1329 0xe1a00000, /* nop (mov r0,r0) */
1330 /* */
1331 /* 00008168 <sp_16_busy>: */
1332 0xe1d160b0, /* ldrh r6, [r1] */
1333 0xe0257006, /* eor r7, r5, r6 */
1334 0xe0147007, /* ands r7, r4, r7 */
1335 0x0a000007, /* beq 8198 <sp_16_cont> */
1336 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1337 0x0afffff9, /* beq 8168 <sp_16_busy> */
1338 0xe1d160b0, /* ldrh r6, [r1] */
1339 0xe0257006, /* eor r7, r5, r6 */
1340 0xe0147007, /* ands r7, r4, r7 */
1341 0x0a000001, /* beq 8198 <sp_16_cont> */
1342 0xe3a05000, /* mov r5, #0 ; 0x0 */
1343 0x1a000004, /* bne 81ac <sp_16_done> */
1344 /* */
1345 /* 00008198 <sp_16_cont>: */
1346 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1347 0x03a05080, /* moveq r5, #128 ; 0x80 */
1348 0x0a000001, /* beq 81ac <sp_16_done> */
1349 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1350 0xeaffffe8, /* b 8158 <sp_16_code> */
1351 /* */
1352 /* 000081ac <sp_16_done>: */
1353 0xeafffffe /* b 81ac <sp_16_done> */
1354 };
1355
1356 static const uint32_t word_16_code_dq7only[] = {
1357 /* <sp_16_code>: */
1358 0xe0d050b2, /* ldrh r5, [r0], #2 */
1359 0xe1c890b0, /* strh r9, [r8] */
1360 0xe1cab0b0, /* strh r11, [r10] */
1361 0xe1c830b0, /* strh r3, [r8] */
1362 0xe1c150b0, /* strh r5, [r1] */
1363 0xe1a00000, /* nop (mov r0,r0) */
1364 /* */
1365 /* <sp_16_busy>: */
1366 0xe1d160b0, /* ldrh r6, [r1] */
1367 0xe0257006, /* eor r7, r5, r6 */
1368 0xe2177080, /* ands r7, #0x80 */
1369 0x1afffffb, /* bne 8168 <sp_16_busy> */
1370 /* */
1371 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1372 0x03a05080, /* moveq r5, #128 ; 0x80 */
1373 0x0a000001, /* beq 81ac <sp_16_done> */
1374 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1375 0xeafffff0, /* b 8158 <sp_16_code> */
1376 /* */
1377 /* 000081ac <sp_16_done>: */
1378 0xeafffffe /* b 81ac <sp_16_done> */
1379 };
1380
1381 static const uint32_t word_8_code[] = {
1382 /* 000081b0 <sp_16_code_end>: */
1383 0xe4d05001, /* ldrb r5, [r0], #1 */
1384 0xe5c89000, /* strb r9, [r8] */
1385 0xe5cab000, /* strb r11, [r10] */
1386 0xe5c83000, /* strb r3, [r8] */
1387 0xe5c15000, /* strb r5, [r1] */
1388 0xe1a00000, /* nop (mov r0,r0) */
1389 /* */
1390 /* 000081c0 <sp_8_busy>: */
1391 0xe5d16000, /* ldrb r6, [r1] */
1392 0xe0257006, /* eor r7, r5, r6 */
1393 0xe0147007, /* ands r7, r4, r7 */
1394 0x0a000007, /* beq 81f0 <sp_8_cont> */
1395 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1396 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1397 0xe5d16000, /* ldrb r6, [r1] */
1398 0xe0257006, /* eor r7, r5, r6 */
1399 0xe0147007, /* ands r7, r4, r7 */
1400 0x0a000001, /* beq 81f0 <sp_8_cont> */
1401 0xe3a05000, /* mov r5, #0 ; 0x0 */
1402 0x1a000004, /* bne 8204 <sp_8_done> */
1403 /* */
1404 /* 000081f0 <sp_8_cont>: */
1405 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1406 0x03a05080, /* moveq r5, #128 ; 0x80 */
1407 0x0a000001, /* beq 8204 <sp_8_done> */
1408 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1409 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1410 /* */
1411 /* 00008204 <sp_8_done>: */
1412 0xeafffffe /* b 8204 <sp_8_done> */
1413 };
1414
1415 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1416 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1417 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1418
1419 int target_code_size;
1420 const uint32_t *target_code_src;
1421
1422 switch (bank->bus_width)
1423 {
1424 case 1 :
1425 target_code_src = word_8_code;
1426 target_code_size = sizeof(word_8_code);
1427 break;
1428 case 2 :
1429 /* Check for DQ5 support */
1430 if( cfi_info->status_poll_mask & (1 << 5) )
1431 {
1432 target_code_src = word_16_code;
1433 target_code_size = sizeof(word_16_code);
1434 }
1435 else
1436 {
1437 /* No DQ5 support. Use DQ7 DATA# polling only. */
1438 target_code_src = word_16_code_dq7only;
1439 target_code_size = sizeof(word_16_code_dq7only);
1440 }
1441 break;
1442 case 4 :
1443 target_code_src = word_32_code;
1444 target_code_size = sizeof(word_32_code);
1445 break;
1446 default:
1447 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1448 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1449 }
1450
1451 /* flash write code */
1452 if (!cfi_info->write_algorithm)
1453 {
1454 uint8_t *target_code;
1455
1456 /* convert bus-width dependent algorithm code to correct endiannes */
1457 target_code = malloc(target_code_size);
1458 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1459
1460 /* allocate working area */
1461 retval = target_alloc_working_area(target, target_code_size,
1462 &cfi_info->write_algorithm);
1463 if (retval != ERROR_OK)
1464 {
1465 free(target_code);
1466 return retval;
1467 }
1468
1469 /* write algorithm code to working area */
1470 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1471 target_code_size, target_code)) != ERROR_OK)
1472 {
1473 free(target_code);
1474 return retval;
1475 }
1476
1477 free(target_code);
1478 }
1479 /* the following code still assumes target code is fixed 24*4 bytes */
1480
1481 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1482 {
1483 buffer_size /= 2;
1484 if (buffer_size <= 256)
1485 {
1486 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1487 if (cfi_info->write_algorithm)
1488 target_free_working_area(target, cfi_info->write_algorithm);
1489
1490 LOG_WARNING("not enough working area available, can't do block memory writes");
1491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1492 }
1493 };
1494
1495 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1496 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1497 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1498 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1499 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1500 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1501 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1502 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1503 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1504 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1505
1506 while (count > 0)
1507 {
1508 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1509
1510 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1511
1512 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1513 buf_set_u32(reg_params[1].value, 0, 32, address);
1514 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1515 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1516 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1517 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1518 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1519 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1520 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1521
1522 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1523 cfi_info->write_algorithm->address,
1524 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1525 10000, &armv4_5_info);
1526
1527 status = buf_get_u32(reg_params[5].value, 0, 32);
1528
1529 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1530 {
1531 LOG_DEBUG("status: 0x%" PRIx32 , status);
1532 exit_code = ERROR_FLASH_OPERATION_FAILED;
1533 break;
1534 }
1535
1536 buffer += thisrun_count;
1537 address += thisrun_count;
1538 count -= thisrun_count;
1539 }
1540
1541 target_free_all_working_areas(target);
1542
1543 destroy_reg_param(&reg_params[0]);
1544 destroy_reg_param(&reg_params[1]);
1545 destroy_reg_param(&reg_params[2]);
1546 destroy_reg_param(&reg_params[3]);
1547 destroy_reg_param(&reg_params[4]);
1548 destroy_reg_param(&reg_params[5]);
1549 destroy_reg_param(&reg_params[6]);
1550 destroy_reg_param(&reg_params[7]);
1551 destroy_reg_param(&reg_params[8]);
1552 destroy_reg_param(&reg_params[9]);
1553
1554 return exit_code;
1555 }
1556
1557 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1558 {
1559 int retval;
1560 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1561 struct target *target = bank->target;
1562 uint8_t command[8];
1563
1564 cfi_intel_clear_status_register(bank);
1565 cfi_command(bank, 0x40, command);
1566 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1567 {
1568 return retval;
1569 }
1570
1571 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1572 {
1573 return retval;
1574 }
1575
1576 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1577 {
1578 cfi_command(bank, 0xff, command);
1579 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1580 {
1581 return retval;
1582 }
1583
1584 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1585 return ERROR_FLASH_OPERATION_FAILED;
1586 }
1587
1588 return ERROR_OK;
1589 }
1590
1591 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1592 {
1593 int retval;
1594 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1595 struct target *target = bank->target;
1596 uint8_t command[8];
1597
1598 /* Calculate buffer size and boundary mask */
1599 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1600 uint32_t buffermask = buffersize-1;
1601 uint32_t bufferwsize;
1602
1603 /* Check for valid range */
1604 if (address & buffermask)
1605 {
1606 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1607 bank->base, address, cfi_info->max_buf_write_size);
1608 return ERROR_FLASH_OPERATION_FAILED;
1609 }
1610 switch (bank->chip_width)
1611 {
1612 case 4 : bufferwsize = buffersize / 4; break;
1613 case 2 : bufferwsize = buffersize / 2; break;
1614 case 1 : bufferwsize = buffersize; break;
1615 default:
1616 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1617 return ERROR_FLASH_OPERATION_FAILED;
1618 }
1619
1620 bufferwsize/=(bank->bus_width / bank->chip_width);
1621
1622
1623 /* Check for valid size */
1624 if (wordcount > bufferwsize)
1625 {
1626 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1627 return ERROR_FLASH_OPERATION_FAILED;
1628 }
1629
1630 /* Write to flash buffer */
1631 cfi_intel_clear_status_register(bank);
1632
1633 /* Initiate buffer operation _*/
1634 cfi_command(bank, 0xE8, command);
1635 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1636 {
1637 return retval;
1638 }
1639 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1640 {
1641 cfi_command(bank, 0xff, command);
1642 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1643 {
1644 return retval;
1645 }
1646
1647 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1648 return ERROR_FLASH_OPERATION_FAILED;
1649 }
1650
1651 /* Write buffer wordcount-1 and data words */
1652 cfi_command(bank, bufferwsize-1, command);
1653 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1654 {
1655 return retval;
1656 }
1657
1658 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1659 {
1660 return retval;
1661 }
1662
1663 /* Commit write operation */
1664 cfi_command(bank, 0xd0, command);
1665 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1666 {
1667 return retval;
1668 }
1669 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1670 {
1671 cfi_command(bank, 0xff, command);
1672 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1673 {
1674 return retval;
1675 }
1676
1677 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1678 return ERROR_FLASH_OPERATION_FAILED;
1679 }
1680
1681 return ERROR_OK;
1682 }
1683
1684 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1685 {
1686 int retval;
1687 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1688 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1689 struct target *target = bank->target;
1690 uint8_t command[8];
1691
1692 cfi_command(bank, 0xaa, command);
1693 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1694 {
1695 return retval;
1696 }
1697
1698 cfi_command(bank, 0x55, command);
1699 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1700 {
1701 return retval;
1702 }
1703
1704 cfi_command(bank, 0xa0, command);
1705 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1706 {
1707 return retval;
1708 }
1709
1710 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1711 {
1712 return retval;
1713 }
1714
1715 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1716 {
1717 cfi_command(bank, 0xf0, command);
1718 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1719 {
1720 return retval;
1721 }
1722
1723 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1724 return ERROR_FLASH_OPERATION_FAILED;
1725 }
1726
1727 return ERROR_OK;
1728 }
1729
1730 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1731 {
1732 int retval;
1733 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1734 struct target *target = bank->target;
1735 uint8_t command[8];
1736 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1737
1738 /* Calculate buffer size and boundary mask */
1739 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1740 uint32_t buffermask = buffersize-1;
1741 uint32_t bufferwsize;
1742
1743 /* Check for valid range */
1744 if (address & buffermask)
1745 {
1746 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1747 return ERROR_FLASH_OPERATION_FAILED;
1748 }
1749 switch (bank->chip_width)
1750 {
1751 case 4 : bufferwsize = buffersize / 4; break;
1752 case 2 : bufferwsize = buffersize / 2; break;
1753 case 1 : bufferwsize = buffersize; break;
1754 default:
1755 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1756 return ERROR_FLASH_OPERATION_FAILED;
1757 }
1758
1759 bufferwsize/=(bank->bus_width / bank->chip_width);
1760
1761 /* Check for valid size */
1762 if (wordcount > bufferwsize)
1763 {
1764 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1765 return ERROR_FLASH_OPERATION_FAILED;
1766 }
1767
1768 // Unlock
1769 cfi_command(bank, 0xaa, command);
1770 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1771 {
1772 return retval;
1773 }
1774
1775 cfi_command(bank, 0x55, command);
1776 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1777 {
1778 return retval;
1779 }
1780
1781 // Buffer load command
1782 cfi_command(bank, 0x25, command);
1783 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1784 {
1785 return retval;
1786 }
1787
1788 /* Write buffer wordcount-1 and data words */
1789 cfi_command(bank, bufferwsize-1, command);
1790 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1791 {
1792 return retval;
1793 }
1794
1795 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1796 {
1797 return retval;
1798 }
1799
1800 /* Commit write operation */
1801 cfi_command(bank, 0x29, command);
1802 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1803 {
1804 return retval;
1805 }
1806
1807 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1808 {
1809 cfi_command(bank, 0xf0, command);
1810 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1811 {
1812 return retval;
1813 }
1814
1815 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1816 return ERROR_FLASH_OPERATION_FAILED;
1817 }
1818
1819 return ERROR_OK;
1820 }
1821
1822 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1823 {
1824 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1825
1826 switch (cfi_info->pri_id)
1827 {
1828 case 1:
1829 case 3:
1830 return cfi_intel_write_word(bank, word, address);
1831 break;
1832 case 2:
1833 return cfi_spansion_write_word(bank, word, address);
1834 break;
1835 default:
1836 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1837 break;
1838 }
1839
1840 return ERROR_FLASH_OPERATION_FAILED;
1841 }
1842
1843 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1844 {
1845 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1846
1847 switch (cfi_info->pri_id)
1848 {
1849 case 1:
1850 case 3:
1851 return cfi_intel_write_words(bank, word, wordcount, address);
1852 break;
1853 case 2:
1854 return cfi_spansion_write_words(bank, word, wordcount, address);
1855 break;
1856 default:
1857 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1858 break;
1859 }
1860
1861 return ERROR_FLASH_OPERATION_FAILED;
1862 }
1863
1864 int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1865 {
1866 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1867 struct target *target = bank->target;
1868 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1869 uint32_t write_p, copy_p;
1870 int align; /* number of unaligned bytes */
1871 int blk_count; /* number of bus_width bytes for block copy */
1872 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1873 int i;
1874 int retval;
1875
1876 if (bank->target->state != TARGET_HALTED)
1877 {
1878 LOG_ERROR("Target not halted");
1879 return ERROR_TARGET_NOT_HALTED;
1880 }
1881
1882 if (offset + count > bank->size)
1883 return ERROR_FLASH_DST_OUT_OF_BANK;
1884
1885 if (cfi_info->qry[0] != 'Q')
1886 return ERROR_FLASH_BANK_NOT_PROBED;
1887
1888 /* start at the first byte of the first word (bus_width size) */
1889 write_p = address & ~(bank->bus_width - 1);
1890 if ((align = address - write_p) != 0)
1891 {
1892 LOG_INFO("Fixup %d unaligned head bytes", align);
1893
1894 for (i = 0; i < bank->bus_width; i++)
1895 current_word[i] = 0;
1896 copy_p = write_p;
1897
1898 /* copy bytes before the first write address */
1899 for (i = 0; i < align; ++i, ++copy_p)
1900 {
1901 uint8_t byte;
1902 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1903 {
1904 return retval;
1905 }
1906 cfi_add_byte(bank, current_word, byte);
1907 }
1908
1909 /* add bytes from the buffer */
1910 for (; (i < bank->bus_width) && (count > 0); i++)
1911 {
1912 cfi_add_byte(bank, current_word, *buffer++);
1913 count--;
1914 copy_p++;
1915 }
1916
1917 /* if the buffer is already finished, copy bytes after the last write address */
1918 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1919 {
1920 uint8_t byte;
1921 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1922 {
1923 return retval;
1924 }
1925 cfi_add_byte(bank, current_word, byte);
1926 }
1927
1928 retval = cfi_write_word(bank, current_word, write_p);
1929 if (retval != ERROR_OK)
1930 return retval;
1931 write_p = copy_p;
1932 }
1933
1934 /* handle blocks of bus_size aligned bytes */
1935 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1936 switch (cfi_info->pri_id)
1937 {
1938 /* try block writes (fails without working area) */
1939 case 1:
1940 case 3:
1941 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1942 break;
1943 case 2:
1944 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1945 break;
1946 default:
1947 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1948 retval = ERROR_FLASH_OPERATION_FAILED;
1949 break;
1950 }
1951 if (retval == ERROR_OK)
1952 {
1953 /* Increment pointers and decrease count on succesful block write */
1954 buffer += blk_count;
1955 write_p += blk_count;
1956 count -= blk_count;
1957 }
1958 else
1959 {
1960 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1961 {
1962 //adjust buffersize for chip width
1963 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1964 uint32_t buffermask = buffersize-1;
1965 uint32_t bufferwsize;
1966
1967 switch (bank->chip_width)
1968 {
1969 case 4 : bufferwsize = buffersize / 4; break;
1970 case 2 : bufferwsize = buffersize / 2; break;
1971 case 1 : bufferwsize = buffersize; break;
1972 default:
1973 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1974 return ERROR_FLASH_OPERATION_FAILED;
1975 }
1976
1977 bufferwsize/=(bank->bus_width / bank->chip_width);
1978
1979 /* fall back to memory writes */
1980 while (count >= (uint32_t)bank->bus_width)
1981 {
1982 int fallback;
1983 if ((write_p & 0xff) == 0)
1984 {
1985 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1986 }
1987 fallback = 1;
1988 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1989 {
1990 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1991 if (retval == ERROR_OK)
1992 {
1993 buffer += buffersize;
1994 write_p += buffersize;
1995 count -= buffersize;
1996 fallback = 0;
1997 }
1998 }
1999 /* try the slow way? */
2000 if (fallback)
2001 {
2002 for (i = 0; i < bank->bus_width; i++)
2003 current_word[i] = 0;
2004
2005 for (i = 0; i < bank->bus_width; i++)
2006 {
2007 cfi_add_byte(bank, current_word, *buffer++);
2008 }
2009
2010 retval = cfi_write_word(bank, current_word, write_p);
2011 if (retval != ERROR_OK)
2012 return retval;
2013
2014 write_p += bank->bus_width;
2015 count -= bank->bus_width;
2016 }
2017 }
2018 }
2019 else
2020 return retval;
2021 }
2022
2023 /* return to read array mode, so we can read from flash again for padding */
2024 cfi_command(bank, 0xf0, current_word);
2025 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2026 {
2027 return retval;
2028 }
2029 cfi_command(bank, 0xff, current_word);
2030 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2031 {
2032 return retval;
2033 }
2034
2035 /* handle unaligned tail bytes */
2036 if (count > 0)
2037 {
2038 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2039
2040 copy_p = write_p;
2041 for (i = 0; i < bank->bus_width; i++)
2042 current_word[i] = 0;
2043
2044 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2045 {
2046 cfi_add_byte(bank, current_word, *buffer++);
2047 count--;
2048 }
2049 for (; i < bank->bus_width; ++i, ++copy_p)
2050 {
2051 uint8_t byte;
2052 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2053 {
2054 return retval;
2055 }
2056 cfi_add_byte(bank, current_word, byte);
2057 }
2058 retval = cfi_write_word(bank, current_word, write_p);
2059 if (retval != ERROR_OK)
2060 return retval;
2061 }
2062
2063 /* return to read array mode */
2064 cfi_command(bank, 0xf0, current_word);
2065 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2066 {
2067 return retval;
2068 }
2069 cfi_command(bank, 0xff, current_word);
2070 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2071 }
2072
2073 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2074 {
2075 (void) param;
2076 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2077 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2078
2079 pri_ext->_reversed_geometry = 1;
2080 }
2081
2082 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2083 {
2084 int i;
2085 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2086 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2087 (void) param;
2088
2089 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2090 {
2091 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2092
2093 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2094 {
2095 int j = (cfi_info->num_erase_regions - 1) - i;
2096 uint32_t swap;
2097
2098 swap = cfi_info->erase_region_info[i];
2099 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2100 cfi_info->erase_region_info[j] = swap;
2101 }
2102 }
2103 }
2104
2105 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2106 {
2107 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2108 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2109 struct cfi_unlock_addresses *unlock_addresses = param;
2110
2111 pri_ext->_unlock1 = unlock_addresses->unlock1;
2112 pri_ext->_unlock2 = unlock_addresses->unlock2;
2113 }
2114
2115
2116 static int cfi_query_string(struct flash_bank *bank, int address)
2117 {
2118 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2119 struct target *target = bank->target;
2120 int retval;
2121 uint8_t command[8];
2122
2123 cfi_command(bank, 0x98, command);
2124 if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2125 {
2126 return retval;
2127 }
2128
2129 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2130 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2131 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2132
2133 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2134
2135 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2136 {
2137 cfi_command(bank, 0xf0, command);
2138 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2139 {
2140 return retval;
2141 }
2142 cfi_command(bank, 0xff, command);
2143 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2144 {
2145 return retval;
2146 }
2147 LOG_ERROR("Could not probe bank: no QRY");
2148 return ERROR_FLASH_BANK_INVALID;
2149 }
2150
2151 return ERROR_OK;
2152 }
2153
2154 static int cfi_probe(struct flash_bank *bank)
2155 {
2156 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2157 struct target *target = bank->target;
2158 uint8_t command[8];
2159 int num_sectors = 0;
2160 int i;
2161 int sector = 0;
2162 uint32_t unlock1 = 0x555;
2163 uint32_t unlock2 = 0x2aa;
2164 int retval;
2165
2166 if (bank->target->state != TARGET_HALTED)
2167 {
2168 LOG_ERROR("Target not halted");
2169 return ERROR_TARGET_NOT_HALTED;
2170 }
2171
2172 cfi_info->probed = 0;
2173
2174 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2175 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2176 */
2177 if (cfi_info->jedec_probe)
2178 {
2179 unlock1 = 0x5555;
2180 unlock2 = 0x2aaa;
2181 }
2182
2183 /* switch to read identifier codes mode ("AUTOSELECT") */
2184 cfi_command(bank, 0xaa, command);
2185 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2186 {
2187 return retval;
2188 }
2189 cfi_command(bank, 0x55, command);
2190 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2191 {
2192 return retval;
2193 }
2194 cfi_command(bank, 0x90, command);
2195 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2196 {
2197 return retval;
2198 }
2199
2200 if (bank->chip_width == 1)
2201 {
2202 uint8_t manufacturer, device_id;
2203 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2204 {
2205 return retval;
2206 }
2207 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2208 {
2209 return retval;
2210 }
2211 cfi_info->manufacturer = manufacturer;
2212 cfi_info->device_id = device_id;
2213 }
2214 else if (bank->chip_width == 2)
2215 {
2216 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2217 {
2218 return retval;
2219 }
2220 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2221 {
2222 return retval;
2223 }
2224 }
2225
2226 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2227 /* switch back to read array mode */
2228 cfi_command(bank, 0xf0, command);
2229 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2230 {
2231 return retval;
2232 }
2233 cfi_command(bank, 0xff, command);
2234 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2235 {
2236 return retval;
2237 }
2238
2239 /* check device/manufacturer ID for known non-CFI flashes. */
2240 cfi_fixup_non_cfi(bank);
2241
2242 /* query only if this is a CFI compatible flash,
2243 * otherwise the relevant info has already been filled in
2244 */
2245 if (cfi_info->not_cfi == 0)
2246 {
2247 int retval;
2248
2249 /* enter CFI query mode
2250 * according to JEDEC Standard No. 68.01,
2251 * a single bus sequence with address = 0x55, data = 0x98 should put
2252 * the device into CFI query mode.
2253 *
2254 * SST flashes clearly violate this, and we will consider them incompatbile for now
2255 */
2256
2257 retval = cfi_query_string(bank, 0x55);
2258 if (retval != ERROR_OK)
2259 {
2260 /*
2261 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2262 * be harmless enough:
2263 *
2264 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2265 */
2266 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2267 retval = cfi_query_string(bank, 0x555);
2268 }
2269 if (retval != ERROR_OK)
2270 return retval;
2271
2272 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2273 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2274 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2275 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2276
2277 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2278
2279 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2280 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2281 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2282 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2283 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2284 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2285 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2286 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2287 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2288 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2289 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2290 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2291
2292 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2293 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2294 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2295 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2296 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2297 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2298 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2299 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2300 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2301 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2302 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2303
2304 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2305 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2306 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2307 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2308
2309 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2310
2311 if (cfi_info->num_erase_regions)
2312 {
2313 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2314 for (i = 0; i < cfi_info->num_erase_regions; i++)
2315 {
2316 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2317 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2318 i,
2319 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2320 (cfi_info->erase_region_info[i] >> 16) * 256);
2321 }
2322 }
2323 else
2324 {
2325 cfi_info->erase_region_info = NULL;
2326 }
2327
2328 /* We need to read the primary algorithm extended query table before calculating
2329 * the sector layout to be able to apply fixups
2330 */
2331 switch (cfi_info->pri_id)
2332 {
2333 /* Intel command set (standard and extended) */
2334 case 0x0001:
2335 case 0x0003:
2336 cfi_read_intel_pri_ext(bank);
2337 break;
2338 /* AMD/Spansion, Atmel, ... command set */
2339 case 0x0002:
2340 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2341 cfi_read_0002_pri_ext(bank);
2342 break;
2343 default:
2344 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2345 break;
2346 }
2347
2348 /* return to read array mode
2349 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2350 */
2351 cfi_command(bank, 0xf0, command);
2352 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2353 {
2354 return retval;
2355 }
2356 cfi_command(bank, 0xff, command);
2357 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2358 {
2359 return retval;
2360 }
2361 } /* end CFI case */
2362
2363 /* apply fixups depending on the primary command set */
2364 switch (cfi_info->pri_id)
2365 {
2366 /* Intel command set (standard and extended) */
2367 case 0x0001:
2368 case 0x0003:
2369 cfi_fixup(bank, cfi_0001_fixups);
2370 break;
2371 /* AMD/Spansion, Atmel, ... command set */
2372 case 0x0002:
2373 cfi_fixup(bank, cfi_0002_fixups);
2374 break;
2375 default:
2376 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2377 break;
2378 }
2379
2380 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2381 {
2382 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2383 }
2384
2385 if (cfi_info->num_erase_regions == 0)
2386 {
2387 /* a device might have only one erase block, spanning the whole device */
2388 bank->num_sectors = 1;
2389 bank->sectors = malloc(sizeof(struct flash_sector));
2390
2391 bank->sectors[sector].offset = 0x0;
2392 bank->sectors[sector].size = bank->size;
2393 bank->sectors[sector].is_erased = -1;
2394 bank->sectors[sector].is_protected = -1;
2395 }
2396 else
2397 {
2398 uint32_t offset = 0;
2399
2400 for (i = 0; i < cfi_info->num_erase_regions; i++)
2401 {
2402 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2403 }
2404
2405 bank->num_sectors = num_sectors;
2406 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2407
2408 for (i = 0; i < cfi_info->num_erase_regions; i++)
2409 {
2410 uint32_t j;
2411 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2412 {
2413 bank->sectors[sector].offset = offset;
2414 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2415 offset += bank->sectors[sector].size;
2416 bank->sectors[sector].is_erased = -1;
2417 bank->sectors[sector].is_protected = -1;
2418 sector++;
2419 }
2420 }
2421 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2422 {
2423 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2424 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2425 }
2426 }
2427
2428 cfi_info->probed = 1;
2429
2430 return ERROR_OK;
2431 }
2432
2433 static int cfi_auto_probe(struct flash_bank *bank)
2434 {
2435 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2436 if (cfi_info->probed)
2437 return ERROR_OK;
2438 return cfi_probe(bank);
2439 }
2440
2441
2442 static int cfi_intel_protect_check(struct flash_bank *bank)
2443 {
2444 int retval;
2445 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2446 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2447 struct target *target = bank->target;
2448 uint8_t command[CFI_MAX_BUS_WIDTH];
2449 int i;
2450
2451 /* check if block lock bits are supported on this device */
2452 if (!(pri_ext->blk_status_reg_mask & 0x1))
2453 return ERROR_FLASH_OPERATION_FAILED;
2454
2455 cfi_command(bank, 0x90, command);
2456 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2457 {
2458 return retval;
2459 }
2460
2461 for (i = 0; i < bank->num_sectors; i++)
2462 {
2463 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2464
2465 if (block_status & 1)
2466 bank->sectors[i].is_protected = 1;
2467 else
2468 bank->sectors[i].is_protected = 0;
2469 }
2470
2471 cfi_command(bank, 0xff, command);
2472 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2473 }
2474
2475 static int cfi_spansion_protect_check(struct flash_bank *bank)
2476 {
2477 int retval;
2478 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2479 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2480 struct target *target = bank->target;
2481 uint8_t command[8];
2482 int i;
2483
2484 cfi_command(bank, 0xaa, command);
2485 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2486 {
2487 return retval;
2488 }
2489
2490 cfi_command(bank, 0x55, command);
2491 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2492 {
2493 return retval;
2494 }
2495
2496 cfi_command(bank, 0x90, command);
2497 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2498 {
2499 return retval;
2500 }
2501
2502 for (i = 0; i < bank->num_sectors; i++)
2503 {
2504 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2505
2506 if (block_status & 1)
2507 bank->sectors[i].is_protected = 1;
2508 else
2509 bank->sectors[i].is_protected = 0;
2510 }
2511
2512 cfi_command(bank, 0xf0, command);
2513 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2514 }
2515
2516 static int cfi_protect_check(struct flash_bank *bank)
2517 {
2518 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2519
2520 if (bank->target->state != TARGET_HALTED)
2521 {
2522 LOG_ERROR("Target not halted");
2523 return ERROR_TARGET_NOT_HALTED;
2524 }
2525
2526 if (cfi_info->qry[0] != 'Q')
2527 return ERROR_FLASH_BANK_NOT_PROBED;
2528
2529 switch (cfi_info->pri_id)
2530 {
2531 case 1:
2532 case 3:
2533 return cfi_intel_protect_check(bank);
2534 break;
2535 case 2:
2536 return cfi_spansion_protect_check(bank);
2537 break;
2538 default:
2539 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2540 break;
2541 }
2542
2543 return ERROR_OK;
2544 }
2545
2546 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2547 {
2548 int printed;
2549 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2550
2551 if (cfi_info->qry[0] == (char)-1)
2552 {
2553 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2554 return ERROR_OK;
2555 }
2556
2557 if (cfi_info->not_cfi == 0)
2558 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2559 else
2560 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2561 buf += printed;
2562 buf_size -= printed;
2563
2564 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2565 cfi_info->manufacturer, cfi_info->device_id);
2566 buf += printed;
2567 buf_size -= printed;
2568
2569 if (cfi_info->not_cfi == 0)
2570 {
2571 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2572 buf += printed;
2573 buf_size -= printed;
2574
2575 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2576 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2577 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2578 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2579 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2580 buf += printed;
2581 buf_size -= printed;
2582
2583 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2584 1 << cfi_info->word_write_timeout_typ,
2585 1 << cfi_info->buf_write_timeout_typ,
2586 1 << cfi_info->block_erase_timeout_typ,
2587 1 << cfi_info->chip_erase_timeout_typ);
2588 buf += printed;
2589 buf_size -= printed;
2590
2591 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2592 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2593 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2594 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2595 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2596 buf += printed;
2597 buf_size -= printed;
2598
2599 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2600 cfi_info->dev_size,
2601 cfi_info->interface_desc,
2602 1 << cfi_info->max_buf_write_size);
2603 buf += printed;
2604 buf_size -= printed;
2605
2606 switch (cfi_info->pri_id)
2607 {
2608 case 1:
2609 case 3:
2610 cfi_intel_info(bank, buf, buf_size);
2611 break;
2612 case 2:
2613 cfi_spansion_info(bank, buf, buf_size);
2614 break;
2615 default:
2616 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2617 break;
2618 }
2619 }
2620
2621 return ERROR_OK;
2622 }
2623
2624 struct flash_driver cfi_flash = {
2625 .name = "cfi",
2626 .register_commands = &cfi_register_commands,
2627 .flash_bank_command = &cfi_flash_bank_command,
2628 .erase = &cfi_erase,
2629 .protect = &cfi_protect,
2630 .write = &cfi_write,
2631 .probe = &cfi_probe,
2632 .auto_probe = &cfi_auto_probe,
2633 .erase_check = &default_flash_blank_check,
2634 .protect_check = &cfi_protect_check,
2635 .info = &cfi_info,
2636 };
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