b11aae94206ef5992e154bffff8e157c1d08ddec
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28
29 #include "flash.h"
30 #include "target.h"
31 #include "log.h"
32 #include "armv4_5.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
35 #include "types.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39 #include <unistd.h>
40
41 int cfi_register_commands(struct command_context_s *cmd_ctx);
42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int cfi_probe(struct flash_bank_s *bank);
47 int cfi_auto_probe(struct flash_bank_s *bank);
48 int cfi_erase_check(struct flash_bank_s *bank);
49 int cfi_protect_check(struct flash_bank_s *bank);
50 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
51
52 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 #define CFI_MAX_BUS_WIDTH 4
55 #define CFI_MAX_CHIP_WIDTH 4
56
57 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
58 #define CFI_MAX_INTEL_CODESIZE 256
59
60 flash_driver_t cfi_flash =
61 {
62 .name = "cfi",
63 .register_commands = cfi_register_commands,
64 .flash_bank_command = cfi_flash_bank_command,
65 .erase = cfi_erase,
66 .protect = cfi_protect,
67 .write = cfi_write,
68 .probe = cfi_probe,
69 .auto_probe = cfi_auto_probe,
70 .erase_check = cfi_erase_check,
71 .protect_check = cfi_protect_check,
72 .info = cfi_info
73 };
74
75 cfi_unlock_addresses_t cfi_unlock_addresses[] =
76 {
77 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
78 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
79 };
80
81 /* CFI fixups foward declarations */
82 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
83 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
84 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
85
86 /* fixup after identifying JEDEC manufactuer and ID */
87 cfi_fixup_t cfi_jedec_fixups[] = {
88 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
94 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
95 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
96 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
97 {0, 0, NULL, NULL}
98 };
99
100 /* fixup after reading cmdset 0002 primary query table */
101 cfi_fixup_t cfi_0002_fixups[] = {
102 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
103 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
104 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
105 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
106 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
107 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
108 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
109 {0, 0, NULL, NULL}
110 };
111
112 /* fixup after reading cmdset 0001 primary query table */
113 cfi_fixup_t cfi_0001_fixups[] = {
114 {0, 0, NULL, NULL}
115 };
116
117 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
118 {
119 cfi_flash_bank_t *cfi_info = bank->driver_priv;
120 cfi_fixup_t *f;
121
122 for (f = fixups; f->fixup; f++)
123 {
124 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
125 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
126 {
127 f->fixup(bank, f->param);
128 }
129 }
130 }
131
132 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
133 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
134 {
135 /* while the sector list isn't built, only accesses to sector 0 work */
136 if (sector == 0)
137 return bank->base + offset * bank->bus_width;
138 else
139 {
140 if (!bank->sectors)
141 {
142 ERROR("BUG: sector list not yet built");
143 exit(-1);
144 }
145 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
146 }
147
148 }
149
150 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
151 {
152 int i;
153
154 /* clear whole buffer, to ensure bits that exceed the bus_width
155 * are set to zero
156 */
157 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
158 cmd_buf[i] = 0;
159
160 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
161 {
162 for (i = bank->bus_width; i > 0; i--)
163 {
164 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
165 }
166 }
167 else
168 {
169 for (i = 1; i <= bank->bus_width; i++)
170 {
171 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
172 }
173 }
174 }
175
176 /* read unsigned 8-bit value from the bank
177 * flash banks are expected to be made of similar chips
178 * the query result should be the same for all
179 */
180 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
181 {
182 target_t *target = bank->target;
183 u8 data[CFI_MAX_BUS_WIDTH];
184
185 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
186
187 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
188 return data[0];
189 else
190 return data[bank->bus_width - 1];
191 }
192
193 /* read unsigned 8-bit value from the bank
194 * in case of a bank made of multiple chips,
195 * the individual values are ORed
196 */
197 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
198 {
199 target_t *target = bank->target;
200 u8 data[CFI_MAX_BUS_WIDTH];
201 int i;
202
203 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
204
205 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
206 {
207 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
208 data[0] |= data[i];
209
210 return data[0];
211 }
212 else
213 {
214 u8 value = 0;
215 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
216 value |= data[bank->bus_width - 1 - i];
217
218 return value;
219 }
220 }
221
222 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
223 {
224 target_t *target = bank->target;
225 u8 data[CFI_MAX_BUS_WIDTH * 2];
226
227 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
228
229 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
230 return data[0] | data[bank->bus_width] << 8;
231 else
232 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
233 }
234
235 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
236 {
237 target_t *target = bank->target;
238 u8 data[CFI_MAX_BUS_WIDTH * 4];
239
240 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
241
242 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
243 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
244 else
245 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
246 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
247 }
248
249 void cfi_intel_clear_status_register(flash_bank_t *bank)
250 {
251 target_t *target = bank->target;
252 u8 command[8];
253
254 if (target->state != TARGET_HALTED)
255 {
256 ERROR("BUG: attempted to clear status register while target wasn't halted");
257 exit(-1);
258 }
259
260 cfi_command(bank, 0x50, command);
261 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
262 }
263
264 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
265 {
266 u8 status;
267
268 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
269 {
270 DEBUG("status: 0x%x", status);
271 usleep(1000);
272 }
273
274 /* mask out bit 0 (reserved) */
275 status = status & 0xfe;
276
277 DEBUG("status: 0x%x", status);
278
279 if ((status & 0x80) != 0x80)
280 {
281 ERROR("timeout while waiting for WSM to become ready");
282 }
283 else if (status != 0x80)
284 {
285 ERROR("status register: 0x%x", status);
286 if (status & 0x2)
287 ERROR("Block Lock-Bit Detected, Operation Abort");
288 if (status & 0x4)
289 ERROR("Program suspended");
290 if (status & 0x8)
291 ERROR("Low Programming Voltage Detected, Operation Aborted");
292 if (status & 0x10)
293 ERROR("Program Error / Error in Setting Lock-Bit");
294 if (status & 0x20)
295 ERROR("Error in Block Erasure or Clear Lock-Bits");
296 if (status & 0x40)
297 ERROR("Block Erase Suspended");
298
299 cfi_intel_clear_status_register(bank);
300 }
301
302 return status;
303 }
304
305 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
306 {
307 u8 status, oldstatus;
308
309 oldstatus = cfi_get_u8(bank, 0, 0x0);
310
311 do {
312 status = cfi_get_u8(bank, 0, 0x0);
313 if ((status ^ oldstatus) & 0x40) {
314 if (status & 0x20) {
315 oldstatus = cfi_get_u8(bank, 0, 0x0);
316 status = cfi_get_u8(bank, 0, 0x0);
317 if ((status ^ oldstatus) & 0x40) {
318 ERROR("dq5 timeout, status: 0x%x", status);
319 return(ERROR_FLASH_OPERATION_FAILED);
320 } else {
321 DEBUG("status: 0x%x", status);
322 return(ERROR_OK);
323 }
324 }
325 } else {
326 DEBUG("status: 0x%x", status);
327 return(ERROR_OK);
328 }
329
330 oldstatus = status;
331 usleep(1000);
332 } while (timeout-- > 0);
333
334 ERROR("timeout, status: 0x%x", status);
335
336 return(ERROR_FLASH_BUSY);
337 }
338
339 int cfi_read_intel_pri_ext(flash_bank_t *bank)
340 {
341 cfi_flash_bank_t *cfi_info = bank->driver_priv;
342 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
343 target_t *target = bank->target;
344 u8 command[8];
345
346 cfi_info->pri_ext = pri_ext;
347
348 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
349 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
350 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
351
352 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
353 {
354 cfi_command(bank, 0xf0, command);
355 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
356 cfi_command(bank, 0xff, command);
357 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
358 return ERROR_FLASH_BANK_INVALID;
359 }
360
361 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
362 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
363
364 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
365
366 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
367 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
368 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
369
370 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
371
372 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
373 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
374
375 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
376 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
377 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
378
379 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
380 if (pri_ext->num_protection_fields != 1)
381 {
382 WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
383 }
384
385 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
386 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
387 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
388
389 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
390
391 return ERROR_OK;
392 }
393
394 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
395 {
396 cfi_flash_bank_t *cfi_info = bank->driver_priv;
397 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
398 target_t *target = bank->target;
399 u8 command[8];
400
401 cfi_info->pri_ext = pri_ext;
402
403 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
404 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
405 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
406
407 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
408 {
409 cfi_command(bank, 0xf0, command);
410 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
411 return ERROR_FLASH_BANK_INVALID;
412 }
413
414 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
415 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
416
417 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
418
419 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
420 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
421 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
422 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
423 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
424 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
425 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
426 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
427 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
428 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
429 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
430
431 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
432 pri_ext->EraseSuspend, pri_ext->BlkProt);
433
434 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
435 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
436
437 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
438
439
440 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
441 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
442 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
443
444 DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
445
446 /* default values for implementation specific workarounds */
447 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
448 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
449 pri_ext->_reversed_geometry = 0;
450
451 return ERROR_OK;
452 }
453
454 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
455 {
456 cfi_atmel_pri_ext_t atmel_pri_ext;
457 cfi_flash_bank_t *cfi_info = bank->driver_priv;
458 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
459 target_t *target = bank->target;
460 u8 command[8];
461
462 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
463 * but a different primary extended query table.
464 * We read the atmel table, and prepare a valid AMD/Spansion query table.
465 */
466
467 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
468
469 cfi_info->pri_ext = pri_ext;
470
471 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
472 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
473 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
474
475 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
476 {
477 cfi_command(bank, 0xf0, command);
478 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
479 return ERROR_FLASH_BANK_INVALID;
480 }
481
482 pri_ext->pri[0] = atmel_pri_ext.pri[0];
483 pri_ext->pri[1] = atmel_pri_ext.pri[1];
484 pri_ext->pri[2] = atmel_pri_ext.pri[2];
485
486 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
487 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
488
489 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
490
491 pri_ext->major_version = atmel_pri_ext.major_version;
492 pri_ext->minor_version = atmel_pri_ext.minor_version;
493
494 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
495 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
496 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
497 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
498
499 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
500 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
501
502 if (atmel_pri_ext.features & 0x02)
503 pri_ext->EraseSuspend = 2;
504
505 if (atmel_pri_ext.bottom_boot)
506 pri_ext->TopBottom = 2;
507 else
508 pri_ext->TopBottom = 3;
509
510 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
511 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
512
513 return ERROR_OK;
514 }
515
516 int cfi_read_0002_pri_ext(flash_bank_t *bank)
517 {
518 cfi_flash_bank_t *cfi_info = bank->driver_priv;
519
520 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
521 {
522 return cfi_read_atmel_pri_ext(bank);
523 }
524 else
525 {
526 return cfi_read_spansion_pri_ext(bank);
527 }
528 }
529
530 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
531 {
532 int printed;
533 cfi_flash_bank_t *cfi_info = bank->driver_priv;
534 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
535
536 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
537 buf += printed;
538 buf_size -= printed;
539
540 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
541 pri_ext->pri[1], pri_ext->pri[2],
542 pri_ext->major_version, pri_ext->minor_version);
543 buf += printed;
544 buf_size -= printed;
545
546 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
547 (pri_ext->SiliconRevision) >> 2,
548 (pri_ext->SiliconRevision) & 0x03);
549 buf += printed;
550 buf_size -= printed;
551
552 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
553 pri_ext->EraseSuspend,
554 pri_ext->BlkProt);
555 buf += printed;
556 buf_size -= printed;
557
558 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
559 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
560 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
561
562 return ERROR_OK;
563 }
564
565 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
566 {
567 int printed;
568 cfi_flash_bank_t *cfi_info = bank->driver_priv;
569 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
570
571 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
572 buf += printed;
573 buf_size -= printed;
574
575 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
576 buf += printed;
577 buf_size -= printed;
578
579 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
580 buf += printed;
581 buf_size -= printed;
582
583 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
584 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
585 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
586 buf += printed;
587 buf_size -= printed;
588
589 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
590
591 return ERROR_OK;
592 }
593
594 int cfi_register_commands(struct command_context_s *cmd_ctx)
595 {
596 /*command_t *cfi_cmd = */
597 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
598 /*
599 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
600 "print part id of cfi flash bank <num>");
601 */
602 return ERROR_OK;
603 }
604
605 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
606 */
607 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
608 {
609 cfi_flash_bank_t *cfi_info;
610 int i;
611
612 if (argc < 6)
613 {
614 WARNING("incomplete flash_bank cfi configuration");
615 return ERROR_FLASH_BANK_INVALID;
616 }
617
618 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
619 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
620 {
621 ERROR("chip and bus width have to specified in bytes");
622 return ERROR_FLASH_BANK_INVALID;
623 }
624
625 cfi_info = malloc(sizeof(cfi_flash_bank_t));
626 cfi_info->probed = 0;
627 bank->driver_priv = cfi_info;
628
629 cfi_info->write_algorithm = NULL;
630 cfi_info->erase_check_algorithm = NULL;
631
632 cfi_info->x16_as_x8 = 0;
633 cfi_info->jedec_probe = 0;
634 cfi_info->not_cfi = 0;
635
636 for (i = 6; i < argc; i++)
637 {
638 if (strcmp(args[i], "x16_as_x8") == 0)
639 {
640 cfi_info->x16_as_x8 = 1;
641 }
642 else if (strcmp(args[i], "jedec_probe") == 0)
643 {
644 cfi_info->jedec_probe = 1;
645 }
646 }
647
648 cfi_info->write_algorithm = NULL;
649
650 /* bank wasn't probed yet */
651 cfi_info->qry[0] = -1;
652
653 return ERROR_OK;
654 }
655
656 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
657 {
658 cfi_flash_bank_t *cfi_info = bank->driver_priv;
659 target_t *target = bank->target;
660 u8 command[8];
661 int i;
662
663 cfi_intel_clear_status_register(bank);
664
665 for (i = first; i <= last; i++)
666 {
667 cfi_command(bank, 0x20, command);
668 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
669
670 cfi_command(bank, 0xd0, command);
671 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
672
673 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
674 bank->sectors[i].is_erased = 1;
675 else
676 {
677 cfi_command(bank, 0xff, command);
678 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
679
680 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
681 return ERROR_FLASH_OPERATION_FAILED;
682 }
683 }
684
685 cfi_command(bank, 0xff, command);
686 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
687
688 return ERROR_OK;
689 }
690
691 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
692 {
693 cfi_flash_bank_t *cfi_info = bank->driver_priv;
694 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
695 target_t *target = bank->target;
696 u8 command[8];
697 int i;
698
699 for (i = first; i <= last; i++)
700 {
701 cfi_command(bank, 0xaa, command);
702 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
703
704 cfi_command(bank, 0x55, command);
705 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
706
707 cfi_command(bank, 0x80, command);
708 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
709
710 cfi_command(bank, 0xaa, command);
711 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
712
713 cfi_command(bank, 0x55, command);
714 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
715
716 cfi_command(bank, 0x30, command);
717 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
718
719 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
720 bank->sectors[i].is_erased = 1;
721 else
722 {
723 cfi_command(bank, 0xf0, command);
724 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
725
726 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
727 return ERROR_FLASH_OPERATION_FAILED;
728 }
729 }
730
731 cfi_command(bank, 0xf0, command);
732 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
733
734 return ERROR_OK;
735 }
736
737 int cfi_erase(struct flash_bank_s *bank, int first, int last)
738 {
739 cfi_flash_bank_t *cfi_info = bank->driver_priv;
740
741 if (bank->target->state != TARGET_HALTED)
742 {
743 return ERROR_TARGET_NOT_HALTED;
744 }
745
746 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
747 {
748 return ERROR_FLASH_SECTOR_INVALID;
749 }
750
751 if (cfi_info->qry[0] != 'Q')
752 return ERROR_FLASH_BANK_NOT_PROBED;
753
754 switch(cfi_info->pri_id)
755 {
756 case 1:
757 case 3:
758 return cfi_intel_erase(bank, first, last);
759 break;
760 case 2:
761 return cfi_spansion_erase(bank, first, last);
762 break;
763 default:
764 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
765 break;
766 }
767
768 return ERROR_OK;
769 }
770
771 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
772 {
773 cfi_flash_bank_t *cfi_info = bank->driver_priv;
774 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
775 target_t *target = bank->target;
776 u8 command[8];
777 int retry = 0;
778 int i;
779
780 /* if the device supports neither legacy lock/unlock (bit 3) nor
781 * instant individual block locking (bit 5).
782 */
783 if (!(pri_ext->feature_support & 0x28))
784 return ERROR_FLASH_OPERATION_FAILED;
785
786 cfi_intel_clear_status_register(bank);
787
788 for (i = first; i <= last; i++)
789 {
790 cfi_command(bank, 0x60, command);
791 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
792 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
793 if (set)
794 {
795 cfi_command(bank, 0x01, command);
796 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
797 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
798 bank->sectors[i].is_protected = 1;
799 }
800 else
801 {
802 cfi_command(bank, 0xd0, command);
803 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
804 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
805 bank->sectors[i].is_protected = 0;
806 }
807
808 /* instant individual block locking doesn't require reading of the status register */
809 if (!(pri_ext->feature_support & 0x20))
810 {
811 /* Clear lock bits operation may take up to 1.4s */
812 cfi_intel_wait_status_busy(bank, 1400);
813 }
814 else
815 {
816 u8 block_status;
817 /* read block lock bit, to verify status */
818 cfi_command(bank, 0x90, command);
819 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
820 block_status = cfi_get_u8(bank, i, 0x2);
821
822 if ((block_status & 0x1) != set)
823 {
824 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
825 cfi_command(bank, 0x70, command);
826 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
827 cfi_intel_wait_status_busy(bank, 10);
828
829 if (retry > 10)
830 return ERROR_FLASH_OPERATION_FAILED;
831 else
832 {
833 i--;
834 retry++;
835 }
836 }
837 }
838 }
839
840 /* if the device doesn't support individual block lock bits set/clear,
841 * all blocks have been unlocked in parallel, so we set those that should be protected
842 */
843 if ((!set) && (!(pri_ext->feature_support & 0x20)))
844 {
845 for (i = 0; i < bank->num_sectors; i++)
846 {
847 if (bank->sectors[i].is_protected == 1)
848 {
849 cfi_intel_clear_status_register(bank);
850
851 cfi_command(bank, 0x60, command);
852 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
853
854 cfi_command(bank, 0x01, command);
855 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
856
857 cfi_intel_wait_status_busy(bank, 100);
858 }
859 }
860 }
861
862 cfi_command(bank, 0xff, command);
863 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
864
865 return ERROR_OK;
866 }
867
868 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
869 {
870 cfi_flash_bank_t *cfi_info = bank->driver_priv;
871
872 if (bank->target->state != TARGET_HALTED)
873 {
874 return ERROR_TARGET_NOT_HALTED;
875 }
876
877 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
878 {
879 return ERROR_FLASH_SECTOR_INVALID;
880 }
881
882 if (cfi_info->qry[0] != 'Q')
883 return ERROR_FLASH_BANK_NOT_PROBED;
884
885 switch(cfi_info->pri_id)
886 {
887 case 1:
888 case 3:
889 cfi_intel_protect(bank, set, first, last);
890 break;
891 default:
892 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
893 break;
894 }
895
896 return ERROR_OK;
897 }
898
899 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
900 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
901 {
902 /* target_t *target = bank->target; */
903
904 int i;
905
906 /* NOTE:
907 * The data to flash must not be changed in endian! We write a bytestrem in
908 * target byte order already. Only the control and status byte lane of the flash
909 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
910 * word (data seems to be in the upper or lower byte lane for u16 accesses).
911 */
912
913 #if 0
914 if (target->endianness == TARGET_LITTLE_ENDIAN)
915 {
916 #endif
917 /* shift bytes */
918 for (i = 0; i < bank->bus_width - 1; i++)
919 word[i] = word[i + 1];
920 word[bank->bus_width - 1] = byte;
921 #if 0
922 }
923 else
924 {
925 /* shift bytes */
926 for (i = bank->bus_width - 1; i > 0; i--)
927 word[i] = word[i - 1];
928 word[0] = byte;
929 }
930 #endif
931 }
932
933 /* Convert code image to target endian */
934 /* FIXME create general block conversion fcts in target.c?) */
935 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
936 {
937 u32 i;
938 for (i=0; i< count; i++)
939 {
940 target_buffer_set_u32(target, dest, *src);
941 dest+=4;
942 src++;
943 }
944 }
945
946 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
947 {
948 target_t *target = bank->target;
949
950 u8 buf[CFI_MAX_BUS_WIDTH];
951 cfi_command(bank, cmd, buf);
952 switch (bank->bus_width)
953 {
954 case 1 :
955 return buf[0];
956 break;
957 case 2 :
958 return target_buffer_get_u16(target, buf);
959 break;
960 case 4 :
961 return target_buffer_get_u32(target, buf);
962 break;
963 default :
964 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
965 return 0;
966 }
967 }
968
969 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
970 {
971 cfi_flash_bank_t *cfi_info = bank->driver_priv;
972 target_t *target = bank->target;
973 reg_param_t reg_params[7];
974 armv4_5_algorithm_t armv4_5_info;
975 working_area_t *source;
976 u32 buffer_size = 32768;
977 u32 write_command_val, busy_pattern_val, error_pattern_val;
978
979 /* algorithm register usage:
980 * r0: source address (in RAM)
981 * r1: target address (in Flash)
982 * r2: count
983 * r3: flash write command
984 * r4: status byte (returned to host)
985 * r5: busy test pattern
986 * r6: error test pattern
987 */
988
989 static const u32 word_32_code[] = {
990 0xe4904004, /* loop: ldr r4, [r0], #4 */
991 0xe5813000, /* str r3, [r1] */
992 0xe5814000, /* str r4, [r1] */
993 0xe5914000, /* busy: ldr r4, [r1] */
994 0xe0047005, /* and r7, r4, r5 */
995 0xe1570005, /* cmp r7, r5 */
996 0x1afffffb, /* bne busy */
997 0xe1140006, /* tst r4, r6 */
998 0x1a000003, /* bne done */
999 0xe2522001, /* subs r2, r2, #1 */
1000 0x0a000001, /* beq done */
1001 0xe2811004, /* add r1, r1 #4 */
1002 0xeafffff2, /* b loop */
1003 0xeafffffe /* done: b -2 */
1004 };
1005
1006 static const u32 word_16_code[] = {
1007 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1008 0xe1c130b0, /* strh r3, [r1] */
1009 0xe1c140b0, /* strh r4, [r1] */
1010 0xe1d140b0, /* busy ldrh r4, [r1] */
1011 0xe0047005, /* and r7, r4, r5 */
1012 0xe1570005, /* cmp r7, r5 */
1013 0x1afffffb, /* bne busy */
1014 0xe1140006, /* tst r4, r6 */
1015 0x1a000003, /* bne done */
1016 0xe2522001, /* subs r2, r2, #1 */
1017 0x0a000001, /* beq done */
1018 0xe2811002, /* add r1, r1 #2 */
1019 0xeafffff2, /* b loop */
1020 0xeafffffe /* done: b -2 */
1021 };
1022
1023 static const u32 word_8_code[] = {
1024 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1025 0xe5c13000, /* strb r3, [r1] */
1026 0xe5c14000, /* strb r4, [r1] */
1027 0xe5d14000, /* busy ldrb r4, [r1] */
1028 0xe0047005, /* and r7, r4, r5 */
1029 0xe1570005, /* cmp r7, r5 */
1030 0x1afffffb, /* bne busy */
1031 0xe1140006, /* tst r4, r6 */
1032 0x1a000003, /* bne done */
1033 0xe2522001, /* subs r2, r2, #1 */
1034 0x0a000001, /* beq done */
1035 0xe2811001, /* add r1, r1 #1 */
1036 0xeafffff2, /* b loop */
1037 0xeafffffe /* done: b -2 */
1038 };
1039 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1040 const u32 *target_code_src;
1041 int target_code_size;
1042 int retval = ERROR_OK;
1043
1044
1045 cfi_intel_clear_status_register(bank);
1046
1047 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1048 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1049 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1050
1051 /* If we are setting up the write_algorith, we need target_code_src */
1052 /* if not we only need target_code_size. */
1053 /* */
1054 /* However, we don't want to create multiple code paths, so we */
1055 /* do the unecessary evaluation of target_code_src, which the */
1056 /* compiler will probably nicely optimize away if not needed */
1057
1058 /* prepare algorithm code for target endian */
1059 switch (bank->bus_width)
1060 {
1061 case 1 :
1062 target_code_src = word_8_code;
1063 target_code_size = sizeof(word_8_code);
1064 break;
1065 case 2 :
1066 target_code_src = word_16_code;
1067 target_code_size = sizeof(word_16_code);
1068 break;
1069 case 4 :
1070 target_code_src = word_32_code;
1071 target_code_size = sizeof(word_32_code);
1072 break;
1073 default:
1074 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1075 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1076 }
1077
1078 /* flash write code */
1079 if (!cfi_info->write_algorithm)
1080 {
1081 if ( target_code_size > sizeof(target_code) )
1082 {
1083 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1084 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1085 }
1086 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1087
1088 /* Get memory for block write handler */
1089 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1090 if (retval != ERROR_OK)
1091 {
1092 WARNING("No working area available, can't do block memory writes");
1093 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1094 };
1095
1096 /* write algorithm code to working area */
1097 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1098 if (retval != ERROR_OK)
1099 {
1100 ERROR("Unable to write block write code to target");
1101 goto cleanup;
1102 }
1103 }
1104
1105 /* Get a workspace buffer for the data to flash starting with 32k size.
1106 Half size until buffer would be smaller 256 Bytem then fail back */
1107 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1108 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1109 {
1110 buffer_size /= 2;
1111 if (buffer_size <= 256)
1112 {
1113 WARNING("no large enough working area available, can't do block memory writes");
1114 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1115 goto cleanup;
1116 }
1117 };
1118
1119 /* setup algo registers */
1120 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1121 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1122 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1123 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1124 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1125 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1126 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1127
1128 /* prepare command and status register patterns */
1129 write_command_val = cfi_command_val(bank, 0x40);
1130 busy_pattern_val = cfi_command_val(bank, 0x80);
1131 error_pattern_val = cfi_command_val(bank, 0x7e);
1132
1133 INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1134
1135 /* Programming main loop */
1136 while (count > 0)
1137 {
1138 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1139 u32 wsm_error;
1140
1141 target_write_buffer(target, source->address, thisrun_count, buffer);
1142
1143 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1144 buf_set_u32(reg_params[1].value, 0, 32, address);
1145 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1146
1147 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1148 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1149 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1150
1151 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1152
1153 /* Execute algorithm, assume breakpoint for last instruction */
1154 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1155 cfi_info->write_algorithm->address,
1156 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1157 10000, /* 10s should be enough for max. 32k of data */
1158 &armv4_5_info);
1159
1160 /* On failure try a fall back to direct word writes */
1161 if (retval != ERROR_OK)
1162 {
1163 cfi_intel_clear_status_register(bank);
1164 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1165 retval = ERROR_FLASH_OPERATION_FAILED;
1166 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1167 /* FIXME To allow fall back or recovery, we must save the actual status
1168 somewhere, so that a higher level code can start recovery. */
1169 goto cleanup;
1170 }
1171
1172 /* Check return value from algo code */
1173 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1174 if (wsm_error)
1175 {
1176 /* read status register (outputs debug inforation) */
1177 cfi_intel_wait_status_busy(bank, 100);
1178 cfi_intel_clear_status_register(bank);
1179 retval = ERROR_FLASH_OPERATION_FAILED;
1180 goto cleanup;
1181 }
1182
1183 buffer += thisrun_count;
1184 address += thisrun_count;
1185 count -= thisrun_count;
1186 }
1187
1188 /* free up resources */
1189 cleanup:
1190 if (source)
1191 target_free_working_area(target, source);
1192
1193 if (cfi_info->write_algorithm)
1194 {
1195 target_free_working_area(target, cfi_info->write_algorithm);
1196 cfi_info->write_algorithm = NULL;
1197 }
1198
1199 destroy_reg_param(&reg_params[0]);
1200 destroy_reg_param(&reg_params[1]);
1201 destroy_reg_param(&reg_params[2]);
1202 destroy_reg_param(&reg_params[3]);
1203 destroy_reg_param(&reg_params[4]);
1204 destroy_reg_param(&reg_params[5]);
1205 destroy_reg_param(&reg_params[6]);
1206
1207 return retval;
1208 }
1209
1210 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1211 {
1212 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1213 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1214 target_t *target = bank->target;
1215 reg_param_t reg_params[10];
1216 armv4_5_algorithm_t armv4_5_info;
1217 working_area_t *source;
1218 u32 buffer_size = 32768;
1219 u32 status;
1220 int retval;
1221 int exit_code = ERROR_OK;
1222
1223 /* input parameters - */
1224 /* R0 = source address */
1225 /* R1 = destination address */
1226 /* R2 = number of writes */
1227 /* R3 = flash write command */
1228 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1229 /* output parameters - */
1230 /* R5 = 0x80 ok 0x00 bad */
1231 /* temp registers - */
1232 /* R6 = value read from flash to test status */
1233 /* R7 = holding register */
1234 /* unlock registers - */
1235 /* R8 = unlock1_addr */
1236 /* R9 = unlock1_cmd */
1237 /* R10 = unlock2_addr */
1238 /* R11 = unlock2_cmd */
1239
1240 static const u32 word_32_code[] = {
1241 /* 00008100 <sp_32_code>: */
1242 0xe4905004, /* ldr r5, [r0], #4 */
1243 0xe5889000, /* str r9, [r8] */
1244 0xe58ab000, /* str r11, [r10] */
1245 0xe5883000, /* str r3, [r8] */
1246 0xe5815000, /* str r5, [r1] */
1247 0xe1a00000, /* nop */
1248 /* */
1249 /* 00008110 <sp_32_busy>: */
1250 0xe5916000, /* ldr r6, [r1] */
1251 0xe0257006, /* eor r7, r5, r6 */
1252 0xe0147007, /* ands r7, r4, r7 */
1253 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1254 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1255 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1256 0xe5916000, /* ldr r6, [r1] */
1257 0xe0257006, /* eor r7, r5, r6 */
1258 0xe0147007, /* ands r7, r4, r7 */
1259 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1260 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1261 0x1a000004, /* bne 8154 <sp_32_done> */
1262 /* */
1263 /* 00008140 <sp_32_cont>: */
1264 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1265 0x03a05080, /* moveq r5, #128 ; 0x80 */
1266 0x0a000001, /* beq 8154 <sp_32_done> */
1267 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1268 0xeaffffe8, /* b 8100 <sp_32_code> */
1269 /* */
1270 /* 00008154 <sp_32_done>: */
1271 0xeafffffe /* b 8154 <sp_32_done> */
1272 };
1273
1274 static const u32 word_16_code[] = {
1275 /* 00008158 <sp_16_code>: */
1276 0xe0d050b2, /* ldrh r5, [r0], #2 */
1277 0xe1c890b0, /* strh r9, [r8] */
1278 0xe1cab0b0, /* strh r11, [r10] */
1279 0xe1c830b0, /* strh r3, [r8] */
1280 0xe1c150b0, /* strh r5, [r1] */
1281 0xe1a00000, /* nop (mov r0,r0) */
1282 /* */
1283 /* 00008168 <sp_16_busy>: */
1284 0xe1d160b0, /* ldrh r6, [r1] */
1285 0xe0257006, /* eor r7, r5, r6 */
1286 0xe0147007, /* ands r7, r4, r7 */
1287 0x0a000007, /* beq 8198 <sp_16_cont> */
1288 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1289 0x0afffff9, /* beq 8168 <sp_16_busy> */
1290 0xe1d160b0, /* ldrh r6, [r1] */
1291 0xe0257006, /* eor r7, r5, r6 */
1292 0xe0147007, /* ands r7, r4, r7 */
1293 0x0a000001, /* beq 8198 <sp_16_cont> */
1294 0xe3a05000, /* mov r5, #0 ; 0x0 */
1295 0x1a000004, /* bne 81ac <sp_16_done> */
1296 /* */
1297 /* 00008198 <sp_16_cont>: */
1298 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1299 0x03a05080, /* moveq r5, #128 ; 0x80 */
1300 0x0a000001, /* beq 81ac <sp_16_done> */
1301 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1302 0xeaffffe8, /* b 8158 <sp_16_code> */
1303 /* */
1304 /* 000081ac <sp_16_done>: */
1305 0xeafffffe /* b 81ac <sp_16_done> */
1306 };
1307
1308 static const u32 word_8_code[] = {
1309 /* 000081b0 <sp_16_code_end>: */
1310 0xe4d05001, /* ldrb r5, [r0], #1 */
1311 0xe5c89000, /* strb r9, [r8] */
1312 0xe5cab000, /* strb r11, [r10] */
1313 0xe5c83000, /* strb r3, [r8] */
1314 0xe5c15000, /* strb r5, [r1] */
1315 0xe1a00000, /* nop (mov r0,r0) */
1316 /* */
1317 /* 000081c0 <sp_8_busy>: */
1318 0xe5d16000, /* ldrb r6, [r1] */
1319 0xe0257006, /* eor r7, r5, r6 */
1320 0xe0147007, /* ands r7, r4, r7 */
1321 0x0a000007, /* beq 81f0 <sp_8_cont> */
1322 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1323 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1324 0xe5d16000, /* ldrb r6, [r1] */
1325 0xe0257006, /* eor r7, r5, r6 */
1326 0xe0147007, /* ands r7, r4, r7 */
1327 0x0a000001, /* beq 81f0 <sp_8_cont> */
1328 0xe3a05000, /* mov r5, #0 ; 0x0 */
1329 0x1a000004, /* bne 8204 <sp_8_done> */
1330 /* */
1331 /* 000081f0 <sp_8_cont>: */
1332 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1333 0x03a05080, /* moveq r5, #128 ; 0x80 */
1334 0x0a000001, /* beq 8204 <sp_8_done> */
1335 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1336 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1337 /* */
1338 /* 00008204 <sp_8_done>: */
1339 0xeafffffe /* b 8204 <sp_8_done> */
1340 };
1341
1342 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1343 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1344 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1345
1346 /* flash write code */
1347 if (!cfi_info->write_algorithm)
1348 {
1349 u8 *target_code;
1350 int target_code_size;
1351 const u32 *src;
1352
1353 /* convert bus-width dependent algorithm code to correct endiannes */
1354 switch (bank->bus_width)
1355 {
1356 case 1:
1357 src = word_8_code;
1358 target_code_size = sizeof(word_8_code);
1359 break;
1360 case 2:
1361 src = word_16_code;
1362 target_code_size = sizeof(word_16_code);
1363 break;
1364 case 4:
1365 src = word_32_code;
1366 target_code_size = sizeof(word_32_code);
1367 break;
1368 default:
1369 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1370 return ERROR_FLASH_OPERATION_FAILED;
1371 }
1372 target_code = malloc(target_code_size);
1373 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1374
1375 /* allocate working area */
1376 retval=target_alloc_working_area(target, target_code_size,
1377 &cfi_info->write_algorithm);
1378 if (retval != ERROR_OK)
1379 return retval;
1380
1381 /* write algorithm code to working area */
1382 target_write_buffer(target, cfi_info->write_algorithm->address,
1383 target_code_size, target_code);
1384
1385 free(target_code);
1386 }
1387 /* the following code still assumes target code is fixed 24*4 bytes */
1388
1389 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1390 {
1391 buffer_size /= 2;
1392 if (buffer_size <= 256)
1393 {
1394 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1395 if (cfi_info->write_algorithm)
1396 target_free_working_area(target, cfi_info->write_algorithm);
1397
1398 WARNING("not enough working area available, can't do block memory writes");
1399 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1400 }
1401 };
1402
1403 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1404 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1405 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1406 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1407 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1408 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1409 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1410 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1411 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1412 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1413
1414 while (count > 0)
1415 {
1416 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1417
1418 target_write_buffer(target, source->address, thisrun_count, buffer);
1419
1420 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1421 buf_set_u32(reg_params[1].value, 0, 32, address);
1422 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1423 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1424 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1425 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1426 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1427 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1428 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1429
1430 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1431 cfi_info->write_algorithm->address,
1432 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1433 10000, &armv4_5_info);
1434
1435 status = buf_get_u32(reg_params[5].value, 0, 32);
1436
1437 if ((retval != ERROR_OK) || status != 0x80)
1438 {
1439 DEBUG("status: 0x%x", status);
1440 exit_code = ERROR_FLASH_OPERATION_FAILED;
1441 break;
1442 }
1443
1444 buffer += thisrun_count;
1445 address += thisrun_count;
1446 count -= thisrun_count;
1447 }
1448
1449 target_free_working_area(target, source);
1450
1451 destroy_reg_param(&reg_params[0]);
1452 destroy_reg_param(&reg_params[1]);
1453 destroy_reg_param(&reg_params[2]);
1454 destroy_reg_param(&reg_params[3]);
1455 destroy_reg_param(&reg_params[4]);
1456 destroy_reg_param(&reg_params[5]);
1457 destroy_reg_param(&reg_params[6]);
1458 destroy_reg_param(&reg_params[7]);
1459 destroy_reg_param(&reg_params[8]);
1460 destroy_reg_param(&reg_params[9]);
1461
1462 return exit_code;
1463 }
1464
1465 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1466 {
1467 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1468 target_t *target = bank->target;
1469 u8 command[8];
1470
1471 cfi_intel_clear_status_register(bank);
1472 cfi_command(bank, 0x40, command);
1473 target->type->write_memory(target, address, bank->bus_width, 1, command);
1474
1475 target->type->write_memory(target, address, bank->bus_width, 1, word);
1476
1477 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1478 {
1479 cfi_command(bank, 0xff, command);
1480 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1481
1482 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1483 return ERROR_FLASH_OPERATION_FAILED;
1484 }
1485
1486 return ERROR_OK;
1487 }
1488
1489 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1490 {
1491 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1492 target_t *target = bank->target;
1493 u8 command[8];
1494
1495 /* Calculate buffer size and boundary mask */
1496 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1497 u32 buffermask = buffersize-1;
1498 u32 bufferwsize;
1499
1500 /* Check for valid range */
1501 if (address & buffermask)
1502 {
1503 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1504 return ERROR_FLASH_OPERATION_FAILED;
1505 }
1506 switch(bank->chip_width)
1507 {
1508 case 4 : bufferwsize = buffersize / 4; break;
1509 case 2 : bufferwsize = buffersize / 2; break;
1510 case 1 : bufferwsize = buffersize; break;
1511 default:
1512 ERROR("Unsupported chip width %d", bank->chip_width);
1513 return ERROR_FLASH_OPERATION_FAILED;
1514 }
1515
1516 /* Check for valid size */
1517 if (wordcount > bufferwsize)
1518 {
1519 ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1520 return ERROR_FLASH_OPERATION_FAILED;
1521 }
1522
1523 /* Write to flash buffer */
1524 cfi_intel_clear_status_register(bank);
1525
1526 /* Initiate buffer operation _*/
1527 cfi_command(bank, 0xE8, command);
1528 target->type->write_memory(target, address, bank->bus_width, 1, command);
1529 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1530 {
1531 cfi_command(bank, 0xff, command);
1532 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1533
1534 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1535 return ERROR_FLASH_OPERATION_FAILED;
1536 }
1537
1538 /* Write buffer wordcount-1 and data words */
1539 cfi_command(bank, bufferwsize-1, command);
1540 target->type->write_memory(target, address, bank->bus_width, 1, command);
1541
1542 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1543
1544 /* Commit write operation */
1545 cfi_command(bank, 0xd0, command);
1546 target->type->write_memory(target, address, bank->bus_width, 1, command);
1547 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1548 {
1549 cfi_command(bank, 0xff, command);
1550 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1551
1552 ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1553 return ERROR_FLASH_OPERATION_FAILED;
1554 }
1555
1556 return ERROR_OK;
1557 }
1558
1559 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1560 {
1561 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1562 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1563 target_t *target = bank->target;
1564 u8 command[8];
1565
1566 cfi_command(bank, 0xaa, command);
1567 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1568
1569 cfi_command(bank, 0x55, command);
1570 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1571
1572 cfi_command(bank, 0xa0, command);
1573 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1574
1575 target->type->write_memory(target, address, bank->bus_width, 1, word);
1576
1577 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1578 {
1579 cfi_command(bank, 0xf0, command);
1580 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1581
1582 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1583 return ERROR_FLASH_OPERATION_FAILED;
1584 }
1585
1586 return ERROR_OK;
1587 }
1588
1589 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1590 {
1591 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1592
1593 switch(cfi_info->pri_id)
1594 {
1595 case 1:
1596 case 3:
1597 return cfi_intel_write_word(bank, word, address);
1598 break;
1599 case 2:
1600 return cfi_spansion_write_word(bank, word, address);
1601 break;
1602 default:
1603 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1604 break;
1605 }
1606
1607 return ERROR_FLASH_OPERATION_FAILED;
1608 }
1609
1610 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1611 {
1612 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1613
1614 switch(cfi_info->pri_id)
1615 {
1616 case 1:
1617 case 3:
1618 return cfi_intel_write_words(bank, word, wordcount, address);
1619 break;
1620 case 2:
1621 /* return cfi_spansion_write_words(bank, word, address); */
1622 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1623 break;
1624 default:
1625 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1626 break;
1627 }
1628
1629 return ERROR_FLASH_OPERATION_FAILED;
1630 }
1631
1632 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1633 {
1634 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1635 target_t *target = bank->target;
1636 u32 address = bank->base + offset; /* address of first byte to be programmed */
1637 u32 write_p, copy_p;
1638 int align; /* number of unaligned bytes */
1639 int blk_count; /* number of bus_width bytes for block copy */
1640 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1641 int i;
1642 int retval;
1643
1644 if (bank->target->state != TARGET_HALTED)
1645 return ERROR_TARGET_NOT_HALTED;
1646
1647 if (offset + count > bank->size)
1648 return ERROR_FLASH_DST_OUT_OF_BANK;
1649
1650 if (cfi_info->qry[0] != 'Q')
1651 return ERROR_FLASH_BANK_NOT_PROBED;
1652
1653 /* start at the first byte of the first word (bus_width size) */
1654 write_p = address & ~(bank->bus_width - 1);
1655 if ((align = address - write_p) != 0)
1656 {
1657 INFO("Fixup %d unaligned head bytes", align );
1658
1659 for (i = 0; i < bank->bus_width; i++)
1660 current_word[i] = 0;
1661 copy_p = write_p;
1662
1663 /* copy bytes before the first write address */
1664 for (i = 0; i < align; ++i, ++copy_p)
1665 {
1666 u8 byte;
1667 target->type->read_memory(target, copy_p, 1, 1, &byte);
1668 cfi_add_byte(bank, current_word, byte);
1669 }
1670
1671 /* add bytes from the buffer */
1672 for (; (i < bank->bus_width) && (count > 0); i++)
1673 {
1674 cfi_add_byte(bank, current_word, *buffer++);
1675 count--;
1676 copy_p++;
1677 }
1678
1679 /* if the buffer is already finished, copy bytes after the last write address */
1680 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1681 {
1682 u8 byte;
1683 target->type->read_memory(target, copy_p, 1, 1, &byte);
1684 cfi_add_byte(bank, current_word, byte);
1685 }
1686
1687 retval = cfi_write_word(bank, current_word, write_p);
1688 if (retval != ERROR_OK)
1689 return retval;
1690 write_p = copy_p;
1691 }
1692
1693 /* handle blocks of bus_size aligned bytes */
1694 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1695 switch(cfi_info->pri_id)
1696 {
1697 /* try block writes (fails without working area) */
1698 case 1:
1699 case 3:
1700 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1701 break;
1702 case 2:
1703 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1704 break;
1705 default:
1706 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1707 retval = ERROR_FLASH_OPERATION_FAILED;
1708 break;
1709 }
1710 if (retval == ERROR_OK)
1711 {
1712 /* Increment pointers and decrease count on succesful block write */
1713 buffer += blk_count;
1714 write_p += blk_count;
1715 count -= blk_count;
1716 }
1717 else
1718 {
1719 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1720 {
1721 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1722 u32 buffermask = buffersize-1;
1723 u32 bufferwsize;
1724
1725 switch(bank->chip_width)
1726 {
1727 case 4 : bufferwsize = buffersize / 4; break;
1728 case 2 : bufferwsize = buffersize / 2; break;
1729 case 1 : bufferwsize = buffersize; break;
1730 default:
1731 ERROR("Unsupported chip width %d", bank->chip_width);
1732 return ERROR_FLASH_OPERATION_FAILED;
1733 }
1734
1735 /* fall back to memory writes */
1736 while (count >= bank->bus_width)
1737 {
1738 if ((write_p & 0xff) == 0)
1739 {
1740 INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1741 }
1742 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1743 {
1744 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1745 if (retval != ERROR_OK)
1746 return retval;
1747
1748 buffer += buffersize;
1749 write_p += buffersize;
1750 count -= buffersize;
1751 }
1752 else
1753 {
1754 for (i = 0; i < bank->bus_width; i++)
1755 current_word[i] = 0;
1756
1757 for (i = 0; i < bank->bus_width; i++)
1758 {
1759 cfi_add_byte(bank, current_word, *buffer++);
1760 }
1761
1762 retval = cfi_write_word(bank, current_word, write_p);
1763 if (retval != ERROR_OK)
1764 return retval;
1765
1766 write_p += bank->bus_width;
1767 count -= bank->bus_width;
1768 }
1769 }
1770 }
1771 else
1772 return retval;
1773 }
1774
1775 /* return to read array mode, so we can read from flash again for padding */
1776 cfi_command(bank, 0xf0, current_word);
1777 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1778 cfi_command(bank, 0xff, current_word);
1779 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1780
1781 /* handle unaligned tail bytes */
1782 if (count > 0)
1783 {
1784 INFO("Fixup %d unaligned tail bytes", count );
1785
1786 copy_p = write_p;
1787 for (i = 0; i < bank->bus_width; i++)
1788 current_word[i] = 0;
1789
1790 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1791 {
1792 cfi_add_byte(bank, current_word, *buffer++);
1793 count--;
1794 }
1795 for (; i < bank->bus_width; ++i, ++copy_p)
1796 {
1797 u8 byte;
1798 target->type->read_memory(target, copy_p, 1, 1, &byte);
1799 cfi_add_byte(bank, current_word, byte);
1800 }
1801 retval = cfi_write_word(bank, current_word, write_p);
1802 if (retval != ERROR_OK)
1803 return retval;
1804 }
1805
1806 /* return to read array mode */
1807 cfi_command(bank, 0xf0, current_word);
1808 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1809 cfi_command(bank, 0xff, current_word);
1810 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1811
1812 return ERROR_OK;
1813 }
1814
1815 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1816 {
1817 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1818 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1819
1820 pri_ext->_reversed_geometry = 1;
1821 }
1822
1823 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1824 {
1825 int i;
1826 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1827 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1828
1829 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1830 {
1831 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1832
1833 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1834 {
1835 int j = (cfi_info->num_erase_regions - 1) - i;
1836 u32 swap;
1837
1838 swap = cfi_info->erase_region_info[i];
1839 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1840 cfi_info->erase_region_info[j] = swap;
1841 }
1842 }
1843 }
1844
1845 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1846 {
1847 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1848 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1849 cfi_unlock_addresses_t *unlock_addresses = param;
1850
1851 pri_ext->_unlock1 = unlock_addresses->unlock1;
1852 pri_ext->_unlock2 = unlock_addresses->unlock2;
1853 }
1854
1855 int cfi_probe(struct flash_bank_s *bank)
1856 {
1857 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1858 target_t *target = bank->target;
1859 u8 command[8];
1860 int num_sectors = 0;
1861 int i;
1862 int sector = 0;
1863 u32 offset = 0;
1864 u32 unlock1 = 0x555;
1865 u32 unlock2 = 0x2aa;
1866
1867 if (bank->target->state != TARGET_HALTED)
1868 {
1869 return ERROR_TARGET_NOT_HALTED;
1870 }
1871
1872 cfi_info->probed = 0;
1873
1874 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1875 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1876 */
1877 if (cfi_info->jedec_probe)
1878 {
1879 unlock1 = 0x5555;
1880 unlock2 = 0x2aaa;
1881 }
1882
1883 /* switch to read identifier codes mode ("AUTOSELECT") */
1884 cfi_command(bank, 0xaa, command);
1885 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1886 cfi_command(bank, 0x55, command);
1887 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1888 cfi_command(bank, 0x90, command);
1889 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1890
1891 if (bank->chip_width == 1)
1892 {
1893 u8 manufacturer, device_id;
1894 target_read_u8(target, bank->base + 0x0, &manufacturer);
1895 target_read_u8(target, bank->base + 0x1, &device_id);
1896 cfi_info->manufacturer = manufacturer;
1897 cfi_info->device_id = device_id;
1898 }
1899 else if (bank->chip_width == 2)
1900 {
1901 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1902 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1903 }
1904
1905 /* switch back to read array mode */
1906 cfi_command(bank, 0xf0, command);
1907 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1908 cfi_command(bank, 0xff, command);
1909 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1910
1911 cfi_fixup(bank, cfi_jedec_fixups);
1912
1913 /* query only if this is a CFI compatible flash,
1914 * otherwise the relevant info has already been filled in
1915 */
1916 if (cfi_info->not_cfi == 0)
1917 {
1918 /* enter CFI query mode
1919 * according to JEDEC Standard No. 68.01,
1920 * a single bus sequence with address = 0x55, data = 0x98 should put
1921 * the device into CFI query mode.
1922 *
1923 * SST flashes clearly violate this, and we will consider them incompatbile for now
1924 */
1925 cfi_command(bank, 0x98, command);
1926 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1927
1928 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1929 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1930 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1931
1932 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1933
1934 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1935 {
1936 cfi_command(bank, 0xf0, command);
1937 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1938 cfi_command(bank, 0xff, command);
1939 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1940 return ERROR_FLASH_BANK_INVALID;
1941 }
1942
1943 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1944 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1945 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1946 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1947
1948 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1949
1950 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1951 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1952 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1953 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1954 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1955 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1956 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1957 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1958 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1959 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1960 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1961 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1962
1963 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1964 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1965 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1966 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1967 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1968 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1969 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1970 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1971 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1972 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1973 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1974
1975 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1976 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1977 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1978 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1979
1980 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1981
1982 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1983 {
1984 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1985 }
1986
1987 if (cfi_info->num_erase_regions)
1988 {
1989 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1990 for (i = 0; i < cfi_info->num_erase_regions; i++)
1991 {
1992 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1993 DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1994 }
1995 }
1996 else
1997 {
1998 cfi_info->erase_region_info = NULL;
1999 }
2000
2001 /* We need to read the primary algorithm extended query table before calculating
2002 * the sector layout to be able to apply fixups
2003 */
2004 switch(cfi_info->pri_id)
2005 {
2006 /* Intel command set (standard and extended) */
2007 case 0x0001:
2008 case 0x0003:
2009 cfi_read_intel_pri_ext(bank);
2010 break;
2011 /* AMD/Spansion, Atmel, ... command set */
2012 case 0x0002:
2013 cfi_read_0002_pri_ext(bank);
2014 break;
2015 default:
2016 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2017 break;
2018 }
2019
2020 /* return to read array mode
2021 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2022 */
2023 cfi_command(bank, 0xf0, command);
2024 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2025 cfi_command(bank, 0xff, command);
2026 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2027 }
2028
2029 /* apply fixups depending on the primary command set */
2030 switch(cfi_info->pri_id)
2031 {
2032 /* Intel command set (standard and extended) */
2033 case 0x0001:
2034 case 0x0003:
2035 cfi_fixup(bank, cfi_0001_fixups);
2036 break;
2037 /* AMD/Spansion, Atmel, ... command set */
2038 case 0x0002:
2039 cfi_fixup(bank, cfi_0002_fixups);
2040 break;
2041 default:
2042 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2043 break;
2044 }
2045
2046 if (cfi_info->num_erase_regions == 0)
2047 {
2048 /* a device might have only one erase block, spanning the whole device */
2049 bank->num_sectors = 1;
2050 bank->sectors = malloc(sizeof(flash_sector_t));
2051
2052 bank->sectors[sector].offset = 0x0;
2053 bank->sectors[sector].size = bank->size;
2054 bank->sectors[sector].is_erased = -1;
2055 bank->sectors[sector].is_protected = -1;
2056 }
2057 else
2058 {
2059 for (i = 0; i < cfi_info->num_erase_regions; i++)
2060 {
2061 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2062 }
2063
2064 bank->num_sectors = num_sectors;
2065 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2066
2067 for (i = 0; i < cfi_info->num_erase_regions; i++)
2068 {
2069 int j;
2070 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2071 {
2072 bank->sectors[sector].offset = offset;
2073 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2074 offset += bank->sectors[sector].size;
2075 bank->sectors[sector].is_erased = -1;
2076 bank->sectors[sector].is_protected = -1;
2077 sector++;
2078 }
2079 }
2080 }
2081
2082 cfi_info->probed = 1;
2083
2084 return ERROR_OK;
2085 }
2086
2087 int cfi_auto_probe(struct flash_bank_s *bank)
2088 {
2089 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2090 if (cfi_info->probed)
2091 return ERROR_OK;
2092 return cfi_probe(bank);
2093 }
2094
2095 int cfi_erase_check(struct flash_bank_s *bank)
2096 {
2097 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2098 target_t *target = bank->target;
2099 int i;
2100 int retval;
2101
2102 if (bank->target->state != TARGET_HALTED)
2103 {
2104 return ERROR_TARGET_NOT_HALTED;
2105 }
2106
2107 if (!cfi_info->erase_check_algorithm)
2108 {
2109 u32 erase_check_code[] =
2110 {
2111 0xe4d03001, /* ldrb r3, [r0], #1 */
2112 0xe0022003, /* and r2, r2, r3 */
2113 0xe2511001, /* subs r1, r1, #1 */
2114 0x1afffffb, /* b -4 */
2115 0xeafffffe /* b 0 */
2116 };
2117
2118 /* make sure we have a working area */
2119 if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
2120 {
2121 WARNING("no working area available, falling back to slow memory reads");
2122 }
2123 else
2124 {
2125 u8 erase_check_code_buf[5 * 4];
2126
2127 for (i = 0; i < 5; i++)
2128 target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
2129
2130 /* write algorithm code to working area */
2131 target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
2132 }
2133 }
2134
2135 if (!cfi_info->erase_check_algorithm)
2136 {
2137 u32 *buffer = malloc(4096);
2138
2139 for (i = 0; i < bank->num_sectors; i++)
2140 {
2141 u32 address = bank->base + bank->sectors[i].offset;
2142 u32 size = bank->sectors[i].size;
2143 u32 check = 0xffffffffU;
2144 int erased = 1;
2145
2146 while (size > 0)
2147 {
2148 u32 thisrun_size = (size > 4096) ? 4096 : size;
2149 int j;
2150
2151 target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
2152
2153 for (j = 0; j < thisrun_size / 4; j++)
2154 check &= buffer[j];
2155
2156 if (check != 0xffffffff)
2157 {
2158 erased = 0;
2159 break;
2160 }
2161
2162 size -= thisrun_size;
2163 address += thisrun_size;
2164 }
2165
2166 bank->sectors[i].is_erased = erased;
2167 }
2168
2169 free(buffer);
2170 }
2171 else
2172 {
2173 for (i = 0; i < bank->num_sectors; i++)
2174 {
2175 u32 address = bank->base + bank->sectors[i].offset;
2176 u32 size = bank->sectors[i].size;
2177
2178 reg_param_t reg_params[3];
2179 armv4_5_algorithm_t armv4_5_info;
2180
2181 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2182 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2183 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2184
2185 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2186 buf_set_u32(reg_params[0].value, 0, 32, address);
2187
2188 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2189 buf_set_u32(reg_params[1].value, 0, 32, size);
2190
2191 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2192 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2193
2194 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
2195 return ERROR_FLASH_OPERATION_FAILED;
2196
2197 if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
2198 bank->sectors[i].is_erased = 1;
2199 else
2200 bank->sectors[i].is_erased = 0;
2201
2202 destroy_reg_param(&reg_params[0]);
2203 destroy_reg_param(&reg_params[1]);
2204 destroy_reg_param(&reg_params[2]);
2205 }
2206 }
2207
2208 return ERROR_OK;
2209 }
2210
2211 int cfi_intel_protect_check(struct flash_bank_s *bank)
2212 {
2213 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2214 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2215 target_t *target = bank->target;
2216 u8 command[CFI_MAX_BUS_WIDTH];
2217 int i;
2218
2219 /* check if block lock bits are supported on this device */
2220 if (!(pri_ext->blk_status_reg_mask & 0x1))
2221 return ERROR_FLASH_OPERATION_FAILED;
2222
2223 cfi_command(bank, 0x90, command);
2224 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2225
2226 for (i = 0; i < bank->num_sectors; i++)
2227 {
2228 u8 block_status = cfi_get_u8(bank, i, 0x2);
2229
2230 if (block_status & 1)
2231 bank->sectors[i].is_protected = 1;
2232 else
2233 bank->sectors[i].is_protected = 0;
2234 }
2235
2236 cfi_command(bank, 0xff, command);
2237 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2238
2239 return ERROR_OK;
2240 }
2241
2242 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2243 {
2244 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2245 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2246 target_t *target = bank->target;
2247 u8 command[8];
2248 int i;
2249
2250 cfi_command(bank, 0xaa, command);
2251 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2252
2253 cfi_command(bank, 0x55, command);
2254 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2255
2256 cfi_command(bank, 0x90, command);
2257 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2258
2259 for (i = 0; i < bank->num_sectors; i++)
2260 {
2261 u8 block_status = cfi_get_u8(bank, i, 0x2);
2262
2263 if (block_status & 1)
2264 bank->sectors[i].is_protected = 1;
2265 else
2266 bank->sectors[i].is_protected = 0;
2267 }
2268
2269 cfi_command(bank, 0xf0, command);
2270 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2271
2272 return ERROR_OK;
2273 }
2274
2275 int cfi_protect_check(struct flash_bank_s *bank)
2276 {
2277 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2278
2279 if (bank->target->state != TARGET_HALTED)
2280 {
2281 return ERROR_TARGET_NOT_HALTED;
2282 }
2283
2284 if (cfi_info->qry[0] != 'Q')
2285 return ERROR_FLASH_BANK_NOT_PROBED;
2286
2287 switch(cfi_info->pri_id)
2288 {
2289 case 1:
2290 case 3:
2291 return cfi_intel_protect_check(bank);
2292 break;
2293 case 2:
2294 return cfi_spansion_protect_check(bank);
2295 break;
2296 default:
2297 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2298 break;
2299 }
2300
2301 return ERROR_OK;
2302 }
2303
2304 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2305 {
2306 int printed;
2307 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2308
2309 if (cfi_info->qry[0] == (char)-1)
2310 {
2311 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2312 return ERROR_OK;
2313 }
2314
2315 if (cfi_info->not_cfi == 0)
2316 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2317 else
2318 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2319 buf += printed;
2320 buf_size -= printed;
2321
2322 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2323 cfi_info->manufacturer, cfi_info->device_id);
2324 buf += printed;
2325 buf_size -= printed;
2326
2327 if (cfi_info->not_cfi == 0)
2328 {
2329 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2330 buf += printed;
2331 buf_size -= printed;
2332
2333 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2334 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2335 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2336 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2337 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2338 buf += printed;
2339 buf_size -= printed;
2340
2341 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2342 1 << cfi_info->word_write_timeout_typ,
2343 1 << cfi_info->buf_write_timeout_typ,
2344 1 << cfi_info->block_erase_timeout_typ,
2345 1 << cfi_info->chip_erase_timeout_typ);
2346 buf += printed;
2347 buf_size -= printed;
2348
2349 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2350 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2351 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2352 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2353 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2354 buf += printed;
2355 buf_size -= printed;
2356
2357 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2358 1 << cfi_info->dev_size,
2359 cfi_info->interface_desc,
2360 cfi_info->max_buf_write_size);
2361 buf += printed;
2362 buf_size -= printed;
2363
2364 switch(cfi_info->pri_id)
2365 {
2366 case 1:
2367 case 3:
2368 cfi_intel_info(bank, buf, buf_size);
2369 break;
2370 case 2:
2371 cfi_spansion_info(bank, buf, buf_size);
2372 break;
2373 default:
2374 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2375 break;
2376 }
2377 }
2378
2379 return ERROR_OK;
2380 }