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Pavel Chromy cleaned up checks for halted, error messages, etc.
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28
29 #include "flash.h"
30 #include "target.h"
31 #include "log.h"
32 #include "armv4_5.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
35 #include "types.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39 #include <unistd.h>
40
41 int cfi_register_commands(struct command_context_s *cmd_ctx);
42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int cfi_probe(struct flash_bank_s *bank);
47 int cfi_auto_probe(struct flash_bank_s *bank);
48 int cfi_erase_check(struct flash_bank_s *bank);
49 int cfi_protect_check(struct flash_bank_s *bank);
50 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
51
52 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 #define CFI_MAX_BUS_WIDTH 4
55 #define CFI_MAX_CHIP_WIDTH 4
56
57 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
58 #define CFI_MAX_INTEL_CODESIZE 256
59
60 flash_driver_t cfi_flash =
61 {
62 .name = "cfi",
63 .register_commands = cfi_register_commands,
64 .flash_bank_command = cfi_flash_bank_command,
65 .erase = cfi_erase,
66 .protect = cfi_protect,
67 .write = cfi_write,
68 .probe = cfi_probe,
69 .auto_probe = cfi_auto_probe,
70 .erase_check = cfi_erase_check,
71 .protect_check = cfi_protect_check,
72 .info = cfi_info
73 };
74
75 cfi_unlock_addresses_t cfi_unlock_addresses[] =
76 {
77 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
78 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
79 };
80
81 /* CFI fixups foward declarations */
82 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
83 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
84 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
85
86 /* fixup after identifying JEDEC manufactuer and ID */
87 cfi_fixup_t cfi_jedec_fixups[] = {
88 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
94 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
95 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
96 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
97 {0, 0, NULL, NULL}
98 };
99
100 /* fixup after reading cmdset 0002 primary query table */
101 cfi_fixup_t cfi_0002_fixups[] = {
102 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
103 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
104 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
105 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
106 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
107 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
108 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
109 {0, 0, NULL, NULL}
110 };
111
112 /* fixup after reading cmdset 0001 primary query table */
113 cfi_fixup_t cfi_0001_fixups[] = {
114 {0, 0, NULL, NULL}
115 };
116
117 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
118 {
119 cfi_flash_bank_t *cfi_info = bank->driver_priv;
120 cfi_fixup_t *f;
121
122 for (f = fixups; f->fixup; f++)
123 {
124 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
125 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
126 {
127 f->fixup(bank, f->param);
128 }
129 }
130 }
131
132 inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
133 {
134 /* while the sector list isn't built, only accesses to sector 0 work */
135 if (sector == 0)
136 return bank->base + offset * bank->bus_width;
137 else
138 {
139 if (!bank->sectors)
140 {
141 ERROR("BUG: sector list not yet built");
142 exit(-1);
143 }
144 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
145 }
146
147 }
148
149 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
150 {
151 int i;
152
153 /* clear whole buffer, to ensure bits that exceed the bus_width
154 * are set to zero
155 */
156 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
157 cmd_buf[i] = 0;
158
159 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
160 {
161 for (i = bank->bus_width; i > 0; i--)
162 {
163 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
164 }
165 }
166 else
167 {
168 for (i = 1; i <= bank->bus_width; i++)
169 {
170 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
171 }
172 }
173 }
174
175 /* read unsigned 8-bit value from the bank
176 * flash banks are expected to be made of similar chips
177 * the query result should be the same for all
178 */
179 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
180 {
181 target_t *target = bank->target;
182 u8 data[CFI_MAX_BUS_WIDTH];
183
184 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
185
186 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
187 return data[0];
188 else
189 return data[bank->bus_width - 1];
190 }
191
192 /* read unsigned 8-bit value from the bank
193 * in case of a bank made of multiple chips,
194 * the individual values are ORed
195 */
196 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
197 {
198 target_t *target = bank->target;
199 u8 data[CFI_MAX_BUS_WIDTH];
200 int i;
201
202 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
203
204 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
205 {
206 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
207 data[0] |= data[i];
208
209 return data[0];
210 }
211 else
212 {
213 u8 value = 0;
214 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
215 value |= data[bank->bus_width - 1 - i];
216
217 return value;
218 }
219 }
220
221 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
222 {
223 target_t *target = bank->target;
224 u8 data[CFI_MAX_BUS_WIDTH * 2];
225
226 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
227
228 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
229 return data[0] | data[bank->bus_width] << 8;
230 else
231 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
232 }
233
234 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
235 {
236 target_t *target = bank->target;
237 u8 data[CFI_MAX_BUS_WIDTH * 4];
238
239 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
240
241 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
242 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
243 else
244 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
245 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
246 }
247
248 void cfi_intel_clear_status_register(flash_bank_t *bank)
249 {
250 target_t *target = bank->target;
251 u8 command[8];
252
253 if (target->state != TARGET_HALTED)
254 {
255 ERROR("BUG: attempted to clear status register while target wasn't halted");
256 exit(-1);
257 }
258
259 cfi_command(bank, 0x50, command);
260 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
261 }
262
263 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
264 {
265 u8 status;
266
267 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
268 {
269 DEBUG("status: 0x%x", status);
270 usleep(1000);
271 }
272
273 /* mask out bit 0 (reserved) */
274 status = status & 0xfe;
275
276 DEBUG("status: 0x%x", status);
277
278 if ((status & 0x80) != 0x80)
279 {
280 ERROR("timeout while waiting for WSM to become ready");
281 }
282 else if (status != 0x80)
283 {
284 ERROR("status register: 0x%x", status);
285 if (status & 0x2)
286 ERROR("Block Lock-Bit Detected, Operation Abort");
287 if (status & 0x4)
288 ERROR("Program suspended");
289 if (status & 0x8)
290 ERROR("Low Programming Voltage Detected, Operation Aborted");
291 if (status & 0x10)
292 ERROR("Program Error / Error in Setting Lock-Bit");
293 if (status & 0x20)
294 ERROR("Error in Block Erasure or Clear Lock-Bits");
295 if (status & 0x40)
296 ERROR("Block Erase Suspended");
297
298 cfi_intel_clear_status_register(bank);
299 }
300
301 return status;
302 }
303
304 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
305 {
306 u8 status, oldstatus;
307
308 oldstatus = cfi_get_u8(bank, 0, 0x0);
309
310 do {
311 status = cfi_get_u8(bank, 0, 0x0);
312 if ((status ^ oldstatus) & 0x40) {
313 if (status & 0x20) {
314 oldstatus = cfi_get_u8(bank, 0, 0x0);
315 status = cfi_get_u8(bank, 0, 0x0);
316 if ((status ^ oldstatus) & 0x40) {
317 ERROR("dq5 timeout, status: 0x%x", status);
318 return(ERROR_FLASH_OPERATION_FAILED);
319 } else {
320 DEBUG("status: 0x%x", status);
321 return(ERROR_OK);
322 }
323 }
324 } else {
325 DEBUG("status: 0x%x", status);
326 return(ERROR_OK);
327 }
328
329 oldstatus = status;
330 usleep(1000);
331 } while (timeout-- > 0);
332
333 ERROR("timeout, status: 0x%x", status);
334
335 return(ERROR_FLASH_BUSY);
336 }
337
338 int cfi_read_intel_pri_ext(flash_bank_t *bank)
339 {
340 cfi_flash_bank_t *cfi_info = bank->driver_priv;
341 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
342 target_t *target = bank->target;
343 u8 command[8];
344
345 cfi_info->pri_ext = pri_ext;
346
347 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
348 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
349 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
350
351 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
352 {
353 cfi_command(bank, 0xf0, command);
354 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
355 cfi_command(bank, 0xff, command);
356 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
357 return ERROR_FLASH_BANK_INVALID;
358 }
359
360 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
361 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
362
363 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
364
365 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
366 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
367 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
368
369 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
370
371 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
372 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
373
374 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
375 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
376 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
377
378 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
379 if (pri_ext->num_protection_fields != 1)
380 {
381 WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
382 }
383
384 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
385 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
386 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
387
388 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
389
390 return ERROR_OK;
391 }
392
393 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
394 {
395 cfi_flash_bank_t *cfi_info = bank->driver_priv;
396 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
397 target_t *target = bank->target;
398 u8 command[8];
399
400 cfi_info->pri_ext = pri_ext;
401
402 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
403 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
404 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
405
406 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
407 {
408 cfi_command(bank, 0xf0, command);
409 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
410 return ERROR_FLASH_BANK_INVALID;
411 }
412
413 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
414 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
415
416 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
417
418 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
419 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
420 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
421 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
422 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
423 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
424 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
425 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
426 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
427 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
428 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
429
430 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
431 pri_ext->EraseSuspend, pri_ext->BlkProt);
432
433 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
434 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
435
436 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
437
438
439 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
440 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
441 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
442
443 DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
444
445 /* default values for implementation specific workarounds */
446 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
447 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
448 pri_ext->_reversed_geometry = 0;
449
450 return ERROR_OK;
451 }
452
453 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
454 {
455 cfi_atmel_pri_ext_t atmel_pri_ext;
456 cfi_flash_bank_t *cfi_info = bank->driver_priv;
457 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
458 target_t *target = bank->target;
459 u8 command[8];
460
461 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
462 * but a different primary extended query table.
463 * We read the atmel table, and prepare a valid AMD/Spansion query table.
464 */
465
466 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
467
468 cfi_info->pri_ext = pri_ext;
469
470 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
471 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
472 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
473
474 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
475 {
476 cfi_command(bank, 0xf0, command);
477 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
478 return ERROR_FLASH_BANK_INVALID;
479 }
480
481 pri_ext->pri[0] = atmel_pri_ext.pri[0];
482 pri_ext->pri[1] = atmel_pri_ext.pri[1];
483 pri_ext->pri[2] = atmel_pri_ext.pri[2];
484
485 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
486 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
487
488 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
489
490 pri_ext->major_version = atmel_pri_ext.major_version;
491 pri_ext->minor_version = atmel_pri_ext.minor_version;
492
493 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
494 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
495 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
496 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
497
498 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
499 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
500
501 if (atmel_pri_ext.features & 0x02)
502 pri_ext->EraseSuspend = 2;
503
504 if (atmel_pri_ext.bottom_boot)
505 pri_ext->TopBottom = 2;
506 else
507 pri_ext->TopBottom = 3;
508
509 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
510 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
511
512 return ERROR_OK;
513 }
514
515 int cfi_read_0002_pri_ext(flash_bank_t *bank)
516 {
517 cfi_flash_bank_t *cfi_info = bank->driver_priv;
518
519 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
520 {
521 return cfi_read_atmel_pri_ext(bank);
522 }
523 else
524 {
525 return cfi_read_spansion_pri_ext(bank);
526 }
527 }
528
529 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
530 {
531 int printed;
532 cfi_flash_bank_t *cfi_info = bank->driver_priv;
533 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
534
535 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
536 buf += printed;
537 buf_size -= printed;
538
539 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
540 pri_ext->pri[1], pri_ext->pri[2],
541 pri_ext->major_version, pri_ext->minor_version);
542 buf += printed;
543 buf_size -= printed;
544
545 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
546 (pri_ext->SiliconRevision) >> 2,
547 (pri_ext->SiliconRevision) & 0x03);
548 buf += printed;
549 buf_size -= printed;
550
551 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
552 pri_ext->EraseSuspend,
553 pri_ext->BlkProt);
554 buf += printed;
555 buf_size -= printed;
556
557 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
558 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
559 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
560
561 return ERROR_OK;
562 }
563
564 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
565 {
566 int printed;
567 cfi_flash_bank_t *cfi_info = bank->driver_priv;
568 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
569
570 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
571 buf += printed;
572 buf_size -= printed;
573
574 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
575 buf += printed;
576 buf_size -= printed;
577
578 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
579 buf += printed;
580 buf_size -= printed;
581
582 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
583 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
584 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
585 buf += printed;
586 buf_size -= printed;
587
588 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
589
590 return ERROR_OK;
591 }
592
593 int cfi_register_commands(struct command_context_s *cmd_ctx)
594 {
595 /*command_t *cfi_cmd = */
596 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
597 /*
598 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
599 "print part id of cfi flash bank <num>");
600 */
601 return ERROR_OK;
602 }
603
604 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
605 */
606 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
607 {
608 cfi_flash_bank_t *cfi_info;
609 int i;
610
611 if (argc < 6)
612 {
613 WARNING("incomplete flash_bank cfi configuration");
614 return ERROR_FLASH_BANK_INVALID;
615 }
616
617 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
618 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
619 {
620 ERROR("chip and bus width have to specified in bytes");
621 return ERROR_FLASH_BANK_INVALID;
622 }
623
624 cfi_info = malloc(sizeof(cfi_flash_bank_t));
625 cfi_info->probed = 0;
626 bank->driver_priv = cfi_info;
627
628 cfi_info->write_algorithm = NULL;
629 cfi_info->erase_check_algorithm = NULL;
630
631 cfi_info->x16_as_x8 = 0;
632 cfi_info->jedec_probe = 0;
633 cfi_info->not_cfi = 0;
634
635 for (i = 6; i < argc; i++)
636 {
637 if (strcmp(args[i], "x16_as_x8") == 0)
638 {
639 cfi_info->x16_as_x8 = 1;
640 }
641 else if (strcmp(args[i], "jedec_probe") == 0)
642 {
643 cfi_info->jedec_probe = 1;
644 }
645 }
646
647 cfi_info->write_algorithm = NULL;
648
649 /* bank wasn't probed yet */
650 cfi_info->qry[0] = -1;
651
652 return ERROR_OK;
653 }
654
655 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
656 {
657 cfi_flash_bank_t *cfi_info = bank->driver_priv;
658 target_t *target = bank->target;
659 u8 command[8];
660 int i;
661
662 cfi_intel_clear_status_register(bank);
663
664 for (i = first; i <= last; i++)
665 {
666 cfi_command(bank, 0x20, command);
667 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
668
669 cfi_command(bank, 0xd0, command);
670 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
671
672 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
673 bank->sectors[i].is_erased = 1;
674 else
675 {
676 cfi_command(bank, 0xff, command);
677 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
678
679 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
680 return ERROR_FLASH_OPERATION_FAILED;
681 }
682 }
683
684 cfi_command(bank, 0xff, command);
685 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
686
687 return ERROR_OK;
688 }
689
690 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
691 {
692 cfi_flash_bank_t *cfi_info = bank->driver_priv;
693 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
694 target_t *target = bank->target;
695 u8 command[8];
696 int i;
697
698 for (i = first; i <= last; i++)
699 {
700 cfi_command(bank, 0xaa, command);
701 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
702
703 cfi_command(bank, 0x55, command);
704 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
705
706 cfi_command(bank, 0x80, command);
707 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
708
709 cfi_command(bank, 0xaa, command);
710 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
711
712 cfi_command(bank, 0x55, command);
713 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
714
715 cfi_command(bank, 0x30, command);
716 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
717
718 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
719 bank->sectors[i].is_erased = 1;
720 else
721 {
722 cfi_command(bank, 0xf0, command);
723 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
724
725 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
726 return ERROR_FLASH_OPERATION_FAILED;
727 }
728 }
729
730 cfi_command(bank, 0xf0, command);
731 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
732
733 return ERROR_OK;
734 }
735
736 int cfi_erase(struct flash_bank_s *bank, int first, int last)
737 {
738 cfi_flash_bank_t *cfi_info = bank->driver_priv;
739
740 if (bank->target->state != TARGET_HALTED)
741 {
742 return ERROR_TARGET_NOT_HALTED;
743 }
744
745 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
746 {
747 return ERROR_FLASH_SECTOR_INVALID;
748 }
749
750 if (cfi_info->qry[0] != 'Q')
751 return ERROR_FLASH_BANK_NOT_PROBED;
752
753 switch(cfi_info->pri_id)
754 {
755 case 1:
756 case 3:
757 return cfi_intel_erase(bank, first, last);
758 break;
759 case 2:
760 return cfi_spansion_erase(bank, first, last);
761 break;
762 default:
763 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
764 break;
765 }
766
767 return ERROR_OK;
768 }
769
770 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
771 {
772 cfi_flash_bank_t *cfi_info = bank->driver_priv;
773 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
774 target_t *target = bank->target;
775 u8 command[8];
776 int retry = 0;
777 int i;
778
779 /* if the device supports neither legacy lock/unlock (bit 3) nor
780 * instant individual block locking (bit 5).
781 */
782 if (!(pri_ext->feature_support & 0x28))
783 return ERROR_FLASH_OPERATION_FAILED;
784
785 cfi_intel_clear_status_register(bank);
786
787 for (i = first; i <= last; i++)
788 {
789 cfi_command(bank, 0x60, command);
790 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
791 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
792 if (set)
793 {
794 cfi_command(bank, 0x01, command);
795 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
796 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
797 bank->sectors[i].is_protected = 1;
798 }
799 else
800 {
801 cfi_command(bank, 0xd0, command);
802 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
803 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
804 bank->sectors[i].is_protected = 0;
805 }
806
807 /* instant individual block locking doesn't require reading of the status register */
808 if (!(pri_ext->feature_support & 0x20))
809 {
810 /* Clear lock bits operation may take up to 1.4s */
811 cfi_intel_wait_status_busy(bank, 1400);
812 }
813 else
814 {
815 u8 block_status;
816 /* read block lock bit, to verify status */
817 cfi_command(bank, 0x90, command);
818 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
819 block_status = cfi_get_u8(bank, i, 0x2);
820
821 if ((block_status & 0x1) != set)
822 {
823 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
824 cfi_command(bank, 0x70, command);
825 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
826 cfi_intel_wait_status_busy(bank, 10);
827
828 if (retry > 10)
829 return ERROR_FLASH_OPERATION_FAILED;
830 else
831 {
832 i--;
833 retry++;
834 }
835 }
836 }
837 }
838
839 /* if the device doesn't support individual block lock bits set/clear,
840 * all blocks have been unlocked in parallel, so we set those that should be protected
841 */
842 if ((!set) && (!(pri_ext->feature_support & 0x20)))
843 {
844 for (i = 0; i < bank->num_sectors; i++)
845 {
846 if (bank->sectors[i].is_protected == 1)
847 {
848 cfi_intel_clear_status_register(bank);
849
850 cfi_command(bank, 0x60, command);
851 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
852
853 cfi_command(bank, 0x01, command);
854 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
855
856 cfi_intel_wait_status_busy(bank, 100);
857 }
858 }
859 }
860
861 cfi_command(bank, 0xff, command);
862 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
863
864 return ERROR_OK;
865 }
866
867 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
868 {
869 cfi_flash_bank_t *cfi_info = bank->driver_priv;
870
871 if (bank->target->state != TARGET_HALTED)
872 {
873 return ERROR_TARGET_NOT_HALTED;
874 }
875
876 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
877 {
878 return ERROR_FLASH_SECTOR_INVALID;
879 }
880
881 if (cfi_info->qry[0] != 'Q')
882 return ERROR_FLASH_BANK_NOT_PROBED;
883
884 switch(cfi_info->pri_id)
885 {
886 case 1:
887 case 3:
888 cfi_intel_protect(bank, set, first, last);
889 break;
890 default:
891 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
892 break;
893 }
894
895 return ERROR_OK;
896 }
897
898 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
899 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
900 {
901 /* target_t *target = bank->target; */
902
903 int i;
904
905 /* NOTE:
906 * The data to flash must not be changed in endian! We write a bytestrem in
907 * target byte order already. Only the control and status byte lane of the flash
908 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
909 * word (data seems to be in the upper or lower byte lane for u16 accesses).
910 */
911
912 #if 0
913 if (target->endianness == TARGET_LITTLE_ENDIAN)
914 {
915 #endif
916 /* shift bytes */
917 for (i = 0; i < bank->bus_width - 1; i++)
918 word[i] = word[i + 1];
919 word[bank->bus_width - 1] = byte;
920 #if 0
921 }
922 else
923 {
924 /* shift bytes */
925 for (i = bank->bus_width - 1; i > 0; i--)
926 word[i] = word[i - 1];
927 word[0] = byte;
928 }
929 #endif
930 }
931
932 /* Convert code image to target endian */
933 /* FIXME create general block conversion fcts in target.c?) */ static
934 void cfi_fix_code_endian(target_t *target, u32 *dest, const u32 *src, u32 count)
935 {
936 u32 i;
937 for (i=0; i< count; i++)
938 {
939 target_buffer_set_u32(target, (u8*)dest, *src);
940 dest++;
941 src++;
942 }
943 }
944
945 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
946 {
947 cfi_flash_bank_t *cfi_info = bank->driver_priv;
948 target_t *target = bank->target;
949 reg_param_t reg_params[7];
950 armv4_5_algorithm_t armv4_5_info;
951 working_area_t *source;
952 u32 buffer_size = 32768;
953 u8 write_command_buf[CFI_MAX_BUS_WIDTH];
954 u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH];
955 u8 error_pattern_buf[CFI_MAX_BUS_WIDTH];
956 u32 write_command_val, busy_pattern_val, error_pattern_val;
957
958 /* algorithm register usage:
959 * r0: source address (in RAM)
960 * r1: target address (in Flash)
961 * r2: count
962 * r3: flash write command
963 * r4: status byte (returned to host)
964 * r5: busy test pattern
965 * r6: error test pattern
966 */
967
968 static const u32 word_32_code[] = {
969 0xe4904004, /* loop: ldr r4, [r0], #4 */
970 0xe5813000, /* str r3, [r1] */
971 0xe5814000, /* str r4, [r1] */
972 0xe5914000, /* busy: ldr r4, [r1] */
973 0xe0047005, /* and r7, r4, r5 */
974 0xe1570005, /* cmp r7, r5 */
975 0x1afffffb, /* bne busy */
976 0xe1140006, /* tst r4, r6 */
977 0x1a000003, /* bne done */
978 0xe2522001, /* subs r2, r2, #1 */
979 0x0a000001, /* beq done */
980 0xe2811004, /* add r1, r1 #4 */
981 0xeafffff2, /* b loop */
982 0xeafffffe /* done: b -2 */
983 };
984
985 static const u32 word_16_code[] = {
986 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
987 0xe1c130b0, /* strh r3, [r1] */
988 0xe1c140b0, /* strh r4, [r1] */
989 0xe1d140b0, /* busy ldrh r4, [r1] */
990 0xe0047005, /* and r7, r4, r5 */
991 0xe1570005, /* cmp r7, r5 */
992 0x1afffffb, /* bne busy */
993 0xe1140006, /* tst r4, r6 */
994 0x1a000003, /* bne done */
995 0xe2522001, /* subs r2, r2, #1 */
996 0x0a000001, /* beq done */
997 0xe2811002, /* add r1, r1 #2 */
998 0xeafffff2, /* b loop */
999 0xeafffffe /* done: b -2 */
1000 };
1001
1002 static const u32 word_8_code[] = {
1003 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1004 0xe5c13000, /* strb r3, [r1] */
1005 0xe5c14000, /* strb r4, [r1] */
1006 0xe5d14000, /* busy ldrb r4, [r1] */
1007 0xe0047005, /* and r7, r4, r5 */
1008 0xe1570005, /* cmp r7, r5 */
1009 0x1afffffb, /* bne busy */
1010 0xe1140006, /* tst r4, r6 */
1011 0x1a000003, /* bne done */
1012 0xe2522001, /* subs r2, r2, #1 */
1013 0x0a000001, /* beq done */
1014 0xe2811001, /* add r1, r1 #1 */
1015 0xeafffff2, /* b loop */
1016 0xeafffffe /* done: b -2 */
1017 };
1018 u32 target_code[CFI_MAX_INTEL_CODESIZE];
1019 const u32 *target_code_src;
1020 int target_code_size;
1021 int retval = ERROR_OK;
1022
1023
1024 cfi_intel_clear_status_register(bank);
1025
1026 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1027 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1028 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1029
1030 /* If we are setting up the write_algorith, we need target_code_src */
1031 /* if not we only need target_code_size. */
1032 /* */
1033 /* However, we don't want to create multiple code paths, so we */
1034 /* do the unecessary evaluation of target_code_src, which the */
1035 /* compiler will probably nicely optimize away if not needed */
1036
1037 /* prepare algorithm code for target endian */
1038 switch (bank->bus_width)
1039 {
1040 case 1 :
1041 target_code_src = word_8_code;
1042 target_code_size = sizeof(word_8_code);
1043 break;
1044 case 2 :
1045 target_code_src = word_16_code;
1046 target_code_size = sizeof(word_16_code);
1047 break;
1048 case 4 :
1049 target_code_src = word_32_code;
1050 target_code_size = sizeof(word_32_code);
1051 break;
1052 default:
1053 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1054 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1055 }
1056
1057 /* flash write code */
1058 if (!cfi_info->write_algorithm)
1059 {
1060 if ( target_code_size > sizeof(target_code) )
1061 {
1062 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1063 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1064 }
1065 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size);
1066
1067 /* Get memory for block write handler */
1068 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1069 if (retval != ERROR_OK)
1070 {
1071 WARNING("No working area available, can't do block memory writes");
1072 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1073 };
1074
1075 /* write algorithm code to working area */
1076 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, (u8*)target_code);
1077 if (retval != ERROR_OK)
1078 {
1079 ERROR("Unable to write block write code to target");
1080 goto cleanup;
1081 }
1082 }
1083
1084 /* Get a workspace buffer for the data to flash starting with 32k size.
1085 Half size until buffer would be smaller 256 Bytem then fail back */
1086 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1087 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1088 {
1089 buffer_size /= 2;
1090 if (buffer_size <= 256)
1091 {
1092 WARNING("no large enough working area available, can't do block memory writes");
1093 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1094 goto cleanup;
1095 }
1096 };
1097
1098 /* setup algo registers */
1099 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1100 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1101 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1102 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1103 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1104 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1105 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1106
1107 /* prepare command and status register patterns */
1108 cfi_command(bank, 0x40, write_command_buf);
1109 cfi_command(bank, 0x80, busy_pattern_buf);
1110 cfi_command(bank, 0x7e, error_pattern_buf);
1111
1112 switch (bank->bus_width)
1113 {
1114 case 1 :
1115 write_command_val = write_command_buf[0];
1116 busy_pattern_val = busy_pattern_buf[0];
1117 error_pattern_val = error_pattern_buf[0];
1118 break;
1119 case 2 :
1120 write_command_val = target_buffer_get_u16(target, write_command_buf);
1121 busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf);
1122 error_pattern_val = target_buffer_get_u16(target, error_pattern_buf);
1123 break;
1124 case 4 :
1125 write_command_val = target_buffer_get_u32(target, write_command_buf);
1126 busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf);
1127 error_pattern_val = target_buffer_get_u32(target, error_pattern_buf);
1128 break;
1129 default :
1130 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1131 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1132 goto cleanup;
1133 }
1134
1135 INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1136
1137 /* Programming main loop */
1138 while (count > 0)
1139 {
1140 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1141 u32 wsm_error;
1142
1143 target_write_buffer(target, source->address, thisrun_count, buffer);
1144
1145 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1146 buf_set_u32(reg_params[1].value, 0, 32, address);
1147 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1148
1149 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1150 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1151 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1152
1153 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1154
1155 /* Execute algorithm, assume breakpoint for last instruction */
1156 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1157 cfi_info->write_algorithm->address,
1158 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1159 10000, /* 10s should be enough for max. 32k of data */
1160 &armv4_5_info);
1161
1162 /* On failure try a fall back to direct word writes */
1163 if (retval != ERROR_OK)
1164 {
1165 cfi_intel_clear_status_register(bank);
1166 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1167 retval = ERROR_FLASH_OPERATION_FAILED;
1168 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1169 /* FIXME To allow fall back or recovery, we must save the actual status
1170 somewhere, so that a higher level code can start recovery. */
1171 goto cleanup;
1172 }
1173
1174 /* Check return value from algo code */
1175 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1176 if (wsm_error)
1177 {
1178 /* read status register (outputs debug inforation) */
1179 cfi_intel_wait_status_busy(bank, 100);
1180 cfi_intel_clear_status_register(bank);
1181 retval = ERROR_FLASH_OPERATION_FAILED;
1182 goto cleanup;
1183 }
1184
1185 buffer += thisrun_count;
1186 address += thisrun_count;
1187 count -= thisrun_count;
1188 }
1189
1190 /* free up resources */
1191 cleanup:
1192 if (source)
1193 target_free_working_area(target, source);
1194
1195 if (cfi_info->write_algorithm)
1196 {
1197 target_free_working_area(target, cfi_info->write_algorithm);
1198 cfi_info->write_algorithm = NULL;
1199 }
1200
1201 destroy_reg_param(&reg_params[0]);
1202 destroy_reg_param(&reg_params[1]);
1203 destroy_reg_param(&reg_params[2]);
1204 destroy_reg_param(&reg_params[3]);
1205 destroy_reg_param(&reg_params[4]);
1206 destroy_reg_param(&reg_params[5]);
1207 destroy_reg_param(&reg_params[6]);
1208
1209 return retval;
1210 }
1211
1212 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1213 {
1214 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1215 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1216 target_t *target = bank->target;
1217 reg_param_t reg_params[10];
1218 armv4_5_algorithm_t armv4_5_info;
1219 working_area_t *source;
1220 u32 buffer_size = 32768;
1221 u8 write_command[CFI_MAX_BUS_WIDTH];
1222 u32 status;
1223 int i;
1224 int retval;
1225 int exit_code = ERROR_OK;
1226
1227 /* input parameters - */
1228 /* R0 = source address */
1229 /* R1 = destination address */
1230 /* R2 = number of writes */
1231 /* R3 = flash write command */
1232 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1233 /* output parameters - */
1234 /* R5 = 0x80 ok 0x00 bad */
1235 /* temp registers - */
1236 /* R6 = value read from flash to test status */
1237 /* R7 = holding register */
1238 /* unlock registers - */
1239 /* R8 = unlock1_addr */
1240 /* R9 = unlock1_cmd */
1241 /* R10 = unlock2_addr */
1242 /* R11 = unlock2_cmd */
1243
1244 u32 word_32_code[] = {
1245 /* 00008100 <sp_32_code>: */
1246 0xe4905004, /* ldr r5, [r0], #4 */
1247 0xe5889000, /* str r9, [r8] */
1248 0xe58ab000, /* str r11, [r10] */
1249 0xe5883000, /* str r3, [r8] */
1250 0xe5815000, /* str r5, [r1] */
1251 0xe1a00000, /* nop */
1252 /* */
1253 /* 00008110 <sp_32_busy>: */
1254 0xe5916000, /* ldr r6, [r1] */
1255 0xe0257006, /* eor r7, r5, r6 */
1256 0xe0147007, /* ands r7, r4, r7 */
1257 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1258 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1259 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1260 0xe5916000, /* ldr r6, [r1] */
1261 0xe0257006, /* eor r7, r5, r6 */
1262 0xe0147007, /* ands r7, r4, r7 */
1263 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1264 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1265 0x1a000004, /* bne 8154 <sp_32_done> */
1266 /* */
1267 /* 00008140 <sp_32_cont>: */
1268 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1269 0x03a05080, /* moveq r5, #128 ; 0x80 */
1270 0x0a000001, /* beq 8154 <sp_32_done> */
1271 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1272 0xeaffffe8, /* b 8100 <sp_32_code> */
1273 /* */
1274 /* 00008154 <sp_32_done>: */
1275 0xeafffffe /* b 8154 <sp_32_done> */
1276 };
1277
1278 u32 word_16_code[] = {
1279 /* 00008158 <sp_16_code>: */
1280 0xe0d050b2, /* ldrh r5, [r0], #2 */
1281 0xe1c890b0, /* strh r9, [r8] */
1282 0xe1cab0b0, /* strh r11, [r10] */
1283 0xe1c830b0, /* strh r3, [r8] */
1284 0xe1c150b0, /* strh r5, [r1] */
1285 0xe1a00000, /* nop (mov r0,r0) */
1286 /* */
1287 /* 00008168 <sp_16_busy>: */
1288 0xe1d160b0, /* ldrh r6, [r1] */
1289 0xe0257006, /* eor r7, r5, r6 */
1290 0xe0147007, /* ands r7, r4, r7 */
1291 0x0a000007, /* beq 8198 <sp_16_cont> */
1292 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1293 0x0afffff9, /* beq 8168 <sp_16_busy> */
1294 0xe1d160b0, /* ldrh r6, [r1] */
1295 0xe0257006, /* eor r7, r5, r6 */
1296 0xe0147007, /* ands r7, r4, r7 */
1297 0x0a000001, /* beq 8198 <sp_16_cont> */
1298 0xe3a05000, /* mov r5, #0 ; 0x0 */
1299 0x1a000004, /* bne 81ac <sp_16_done> */
1300 /* */
1301 /* 00008198 <sp_16_cont>: */
1302 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1303 0x03a05080, /* moveq r5, #128 ; 0x80 */
1304 0x0a000001, /* beq 81ac <sp_16_done> */
1305 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1306 0xeaffffe8, /* b 8158 <sp_16_code> */
1307 /* */
1308 /* 000081ac <sp_16_done>: */
1309 0xeafffffe /* b 81ac <sp_16_done> */
1310 };
1311
1312 u32 word_8_code[] = {
1313 /* 000081b0 <sp_16_code_end>: */
1314 0xe4d05001, /* ldrb r5, [r0], #1 */
1315 0xe5c89000, /* strb r9, [r8] */
1316 0xe5cab000, /* strb r11, [r10] */
1317 0xe5c83000, /* strb r3, [r8] */
1318 0xe5c15000, /* strb r5, [r1] */
1319 0xe1a00000, /* nop (mov r0,r0) */
1320 /* */
1321 /* 000081c0 <sp_8_busy>: */
1322 0xe5d16000, /* ldrb r6, [r1] */
1323 0xe0257006, /* eor r7, r5, r6 */
1324 0xe0147007, /* ands r7, r4, r7 */
1325 0x0a000007, /* beq 81f0 <sp_8_cont> */
1326 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1327 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1328 0xe5d16000, /* ldrb r6, [r1] */
1329 0xe0257006, /* eor r7, r5, r6 */
1330 0xe0147007, /* ands r7, r4, r7 */
1331 0x0a000001, /* beq 81f0 <sp_8_cont> */
1332 0xe3a05000, /* mov r5, #0 ; 0x0 */
1333 0x1a000004, /* bne 8204 <sp_8_done> */
1334 /* */
1335 /* 000081f0 <sp_8_cont>: */
1336 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1337 0x03a05080, /* moveq r5, #128 ; 0x80 */
1338 0x0a000001, /* beq 8204 <sp_8_done> */
1339 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1340 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1341 /* */
1342 /* 00008204 <sp_8_done>: */
1343 0xeafffffe /* b 8204 <sp_8_done> */
1344 };
1345
1346 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1347 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1348 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1349
1350 /* flash write code */
1351 if (!cfi_info->write_algorithm)
1352 {
1353 u8 *code_p;
1354
1355 /* convert bus-width dependent algorithm code to correct endiannes */
1356 if (bank->bus_width == 1)
1357 {
1358 code_p = malloc(24 * 4);
1359
1360 for (i = 0; i < 24; i++)
1361 target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]);
1362 }
1363 else if (bank->bus_width == 2)
1364 {
1365 code_p = malloc(24 * 4);
1366
1367 for (i = 0; i < 24; i++)
1368 target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]);
1369 }
1370 else if (bank->bus_width == 4)
1371 {
1372 code_p = malloc(24 * 4);
1373
1374 for (i = 0; i < 24; i++)
1375 target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]);
1376 }
1377 else
1378 {
1379 return ERROR_FLASH_OPERATION_FAILED;
1380 }
1381
1382 /* allocate working area */
1383 retval=target_alloc_working_area(target, 24 * 4,
1384 &cfi_info->write_algorithm);
1385 if (retval != ERROR_OK)
1386 {
1387 return retval;
1388 }
1389
1390 /* write algorithm code to working area */
1391 target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p);
1392
1393 free(code_p);
1394 }
1395
1396 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1397 {
1398 buffer_size /= 2;
1399 if (buffer_size <= 256)
1400 {
1401 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1402 if (cfi_info->write_algorithm)
1403 target_free_working_area(target, cfi_info->write_algorithm);
1404
1405 WARNING("not enough working area available, can't do block memory writes");
1406 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1407 }
1408 };
1409
1410 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1411 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1412 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1413 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1414 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1415 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1416 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1417 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1418 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1419 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1420
1421 while (count > 0)
1422 {
1423 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1424
1425 target_write_buffer(target, source->address, thisrun_count, buffer);
1426
1427 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1428 buf_set_u32(reg_params[1].value, 0, 32, address);
1429 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1430 cfi_command(bank, 0xA0, write_command);
1431 buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32));
1432 cfi_command(bank, 0x80, write_command);
1433 buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32));
1434 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1435 buf_set_u32(reg_params[7].value, 0, 32, 0xaa);
1436 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1437 buf_set_u32(reg_params[9].value, 0, 32, 0x55);
1438
1439 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1440 cfi_info->write_algorithm->address,
1441 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1442 10000, &armv4_5_info);
1443
1444 status = buf_get_u32(reg_params[5].value, 0, 32);
1445
1446 if ((retval != ERROR_OK) || status != 0x80)
1447 {
1448 DEBUG("status: 0x%x", status);
1449 exit_code = ERROR_FLASH_OPERATION_FAILED;
1450 break;
1451 }
1452
1453 buffer += thisrun_count;
1454 address += thisrun_count;
1455 count -= thisrun_count;
1456 }
1457
1458 target_free_working_area(target, source);
1459
1460 destroy_reg_param(&reg_params[0]);
1461 destroy_reg_param(&reg_params[1]);
1462 destroy_reg_param(&reg_params[2]);
1463 destroy_reg_param(&reg_params[3]);
1464 destroy_reg_param(&reg_params[4]);
1465 destroy_reg_param(&reg_params[5]);
1466 destroy_reg_param(&reg_params[6]);
1467 destroy_reg_param(&reg_params[7]);
1468 destroy_reg_param(&reg_params[8]);
1469 destroy_reg_param(&reg_params[9]);
1470
1471 return exit_code;
1472 }
1473
1474 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1475 {
1476 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1477 target_t *target = bank->target;
1478 u8 command[8];
1479
1480 cfi_intel_clear_status_register(bank);
1481 cfi_command(bank, 0x40, command);
1482 target->type->write_memory(target, address, bank->bus_width, 1, command);
1483
1484 target->type->write_memory(target, address, bank->bus_width, 1, word);
1485
1486 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1487 {
1488 cfi_command(bank, 0xff, command);
1489 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1490
1491 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1492 return ERROR_FLASH_OPERATION_FAILED;
1493 }
1494
1495 return ERROR_OK;
1496 }
1497
1498 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1499 {
1500 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1501 target_t *target = bank->target;
1502 u8 command[8];
1503
1504 /* Calculate buffer size and boundary mask */
1505 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1506 u32 buffermask = buffersize-1;
1507 u32 bufferwsize;
1508
1509 /* Check for valid range */
1510 if (address & buffermask)
1511 {
1512 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1513 return ERROR_FLASH_OPERATION_FAILED;
1514 }
1515 switch(bank->chip_width)
1516 {
1517 case 4 : bufferwsize = buffersize / 4; break;
1518 case 2 : bufferwsize = buffersize / 2; break;
1519 case 1 : bufferwsize = buffersize; break;
1520 default:
1521 ERROR("Unsupported chip width %d", bank->chip_width);
1522 return ERROR_FLASH_OPERATION_FAILED;
1523 }
1524
1525 /* Check for valid size */
1526 if (wordcount > bufferwsize)
1527 {
1528 ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1529 return ERROR_FLASH_OPERATION_FAILED;
1530 }
1531
1532 /* Write to flash buffer */
1533 cfi_intel_clear_status_register(bank);
1534
1535 /* Initiate buffer operation _*/
1536 cfi_command(bank, 0xE8, command);
1537 target->type->write_memory(target, address, bank->bus_width, 1, command);
1538 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1539 {
1540 cfi_command(bank, 0xff, command);
1541 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1542
1543 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1544 return ERROR_FLASH_OPERATION_FAILED;
1545 }
1546
1547 /* Write buffer wordcount-1 and data words */
1548 cfi_command(bank, bufferwsize-1, command);
1549 target->type->write_memory(target, address, bank->bus_width, 1, command);
1550
1551 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1552
1553 /* Commit write operation */
1554 cfi_command(bank, 0xd0, command);
1555 target->type->write_memory(target, address, bank->bus_width, 1, command);
1556 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1557 {
1558 cfi_command(bank, 0xff, command);
1559 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1560
1561 ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1562 return ERROR_FLASH_OPERATION_FAILED;
1563 }
1564
1565 return ERROR_OK;
1566 }
1567
1568 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1569 {
1570 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1571 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1572 target_t *target = bank->target;
1573 u8 command[8];
1574
1575 cfi_command(bank, 0xaa, command);
1576 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1577
1578 cfi_command(bank, 0x55, command);
1579 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1580
1581 cfi_command(bank, 0xa0, command);
1582 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1583
1584 target->type->write_memory(target, address, bank->bus_width, 1, word);
1585
1586 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1587 {
1588 cfi_command(bank, 0xf0, command);
1589 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1590
1591 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1592 return ERROR_FLASH_OPERATION_FAILED;
1593 }
1594
1595 return ERROR_OK;
1596 }
1597
1598 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1599 {
1600 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1601
1602 switch(cfi_info->pri_id)
1603 {
1604 case 1:
1605 case 3:
1606 return cfi_intel_write_word(bank, word, address);
1607 break;
1608 case 2:
1609 return cfi_spansion_write_word(bank, word, address);
1610 break;
1611 default:
1612 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1613 break;
1614 }
1615
1616 return ERROR_FLASH_OPERATION_FAILED;
1617 }
1618
1619 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1620 {
1621 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1622
1623 switch(cfi_info->pri_id)
1624 {
1625 case 1:
1626 case 3:
1627 return cfi_intel_write_words(bank, word, wordcount, address);
1628 break;
1629 case 2:
1630 /* return cfi_spansion_write_words(bank, word, address); */
1631 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1632 break;
1633 default:
1634 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1635 break;
1636 }
1637
1638 return ERROR_FLASH_OPERATION_FAILED;
1639 }
1640
1641 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1642 {
1643 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1644 target_t *target = bank->target;
1645 u32 address = bank->base + offset; /* address of first byte to be programmed */
1646 u32 write_p, copy_p;
1647 int align; /* number of unaligned bytes */
1648 int blk_count; /* number of bus_width bytes for block copy */
1649 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1650 int i;
1651 int retval;
1652
1653 if (bank->target->state != TARGET_HALTED)
1654 return ERROR_TARGET_NOT_HALTED;
1655
1656 if (offset + count > bank->size)
1657 return ERROR_FLASH_DST_OUT_OF_BANK;
1658
1659 if (cfi_info->qry[0] != 'Q')
1660 return ERROR_FLASH_BANK_NOT_PROBED;
1661
1662 /* start at the first byte of the first word (bus_width size) */
1663 write_p = address & ~(bank->bus_width - 1);
1664 if ((align = address - write_p) != 0)
1665 {
1666 INFO("Fixup %d unaligned head bytes", align );
1667
1668 for (i = 0; i < bank->bus_width; i++)
1669 current_word[i] = 0;
1670 copy_p = write_p;
1671
1672 /* copy bytes before the first write address */
1673 for (i = 0; i < align; ++i, ++copy_p)
1674 {
1675 u8 byte;
1676 target->type->read_memory(target, copy_p, 1, 1, &byte);
1677 cfi_add_byte(bank, current_word, byte);
1678 }
1679
1680 /* add bytes from the buffer */
1681 for (; (i < bank->bus_width) && (count > 0); i++)
1682 {
1683 cfi_add_byte(bank, current_word, *buffer++);
1684 count--;
1685 copy_p++;
1686 }
1687
1688 /* if the buffer is already finished, copy bytes after the last write address */
1689 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1690 {
1691 u8 byte;
1692 target->type->read_memory(target, copy_p, 1, 1, &byte);
1693 cfi_add_byte(bank, current_word, byte);
1694 }
1695
1696 retval = cfi_write_word(bank, current_word, write_p);
1697 if (retval != ERROR_OK)
1698 return retval;
1699 write_p = copy_p;
1700 }
1701
1702 /* handle blocks of bus_size aligned bytes */
1703 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1704 switch(cfi_info->pri_id)
1705 {
1706 /* try block writes (fails without working area) */
1707 case 1:
1708 case 3:
1709 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1710 break;
1711 case 2:
1712 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1713 break;
1714 default:
1715 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1716 retval = ERROR_FLASH_OPERATION_FAILED;
1717 break;
1718 }
1719 if (retval == ERROR_OK)
1720 {
1721 /* Increment pointers and decrease count on succesful block write */
1722 buffer += blk_count;
1723 write_p += blk_count;
1724 count -= blk_count;
1725 }
1726 else
1727 {
1728 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1729 {
1730 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1731 u32 buffermask = buffersize-1;
1732 u32 bufferwsize;
1733
1734 switch(bank->chip_width)
1735 {
1736 case 4 : bufferwsize = buffersize / 4; break;
1737 case 2 : bufferwsize = buffersize / 2; break;
1738 case 1 : bufferwsize = buffersize; break;
1739 default:
1740 ERROR("Unsupported chip width %d", bank->chip_width);
1741 return ERROR_FLASH_OPERATION_FAILED;
1742 }
1743
1744 /* fall back to memory writes */
1745 while (count > bank->bus_width)
1746 {
1747 if ((write_p & 0xff) == 0)
1748 {
1749 INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1750 }
1751 #if 0
1752 /* NB! this is broken for spansion! */
1753 if ((count > bufferwsize) && !(write_p & buffermask))
1754 {
1755 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1756 if (retval != ERROR_OK)
1757 return retval;
1758
1759 buffer += buffersize;
1760 write_p += buffersize;
1761 count -= buffersize;
1762 }
1763 else
1764 #endif
1765 {
1766 for (i = 0; i < bank->bus_width; i++)
1767 current_word[i] = 0;
1768
1769 for (i = 0; i < bank->bus_width; i++)
1770 {
1771 cfi_add_byte(bank, current_word, *buffer++);
1772 }
1773
1774 retval = cfi_write_word(bank, current_word, write_p);
1775 if (retval != ERROR_OK)
1776 return retval;
1777
1778 write_p += bank->bus_width;
1779 count -= bank->bus_width;
1780 }
1781 }
1782 }
1783 else
1784 return retval;
1785 }
1786
1787 /* return to read array mode, so we can read from flash again for padding */
1788 cfi_command(bank, 0xf0, current_word);
1789 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1790 cfi_command(bank, 0xff, current_word);
1791 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1792
1793 /* handle unaligned tail bytes */
1794 if (count > 0)
1795 {
1796 INFO("Fixup %d unaligned tail bytes", count );
1797
1798 copy_p = write_p;
1799 for (i = 0; i < bank->bus_width; i++)
1800 current_word[i] = 0;
1801
1802 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1803 {
1804 cfi_add_byte(bank, current_word, *buffer++);
1805 count--;
1806 }
1807 for (; i < bank->bus_width; ++i, ++copy_p)
1808 {
1809 u8 byte;
1810 target->type->read_memory(target, copy_p, 1, 1, &byte);
1811 cfi_add_byte(bank, current_word, byte);
1812 }
1813 retval = cfi_write_word(bank, current_word, write_p);
1814 if (retval != ERROR_OK)
1815 return retval;
1816 }
1817
1818 /* return to read array mode */
1819 cfi_command(bank, 0xf0, current_word);
1820 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1821 cfi_command(bank, 0xff, current_word);
1822 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1823
1824 return ERROR_OK;
1825 }
1826
1827 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1828 {
1829 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1830 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1831
1832 pri_ext->_reversed_geometry = 1;
1833 }
1834
1835 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1836 {
1837 int i;
1838 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1839 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1840
1841 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1842 {
1843 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1844
1845 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1846 {
1847 int j = (cfi_info->num_erase_regions - 1) - i;
1848 u32 swap;
1849
1850 swap = cfi_info->erase_region_info[i];
1851 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1852 cfi_info->erase_region_info[j] = swap;
1853 }
1854 }
1855 }
1856
1857 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1858 {
1859 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1860 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1861 cfi_unlock_addresses_t *unlock_addresses = param;
1862
1863 pri_ext->_unlock1 = unlock_addresses->unlock1;
1864 pri_ext->_unlock2 = unlock_addresses->unlock2;
1865 }
1866
1867 int cfi_probe(struct flash_bank_s *bank)
1868 {
1869 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1870 target_t *target = bank->target;
1871 u8 command[8];
1872 int num_sectors = 0;
1873 int i;
1874 int sector = 0;
1875 u32 offset = 0;
1876 u32 unlock1 = 0x555;
1877 u32 unlock2 = 0x2aa;
1878
1879 if (bank->target->state != TARGET_HALTED)
1880 {
1881 return ERROR_TARGET_NOT_HALTED;
1882 }
1883
1884 cfi_info->probed = 0;
1885
1886 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1887 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1888 */
1889 if (cfi_info->jedec_probe)
1890 {
1891 unlock1 = 0x5555;
1892 unlock2 = 0x2aaa;
1893 }
1894
1895 /* switch to read identifier codes mode ("AUTOSELECT") */
1896 cfi_command(bank, 0xaa, command);
1897 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1898 cfi_command(bank, 0x55, command);
1899 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1900 cfi_command(bank, 0x90, command);
1901 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1902
1903 if (bank->chip_width == 1)
1904 {
1905 u8 manufacturer, device_id;
1906 target_read_u8(target, bank->base + 0x0, &manufacturer);
1907 target_read_u8(target, bank->base + 0x1, &device_id);
1908 cfi_info->manufacturer = manufacturer;
1909 cfi_info->device_id = device_id;
1910 }
1911 else if (bank->chip_width == 2)
1912 {
1913 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1914 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1915 }
1916
1917 /* switch back to read array mode */
1918 cfi_command(bank, 0xf0, command);
1919 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1920 cfi_command(bank, 0xff, command);
1921 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1922
1923 cfi_fixup(bank, cfi_jedec_fixups);
1924
1925 /* query only if this is a CFI compatible flash,
1926 * otherwise the relevant info has already been filled in
1927 */
1928 if (cfi_info->not_cfi == 0)
1929 {
1930 /* enter CFI query mode
1931 * according to JEDEC Standard No. 68.01,
1932 * a single bus sequence with address = 0x55, data = 0x98 should put
1933 * the device into CFI query mode.
1934 *
1935 * SST flashes clearly violate this, and we will consider them incompatbile for now
1936 */
1937 cfi_command(bank, 0x98, command);
1938 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1939
1940 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1941 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1942 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1943
1944 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1945
1946 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1947 {
1948 cfi_command(bank, 0xf0, command);
1949 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1950 cfi_command(bank, 0xff, command);
1951 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1952 return ERROR_FLASH_BANK_INVALID;
1953 }
1954
1955 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1956 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1957 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1958 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1959
1960 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1961
1962 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1963 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1964 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1965 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1966 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1967 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1968 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1969 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1970 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1971 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1972 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1973 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1974
1975 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1976 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1977 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1978 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1979 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1980 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1981 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1982 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1983 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1984 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1985 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1986
1987 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1988 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1989 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1990 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1991
1992 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1993
1994 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1995 {
1996 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1997 }
1998
1999 if (cfi_info->num_erase_regions)
2000 {
2001 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2002 for (i = 0; i < cfi_info->num_erase_regions; i++)
2003 {
2004 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2005 DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2006 }
2007 }
2008 else
2009 {
2010 cfi_info->erase_region_info = NULL;
2011 }
2012
2013 /* We need to read the primary algorithm extended query table before calculating
2014 * the sector layout to be able to apply fixups
2015 */
2016 switch(cfi_info->pri_id)
2017 {
2018 /* Intel command set (standard and extended) */
2019 case 0x0001:
2020 case 0x0003:
2021 cfi_read_intel_pri_ext(bank);
2022 break;
2023 /* AMD/Spansion, Atmel, ... command set */
2024 case 0x0002:
2025 cfi_read_0002_pri_ext(bank);
2026 break;
2027 default:
2028 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2029 break;
2030 }
2031
2032 /* return to read array mode
2033 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2034 */
2035 cfi_command(bank, 0xf0, command);
2036 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2037 cfi_command(bank, 0xff, command);
2038 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2039 }
2040
2041 /* apply fixups depending on the primary command set */
2042 switch(cfi_info->pri_id)
2043 {
2044 /* Intel command set (standard and extended) */
2045 case 0x0001:
2046 case 0x0003:
2047 cfi_fixup(bank, cfi_0001_fixups);
2048 break;
2049 /* AMD/Spansion, Atmel, ... command set */
2050 case 0x0002:
2051 cfi_fixup(bank, cfi_0002_fixups);
2052 break;
2053 default:
2054 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2055 break;
2056 }
2057
2058 if (cfi_info->num_erase_regions == 0)
2059 {
2060 /* a device might have only one erase block, spanning the whole device */
2061 bank->num_sectors = 1;
2062 bank->sectors = malloc(sizeof(flash_sector_t));
2063
2064 bank->sectors[sector].offset = 0x0;
2065 bank->sectors[sector].size = bank->size;
2066 bank->sectors[sector].is_erased = -1;
2067 bank->sectors[sector].is_protected = -1;
2068 }
2069 else
2070 {
2071 for (i = 0; i < cfi_info->num_erase_regions; i++)
2072 {
2073 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2074 }
2075
2076 bank->num_sectors = num_sectors;
2077 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2078
2079 for (i = 0; i < cfi_info->num_erase_regions; i++)
2080 {
2081 int j;
2082 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2083 {
2084 bank->sectors[sector].offset = offset;
2085 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2086 offset += bank->sectors[sector].size;
2087 bank->sectors[sector].is_erased = -1;
2088 bank->sectors[sector].is_protected = -1;
2089 sector++;
2090 }
2091 }
2092 }
2093
2094 cfi_info->probed = 1;
2095
2096 return ERROR_OK;
2097 }
2098
2099 int cfi_auto_probe(struct flash_bank_s *bank)
2100 {
2101 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2102 if (cfi_info->probed)
2103 return ERROR_OK;
2104 return cfi_probe(bank);
2105 }
2106
2107 int cfi_erase_check(struct flash_bank_s *bank)
2108 {
2109 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2110 target_t *target = bank->target;
2111 int i;
2112 int retval;
2113
2114 if (bank->target->state != TARGET_HALTED)
2115 {
2116 return ERROR_TARGET_NOT_HALTED;
2117 }
2118
2119 if (!cfi_info->erase_check_algorithm)
2120 {
2121 u32 erase_check_code[] =
2122 {
2123 0xe4d03001, /* ldrb r3, [r0], #1 */
2124 0xe0022003, /* and r2, r2, r3 */
2125 0xe2511001, /* subs r1, r1, #1 */
2126 0x1afffffb, /* b -4 */
2127 0xeafffffe /* b 0 */
2128 };
2129
2130 /* make sure we have a working area */
2131 if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
2132 {
2133 WARNING("no working area available, falling back to slow memory reads");
2134 }
2135 else
2136 {
2137 u8 erase_check_code_buf[5 * 4];
2138
2139 for (i = 0; i < 5; i++)
2140 target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
2141
2142 /* write algorithm code to working area */
2143 target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
2144 }
2145 }
2146
2147 if (!cfi_info->erase_check_algorithm)
2148 {
2149 u32 *buffer = malloc(4096);
2150
2151 for (i = 0; i < bank->num_sectors; i++)
2152 {
2153 u32 address = bank->base + bank->sectors[i].offset;
2154 u32 size = bank->sectors[i].size;
2155 u32 check = 0xffffffffU;
2156 int erased = 1;
2157
2158 while (size > 0)
2159 {
2160 u32 thisrun_size = (size > 4096) ? 4096 : size;
2161 int j;
2162
2163 target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
2164
2165 for (j = 0; j < thisrun_size / 4; j++)
2166 check &= buffer[j];
2167
2168 if (check != 0xffffffff)
2169 {
2170 erased = 0;
2171 break;
2172 }
2173
2174 size -= thisrun_size;
2175 address += thisrun_size;
2176 }
2177
2178 bank->sectors[i].is_erased = erased;
2179 }
2180
2181 free(buffer);
2182 }
2183 else
2184 {
2185 for (i = 0; i < bank->num_sectors; i++)
2186 {
2187 u32 address = bank->base + bank->sectors[i].offset;
2188 u32 size = bank->sectors[i].size;
2189
2190 reg_param_t reg_params[3];
2191 armv4_5_algorithm_t armv4_5_info;
2192
2193 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2194 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2195 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2196
2197 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2198 buf_set_u32(reg_params[0].value, 0, 32, address);
2199
2200 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2201 buf_set_u32(reg_params[1].value, 0, 32, size);
2202
2203 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2204 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2205
2206 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
2207 return ERROR_FLASH_OPERATION_FAILED;
2208
2209 if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
2210 bank->sectors[i].is_erased = 1;
2211 else
2212 bank->sectors[i].is_erased = 0;
2213
2214 destroy_reg_param(&reg_params[0]);
2215 destroy_reg_param(&reg_params[1]);
2216 destroy_reg_param(&reg_params[2]);
2217 }
2218 }
2219
2220 return ERROR_OK;
2221 }
2222
2223 int cfi_intel_protect_check(struct flash_bank_s *bank)
2224 {
2225 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2226 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2227 target_t *target = bank->target;
2228 u8 command[CFI_MAX_BUS_WIDTH];
2229 int i;
2230
2231 /* check if block lock bits are supported on this device */
2232 if (!(pri_ext->blk_status_reg_mask & 0x1))
2233 return ERROR_FLASH_OPERATION_FAILED;
2234
2235 cfi_command(bank, 0x90, command);
2236 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2237
2238 for (i = 0; i < bank->num_sectors; i++)
2239 {
2240 u8 block_status = cfi_get_u8(bank, i, 0x2);
2241
2242 if (block_status & 1)
2243 bank->sectors[i].is_protected = 1;
2244 else
2245 bank->sectors[i].is_protected = 0;
2246 }
2247
2248 cfi_command(bank, 0xff, command);
2249 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2250
2251 return ERROR_OK;
2252 }
2253
2254 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2255 {
2256 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2257 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2258 target_t *target = bank->target;
2259 u8 command[8];
2260 int i;
2261
2262 cfi_command(bank, 0xaa, command);
2263 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2264
2265 cfi_command(bank, 0x55, command);
2266 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2267
2268 cfi_command(bank, 0x90, command);
2269 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2270
2271 for (i = 0; i < bank->num_sectors; i++)
2272 {
2273 u8 block_status = cfi_get_u8(bank, i, 0x2);
2274
2275 if (block_status & 1)
2276 bank->sectors[i].is_protected = 1;
2277 else
2278 bank->sectors[i].is_protected = 0;
2279 }
2280
2281 cfi_command(bank, 0xf0, command);
2282 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2283
2284 return ERROR_OK;
2285 }
2286
2287 int cfi_protect_check(struct flash_bank_s *bank)
2288 {
2289 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2290
2291 if (bank->target->state != TARGET_HALTED)
2292 {
2293 return ERROR_TARGET_NOT_HALTED;
2294 }
2295
2296 if (cfi_info->qry[0] != 'Q')
2297 return ERROR_FLASH_BANK_NOT_PROBED;
2298
2299 switch(cfi_info->pri_id)
2300 {
2301 case 1:
2302 case 3:
2303 return cfi_intel_protect_check(bank);
2304 break;
2305 case 2:
2306 return cfi_spansion_protect_check(bank);
2307 break;
2308 default:
2309 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2310 break;
2311 }
2312
2313 return ERROR_OK;
2314 }
2315
2316 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2317 {
2318 int printed;
2319 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2320
2321 if (cfi_info->qry[0] == (char)-1)
2322 {
2323 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2324 return ERROR_OK;
2325 }
2326
2327 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2328 buf += printed;
2329 buf_size -= printed;
2330
2331 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2332 cfi_info->manufacturer, cfi_info->device_id);
2333 buf += printed;
2334 buf_size -= printed;
2335
2336 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2337 buf += printed;
2338 buf_size -= printed;
2339
2340 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2341 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2342 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2343 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2344 buf += printed;
2345 buf_size -= printed;
2346
2347 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2348 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2349 buf += printed;
2350 buf_size -= printed;
2351
2352 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2353 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2354 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2355 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2356 buf += printed;
2357 buf_size -= printed;
2358
2359 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size);
2360 buf += printed;
2361 buf_size -= printed;
2362
2363 switch(cfi_info->pri_id)
2364 {
2365 case 1:
2366 case 3:
2367 cfi_intel_info(bank, buf, buf_size);
2368 break;
2369 case 2:
2370 cfi_spansion_info(bank, buf, buf_size);
2371 break;
2372 default:
2373 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2374 break;
2375 }
2376
2377 return ERROR_OK;
2378 }
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