Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
- added patch from Dominic to unlock the ATMEL flash in cfi_read_atmel_pri_ext
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27
28 #include "flash.h"
29 #include "target.h"
30 #include "log.h"
31 #include "armv4_5.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
34 #include "types.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 int cfi_register_commands(struct command_context_s *cmd_ctx);
41 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
42 int cfi_erase(struct flash_bank_s *bank, int first, int last);
43 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
44 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 int cfi_probe(struct flash_bank_s *bank);
46 int cfi_erase_check(struct flash_bank_s *bank);
47 int cfi_protect_check(struct flash_bank_s *bank);
48 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
49
50 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 #define CFI_MAX_BUS_WIDTH 4
53 #define CFI_MAX_CHIP_WIDTH 4
54
55 flash_driver_t cfi_flash =
56 {
57 .name = "cfi",
58 .register_commands = cfi_register_commands,
59 .flash_bank_command = cfi_flash_bank_command,
60 .erase = cfi_erase,
61 .protect = cfi_protect,
62 .write = cfi_write,
63 .probe = cfi_probe,
64 .erase_check = cfi_erase_check,
65 .protect_check = cfi_protect_check,
66 .info = cfi_info
67 };
68
69 cfi_unlock_addresses_t cfi_unlock_addresses[] =
70 {
71 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
72 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
73 };
74
75 /* CFI fixups foward declarations */
76 void cfi_fixup_non_cfi(flash_bank_t *flash, void *param);
77 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
78 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
79 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
80
81 /* fixup after identifying JEDEC manufactuer and ID */
82 cfi_fixup_t cfi_jedec_fixups[] = {
83 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
84 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
85 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
86 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
87 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
88 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
91 {0, 0, NULL, NULL}
92 };
93
94 /* fixup after reading cmdset 0002 primary query table */
95 cfi_fixup_t cfi_0002_fixups[] = {
96 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
97 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
98 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
99 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
100 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
101 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
102 {0, 0, NULL, NULL}
103 };
104
105 /* fixup after reading cmdset 0001 primary query table */
106 cfi_fixup_t cfi_0001_fixups[] = {
107 {0, 0, NULL, NULL}
108 };
109
110 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
111 {
112 cfi_flash_bank_t *cfi_info = bank->driver_priv;
113 cfi_fixup_t *f;
114
115 for (f = fixups; f->fixup; f++)
116 {
117 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
118 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
119 {
120 f->fixup(bank, f->param);
121 }
122 }
123 }
124
125 inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
126 {
127 /* while the sector list isn't built, only accesses to sector 0 work */
128 if (sector == 0)
129 return bank->base + offset * bank->bus_width;
130 else
131 {
132 if (!bank->sectors)
133 {
134 ERROR("BUG: sector list not yet built");
135 exit(-1);
136 }
137 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
138 }
139
140 }
141
142 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
143 {
144 int i;
145
146 /* clear whole buffer, to ensure bits that exceed the bus_width
147 * are set to zero
148 */
149 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
150 cmd_buf[i] = 0;
151
152 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
153 {
154 for (i = bank->bus_width; i > 0; i--)
155 {
156 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
157 }
158 }
159 else
160 {
161 for (i = 1; i <= bank->bus_width; i++)
162 {
163 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
164 }
165 }
166 }
167
168 /* read unsigned 8-bit value from the bank
169 * flash banks are expected to be made of similar chips
170 * the query result should be the same for all
171 */
172 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
173 {
174 target_t *target = bank->target;
175 u8 data[CFI_MAX_BUS_WIDTH];
176
177 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
178
179 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
180 return data[0];
181 else
182 return data[bank->bus_width - 1];
183 }
184
185 /* read unsigned 8-bit value from the bank
186 * in case of a bank made of multiple chips,
187 * the individual values are ORed
188 */
189 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
190 {
191 target_t *target = bank->target;
192 u8 data[CFI_MAX_BUS_WIDTH];
193 int i;
194
195 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
196
197 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
198 {
199 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
200 data[0] |= data[i];
201
202 return data[0];
203 }
204 else
205 {
206 u8 value = 0;
207 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
208 value |= data[bank->bus_width - 1 - i];
209
210 return value;
211 }
212 }
213
214 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
215 {
216 target_t *target = bank->target;
217 u8 data[CFI_MAX_BUS_WIDTH * 2];
218
219 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
220
221 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
222 return data[0] | data[bank->bus_width] << 8;
223 else
224 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
225 }
226
227 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
228 {
229 target_t *target = bank->target;
230 u8 data[CFI_MAX_BUS_WIDTH * 4];
231
232 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
233
234 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
235 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
236 else
237 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
238 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
239 }
240
241 void cfi_intel_clear_status_register(flash_bank_t *bank)
242 {
243 target_t *target = bank->target;
244 u8 command[8];
245
246 if (target->state != TARGET_HALTED)
247 {
248 ERROR("BUG: attempted to clear status register while target wasn't halted");
249 exit(-1);
250 }
251
252 cfi_command(bank, 0x50, command);
253 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
254 }
255
256 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
257 {
258 u8 status;
259
260 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
261 {
262 DEBUG("status: 0x%x", status);
263 usleep(1000);
264 }
265
266 /* mask out bit 0 (reserved) */
267 status = status & 0xfe;
268
269 DEBUG("status: 0x%x", status);
270
271 if ((status & 0x80) != 0x80)
272 {
273 ERROR("timeout while waiting for WSM to become ready");
274 }
275 else if (status != 0x80)
276 {
277 ERROR("status register: 0x%x", status);
278 if (status & 0x2)
279 ERROR("Block Lock-Bit Detected, Operation Abort");
280 if (status & 0x4)
281 ERROR("Program suspended");
282 if (status & 0x8)
283 ERROR("Low Programming Voltage Detected, Operation Aborted");
284 if (status & 0x10)
285 ERROR("Program Error / Error in Setting Lock-Bit");
286 if (status & 0x20)
287 ERROR("Error in Block Erasure or Clear Lock-Bits");
288 if (status & 0x40)
289 ERROR("Block Erase Suspended");
290
291 cfi_intel_clear_status_register(bank);
292 }
293
294 return status;
295 }
296
297 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
298 {
299 u8 status, oldstatus;
300
301 oldstatus = cfi_get_u8(bank, 0, 0x0);
302
303 do {
304 status = cfi_get_u8(bank, 0, 0x0);
305 if ((status ^ oldstatus) & 0x40) {
306 if (status & 0x20) {
307 oldstatus = cfi_get_u8(bank, 0, 0x0);
308 status = cfi_get_u8(bank, 0, 0x0);
309 if ((status ^ oldstatus) & 0x40) {
310 ERROR("dq5 timeout, status: 0x%x", status);
311 return(ERROR_FLASH_OPERATION_FAILED);
312 } else {
313 DEBUG("status: 0x%x", status);
314 return(ERROR_OK);
315 }
316 }
317 } else {
318 DEBUG("status: 0x%x", status);
319 return(ERROR_OK);
320 }
321
322 oldstatus = status;
323 usleep(1000);
324 } while (timeout-- > 0);
325
326 ERROR("timeout, status: 0x%x", status);
327
328 return(ERROR_FLASH_BUSY);
329 }
330
331 int cfi_read_intel_pri_ext(flash_bank_t *bank)
332 {
333 cfi_flash_bank_t *cfi_info = bank->driver_priv;
334 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
335 target_t *target = bank->target;
336 u8 command[8];
337
338 cfi_info->pri_ext = pri_ext;
339
340 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
341 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
342 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
343
344 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
345 {
346 cfi_command(bank, 0xf0, command);
347 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
348 cfi_command(bank, 0xff, command);
349 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
350 return ERROR_FLASH_BANK_INVALID;
351 }
352
353 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
354 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
355
356 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
357
358 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
359 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
360 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
361
362 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
363
364 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
365 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
366
367 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
368 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
369 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
370
371 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
372 if (pri_ext->num_protection_fields != 1)
373 {
374 WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
375 }
376
377 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
378 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
379 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
380
381 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
382
383 return ERROR_OK;
384 }
385
386 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
387 {
388 cfi_flash_bank_t *cfi_info = bank->driver_priv;
389 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
390 target_t *target = bank->target;
391 u8 command[8];
392
393 cfi_info->pri_ext = pri_ext;
394
395 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
396 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
397 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
398
399 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
400 {
401 cfi_command(bank, 0xf0, command);
402 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
403 return ERROR_FLASH_BANK_INVALID;
404 }
405
406 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
407 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
408
409 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
410
411 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
412 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
413 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
414 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
415 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
416 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
417 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
418 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
419 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
420 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
421 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
422
423 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
424 pri_ext->EraseSuspend, pri_ext->BlkProt);
425
426 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
427 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
428
429 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
430
431
432 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
433 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
434 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
435
436 DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
437
438 /* default values for implementation specific workarounds */
439 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
440 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
441 pri_ext->_reversed_geometry = 0;
442
443 return ERROR_OK;
444 }
445
446 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
447 {
448 cfi_atmel_pri_ext_t atmel_pri_ext;
449 cfi_flash_bank_t *cfi_info = bank->driver_priv;
450 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
451 target_t *target = bank->target;
452 u8 command[8];
453
454 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
455 * but a different primary extended query table.
456 * We read the atmel table, and prepare a valid AMD/Spansion query table.
457 */
458
459 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
460
461 cfi_info->pri_ext = pri_ext;
462
463 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
464 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
465 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
466
467 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
468 {
469 cfi_command(bank, 0xf0, command);
470 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
471 return ERROR_FLASH_BANK_INVALID;
472 }
473
474 pri_ext->pri[0] = atmel_pri_ext.pri[0];
475 pri_ext->pri[1] = atmel_pri_ext.pri[1];
476 pri_ext->pri[2] = atmel_pri_ext.pri[2];
477
478 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
479 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
480
481 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
482
483 pri_ext->major_version = atmel_pri_ext.major_version;
484 pri_ext->minor_version = atmel_pri_ext.minor_version;
485
486 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
487 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
488 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
489 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
490
491 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
492 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
493
494 if (atmel_pri_ext.features & 0x02)
495 pri_ext->EraseSuspend = 2;
496
497 if (atmel_pri_ext.bottom_boot)
498 pri_ext->TopBottom = 2;
499 else
500 pri_ext->TopBottom = 3;
501
502 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
503 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
504
505 return ERROR_OK;
506 }
507
508 int cfi_read_0002_pri_ext(flash_bank_t *bank)
509 {
510 cfi_flash_bank_t *cfi_info = bank->driver_priv;
511
512 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
513 {
514 return cfi_read_atmel_pri_ext(bank);
515 }
516 else
517 {
518 return cfi_read_spansion_pri_ext(bank);
519 }
520 }
521
522 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
523 {
524 int printed;
525 cfi_flash_bank_t *cfi_info = bank->driver_priv;
526 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
527
528 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
529 buf += printed;
530 buf_size -= printed;
531
532 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
533 pri_ext->pri[1], pri_ext->pri[2],
534 pri_ext->major_version, pri_ext->minor_version);
535 buf += printed;
536 buf_size -= printed;
537
538 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
539 (pri_ext->SiliconRevision) >> 2,
540 (pri_ext->SiliconRevision) & 0x03);
541 buf += printed;
542 buf_size -= printed;
543
544 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
545 pri_ext->EraseSuspend,
546 pri_ext->BlkProt);
547 buf += printed;
548 buf_size -= printed;
549
550 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
551 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
552 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
553
554 return ERROR_OK;
555 }
556
557 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
558 {
559 int printed;
560 cfi_flash_bank_t *cfi_info = bank->driver_priv;
561 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
562
563 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
564 buf += printed;
565 buf_size -= printed;
566
567 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
568 buf += printed;
569 buf_size -= printed;
570
571 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
572 buf += printed;
573 buf_size -= printed;
574
575 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
576 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
577 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
578 buf += printed;
579 buf_size -= printed;
580
581 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
582
583 return ERROR_OK;
584 }
585
586 int cfi_register_commands(struct command_context_s *cmd_ctx)
587 {
588 /*command_t *cfi_cmd = */register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, NULL);
589 /*
590 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
591 "print part id of cfi flash bank <num>");
592 */
593 return ERROR_OK;
594 }
595
596 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
597 */
598 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
599 {
600 cfi_flash_bank_t *cfi_info;
601 int i;
602
603 if (argc < 6)
604 {
605 WARNING("incomplete flash_bank cfi configuration");
606 return ERROR_FLASH_BANK_INVALID;
607 }
608
609 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
610 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
611 {
612 ERROR("chip and bus width have to specified in byte");
613 return ERROR_FLASH_BANK_INVALID;
614 }
615
616 cfi_info = malloc(sizeof(cfi_flash_bank_t));
617 bank->driver_priv = cfi_info;
618
619 cfi_info->write_algorithm = NULL;
620 cfi_info->erase_check_algorithm = NULL;
621
622 cfi_info->x16_as_x8 = 0;
623 cfi_info->jedec_probe = 0;
624 cfi_info->not_cfi = 0;
625
626 for (i = 6; i < argc; i++)
627 {
628 if (strcmp(args[i], "x16_as_x8") == 0)
629 {
630 cfi_info->x16_as_x8 = 1;
631 }
632 else if (strcmp(args[i], "jedec_probe") == 0)
633 {
634 cfi_info->jedec_probe = 1;
635 }
636 }
637
638 cfi_info->write_algorithm = NULL;
639
640 /* bank wasn't probed yet */
641 cfi_info->qry[0] = -1;
642
643 return ERROR_OK;
644 }
645
646 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
647 {
648 cfi_flash_bank_t *cfi_info = bank->driver_priv;
649 target_t *target = bank->target;
650 u8 command[8];
651 int i;
652
653 cfi_intel_clear_status_register(bank);
654
655 for (i = first; i <= last; i++)
656 {
657 cfi_command(bank, 0x20, command);
658 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
659
660 cfi_command(bank, 0xd0, command);
661 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
662
663 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
664 bank->sectors[i].is_erased = 1;
665 else
666 {
667 cfi_command(bank, 0xff, command);
668 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
669
670 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
671 return ERROR_FLASH_OPERATION_FAILED;
672 }
673 }
674
675 cfi_command(bank, 0xff, command);
676 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
677
678 return ERROR_OK;
679 }
680
681 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
682 {
683 cfi_flash_bank_t *cfi_info = bank->driver_priv;
684 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
685 target_t *target = bank->target;
686 u8 command[8];
687 int i;
688
689 for (i = first; i <= last; i++)
690 {
691 cfi_command(bank, 0xaa, command);
692 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
693
694 cfi_command(bank, 0x55, command);
695 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
696
697 cfi_command(bank, 0x80, command);
698 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
699
700 cfi_command(bank, 0xaa, command);
701 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
702
703 cfi_command(bank, 0x55, command);
704 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
705
706 cfi_command(bank, 0x30, command);
707 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
708
709 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
710 bank->sectors[i].is_erased = 1;
711 else
712 {
713 cfi_command(bank, 0xf0, command);
714 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
715
716 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
717 return ERROR_FLASH_OPERATION_FAILED;
718 }
719 }
720
721 cfi_command(bank, 0xf0, command);
722 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
723
724 return ERROR_OK;
725 }
726
727 int cfi_erase(struct flash_bank_s *bank, int first, int last)
728 {
729 cfi_flash_bank_t *cfi_info = bank->driver_priv;
730
731 if (bank->target->state != TARGET_HALTED)
732 {
733 return ERROR_TARGET_NOT_HALTED;
734 }
735
736 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
737 {
738 return ERROR_FLASH_SECTOR_INVALID;
739 }
740
741 if (cfi_info->qry[0] != 'Q')
742 return ERROR_FLASH_BANK_NOT_PROBED;
743
744 switch(cfi_info->pri_id)
745 {
746 case 1:
747 case 3:
748 return cfi_intel_erase(bank, first, last);
749 break;
750 case 2:
751 return cfi_spansion_erase(bank, first, last);
752 break;
753 default:
754 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
755 break;
756 }
757
758 return ERROR_OK;
759 }
760
761 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
762 {
763 cfi_flash_bank_t *cfi_info = bank->driver_priv;
764 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
765 target_t *target = bank->target;
766 u8 command[8];
767 int retry = 0;
768 int i;
769
770 /* if the device supports neither legacy lock/unlock (bit 3) nor
771 * instant individual block locking (bit 5).
772 */
773 if (!(pri_ext->feature_support & 0x28))
774 return ERROR_FLASH_OPERATION_FAILED;
775
776 cfi_intel_clear_status_register(bank);
777
778 for (i = first; i <= last; i++)
779 {
780 cfi_command(bank, 0x60, command);
781 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
782 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
783 if (set)
784 {
785 cfi_command(bank, 0x01, command);
786 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
787 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
788 bank->sectors[i].is_protected = 1;
789 }
790 else
791 {
792 cfi_command(bank, 0xd0, command);
793 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
794 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
795 bank->sectors[i].is_protected = 0;
796 }
797
798 /* instant individual block locking doesn't require reading of the status register */
799 if (!(pri_ext->feature_support & 0x20))
800 {
801 /* Clear lock bits operation may take up to 1.4s */
802 cfi_intel_wait_status_busy(bank, 1400);
803 }
804 else
805 {
806 u8 block_status;
807 /* read block lock bit, to verify status */
808 cfi_command(bank, 0x90, command);
809 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
810 block_status = cfi_get_u8(bank, i, 0x2);
811
812 if ((block_status & 0x1) != set)
813 {
814 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
815 cfi_command(bank, 0x70, command);
816 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
817 cfi_intel_wait_status_busy(bank, 10);
818
819 if (retry > 10)
820 return ERROR_FLASH_OPERATION_FAILED;
821 else
822 {
823 i--;
824 retry++;
825 }
826 }
827 }
828 }
829
830 /* if the device doesn't support individual block lock bits set/clear,
831 * all blocks have been unlocked in parallel, so we set those that should be protected
832 */
833 if ((!set) && (!(pri_ext->feature_support & 0x20)))
834 {
835 for (i = 0; i < bank->num_sectors; i++)
836 {
837 cfi_intel_clear_status_register(bank);
838 cfi_command(bank, 0x60, command);
839 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
840 if (bank->sectors[i].is_protected == 1)
841 {
842 cfi_command(bank, 0x01, command);
843 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
844 }
845
846 cfi_intel_wait_status_busy(bank, 100);
847 }
848 }
849
850 cfi_command(bank, 0xff, command);
851 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
852
853 return ERROR_OK;
854 }
855
856 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
857 {
858 cfi_flash_bank_t *cfi_info = bank->driver_priv;
859
860 if (bank->target->state != TARGET_HALTED)
861 {
862 return ERROR_TARGET_NOT_HALTED;
863 }
864
865 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
866 {
867 return ERROR_FLASH_SECTOR_INVALID;
868 }
869
870 if (cfi_info->qry[0] != 'Q')
871 return ERROR_FLASH_BANK_NOT_PROBED;
872
873 switch(cfi_info->pri_id)
874 {
875 case 1:
876 case 3:
877 cfi_intel_protect(bank, set, first, last);
878 break;
879 default:
880 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
881 break;
882 }
883
884 return ERROR_OK;
885 }
886
887 void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
888 {
889 target_t *target = bank->target;
890
891 int i;
892
893 if (target->endianness == TARGET_LITTLE_ENDIAN)
894 {
895 /* shift bytes */
896 for (i = 0; i < bank->bus_width - 1; i++)
897 word[i] = word[i + 1];
898 word[bank->bus_width - 1] = byte;
899 }
900 else
901 {
902 /* shift bytes */
903 for (i = bank->bus_width - 1; i > 0; i--)
904 word[i] = word[i - 1];
905 word[0] = byte;
906 }
907 }
908
909 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
910 {
911 cfi_flash_bank_t *cfi_info = bank->driver_priv;
912 target_t *target = bank->target;
913 reg_param_t reg_params[7];
914 armv4_5_algorithm_t armv4_5_info;
915 working_area_t *source;
916 u32 buffer_size = 32768;
917 u8 write_command_buf[CFI_MAX_BUS_WIDTH];
918 u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH];
919 u8 error_pattern_buf[CFI_MAX_BUS_WIDTH];
920 u32 write_command_val, busy_pattern_val, error_pattern_val;
921 int retval;
922
923 /* algorithm register usage:
924 * r0: source address (in RAM)
925 * r1: target address (in Flash)
926 * r2: count
927 * r3: flash write command
928 * r4: status byte (returned to host)
929 * r5: busy test pattern
930 * r6: error test pattern
931 */
932
933 static const u32 word_32_code[] = {
934 0xe4904004, /* loop: ldr r4, [r0], #4 */
935 0xe5813000, /* str r3, [r1] */
936 0xe5814000, /* str r4, [r1] */
937 0xe5914000, /* busy: ldr r4, [r1] */
938 0xe0047005, /* and r7, r4, r5 */
939 0xe1570005, /* cmp r7, r5 */
940 0x1afffffb, /* bne busy */
941 0xe1140006, /* tst r4, r6 */
942 0x1a000003, /* bne done */
943 0xe2522001, /* subs r2, r2, #1 */
944 0x0a000001, /* beq done */
945 0xe2811004, /* add r1, r1 #4 */
946 0xeafffff2, /* b loop */
947 0xeafffffe, /* done: b -2 */
948 };
949
950 static const u32 word_16_code[] = {
951 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
952 0xe1c130b0, /* strh r3, [r1] */
953 0xe1c140b0, /* strh r4, [r1] */
954 0xe1d140b0, /* busy ldrh r4, [r1] */
955 0xe0047005, /* and r7, r4, r5 */
956 0xe1570005, /* cmp r7, r5 */
957 0x1afffffb, /* bne busy */
958 0xe1140006, /* tst r4, r6 */
959 0x1a000003, /* bne done */
960 0xe2522001, /* subs r2, r2, #1 */
961 0x0a000001, /* beq done */
962 0xe2811002, /* add r1, r1 #2 */
963 0xeafffff2, /* b loop */
964 0xeafffffe, /* done: b -2 */
965 };
966
967 static const u32 word_8_code[] = {
968 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
969 0xe5c13000, /* strb r3, [r1] */
970 0xe5c14000, /* strb r4, [r1] */
971 0xe5d14000, /* busy ldrb r4, [r1] */
972 0xe0047005, /* and r7, r4, r5 */
973 0xe1570005, /* cmp r7, r5 */
974 0x1afffffb, /* bne busy */
975 0xe1140006, /* tst r4, r6 */
976 0x1a000003, /* bne done */
977 0xe2522001, /* subs r2, r2, #1 */
978 0x0a000001, /* beq done */
979 0xe2811001, /* add r1, r1 #1 */
980 0xeafffff2, /* b loop */
981 0xeafffffe, /* done: b -2 */
982 };
983
984 cfi_intel_clear_status_register(bank);
985
986 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
987 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
988 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
989
990 /* flash write code */
991 if (!cfi_info->write_algorithm)
992 {
993 u8 write_code_buf[14 * 4];
994 int i;
995
996 if (target_alloc_working_area(target, 4 * 14, &cfi_info->write_algorithm) != ERROR_OK)
997 {
998 WARNING("no working area available, can't do block memory writes");
999 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1000 };
1001
1002 /* write algorithm code to working area */
1003 if (bank->bus_width == 1)
1004 {
1005 for (i = 0; i < 14; i++)
1006 target_buffer_set_u32(target, write_code_buf + (i*4), word_8_code[i]);
1007 }
1008 else if (bank->bus_width == 2)
1009 {
1010 for (i = 0; i < 14; i++)
1011 target_buffer_set_u32(target, write_code_buf + (i*4), word_16_code[i]);
1012 }
1013 else if (bank->bus_width == 4)
1014 {
1015 for (i = 0; i < 14; i++)
1016 target_buffer_set_u32(target, write_code_buf + (i*4), word_32_code[i]);
1017 }
1018 else
1019 {
1020 return ERROR_FLASH_OPERATION_FAILED;
1021 }
1022
1023 target_write_buffer(target, cfi_info->write_algorithm->address, 14 * 4, write_code_buf);
1024 }
1025
1026 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1027 {
1028 buffer_size /= 2;
1029 if (buffer_size <= 256)
1030 {
1031 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1032 if (cfi_info->write_algorithm)
1033 target_free_working_area(target, cfi_info->write_algorithm);
1034
1035 WARNING("no large enough working area available, can't do block memory writes");
1036 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1037 }
1038 };
1039
1040 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1041 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1042 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1043 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1044 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1045 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1046 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1047
1048 /* prepare command and status register patterns */
1049 cfi_command(bank, 0x40, write_command_buf);
1050 cfi_command(bank, 0x80, busy_pattern_buf);
1051 cfi_command(bank, 0x7e, error_pattern_buf);
1052
1053 if (bank->bus_width == 1)
1054 {
1055 write_command_val = write_command_buf[0];
1056 busy_pattern_val = busy_pattern_buf[0];
1057 error_pattern_val = error_pattern_buf[0];
1058 }
1059 else if (bank->bus_width == 2)
1060 {
1061 write_command_val = target_buffer_get_u16(target, write_command_buf);
1062 busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf);
1063 error_pattern_val = target_buffer_get_u16(target, error_pattern_buf);
1064 }
1065 else if (bank->bus_width == 4)
1066 {
1067 write_command_val = target_buffer_get_u32(target, write_command_buf);
1068 busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf);
1069 error_pattern_val = target_buffer_get_u32(target, error_pattern_buf);
1070 }
1071
1072 while (count > 0)
1073 {
1074 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1075
1076 target_write_buffer(target, source->address, thisrun_count, buffer);
1077
1078 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1079 buf_set_u32(reg_params[1].value, 0, 32, address);
1080 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1081 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1082 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1083 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1084
1085 if ((retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params, cfi_info->write_algorithm->address, cfi_info->write_algorithm->address + (13 * 4), 10000, &armv4_5_info)) != ERROR_OK)
1086 {
1087 cfi_intel_clear_status_register(bank);
1088 return ERROR_FLASH_OPERATION_FAILED;
1089 }
1090
1091 if (buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val)
1092 {
1093 /* read status register (outputs debug inforation) */
1094 cfi_intel_wait_status_busy(bank, 100);
1095 cfi_intel_clear_status_register(bank);
1096 return ERROR_FLASH_OPERATION_FAILED;
1097 }
1098
1099 buffer += thisrun_count;
1100 address += thisrun_count;
1101 count -= thisrun_count;
1102 }
1103
1104 target_free_working_area(target, source);
1105
1106 destroy_reg_param(&reg_params[0]);
1107 destroy_reg_param(&reg_params[1]);
1108 destroy_reg_param(&reg_params[2]);
1109 destroy_reg_param(&reg_params[3]);
1110 destroy_reg_param(&reg_params[4]);
1111 destroy_reg_param(&reg_params[5]);
1112 destroy_reg_param(&reg_params[6]);
1113
1114 return ERROR_OK;
1115 }
1116
1117 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1118 {
1119 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1120 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1121 target_t *target = bank->target;
1122 reg_param_t reg_params[10];
1123 armv4_5_algorithm_t armv4_5_info;
1124 working_area_t *source;
1125 u32 buffer_size = 32768;
1126 u8 write_command[CFI_MAX_BUS_WIDTH];
1127 u32 status;
1128 int i;
1129 int retval;
1130 int exit_code = ERROR_OK;
1131
1132 /* input parameters - */
1133 /* R0 = source address */
1134 /* R1 = destination address */
1135 /* R2 = number of writes */
1136 /* R3 = flash write command */
1137 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1138 /* output parameters - */
1139 /* R5 = 0x80 ok 0x00 bad */
1140 /* temp registers - */
1141 /* R6 = value read from flash to test status */
1142 /* R7 = holding register */
1143 /* unlock registers - */
1144 /* R8 = unlock1_addr */
1145 /* R9 = unlock1_cmd */
1146 /* R10 = unlock2_addr */
1147 /* R11 = unlock2_cmd */
1148
1149 u32 word_32_code[] = {
1150 /* 00008100 <sp_32_code>: */
1151 0xe4905004, /* ldr r5, [r0], #4 */
1152 0xe5889000, /* str r9, [r8] */
1153 0xe58ab000, /* str r11, [r10] */
1154 0xe5883000, /* str r3, [r8] */
1155 0xe5815000, /* str r5, [r1] */
1156 0xe1a00000, /* nop */
1157 /* */
1158 /* 00008110 <sp_32_busy>: */
1159 0xe5916000, /* ldr r6, [r1] */
1160 0xe0257006, /* eor r7, r5, r6 */
1161 0xe0147007, /* ands r7, r4, r7 */
1162 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1163 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1164 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1165 0xe5916000, /* ldr r6, [r1] */
1166 0xe0257006, /* eor r7, r5, r6 */
1167 0xe0147007, /* ands r7, r4, r7 */
1168 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1169 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1170 0x1a000004, /* bne 8154 <sp_32_done> */
1171 /* */
1172 /* 00008140 <sp_32_cont>: */
1173 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1174 0x03a05080, /* moveq r5, #128 ; 0x80 */
1175 0x0a000001, /* beq 8154 <sp_32_done> */
1176 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1177 0xeaffffe8, /* b 8100 <sp_32_code> */
1178 /* */
1179 /* 00008154 <sp_32_done>: */
1180 0xeafffffe /* b 8154 <sp_32_done> */
1181 };
1182
1183 u32 word_16_code[] = {
1184 /* 00008158 <sp_16_code>: */
1185 0xe0d050b2, /* ldrh r5, [r0], #2 */
1186 0xe1c890b0, /* strh r9, [r8] */
1187 0xe1cab0b0, /* strh r11, [r10] */
1188 0xe1c830b0, /* strh r3, [r8] */
1189 0xe1c150b0, /* strh r5, [r1] */
1190 0xe1a00000, /* nop (mov r0,r0) */
1191 /* */
1192 /* 00008168 <sp_16_busy>: */
1193 0xe1d160b0, /* ldrh r6, [r1] */
1194 0xe0257006, /* eor r7, r5, r6 */
1195 0xe0147007, /* ands r7, r4, r7 */
1196 0x0a000007, /* beq 8198 <sp_16_cont> */
1197 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1198 0x0afffff9, /* beq 8168 <sp_16_busy> */
1199 0xe1d160b0, /* ldrh r6, [r1] */
1200 0xe0257006, /* eor r7, r5, r6 */
1201 0xe0147007, /* ands r7, r4, r7 */
1202 0x0a000001, /* beq 8198 <sp_16_cont> */
1203 0xe3a05000, /* mov r5, #0 ; 0x0 */
1204 0x1a000004, /* bne 81ac <sp_16_done> */
1205 /* */
1206 /* 00008198 <sp_16_cont>: */
1207 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1208 0x03a05080, /* moveq r5, #128 ; 0x80 */
1209 0x0a000001, /* beq 81ac <sp_16_done> */
1210 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1211 0xeaffffe8, /* b 8158 <sp_16_code> */
1212 /* */
1213 /* 000081ac <sp_16_done>: */
1214 0xeafffffe /* b 81ac <sp_16_done> */
1215 };
1216
1217 u32 word_8_code[] = {
1218 /* 000081b0 <sp_16_code_end>: */
1219 0xe4d05001, /* ldrb r5, [r0], #1 */
1220 0xe5c89000, /* strb r9, [r8] */
1221 0xe5cab000, /* strb r11, [r10] */
1222 0xe5c83000, /* strb r3, [r8] */
1223 0xe5c15000, /* strb r5, [r1] */
1224 0xe1a00000, /* nop (mov r0,r0) */
1225 /* */
1226 /* 000081c0 <sp_8_busy>: */
1227 0xe5d16000, /* ldrb r6, [r1] */
1228 0xe0257006, /* eor r7, r5, r6 */
1229 0xe0147007, /* ands r7, r4, r7 */
1230 0x0a000007, /* beq 81f0 <sp_8_cont> */
1231 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1232 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1233 0xe5d16000, /* ldrb r6, [r1] */
1234 0xe0257006, /* eor r7, r5, r6 */
1235 0xe0147007, /* ands r7, r4, r7 */
1236 0x0a000001, /* beq 81f0 <sp_8_cont> */
1237 0xe3a05000, /* mov r5, #0 ; 0x0 */
1238 0x1a000004, /* bne 8204 <sp_8_done> */
1239 /* */
1240 /* 000081f0 <sp_8_cont>: */
1241 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1242 0x03a05080, /* moveq r5, #128 ; 0x80 */
1243 0x0a000001, /* beq 8204 <sp_8_done> */
1244 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1245 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1246 /* */
1247 /* 00008204 <sp_8_done>: */
1248 0xeafffffe /* b 8204 <sp_8_done> */
1249 };
1250
1251 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1252 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1253 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1254
1255 /* flash write code */
1256 if (!cfi_info->write_algorithm)
1257 {
1258 u8 *code_p;
1259
1260 /* convert bus-width dependent algorithm code to correct endiannes */
1261 if (bank->bus_width == 1)
1262 {
1263 code_p = malloc(24 * 4);
1264
1265 for (i = 0; i < 24; i++)
1266 target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]);
1267 }
1268 else if (bank->bus_width == 2)
1269 {
1270 code_p = malloc(24 * 4);
1271
1272 for (i = 0; i < 24; i++)
1273 target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]);
1274 }
1275 else if (bank->bus_width == 4)
1276 {
1277 code_p = malloc(24 * 4);
1278
1279 for (i = 0; i < 24; i++)
1280 target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]);
1281 }
1282 else
1283 {
1284 return ERROR_FLASH_OPERATION_FAILED;
1285 }
1286
1287 /* allocate working area */
1288 if (target_alloc_working_area(target, 24 * 4,
1289 &cfi_info->write_algorithm) != ERROR_OK)
1290 {
1291 WARNING("no working area available, can't do block memory writes");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1293 }
1294
1295 /* write algorithm code to working area */
1296 target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p);
1297
1298 free(code_p);
1299 }
1300
1301 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1302 {
1303 buffer_size /= 2;
1304 if (buffer_size <= 256)
1305 {
1306 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1307 if (cfi_info->write_algorithm)
1308 target_free_working_area(target, cfi_info->write_algorithm);
1309
1310 WARNING("not enough working area available, can't do block memory writes");
1311 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1312 }
1313 };
1314
1315 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1316 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1317 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1318 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1319 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1320 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1321 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1322 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1323 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1324 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1325
1326 while (count > 0)
1327 {
1328 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1329
1330 target_write_buffer(target, source->address, thisrun_count, buffer);
1331
1332 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1333 buf_set_u32(reg_params[1].value, 0, 32, address);
1334 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1335 cfi_command(bank, 0xA0, write_command);
1336 buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32));
1337 cfi_command(bank, 0x80, write_command);
1338 buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32));
1339 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1340 buf_set_u32(reg_params[7].value, 0, 32, 0xaa);
1341 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1342 buf_set_u32(reg_params[9].value, 0, 32, 0x55);
1343
1344 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1345 cfi_info->write_algorithm->address,
1346 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1347 10000, &armv4_5_info);
1348
1349 status = buf_get_u32(reg_params[5].value, 0, 32);
1350
1351 if ((retval != ERROR_OK) || status != 0x80)
1352 {
1353 DEBUG("status: 0x%x", status);
1354 exit_code = ERROR_FLASH_OPERATION_FAILED;
1355 break;
1356 }
1357
1358 buffer += thisrun_count;
1359 address += thisrun_count;
1360 count -= thisrun_count;
1361 }
1362
1363 target_free_working_area(target, source);
1364
1365 destroy_reg_param(&reg_params[0]);
1366 destroy_reg_param(&reg_params[1]);
1367 destroy_reg_param(&reg_params[2]);
1368 destroy_reg_param(&reg_params[3]);
1369 destroy_reg_param(&reg_params[4]);
1370 destroy_reg_param(&reg_params[5]);
1371 destroy_reg_param(&reg_params[6]);
1372 destroy_reg_param(&reg_params[7]);
1373 destroy_reg_param(&reg_params[8]);
1374 destroy_reg_param(&reg_params[9]);
1375
1376 return exit_code;
1377 }
1378
1379 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1380 {
1381 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1382 target_t *target = bank->target;
1383 u8 command[8];
1384
1385 cfi_intel_clear_status_register(bank);
1386 cfi_command(bank, 0x40, command);
1387 target->type->write_memory(target, address, bank->bus_width, 1, command);
1388
1389 target->type->write_memory(target, address, bank->bus_width, 1, word);
1390
1391 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1392 {
1393 cfi_command(bank, 0xff, command);
1394 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1395
1396 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1397 return ERROR_FLASH_OPERATION_FAILED;
1398 }
1399
1400 return ERROR_OK;
1401 }
1402
1403 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1404 {
1405 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1406 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1407 target_t *target = bank->target;
1408 u8 command[8];
1409
1410 cfi_command(bank, 0xaa, command);
1411 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1412
1413 cfi_command(bank, 0x55, command);
1414 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1415
1416 cfi_command(bank, 0xa0, command);
1417 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1418
1419 target->type->write_memory(target, address, bank->bus_width, 1, word);
1420
1421 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1422 {
1423 cfi_command(bank, 0xf0, command);
1424 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1425
1426 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1427 return ERROR_FLASH_OPERATION_FAILED;
1428 }
1429
1430 return ERROR_OK;
1431 }
1432
1433 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1434 {
1435 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1436
1437 switch(cfi_info->pri_id)
1438 {
1439 case 1:
1440 case 3:
1441 return cfi_intel_write_word(bank, word, address);
1442 break;
1443 case 2:
1444 return cfi_spansion_write_word(bank, word, address);
1445 break;
1446 default:
1447 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1448 break;
1449 }
1450
1451 return ERROR_FLASH_OPERATION_FAILED;
1452 }
1453
1454 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1455 {
1456 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1457 target_t *target = bank->target;
1458 u32 address = bank->base + offset; /* address of first byte to be programmed */
1459 u32 write_p, copy_p;
1460 int align; /* number of unaligned bytes */
1461 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1462 int i;
1463 int retval;
1464
1465 if (bank->target->state != TARGET_HALTED)
1466 {
1467 return ERROR_TARGET_NOT_HALTED;
1468 }
1469
1470 if (offset + count > bank->size)
1471 return ERROR_FLASH_DST_OUT_OF_BANK;
1472
1473 if (cfi_info->qry[0] != 'Q')
1474 return ERROR_FLASH_BANK_NOT_PROBED;
1475
1476 /* start at the first byte of the first word (bus_width size) */
1477 write_p = address & ~(bank->bus_width - 1);
1478 if ((align = address - write_p) != 0)
1479 {
1480 for (i = 0; i < bank->bus_width; i++)
1481 current_word[i] = 0;
1482 copy_p = write_p;
1483
1484 /* copy bytes before the first write address */
1485 for (i = 0; i < align; ++i, ++copy_p)
1486 {
1487 u8 byte;
1488 target->type->read_memory(target, copy_p, 1, 1, &byte);
1489 cfi_add_byte(bank, current_word, byte);
1490 }
1491
1492 /* add bytes from the buffer */
1493 for (; (i < bank->bus_width) && (count > 0); i++)
1494 {
1495 cfi_add_byte(bank, current_word, *buffer++);
1496 count--;
1497 copy_p++;
1498 }
1499
1500 /* if the buffer is already finished, copy bytes after the last write address */
1501 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1502 {
1503 u8 byte;
1504 target->type->read_memory(target, copy_p, 1, 1, &byte);
1505 cfi_add_byte(bank, current_word, byte);
1506 }
1507
1508 retval = cfi_write_word(bank, current_word, write_p);
1509 if (retval != ERROR_OK)
1510 return retval;
1511 write_p = copy_p;
1512 }
1513
1514 /* handle blocks of bus_size aligned bytes */
1515 switch(cfi_info->pri_id)
1516 {
1517 /* try block writes (fails without working area) */
1518 case 1:
1519 case 3:
1520 retval = cfi_intel_write_block(bank, buffer, write_p, count);
1521 break;
1522 case 2:
1523 retval = cfi_spansion_write_block(bank, buffer, write_p, count);
1524 break;
1525 default:
1526 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1527 retval = ERROR_FLASH_OPERATION_FAILED;
1528 break;
1529 }
1530 if (retval != ERROR_OK)
1531 {
1532 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1533 {
1534 /* fall back to memory writes */
1535 while (count > bank->bus_width)
1536 {
1537 for (i = 0; i < bank->bus_width; i++)
1538 current_word[i] = 0;
1539
1540 for (i = 0; i < bank->bus_width; i++)
1541 {
1542 cfi_add_byte(bank, current_word, *buffer++);
1543 }
1544
1545 retval = cfi_write_word(bank, current_word, write_p);
1546 if (retval != ERROR_OK)
1547 return retval;
1548 write_p += bank->bus_width;
1549 count -= bank->bus_width;
1550 }
1551 }
1552 else
1553 return retval;
1554 }
1555
1556 /* handle unaligned tail bytes */
1557 if (count > 0)
1558 {
1559 copy_p = write_p;
1560 for (i = 0; i < bank->bus_width; i++)
1561 current_word[i] = 0;
1562
1563 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1564 {
1565 cfi_add_byte(bank, current_word, *buffer++);
1566 count--;
1567 }
1568 for (; i < bank->bus_width; ++i, ++copy_p)
1569 {
1570 u8 byte;
1571 target->type->read_memory(target, copy_p, 1, 1, &byte);
1572 cfi_add_byte(bank, current_word, byte);
1573 }
1574 retval = cfi_write_word(bank, current_word, write_p);
1575 if (retval != ERROR_OK)
1576 return retval;
1577 }
1578
1579 /* return to read array mode */
1580 cfi_command(bank, 0xf0, current_word);
1581 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1582 cfi_command(bank, 0xff, current_word);
1583 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1584
1585 return ERROR_OK;
1586 }
1587
1588 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1589 {
1590 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1591 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1592
1593 pri_ext->_reversed_geometry = 1;
1594 }
1595
1596 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1597 {
1598 int i;
1599 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1600 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1601
1602 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1603 {
1604 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1605
1606 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1607 {
1608 int j = (cfi_info->num_erase_regions - 1) - i;
1609 u32 swap;
1610
1611 swap = cfi_info->erase_region_info[i];
1612 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1613 cfi_info->erase_region_info[j] = swap;
1614 }
1615 }
1616 }
1617
1618 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1619 {
1620 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1621 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1622 cfi_unlock_addresses_t *unlock_addresses = param;
1623
1624 pri_ext->_unlock1 = unlock_addresses->unlock1;
1625 pri_ext->_unlock2 = unlock_addresses->unlock2;
1626 }
1627
1628 int cfi_probe(struct flash_bank_s *bank)
1629 {
1630 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1631 target_t *target = bank->target;
1632 u8 command[8];
1633 int num_sectors = 0;
1634 int i;
1635 int sector = 0;
1636 u32 offset = 0;
1637 u32 unlock1 = 0x555;
1638 u32 unlock2 = 0x2aa;
1639
1640 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1641 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1642 */
1643 if (cfi_info->jedec_probe)
1644 {
1645 unlock1 = 0x5555;
1646 unlock2 = 0x2aaa;
1647 }
1648
1649 /* switch to read identifier codes mode ("AUTOSELECT") */
1650 cfi_command(bank, 0xaa, command);
1651 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1652 cfi_command(bank, 0x55, command);
1653 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1654 cfi_command(bank, 0x90, command);
1655 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1656
1657 if (bank->chip_width == 1)
1658 {
1659 u8 manufacturer, device_id;
1660 target_read_u8(target, bank->base + 0x0, &manufacturer);
1661 target_read_u8(target, bank->base + 0x1, &device_id);
1662 cfi_info->manufacturer = manufacturer;
1663 cfi_info->device_id = device_id;
1664 }
1665 else if (bank->chip_width == 2)
1666 {
1667 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1668 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1669 }
1670
1671 /* switch back to read array mode */
1672 cfi_command(bank, 0xf0, command);
1673 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1674 cfi_command(bank, 0xff, command);
1675 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1676
1677 cfi_fixup(bank, cfi_jedec_fixups);
1678
1679 /* query only if this is a CFI compatible flash,
1680 * otherwise the relevant info has already been filled in
1681 */
1682 if (cfi_info->not_cfi == 0)
1683 {
1684 /* enter CFI query mode
1685 * according to JEDEC Standard No. 68.01,
1686 * a single bus sequence with address = 0x55, data = 0x98 should put
1687 * the device into CFI query mode.
1688 *
1689 * SST flashes clearly violate this, and we will consider them incompatbile for now
1690 */
1691 cfi_command(bank, 0x98, command);
1692 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1693
1694 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1695 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1696 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1697
1698 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1699
1700 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1701 {
1702 cfi_command(bank, 0xf0, command);
1703 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1704 cfi_command(bank, 0xff, command);
1705 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1706 return ERROR_FLASH_BANK_INVALID;
1707 }
1708
1709 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1710 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1711 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1712 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1713
1714 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1715
1716 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1717 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1718 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1719 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1720 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1721 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1722 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1723 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1724 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1725 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1726 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1727 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1728
1729 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1730 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1731 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1732 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1733 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1734 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1735 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1736 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1737 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1738 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1739 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1740
1741 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1742 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1743 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1744 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1745
1746 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1747
1748 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1749 {
1750 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1751 }
1752
1753 if (cfi_info->num_erase_regions)
1754 {
1755 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1756 for (i = 0; i < cfi_info->num_erase_regions; i++)
1757 {
1758 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1759 DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1760 }
1761 }
1762 else
1763 {
1764 cfi_info->erase_region_info = NULL;
1765 }
1766
1767 /* We need to read the primary algorithm extended query table before calculating
1768 * the sector layout to be able to apply fixups
1769 */
1770 switch(cfi_info->pri_id)
1771 {
1772 /* Intel command set (standard and extended) */
1773 case 0x0001:
1774 case 0x0003:
1775 cfi_read_intel_pri_ext(bank);
1776 break;
1777 /* AMD/Spansion, Atmel, ... command set */
1778 case 0x0002:
1779 cfi_read_0002_pri_ext(bank);
1780 break;
1781 default:
1782 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1783 break;
1784 }
1785
1786 /* return to read array mode
1787 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
1788 */
1789 cfi_command(bank, 0xf0, command);
1790 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1791 cfi_command(bank, 0xff, command);
1792 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1793 }
1794
1795 /* apply fixups depending on the primary command set */
1796 switch(cfi_info->pri_id)
1797 {
1798 /* Intel command set (standard and extended) */
1799 case 0x0001:
1800 case 0x0003:
1801 cfi_fixup(bank, cfi_0001_fixups);
1802 break;
1803 /* AMD/Spansion, Atmel, ... command set */
1804 case 0x0002:
1805 cfi_fixup(bank, cfi_0002_fixups);
1806 break;
1807 default:
1808 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1809 break;
1810 }
1811
1812 if (cfi_info->num_erase_regions == 0)
1813 {
1814 /* a device might have only one erase block, spanning the whole device */
1815 bank->num_sectors = 1;
1816 bank->sectors = malloc(sizeof(flash_sector_t));
1817
1818 bank->sectors[sector].offset = 0x0;
1819 bank->sectors[sector].size = bank->size;
1820 bank->sectors[sector].is_erased = -1;
1821 bank->sectors[sector].is_protected = -1;
1822 }
1823 else
1824 {
1825 for (i = 0; i < cfi_info->num_erase_regions; i++)
1826 {
1827 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
1828 }
1829
1830 bank->num_sectors = num_sectors;
1831 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
1832
1833 for (i = 0; i < cfi_info->num_erase_regions; i++)
1834 {
1835 int j;
1836 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
1837 {
1838 bank->sectors[sector].offset = offset;
1839 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
1840 offset += bank->sectors[sector].size;
1841 bank->sectors[sector].is_erased = -1;
1842 bank->sectors[sector].is_protected = -1;
1843 sector++;
1844 }
1845 }
1846 }
1847
1848 return ERROR_OK;
1849 }
1850
1851 int cfi_erase_check(struct flash_bank_s *bank)
1852 {
1853 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1854 target_t *target = bank->target;
1855 int i;
1856 int retval;
1857
1858 if (!cfi_info->erase_check_algorithm)
1859 {
1860 u32 erase_check_code[] =
1861 {
1862 0xe4d03001, /* ldrb r3, [r0], #1 */
1863 0xe0022003, /* and r2, r2, r3 */
1864 0xe2511001, /* subs r1, r1, #1 */
1865 0x1afffffb, /* b -4 */
1866 0xeafffffe /* b 0 */
1867 };
1868
1869 /* make sure we have a working area */
1870 if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
1871 {
1872 WARNING("no working area available, falling back to slow memory reads");
1873 }
1874 else
1875 {
1876 u8 erase_check_code_buf[5 * 4];
1877
1878 for (i = 0; i < 5; i++)
1879 target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
1880
1881 /* write algorithm code to working area */
1882 target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
1883 }
1884 }
1885
1886 if (!cfi_info->erase_check_algorithm)
1887 {
1888 u32 *buffer = malloc(4096);
1889
1890 for (i = 0; i < bank->num_sectors; i++)
1891 {
1892 u32 address = bank->base + bank->sectors[i].offset;
1893 u32 size = bank->sectors[i].size;
1894 u32 check = 0xffffffffU;
1895 int erased = 1;
1896
1897 while (size > 0)
1898 {
1899 u32 thisrun_size = (size > 4096) ? 4096 : size;
1900 int j;
1901
1902 target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
1903
1904 for (j = 0; j < thisrun_size / 4; j++)
1905 check &= buffer[j];
1906
1907 if (check != 0xffffffff)
1908 {
1909 erased = 0;
1910 break;
1911 }
1912
1913 size -= thisrun_size;
1914 address += thisrun_size;
1915 }
1916
1917 bank->sectors[i].is_erased = erased;
1918 }
1919
1920 free(buffer);
1921 }
1922 else
1923 {
1924 for (i = 0; i < bank->num_sectors; i++)
1925 {
1926 u32 address = bank->base + bank->sectors[i].offset;
1927 u32 size = bank->sectors[i].size;
1928
1929 reg_param_t reg_params[3];
1930 armv4_5_algorithm_t armv4_5_info;
1931
1932 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1933 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1934 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1935
1936 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1937 buf_set_u32(reg_params[0].value, 0, 32, address);
1938
1939 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1940 buf_set_u32(reg_params[1].value, 0, 32, size);
1941
1942 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1943 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1944
1945 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
1946 return ERROR_FLASH_OPERATION_FAILED;
1947
1948 if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
1949 bank->sectors[i].is_erased = 1;
1950 else
1951 bank->sectors[i].is_erased = 0;
1952
1953 destroy_reg_param(&reg_params[0]);
1954 destroy_reg_param(&reg_params[1]);
1955 destroy_reg_param(&reg_params[2]);
1956 }
1957 }
1958
1959 return ERROR_OK;
1960 }
1961
1962 int cfi_intel_protect_check(struct flash_bank_s *bank)
1963 {
1964 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1965 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
1966 target_t *target = bank->target;
1967 u8 command[CFI_MAX_BUS_WIDTH];
1968 int i;
1969
1970 /* check if block lock bits are supported on this device */
1971 if (!(pri_ext->blk_status_reg_mask & 0x1))
1972 return ERROR_FLASH_OPERATION_FAILED;
1973
1974 cfi_command(bank, 0x90, command);
1975 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1976
1977 for (i = 0; i < bank->num_sectors; i++)
1978 {
1979 u8 block_status = cfi_get_u8(bank, i, 0x2);
1980
1981 if (block_status & 1)
1982 bank->sectors[i].is_protected = 1;
1983 else
1984 bank->sectors[i].is_protected = 0;
1985 }
1986
1987 cfi_command(bank, 0xff, command);
1988 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1989
1990 return ERROR_OK;
1991 }
1992
1993 int cfi_spansion_protect_check(struct flash_bank_s *bank)
1994 {
1995 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1996 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1997 target_t *target = bank->target;
1998 u8 command[8];
1999 int i;
2000
2001 cfi_command(bank, 0xaa, command);
2002 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2003
2004 cfi_command(bank, 0x55, command);
2005 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2006
2007 cfi_command(bank, 0x90, command);
2008 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2009
2010 for (i = 0; i < bank->num_sectors; i++)
2011 {
2012 u8 block_status = cfi_get_u8(bank, i, 0x2);
2013
2014 if (block_status & 1)
2015 bank->sectors[i].is_protected = 1;
2016 else
2017 bank->sectors[i].is_protected = 0;
2018 }
2019
2020 cfi_command(bank, 0xf0, command);
2021 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2022
2023 return ERROR_OK;
2024 }
2025
2026 int cfi_protect_check(struct flash_bank_s *bank)
2027 {
2028 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2029
2030 if (cfi_info->qry[0] != 'Q')
2031 return ERROR_FLASH_BANK_NOT_PROBED;
2032
2033 switch(cfi_info->pri_id)
2034 {
2035 case 1:
2036 case 3:
2037 return cfi_intel_protect_check(bank);
2038 break;
2039 case 2:
2040 return cfi_spansion_protect_check(bank);
2041 break;
2042 default:
2043 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2044 break;
2045 }
2046
2047 return ERROR_OK;
2048 }
2049
2050 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2051 {
2052 int printed;
2053 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2054
2055 if (cfi_info->qry[0] == (char)-1)
2056 {
2057 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2058 return ERROR_OK;
2059 }
2060
2061 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2062 buf += printed;
2063 buf_size -= printed;
2064
2065 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2066 cfi_info->manufacturer, cfi_info->device_id);
2067 buf += printed;
2068 buf_size -= printed;
2069
2070 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2071 buf += printed;
2072 buf_size -= printed;
2073
2074 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2075 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2076 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2077 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2078 buf += printed;
2079 buf_size -= printed;
2080
2081 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2082 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2083 buf += printed;
2084 buf_size -= printed;
2085
2086 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2087 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2088 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2089 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2090 buf += printed;
2091 buf_size -= printed;
2092
2093 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size);
2094 buf += printed;
2095 buf_size -= printed;
2096
2097 switch(cfi_info->pri_id)
2098 {
2099 case 1:
2100 case 3:
2101 cfi_intel_info(bank, buf, buf_size);
2102 break;
2103 case 2:
2104 cfi_spansion_info(bank, buf, buf_size);
2105 break;
2106 default:
2107 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2108 break;
2109 }
2110
2111 return ERROR_OK;
2112 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)