f9142348a2900af36e7e5837d933916bbbcd73b1
[openocd.git] / src / flash / aduc702x.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Kevin McGuire *
3 * Copyright (C) 2008 by Marcel Wijlaars *
4 * Copyright (C) 2009 by Michael Ashton *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "replacements.h"
27 #include "time_support.h"
28 #include "flash.h"
29 #include "target.h"
30 #include "log.h"
31 #include "armv4_5.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
34
35 #include <stdlib.h>
36 #include <string.h>
37 #include <unistd.h>
38
39 int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
40 int aduc702x_register_commands(struct command_context_s *cmd_ctx);
41 int aduc702x_erase(struct flash_bank_s *bank, int first, int last);
42 int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last);
43 int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
44 int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int aduc702x_probe(struct flash_bank_s *bank);
47 int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size);
48 int aduc702x_protect_check(struct flash_bank_s *bank);
49 int aduc702x_build_sector_list(struct flash_bank_s *bank);
50 int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
51 int aduc702x_set_write_enable(target_t *target, int enable);
52
53 #define ADUC702x_FLASH 0xfffff800
54 #define ADUC702x_FLASH_FEESTA (0*4)
55 #define ADUC702x_FLASH_FEEMOD (1*4)
56 #define ADUC702x_FLASH_FEECON (2*4)
57 #define ADUC702x_FLASH_FEEDAT (3*4)
58 #define ADUC702x_FLASH_FEEADR (4*4)
59 #define ADUC702x_FLASH_FEESIGN (5*4)
60 #define ADUC702x_FLASH_FEEPRO (6*4)
61 #define ADUC702x_FLASH_FEEHIDE (7*4)
62
63 typedef struct {
64 u32 feesta;
65 u32 feemod;
66 u32 feecon;
67 u32 feedat;
68 u32 feeadr;
69 u32 feesign;
70 u32 feepro;
71 u32 feehide;
72 } ADUC702x_FLASH_MMIO;
73
74 typedef struct
75 {
76 working_area_t *write_algorithm;
77 } aduc702x_flash_bank_t;
78
79 flash_driver_t aduc702x_flash =
80 {
81 .name = "aduc702x",
82 .register_commands = aduc702x_register_commands,
83 .flash_bank_command = aduc702x_flash_bank_command,
84 .erase = aduc702x_erase,
85 .protect = aduc702x_protect,
86 .write = aduc702x_write,
87 .probe = aduc702x_probe,
88 .auto_probe = aduc702x_probe,
89 .erase_check = default_flash_blank_check,
90 .protect_check = aduc702x_protect_check,
91 .info = aduc702x_info
92 };
93
94 int aduc702x_register_commands(struct command_context_s *cmd_ctx)
95 {
96 return ERROR_OK;
97 }
98
99 /* flash bank aduc702x 0 0 0 0 <target#>
100 * The ADC7019-28 devices all have the same flash layout */
101 int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
102 {
103 aduc702x_flash_bank_t *nbank;
104
105 nbank = malloc(sizeof(aduc702x_flash_bank_t));
106
107 bank->base = 0x80000;
108 bank->size = 0xF800; // top 4k not accessible
109 bank->driver_priv = nbank;
110
111 aduc702x_build_sector_list(bank);
112
113 return ERROR_OK;
114 }
115
116 int aduc702x_build_sector_list(struct flash_bank_s *bank)
117 {
118 //aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
119
120 int i = 0;
121 u32 offset = 0;
122
123 // sector size is 512
124 bank->num_sectors = bank->size / 512;
125 bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
126 for (i = 0; i < bank->num_sectors; ++i)
127 {
128 bank->sectors[i].offset = offset;
129 bank->sectors[i].size = 512;
130 offset += bank->sectors[i].size;
131 bank->sectors[i].is_erased = -1;
132 bank->sectors[i].is_protected = 0;
133 }
134
135 return ERROR_OK;
136 }
137
138 int aduc702x_protect_check(struct flash_bank_s *bank)
139 {
140 printf("aduc702x_protect_check not implemented yet.\n");
141 return ERROR_OK;
142 }
143
144 int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
145 {
146 //int res;
147 int x;
148 int count;
149 //u32 v;
150 target_t *target = bank->target;
151
152 aduc702x_set_write_enable(target, 1);
153
154 /* mass erase */
155 if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
156 LOG_DEBUG("performing mass erase.\n");
157 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
158 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
159 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
160
161 if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK)
162 {
163 LOG_ERROR("mass erase failed\n");
164 aduc702x_set_write_enable(target, 0);
165 return ERROR_FLASH_OPERATION_FAILED;
166 }
167
168 LOG_DEBUG("mass erase successful.\n");
169 return ERROR_OK;
170 } else {
171 unsigned long adr;
172
173 count = last - first + 1;
174 for (x = 0; x < count; ++x)
175 {
176 adr = bank->base + ((first + x) * 512);
177
178 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
179 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
180
181 if (aduc702x_check_flash_completion(target, 50) != ERROR_OK)
182 {
183 LOG_ERROR("failed to erase sector at address 0x%08lX\n", adr);
184 aduc702x_set_write_enable(target, 0);
185 return ERROR_FLASH_SECTOR_NOT_ERASED;
186 }
187
188 LOG_DEBUG("erased sector at address 0x%08lX\n", adr);
189 }
190 }
191
192 aduc702x_set_write_enable(target, 0);
193
194 return ERROR_OK;
195 }
196
197 int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last)
198 {
199 printf("aduc702x_protect not implemented yet.\n");
200 return ERROR_FLASH_OPERATION_FAILED;
201 }
202
203 int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
204 {
205 aduc702x_flash_bank_t *aduc702x_info = bank->driver_priv;
206 target_t *target = bank->target;
207 u32 buffer_size = 7000;
208 working_area_t *source;
209 u32 address = bank->base + offset;
210 reg_param_t reg_params[6];
211 armv4_5_algorithm_t armv4_5_info;
212 int retval = ERROR_OK;
213
214 /* parameters:
215
216 r0 - address of source data (absolute)
217 r1 - number of halfwords to be copied
218 r2 - start address in flash (offset from beginning of flash memory)
219 r3 - exit code
220 r4 - base address of flash controller (0xFFFFF800)
221
222 registers:
223
224 r5 - scratch
225 r6 - set to 2, used to write flash command
226
227 */
228 u32 aduc702x_flash_write_code[] = {
229 //<_start>:
230 0xe3a05008, // mov r5, #8 ; 0x8
231 0xe5845004, // str r5, [r4, #4]
232 0xe3a06002, // mov r6, #2 ; 0x2
233 //<next>:
234 0xe1c421b0, // strh r2, [r4, #16]
235 0xe0d050b2, // ldrh r5, [r0], #2
236 0xe1c450bc, // strh r5, [r4, #12]
237 0xe5c46008, // strb r6, [r4, #8]
238 //<wait_complete>:
239 0xe1d430b0, // ldrh r3, [r4]
240 0xe3130004, // tst r3, #4 ; 0x4
241 0x1afffffc, // bne 1001c <wait_complete>
242 0xe2822002, // add r2, r2, #2 ; 0x2
243 0xe2511001, // subs r1, r1, #1 ; 0x1
244 0x0a000001, // beq 1003c <done>
245 0xe3130001, // tst r3, #1 ; 0x1
246 0x1afffff3, // bne 1000c <next>
247 //<done>:
248 0xeafffffe // b 1003c <done>
249 };
250
251 /* flash write code */
252 if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
253 &aduc702x_info->write_algorithm) != ERROR_OK)
254 {
255 LOG_WARNING("no working area available, can't do block memory writes");
256 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
257 };
258
259 target_write_buffer(target, aduc702x_info->write_algorithm->address,
260 sizeof(aduc702x_flash_write_code), (u8*)aduc702x_flash_write_code);
261
262 /* memory buffer */
263 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
264 {
265 buffer_size /= 2;
266 if (buffer_size <= 256)
267 {
268 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
269 if (aduc702x_info->write_algorithm)
270 target_free_working_area(target, aduc702x_info->write_algorithm);
271
272 LOG_WARNING("no large enough working area available, can't do block memory writes");
273 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
274 }
275 }
276
277 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
278 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
279 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
280
281 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
282 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
283 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
284 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
285 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
286
287 while (count > 0)
288 {
289 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
290
291 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
292
293 buf_set_u32(reg_params[0].value, 0, 32, source->address);
294 buf_set_u32(reg_params[1].value, 0, 32, thisrun_count);
295 buf_set_u32(reg_params[2].value, 0, 32, address);
296 buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
297
298 if ((retval = target->type->run_algorithm(target, 0, NULL, 5,
299 reg_params, aduc702x_info->write_algorithm->address,
300 aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
301 10000, &armv4_5_info)) != ERROR_OK)
302 {
303 LOG_ERROR("error executing aduc702x flash write algorithm");
304 retval = ERROR_FLASH_OPERATION_FAILED;
305 break;
306 }
307
308 if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
309 retval = ERROR_FLASH_OPERATION_FAILED;
310 break;
311 }
312
313 buffer += thisrun_count * 2;
314 address += thisrun_count * 2;
315 count -= thisrun_count;
316 }
317
318 target_free_working_area(target, source);
319 target_free_working_area(target, aduc702x_info->write_algorithm);
320
321 destroy_reg_param(&reg_params[0]);
322 destroy_reg_param(&reg_params[1]);
323 destroy_reg_param(&reg_params[2]);
324 destroy_reg_param(&reg_params[3]);
325 destroy_reg_param(&reg_params[4]);
326
327 return retval;
328 }
329
330 /* All-JTAG, single-access method. Very slow. Used only if there is no
331 * working area available. */
332 int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
333 {
334 int x;
335 u8 b;
336 target_t *target = bank->target;
337
338 aduc702x_set_write_enable(target, 1);
339
340 for (x = 0; x < count; x += 2) {
341 // FEEADR = address
342 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
343
344 // set up data
345 if ((x + 1) == count)
346 {
347 // last byte
348 target_read_u8(target, offset + x + 1, &b);
349 }
350 else
351 b = buffer[x + 1];
352
353 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
354
355 // do single-write command
356 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
357
358 if (aduc702x_check_flash_completion(target, 1) != ERROR_OK)
359 {
360 LOG_ERROR("single write failed for address 0x%08lX\n", (unsigned long)(offset + x));
361 aduc702x_set_write_enable(target, 0);
362 return ERROR_FLASH_OPERATION_FAILED;
363 }
364
365 }
366 LOG_DEBUG("wrote %d bytes at address 0x%08lX\n", (int)count, (unsigned long)(offset + x));
367
368 aduc702x_set_write_enable(target, 0);
369
370 return ERROR_OK;
371 }
372
373 int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
374 {
375 int retval;
376
377 /* try using a block write */
378 if ((retval = aduc702x_write_block(bank, buffer, offset, count)) != ERROR_OK)
379 {
380 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
381 {
382 /* if block write failed (no sufficient working area),
383 * use normal (slow) JTAG method */
384 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
385
386 if ((retval = aduc702x_write_single(bank, buffer, offset, count)) != ERROR_OK)
387 {
388 LOG_ERROR("slow write failed");
389 return ERROR_FLASH_OPERATION_FAILED;
390 }
391 }
392 else if (retval == ERROR_FLASH_OPERATION_FAILED)
393 {
394 LOG_ERROR("flash block writing failed");
395 return ERROR_FLASH_OPERATION_FAILED;
396 }
397 }
398
399 return ERROR_OK;
400 }
401
402 int aduc702x_probe(struct flash_bank_s *bank)
403 {
404 return ERROR_OK;
405 }
406
407 int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
408 {
409 snprintf(buf, buf_size, "aduc702x flash driver info" );
410 return ERROR_OK;
411 }
412
413 /* sets FEEMOD bit 3
414 * enable = 1 enables writes & erases, 0 disables them */
415 int aduc702x_set_write_enable(target_t *target, int enable)
416 {
417 // don't bother to preserve int enable bit here
418 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
419
420 return ERROR_OK;
421 }
422
423 /* wait up to timeout_ms for controller to not be busy,
424 * then check whether the command passed or failed.
425 *
426 * this function sleeps 1ms between checks (after the first one),
427 * so in some cases may slow things down without a usleep after the first read */
428 int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
429 {
430 u8 v = 4;
431
432 long long endtime = timeval_ms() + timeout_ms;
433 while (1) {
434 target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
435 if ((v & 4) == 0) break;
436 alive_sleep(1);
437 if (timeval_ms() >= endtime) break;
438 }
439
440 if (v & 2) return ERROR_FAIL;
441 // if a command is ignored, both the success and fail bits may be 0
442 else if ((v & 3) == 0) return ERROR_FAIL;
443 else return ERROR_OK;
444 }
445

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