c17335e15a9dac5adc0d9d8699c26c18f3ded2c1
[openocd.git] / src / flash / aduc702x.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Kevin McGuire *
3 * Copyright (C) 2008 by Marcel Wijlaars *
4 * Copyright (C) 2009 by Michael Ashton *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "flash.h"
27 #include "armv4_5.h"
28 #include "binarybuffer.h"
29 #include "time_support.h"
30
31
32 static int aduc702x_build_sector_list(struct flash_bank_s *bank);
33 static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
34 static int aduc702x_set_write_enable(target_t *target, int enable);
35
36 #define ADUC702x_FLASH 0xfffff800
37 #define ADUC702x_FLASH_FEESTA (0*4)
38 #define ADUC702x_FLASH_FEEMOD (1*4)
39 #define ADUC702x_FLASH_FEECON (2*4)
40 #define ADUC702x_FLASH_FEEDAT (3*4)
41 #define ADUC702x_FLASH_FEEADR (4*4)
42 #define ADUC702x_FLASH_FEESIGN (5*4)
43 #define ADUC702x_FLASH_FEEPRO (6*4)
44 #define ADUC702x_FLASH_FEEHIDE (7*4)
45
46 typedef struct {
47 uint32_t feesta;
48 uint32_t feemod;
49 uint32_t feecon;
50 uint32_t feedat;
51 uint32_t feeadr;
52 uint32_t feesign;
53 uint32_t feepro;
54 uint32_t feehide;
55 } ADUC702x_FLASH_MMIO;
56
57 typedef struct
58 {
59 working_area_t *write_algorithm;
60 } aduc702x_flash_bank_t;
61
62 /* flash bank aduc702x 0 0 0 0 <target#>
63 * The ADC7019-28 devices all have the same flash layout */
64 FLASH_BANK_COMMAND_HANDLER(aduc702x_flash_bank_command)
65 {
66 aduc702x_flash_bank_t *nbank;
67
68 nbank = malloc(sizeof(aduc702x_flash_bank_t));
69
70 bank->base = 0x80000;
71 bank->size = 0xF800; // top 4k not accessible
72 bank->driver_priv = nbank;
73
74 aduc702x_build_sector_list(bank);
75
76 return ERROR_OK;
77 }
78
79 static int aduc702x_build_sector_list(struct flash_bank_s *bank)
80 {
81 //aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
82
83 int i = 0;
84 uint32_t offset = 0;
85
86 // sector size is 512
87 bank->num_sectors = bank->size / 512;
88 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
89 for (i = 0; i < bank->num_sectors; ++i)
90 {
91 bank->sectors[i].offset = offset;
92 bank->sectors[i].size = 512;
93 offset += bank->sectors[i].size;
94 bank->sectors[i].is_erased = -1;
95 bank->sectors[i].is_protected = 0;
96 }
97
98 return ERROR_OK;
99 }
100
101 static int aduc702x_protect_check(struct flash_bank_s *bank)
102 {
103 printf("aduc702x_protect_check not implemented yet.\n");
104 return ERROR_OK;
105 }
106
107 static int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
108 {
109 //int res;
110 int x;
111 int count;
112 //uint32_t v;
113 target_t *target = bank->target;
114
115 aduc702x_set_write_enable(target, 1);
116
117 /* mass erase */
118 if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
119 LOG_DEBUG("performing mass erase.\n");
120 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
121 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
122 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
123
124 if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK)
125 {
126 LOG_ERROR("mass erase failed\n");
127 aduc702x_set_write_enable(target, 0);
128 return ERROR_FLASH_OPERATION_FAILED;
129 }
130
131 LOG_DEBUG("mass erase successful.\n");
132 return ERROR_OK;
133 } else {
134 unsigned long adr;
135
136 count = last - first + 1;
137 for (x = 0; x < count; ++x)
138 {
139 adr = bank->base + ((first + x) * 512);
140
141 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
142 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
143
144 if (aduc702x_check_flash_completion(target, 50) != ERROR_OK)
145 {
146 LOG_ERROR("failed to erase sector at address 0x%08lX\n", adr);
147 aduc702x_set_write_enable(target, 0);
148 return ERROR_FLASH_SECTOR_NOT_ERASED;
149 }
150
151 LOG_DEBUG("erased sector at address 0x%08lX\n", adr);
152 }
153 }
154
155 aduc702x_set_write_enable(target, 0);
156
157 return ERROR_OK;
158 }
159
160 static int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last)
161 {
162 printf("aduc702x_protect not implemented yet.\n");
163 return ERROR_FLASH_OPERATION_FAILED;
164 }
165
166 /* If this fn returns ERROR_TARGET_RESOURCE_NOT_AVAILABLE, then the caller can fall
167 * back to another mechanism that does not require onboard RAM
168 *
169 * Caller should not check for other return values specifically
170 */
171 static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
172 {
173 aduc702x_flash_bank_t *aduc702x_info = bank->driver_priv;
174 target_t *target = bank->target;
175 uint32_t buffer_size = 7000;
176 working_area_t *source;
177 uint32_t address = bank->base + offset;
178 reg_param_t reg_params[6];
179 armv4_5_algorithm_t armv4_5_info;
180 int retval = ERROR_OK;
181
182 if (((count%2)!=0)||((offset%2)!=0))
183 {
184 LOG_ERROR("write block must be multiple of two bytes in offset & length");
185 return ERROR_FAIL;
186 }
187
188 /* parameters:
189
190 r0 - address of source data (absolute)
191 r1 - number of halfwords to be copied
192 r2 - start address in flash (offset from beginning of flash memory)
193 r3 - exit code
194 r4 - base address of flash controller (0xFFFFF800)
195
196 registers:
197
198 r5 - scratch
199 r6 - set to 2, used to write flash command
200
201 */
202 uint32_t aduc702x_flash_write_code[] = {
203 //<_start>:
204 0xe3a05008, // mov r5, #8 ; 0x8
205 0xe5845004, // str r5, [r4, #4]
206 0xe3a06002, // mov r6, #2 ; 0x2
207 //<next>:
208 0xe1c421b0, // strh r2, [r4, #16]
209 0xe0d050b2, // ldrh r5, [r0], #2
210 0xe1c450bc, // strh r5, [r4, #12]
211 0xe5c46008, // strb r6, [r4, #8]
212 //<wait_complete>:
213 0xe1d430b0, // ldrh r3, [r4]
214 0xe3130004, // tst r3, #4 ; 0x4
215 0x1afffffc, // bne 1001c <wait_complete>
216 0xe2822002, // add r2, r2, #2 ; 0x2
217 0xe2511001, // subs r1, r1, #1 ; 0x1
218 0x0a000001, // beq 1003c <done>
219 0xe3130001, // tst r3, #1 ; 0x1
220 0x1afffff3, // bne 1000c <next>
221 //<done>:
222 0xeafffffe // b 1003c <done>
223 };
224
225 /* flash write code */
226 if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
227 &aduc702x_info->write_algorithm) != ERROR_OK)
228 {
229 LOG_WARNING("no working area available, can't do block memory writes");
230 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
231 };
232
233 retval=target_write_buffer(target, aduc702x_info->write_algorithm->address,
234 sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);
235 if (retval!=ERROR_OK)
236 {
237 return retval;
238 }
239
240 /* memory buffer */
241 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
242 {
243 buffer_size /= 2;
244 if (buffer_size <= 256)
245 {
246 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
247 if (aduc702x_info->write_algorithm)
248 target_free_working_area(target, aduc702x_info->write_algorithm);
249
250 LOG_WARNING("no large enough working area available, can't do block memory writes");
251 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
252 }
253 }
254
255 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
256 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
257 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
258
259 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
260 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
261 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
262 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
263 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
264
265 while (count > 0)
266 {
267 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
268
269 retval=target_write_buffer(target, source->address, thisrun_count, buffer);
270 if (retval!=ERROR_OK)
271 {
272 break;
273 }
274
275 buf_set_u32(reg_params[0].value, 0, 32, source->address);
276 buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
277 buf_set_u32(reg_params[2].value, 0, 32, address);
278 buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
279
280 if ((retval = target_run_algorithm(target, 0, NULL, 5,
281 reg_params, aduc702x_info->write_algorithm->address,
282 aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
283 10000, &armv4_5_info)) != ERROR_OK)
284 {
285 LOG_ERROR("error executing aduc702x flash write algorithm");
286 break;
287 }
288
289 if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1)
290 {
291 /* FIX!!!! what does this mean??? replace w/sensible error message */
292 LOG_ERROR("aduc702x detected error writing flash");
293 retval = ERROR_FAIL;
294 break;
295 }
296
297 buffer += thisrun_count;
298 address += thisrun_count;
299 count -= thisrun_count;
300 }
301
302 target_free_working_area(target, source);
303 target_free_working_area(target, aduc702x_info->write_algorithm);
304
305 destroy_reg_param(&reg_params[0]);
306 destroy_reg_param(&reg_params[1]);
307 destroy_reg_param(&reg_params[2]);
308 destroy_reg_param(&reg_params[3]);
309 destroy_reg_param(&reg_params[4]);
310
311 return retval;
312 }
313
314 /* All-JTAG, single-access method. Very slow. Used only if there is no
315 * working area available. */
316 static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
317 {
318 uint32_t x;
319 uint8_t b;
320 target_t *target = bank->target;
321
322 aduc702x_set_write_enable(target, 1);
323
324 for (x = 0; x < count; x += 2) {
325 // FEEADR = address
326 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
327
328 // set up data
329 if ((x + 1) == count)
330 {
331 // last byte
332 target_read_u8(target, offset + x + 1, &b);
333 }
334 else
335 b = buffer[x + 1];
336
337 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
338
339 // do single-write command
340 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
341
342 if (aduc702x_check_flash_completion(target, 1) != ERROR_OK)
343 {
344 LOG_ERROR("single write failed for address 0x%08lX\n", (unsigned long)(offset + x));
345 aduc702x_set_write_enable(target, 0);
346 return ERROR_FLASH_OPERATION_FAILED;
347 }
348
349 }
350 LOG_DEBUG("wrote %d bytes at address 0x%08lX\n", (int)count, (unsigned long)(offset + x));
351
352 aduc702x_set_write_enable(target, 0);
353
354 return ERROR_OK;
355 }
356
357 int aduc702x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
358 {
359 int retval;
360
361 /* try using a block write */
362 if ((retval = aduc702x_write_block(bank, buffer, offset, count)) != ERROR_OK)
363 {
364 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
365 {
366 /* if block write failed (no sufficient working area),
367 * use normal (slow) JTAG method */
368 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
369
370 if ((retval = aduc702x_write_single(bank, buffer, offset, count)) != ERROR_OK)
371 {
372 LOG_ERROR("slow write failed");
373 return ERROR_FLASH_OPERATION_FAILED;
374 }
375 }
376 }
377
378 return retval;
379 }
380
381 static int aduc702x_probe(struct flash_bank_s *bank)
382 {
383 return ERROR_OK;
384 }
385
386 static int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
387 {
388 snprintf(buf, buf_size, "aduc702x flash driver info");
389 return ERROR_OK;
390 }
391
392 /* sets FEEMOD bit 3
393 * enable = 1 enables writes & erases, 0 disables them */
394 static int aduc702x_set_write_enable(target_t *target, int enable)
395 {
396 // don't bother to preserve int enable bit here
397 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
398
399 return ERROR_OK;
400 }
401
402 /* wait up to timeout_ms for controller to not be busy,
403 * then check whether the command passed or failed.
404 *
405 * this function sleeps 1ms between checks (after the first one),
406 * so in some cases may slow things down without a usleep after the first read */
407 static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
408 {
409 uint8_t v = 4;
410
411 long long endtime = timeval_ms() + timeout_ms;
412 while (1) {
413 target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
414 if ((v & 4) == 0) break;
415 alive_sleep(1);
416 if (timeval_ms() >= endtime) break;
417 }
418
419 if (v & 2) return ERROR_FAIL;
420 // if a command is ignored, both the success and fail bits may be 0
421 else if ((v & 3) == 0) return ERROR_FAIL;
422 else return ERROR_OK;
423 }
424
425 struct flash_driver aduc702x_flash = {
426 .name = "aduc702x",
427 .flash_bank_command = &aduc702x_flash_bank_command,
428 .erase = &aduc702x_erase,
429 .protect = &aduc702x_protect,
430 .write = &aduc702x_write,
431 .probe = &aduc702x_probe,
432 .auto_probe = &aduc702x_probe,
433 .erase_check = &default_flash_blank_check,
434 .protect_check = &aduc702x_protect_check,
435 .info = &aduc702x_info
436 };