1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are three things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
257 @item @b{Connection} Printer Ports - Does your computer have one?
258 @item @b{Connection} Is that long printer bit-bang cable practical?
259 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
262 @section Stand alone Systems
264 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
265 dongle, but a standalone box. The ZY1000 has the advantage that it does
266 not require any drivers installed on the developer PC. It also has
267 a built in web interface. It supports RTCK/RCLK or adaptive clocking
268 and has a built in relay to power cycle targets remotely.
270 @section USB FT2232 Based
272 There are many USB JTAG dongles on the market, many of them are based
273 on a chip from ``Future Technology Devices International'' (FTDI)
274 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
275 See: @url{http://www.ftdichip.com} for more information.
276 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
277 chips are starting to become available in JTAG adapters.
281 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
283 @* See: @url{http://www.amontec.com/jtagkey.shtml}
285 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
287 @* See: @url{http://www.signalyzer.com}
288 @item @b{evb_lm3s811}
289 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
290 @item @b{luminary_icdi}
291 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
292 @item @b{olimex-jtag}
293 @* See: @url{http://www.olimex.com}
295 @* See: @url{http://www.tincantools.com}
296 @item @b{turtelizer2}
298 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
299 @url{http://www.ethernut.de}
301 @* Link: @url{http://www.hitex.com/index.php?id=383}
303 @* Link @url{http://www.hitex.com/stm32-stick}
304 @item @b{axm0432_jtag}
305 @* Axiom AXM-0432 Link @url{http://www.axman.com}
307 @* Link @url{http://www.hitex.com/index.php?id=cortino}
310 @section USB JLINK based
311 There are several OEM versions of the Segger @b{JLINK} adapter. It is
312 an example of a micro controller based JTAG adapter, it uses an
313 AT91SAM764 internally.
316 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
317 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
318 @item @b{SEGGER JLINK}
319 @* Link: @url{http://www.segger.com/jlink.html}
321 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
324 @section USB RLINK based
325 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
328 @item @b{Raisonance RLink}
329 @* Link: @url{http://www.raisonance.com/products/RLink.php}
330 @item @b{STM32 Primer}
331 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
332 @item @b{STM32 Primer2}
333 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
339 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
341 @item @b{USB - Presto}
342 @* Link: @url{http://tools.asix.net/prg_presto.htm}
344 @item @b{Versaloon-Link}
345 @* Link: @url{http://www.simonqian.com/en/Versaloon}
347 @item @b{ARM-JTAG-EW}
348 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
351 @section IBM PC Parallel Printer Port Based
353 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
354 and the MacGraigor Wiggler. There are many clones and variations of
359 @item @b{Wiggler} - There are many clones of this.
360 @* Link: @url{http://www.macraigor.com/wiggler.htm}
362 @item @b{DLC5} - From XILINX - There are many clones of this
363 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
364 produced, PDF schematics are easily found and it is easy to make.
366 @item @b{Amontec - JTAG Accelerator}
367 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
370 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
373 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
374 Improved parallel-port wiggler-style JTAG adapter}
376 @item @b{Wiggler_ntrst_inverted}
377 @* Yet another variation - See the source code, src/jtag/parport.c
379 @item @b{old_amt_wiggler}
380 @* Unknown - probably not on the market today
383 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
386 @* Link: @url{http://www.amontec.com/chameleon.shtml}
392 @* ispDownload from Lattice Semiconductor
393 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
396 @* From ST Microsystems;
397 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
398 FlashLINK JTAG programing cable for PSD and uPSD}
406 @* An EP93xx based Linux machine using the GPIO pins directly.
409 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
414 @chapter About JIM-Tcl
418 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
419 This programming language provides a simple and extensible
422 All commands presented in this Guide are extensions to JIM-Tcl.
423 You can use them as simple commands, without needing to learn
424 much of anything about Tcl.
425 Alternatively, can write Tcl programs with them.
427 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
430 @item @b{JIM vs. Tcl}
431 @* JIM-TCL is a stripped down version of the well known Tcl language,
432 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
433 fewer features. JIM-Tcl is a single .C file and a single .H file and
434 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
435 4.2 MB .zip file containing 1540 files.
437 @item @b{Missing Features}
438 @* Our practice has been: Add/clone the real Tcl feature if/when
439 needed. We welcome JIM Tcl improvements, not bloat.
442 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
443 command interpreter today is a mixture of (newer)
444 JIM-Tcl commands, and (older) the orginal command interpreter.
447 @* At the OpenOCD telnet command line (or via the GDB mon command) one
448 can type a Tcl for() loop, set variables, etc.
449 Some of the commands documented in this guide are implemented
450 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
452 @item @b{Historical Note}
453 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
455 @item @b{Need a crash course in Tcl?}
456 @*@xref{Tcl Crash Course}.
461 @cindex command line options
463 @cindex directory search
465 The @option{--help} option shows:
469 --help | -h display this help
470 --version | -v display OpenOCD version
471 --file | -f use configuration file <name>
472 --search | -s dir to search for config files and scripts
473 --debug | -d set debug level <0-3>
474 --log_output | -l redirect log output to file <name>
475 --command | -c run <command>
476 --pipe | -p use pipes when talking to gdb
479 By default OpenOCD reads the file configuration file ``openocd.cfg''
480 in the current directory. To specify a different (or multiple)
481 configuration file, you can use the ``-f'' option. For example:
484 openocd -f config1.cfg -f config2.cfg -f config3.cfg
487 Once started, OpenOCD runs as a daemon, waiting for connections from
488 clients (Telnet, GDB, Other).
490 If you are having problems, you can enable internal debug messages via
493 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
494 @option{-c} command line switch.
496 To enable debug output (when reporting problems or working on OpenOCD
497 itself), use the @option{-d} command line switch. This sets the
498 @option{debug_level} to "3", outputting the most information,
499 including debug messages. The default setting is "2", outputting only
500 informational messages, warnings and errors. You can also change this
501 setting from within a telnet or gdb session using @command{debug_level
502 <n>} (@pxref{debug_level}).
504 You can redirect all output from the daemon to a file using the
505 @option{-l <logfile>} switch.
507 Search paths for config/script files can be added to OpenOCD by using
508 the @option{-s <search>} switch. The current directory and the OpenOCD
509 target library is in the search path by default.
511 For details on the @option{-p} option. @xref{Connecting to GDB}.
513 Note! OpenOCD will launch the GDB & telnet server even if it can not
514 establish a connection with the target. In general, it is possible for
515 the JTAG controller to be unresponsive until the target is set up
516 correctly via e.g. GDB monitor commands in a GDB init script.
518 @node OpenOCD Project Setup
519 @chapter OpenOCD Project Setup
521 To use OpenOCD with your development projects, you need to do more than
522 just connecting the JTAG adapter hardware (dongle) to your development board
523 and then starting the OpenOCD server.
524 You also need to configure that server so that it knows
525 about that adapter and board, and helps your work.
527 @section Hooking up the JTAG Adapter
529 Today's most common case is a dongle with a JTAG cable on one side
530 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
531 and a USB cable on the other.
532 Instead of USB, some cables use Ethernet;
533 older ones may use a PC parallel port, or even a serial port.
536 @item @emph{Start with power to your target board turned off},
537 and nothing connected to your JTAG adapter.
538 If you're particularly paranoid, unplug power to the board.
539 It's important to have the ground signal properly set up,
540 unless you are using a JTAG adapter which provides
541 galvanic isolation between the target board and the
544 @item @emph{Be sure it's the right kind of JTAG connector.}
545 If your dongle has a 20-pin ARM connector, you need some kind
546 of adapter (or octopus, see below) to hook it up to
547 boards using 14-pin or 10-pin connectors ... or to 20-pin
548 connectors which don't use ARM's pinout.
550 In the same vein, make sure the voltage levels are compatible.
551 Not all JTAG adapters have the level shifters needed to work
552 with 1.2 Volt boards.
554 @item @emph{Be certain the cable is properly oriented} or you might
555 damage your board. In most cases there are only two possible
556 ways to connect the cable.
557 Connect the JTAG cable from your adapter to the board.
558 Be sure it's firmly connected.
560 In the best case, the connector is keyed to physically
561 prevent you from inserting it wrong.
562 This is most often done using a slot on the board's male connector
563 housing, which must match a key on the JTAG cable's female connector.
564 If there's no housing, then you must look carefully and
565 make sure pin 1 on the cable hooks up to pin 1 on the board.
566 Ribbon cables are frequently all grey except for a wire on one
567 edge, which is red. The red wire is pin 1.
569 Sometimes dongles provide cables where one end is an ``octopus'' of
570 color coded single-wire connectors, instead of a connector block.
571 These are great when converting from one JTAG pinout to another,
572 but are tedious to set up.
573 Use these with connector pinout diagrams to help you match up the
574 adapter signals to the right board pins.
576 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
577 A USB, parallel, or serial port connector will go to the host which
578 you are using to run OpenOCD.
579 For Ethernet, consult the documentation and your network administrator.
581 For USB based JTAG adapters you have an easy sanity check at this point:
582 does the host operating system see the JTAG adapter?
584 @item @emph{Connect the adapter's power supply, if needed.}
585 This step is primarily for non-USB adapters,
586 but sometimes USB adapters need extra power.
588 @item @emph{Power up the target board.}
589 Unless you just let the magic smoke escape,
590 you're now ready to set up the OpenOCD server
591 so you can use JTAG to work with that board.
595 Talk with the OpenOCD server using
596 telnet (@code{telnet localhost 4444} on many systems) or GDB.
597 @xref{GDB and OpenOCD}.
599 @section Project Directory
601 There are many ways you can configure OpenOCD and start it up.
603 A simple way to organize them all involves keeping a
604 single directory for your work with a given board.
605 When you start OpenOCD from that directory,
606 it searches there first for configuration files, scripts,
607 and for code you upload to the target board.
608 It is also the natural place to write files,
609 such as log files and data you download from the board.
611 @section Configuration Basics
613 There are two basic ways of configuring OpenOCD, and
614 a variety of ways you can mix them.
615 Think of the difference as just being how you start the server:
618 @item Many @option{-f file} or @option{-c command} options on the command line
619 @item No options, but a @dfn{user config file}
620 in the current directory named @file{openocd.cfg}
623 Here is an example @file{openocd.cfg} file for a setup
624 using a Signalyzer FT2232-based JTAG adapter to talk to
625 a board with an Atmel AT91SAM7X256 microcontroller:
628 source [find interface/signalyzer.cfg]
630 # GDB can also flash my flash!
631 gdb_memory_map enable
632 gdb_flash_program enable
634 source [find target/sam7x256.cfg]
637 Here is the command line equivalent of that configuration:
640 openocd -f interface/signalyzer.cfg \
641 -c "gdb_memory_map enable" \
642 -c "gdb_flash_program enable" \
643 -f target/sam7x256.cfg
646 You could wrap such long command lines in shell scripts,
647 each supporting a different development task.
648 One might re-flash the board with a specific firmware version.
649 Another might set up a particular debugging or run-time environment.
651 Here we will focus on the simpler solution: one user config
652 file, including basic configuration plus any TCL procedures
653 to simplify your work.
655 @section User Config Files
656 @cindex config file, user
657 @cindex user config file
658 @cindex config file, overview
660 A user configuration file ties together all the parts of a project
662 One of the following will match your situation best:
665 @item Ideally almost everything comes from configuration files
666 provided by someone else.
667 For example, OpenOCD distributes a @file{scripts} directory
668 (probably in @file{/usr/share/openocd/scripts} on Linux).
669 Board and tool vendors can provide these too, as can individual
670 user sites; the @option{-s} command line option lets you say
671 where to find these files. (@xref{Running}.)
672 The AT91SAM7X256 example above works this way.
674 Three main types of non-user configuration file each have their
675 own subdirectory in the @file{scripts} directory:
678 @item @b{interface} -- one for each kind of JTAG adapter/dongle
679 @item @b{board} -- one for each different board
680 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
683 Best case: include just two files, and they handle everything else.
684 The first is an interface config file.
685 The second is board-specific, and it sets up the JTAG TAPs and
686 their GDB targets (by deferring to some @file{target.cfg} file),
687 declares all flash memory, and leaves you nothing to do except
691 source [find interface/olimex-jtag-tiny.cfg]
692 source [find board/csb337.cfg]
695 Boards with a single microcontroller often won't need more
696 than the target config file, as in the AT91SAM7X256 example.
697 That's because there is no external memory (flash, DDR RAM), and
698 the board differences are encapsulated by application code.
700 @item You can often reuse some standard config files but
701 need to write a few new ones, probably a @file{board.cfg} file.
702 You will be using commands described later in this User's Guide,
703 and working with the guidelines in the next chapter.
705 For example, there may be configuration files for your JTAG adapter
706 and target chip, but you need a new board-specific config file
707 giving access to your particular flash chips.
708 Or you might need to write another target chip configuration file
709 for a new chip built around the Cortex M3 core.
712 When you write new configuration files, please submit
713 them for inclusion in the next OpenOCD release.
714 For example, a @file{board/newboard.cfg} file will help the
715 next users of that board, and a @file{target/newcpu.cfg}
716 will help support users of any board using that chip.
720 You may may need to write some C code.
721 It may be as simple as a supporting a new ft2232 or parport
722 based dongle; a bit more involved, like a NAND or NOR flash
723 controller driver; or a big piece of work like supporting
724 a new chip architecture.
727 Reuse the existing config files when you can.
728 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
729 You may find a board configuration that's a good example to follow.
731 When you write config files, separate the reusable parts
732 (things every user of that interface, chip, or board needs)
733 from ones specific to your environment and debugging approach.
735 For example, a @code{gdb-attach} event handler that invokes
736 the @command{reset init} command will interfere with debugging
737 early boot code, which performs some of the same actions
738 that the @code{reset-init} event handler does.
739 Likewise, the @command{arm9tdmi vector_catch} command (or
741 its siblings @command{xscale vector_catch}
742 and @command{cortex_m3 vector_catch}) can be a timesaver
743 during some debug sessions, but don't make everyone use that either.
744 Keep those kinds of debugging aids in your user config file,
745 along with messaging and tracing setup.
746 (@xref{Software Debug Messages and Tracing}.)
748 TCP/IP port configuration is another example of something which
749 is environment-specific, and should only appear in
750 a user config file. @xref{TCP/IP Ports}.
752 @section Project-Specific Utilities
754 A few project-specific utility
755 routines may well speed up your work.
756 Write them, and keep them in your project's user config file.
758 For example, if you are making a boot loader work on a
759 board, it's nice to be able to debug the ``after it's
760 loaded to RAM'' parts separately from the finicky early
761 code which sets up the DDR RAM controller and clocks.
762 A script like this one, or a more GDB-aware sibling,
766 proc ramboot @{ @} @{
767 # Reset, running the target's "reset-init" scripts
768 # to initialize clocks and the DDR RAM controller.
769 # Leave the CPU halted.
772 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
773 load_image u-boot.bin 0x20000000
780 Then once that code is working you will need to make it
781 boot from NOR flash; a different utility would help.
782 Alternatively, some developers write to flash using GDB.
783 (You might use a similar script if you're working with a flash
784 based microcontroller application instead of a boot loader.)
787 proc newboot @{ @} @{
788 # Reset, leaving the CPU halted. The "reset-init" event
789 # proc gives faster access to the CPU and to NOR flash;
790 # "reset halt" would be slower.
793 # Write standard version of U-Boot into the first two
794 # sectors of NOR flash ... the standard version should
795 # do the same lowlevel init as "reset-init".
796 flash protect 0 0 1 off
797 flash erase_sector 0 0 1
798 flash write_bank 0 u-boot.bin 0x0
799 flash protect 0 0 1 on
801 # Reboot from scratch using that new boot loader.
806 You may need more complicated utility procedures when booting
808 That often involves an extra bootloader stage,
809 running from on-chip SRAM to perform DDR RAM setup so it can load
810 the main bootloader code (which won't fit into that SRAM).
812 Other helper scripts might be used to write production system images,
813 involving considerably more than just a three stage bootloader.
816 @node Config File Guidelines
817 @chapter Config File Guidelines
819 This chapter is aimed at any user who needs to write a config file,
820 including developers and integrators of OpenOCD and any user who
821 needs to get a new board working smoothly.
822 It provides guidelines for creating those files.
824 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
827 @item @file{interface} ...
828 think JTAG Dongle. Files that configure JTAG adapters go here.
829 @item @file{board} ...
830 think Circuit Board, PWA, PCB, they go by many names. Board files
831 contain initialization items that are specific to a board. For
832 example, the SDRAM initialization sequence for the board, or the type
833 of external flash and what address it uses. Any initialization
834 sequence to enable that external flash or SDRAM should be found in the
835 board file. Boards may also contain multiple targets: two CPUs; or
836 a CPU and an FPGA or CPLD.
837 @item @file{target} ...
838 think chip. The ``target'' directory represents the JTAG TAPs
840 which OpenOCD should control, not a board. Two common types of targets
841 are ARM chips and FPGA or CPLD chips.
842 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
843 the target config file defines all of them.
846 The @file{openocd.cfg} user config
847 file may override features in any of the above files by
848 setting variables before sourcing the target file, or by adding
849 commands specific to their situation.
851 @section Interface Config Files
854 should be able to source one of these files with a command like this:
857 source [find interface/FOOBAR.cfg]
860 A preconfigured interface file should exist for every interface in use
861 today, that said, perhaps some interfaces have only been used by the
862 sole developer who created it.
864 A separate chapter gives information about how to set these up.
865 @xref{Interface - Dongle Configuration}.
866 Read the OpenOCD source code if you have a new kind of hardware interface
867 and need to provide a driver for it.
869 @section Board Config Files
870 @cindex config file, board
871 @cindex board config file
874 should be able to source one of these files with a command like this:
877 source [find board/FOOBAR.cfg]
880 The point of a board config file is to package everything
881 about a given board that user config files need to know.
882 In summary the board files should contain (if present)
885 @item One or more @command{source [target/...cfg]} statements
886 @item NOR flash configuration (@pxref{NOR Configuration})
887 @item NAND flash configuration (@pxref{NAND Configuration})
888 @item Target @code{reset} handlers for SDRAM and I/O configuration
889 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
890 @item All things that are not ``inside a chip''
893 Generic things inside target chips belong in target config files,
894 not board config files. So for example a @code{reset-init} event
895 handler should know board-specific oscillator and PLL parameters,
896 which it passes to target-specific utility code.
898 The most complex task of a board config file is creating such a
899 @code{reset-init} event handler.
900 Define those handlers last, after you verify the rest of the board
903 @subsection Communication Between Config files
905 In addition to target-specific utility code, another way that
906 board and target config files communicate is by following a
907 convention on how to use certain variables.
909 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
910 Thus the rule we follow in OpenOCD is this: Variables that begin with
911 a leading underscore are temporary in nature, and can be modified and
912 used at will within a target configuration file.
914 Complex board config files can do the things like this,
915 for a board with three chips:
918 # Chip #1: PXA270 for network side, big endian
921 source [find target/pxa270.cfg]
922 # on return: _TARGETNAME = network.cpu
923 # other commands can refer to the "network.cpu" target.
924 $_TARGETNAME configure .... events for this CPU..
926 # Chip #2: PXA270 for video side, little endian
929 source [find target/pxa270.cfg]
930 # on return: _TARGETNAME = video.cpu
931 # other commands can refer to the "video.cpu" target.
932 $_TARGETNAME configure .... events for this CPU..
934 # Chip #3: Xilinx FPGA for glue logic
937 source [find target/spartan3.cfg]
940 That example is oversimplified because it doesn't show any flash memory,
941 or the @code{reset-init} event handlers to initialize external DRAM
942 or (assuming it needs it) load a configuration into the FPGA.
943 Such features are usually needed for low-level work with many boards,
944 where ``low level'' implies that the board initialization software may
945 not be working. (That's a common reason to need JTAG tools. Another
946 is to enable working with microcontroller-based systems, which often
947 have no debugging support except a JTAG connector.)
949 Target config files may also export utility functions to board and user
950 config files. Such functions should use name prefixes, to help avoid
953 Board files could also accept input variables from user config files.
954 For example, there might be a @code{J4_JUMPER} setting used to identify
955 what kind of flash memory a development board is using, or how to set
956 up other clocks and peripherals.
958 @subsection Variable Naming Convention
959 @cindex variable names
961 Most boards have only one instance of a chip.
962 However, it should be easy to create a board with more than
963 one such chip (as shown above).
964 Accordingly, we encourage these conventions for naming
965 variables associated with different @file{target.cfg} files,
966 to promote consistency and
967 so that board files can override target defaults.
969 Inputs to target config files include:
972 @item @code{CHIPNAME} ...
973 This gives a name to the overall chip, and is used as part of
974 tap identifier dotted names.
975 While the default is normally provided by the chip manufacturer,
976 board files may need to distinguish between instances of a chip.
977 @item @code{ENDIAN} ...
978 By default @option{little} - although chips may hard-wire @option{big}.
979 Chips that can't change endianness don't need to use this variable.
980 @item @code{CPUTAPID} ...
981 When OpenOCD examines the JTAG chain, it can be told verify the
982 chips against the JTAG IDCODE register.
983 The target file will hold one or more defaults, but sometimes the
984 chip in a board will use a different ID (perhaps a newer revision).
987 Outputs from target config files include:
990 @item @code{_TARGETNAME} ...
991 By convention, this variable is created by the target configuration
992 script. The board configuration file may make use of this variable to
993 configure things like a ``reset init'' script, or other things
994 specific to that board and that target.
995 If the chip has 2 targets, the names are @code{_TARGETNAME0},
996 @code{_TARGETNAME1}, ... etc.
999 @subsection The reset-init Event Handler
1000 @cindex event, reset-init
1001 @cindex reset-init handler
1003 Board config files run in the OpenOCD configuration stage;
1004 they can't use TAPs or targets, since they haven't been
1006 This means you can't write memory or access chip registers;
1007 you can't even verify that a flash chip is present.
1008 That's done later in event handlers, of which the target @code{reset-init}
1009 handler is one of the most important.
1011 Except on microcontrollers, the basic job of @code{reset-init} event
1012 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1013 Microcontrollers rarely use boot loaders; they run right out of their
1014 on-chip flash and SRAM memory. But they may want to use one of these
1015 handlers too, if just for developer convenience.
1018 Because this is so very board-specific, and chip-specific, no examples
1020 Instead, look at the board config files distributed with OpenOCD.
1021 If you have a boot loader, its source code may also be useful.
1024 Some of this code could probably be shared between different boards.
1025 For example, setting up a DRAM controller often doesn't differ by
1026 much except the bus width (16 bits or 32?) and memory timings, so a
1027 reusable TCL procedure loaded by the @file{target.cfg} file might take
1028 those as parameters.
1029 Similarly with oscillator, PLL, and clock setup;
1030 and disabling the watchdog.
1031 Structure the code cleanly, and provide comments to help
1032 the next developer doing such work.
1033 (@emph{You might be that next person} trying to reuse init code!)
1035 The last thing normally done in a @code{reset-init} handler is probing
1036 whatever flash memory was configured. For most chips that needs to be
1037 done while the associated target is halted, either because JTAG memory
1038 access uses the CPU or to prevent conflicting CPU access.
1040 @subsection JTAG Clock Rate
1042 Before your @code{reset-init} handler has set up
1043 the PLLs and clocking, you may need to use
1044 a low JTAG clock rate; then you'd increase it later.
1045 (The rule of thumb for ARM-based processors is 1/8 the CPU clock.)
1046 If the board supports adaptive clocking, use the @command{jtag_rclk}
1047 command, in case your board is used with JTAG adapter which
1048 also supports it. Otherwise use @command{jtag_khz}.
1049 Set the slow rate at the beginning of the reset sequence,
1050 and the faster rate as soon as the clocks are at full speed.
1052 @section Target Config Files
1053 @cindex config file, target
1054 @cindex target config file
1056 Board config files communicate with target config files using
1057 naming conventions as described above, and may source one or
1058 more target config files like this:
1061 source [find target/FOOBAR.cfg]
1064 The point of a target config file is to package everything
1065 about a given chip that board config files need to know.
1066 In summary the target files should contain
1070 @item Add TAPs to the scan chain
1071 @item Add CPU targets (includes GDB support)
1072 @item CPU/Chip/CPU-Core specific features
1076 As a rule of thumb, a target file sets up only one chip.
1077 For a microcontroller, that will often include a single TAP,
1078 which is a CPU needing a GDB target, and its on-chip flash.
1080 More complex chips may include multiple TAPs, and the target
1081 config file may need to define them all before OpenOCD
1082 can talk to the chip.
1083 For example, some phone chips have JTAG scan chains that include
1084 an ARM core for operating system use, a DSP,
1085 another ARM core embedded in an image processing engine,
1086 and other processing engines.
1088 @subsection Default Value Boiler Plate Code
1090 All target configuration files should start with code like this,
1091 letting board config files express environment-specific
1092 differences in how things should be set up.
1095 # Boards may override chip names, perhaps based on role,
1096 # but the default should match what the vendor uses
1097 if @{ [info exists CHIPNAME] @} @{
1098 set _CHIPNAME $CHIPNAME
1100 set _CHIPNAME sam7x256
1103 # ONLY use ENDIAN with targets that can change it.
1104 if @{ [info exists ENDIAN] @} @{
1110 # TAP identifiers may change as chips mature, for example with
1111 # new revision fields (the "3" here). Pick a good default; you
1112 # can pass several such identifiers to the "jtag newtap" command.
1113 if @{ [info exists CPUTAPID ] @} @{
1114 set _CPUTAPID $CPUTAPID
1116 set _CPUTAPID 0x3f0f0f0f
1119 @c but 0x3f0f0f0f is for an str73x part ...
1121 @emph{Remember:} Board config files may include multiple target
1122 config files, or the same target file multiple times
1123 (changing at least @code{CHIPNAME}).
1125 Likewise, the target configuration file should define
1126 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1127 use it later on when defining debug targets:
1130 set _TARGETNAME $_CHIPNAME.cpu
1131 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1134 @subsection Adding TAPs to the Scan Chain
1135 After the ``defaults'' are set up,
1136 add the TAPs on each chip to the JTAG scan chain.
1137 @xref{TAP Declaration}, and the naming convention
1140 In the simplest case the chip has only one TAP,
1141 probably for a CPU or FPGA.
1142 The config file for the Atmel AT91SAM7X256
1143 looks (in part) like this:
1146 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1147 -expected-id $_CPUTAPID
1150 A board with two such at91sam7 chips would be able
1151 to source such a config file twice, with different
1152 values for @code{CHIPNAME}, so
1153 it adds a different TAP each time.
1155 If there are one or more nonzero @option{-expected-id} values,
1156 OpenOCD attempts to verify the actual tap id against those values.
1157 It will issue error messages if there is mismatch, which
1158 can help to pinpoint problems in OpenOCD configurations.
1161 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1162 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1163 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1164 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1165 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1168 There are more complex examples too, with chips that have
1169 multiple TAPs. Ones worth looking at include:
1172 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1173 plus a JRC to enable them
1174 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1175 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1176 is not currently used)
1179 @subsection Add CPU targets
1181 After adding a TAP for a CPU, you should set it up so that
1182 GDB and other commands can use it.
1183 @xref{CPU Configuration}.
1184 For the at91sam7 example above, the command can look like this;
1185 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1186 to little endian, and this chip doesn't support changing that.
1189 set _TARGETNAME $_CHIPNAME.cpu
1190 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1193 Work areas are small RAM areas associated with CPU targets.
1194 They are used by OpenOCD to speed up downloads,
1195 and to download small snippets of code to program flash chips.
1196 If the chip includes a form of ``on-chip-ram'' - and many do - define
1197 a work area if you can.
1198 Again using the at91sam7 as an example, this can look like:
1201 $_TARGETNAME configure -work-area-phys 0x00200000 \
1202 -work-area-size 0x4000 -work-area-backup 0
1205 @subsection Chip Reset Setup
1207 As a rule, you should put the @command{reset_config} command
1208 into the board file. Most things you think you know about a
1209 chip can be tweaked by the board.
1211 Some chips have specific ways the TRST and SRST signals are
1212 managed. In the unusual case that these are @emph{chip specific}
1213 and can never be changed by board wiring, they could go here.
1215 Some chips need special attention during reset handling if
1216 they're going to be used with JTAG.
1217 An example might be needing to send some commands right
1218 after the target's TAP has been reset, providing a
1219 @code{reset-deassert-post} event handler that writes a chip
1220 register to report that JTAG debugging is being done.
1222 @subsection ARM Core Specific Hacks
1224 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1225 special high speed download features - enable it.
1227 If present, the MMU, the MPU and the CACHE should be disabled.
1229 Some ARM cores are equipped with trace support, which permits
1230 examination of the instruction and data bus activity. Trace
1231 activity is controlled through an ``Embedded Trace Module'' (ETM)
1232 on one of the core's scan chains. The ETM emits voluminous data
1233 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1234 If you are using an external trace port,
1235 configure it in your board config file.
1236 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1237 configure it in your target config file.
1240 etm config $_TARGETNAME 16 normal full etb
1241 etb config $_TARGETNAME $_CHIPNAME.etb
1244 @subsection Internal Flash Configuration
1246 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1248 @b{Never ever} in the ``target configuration file'' define any type of
1249 flash that is external to the chip. (For example a BOOT flash on
1250 Chip Select 0.) Such flash information goes in a board file - not
1251 the TARGET (chip) file.
1255 @item at91sam7x256 - has 256K flash YES enable it.
1256 @item str912 - has flash internal YES enable it.
1257 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1258 @item pxa270 - again - CS0 flash - it goes in the board file.
1261 @node Daemon Configuration
1262 @chapter Daemon Configuration
1263 @cindex initialization
1264 The commands here are commonly found in the openocd.cfg file and are
1265 used to specify what TCP/IP ports are used, and how GDB should be
1268 @section Configuration Stage
1269 @cindex configuration stage
1270 @cindex config command
1272 When the OpenOCD server process starts up, it enters a
1273 @emph{configuration stage} which is the only time that
1274 certain commands, @emph{configuration commands}, may be issued.
1275 In this manual, the definition of a configuration command is
1276 presented as a @emph{Config Command}, not as a @emph{Command}
1277 which may be issued interactively.
1279 Those configuration commands include declaration of TAPs,
1281 the interface used for JTAG communication,
1282 and other basic setup.
1283 The server must leave the configuration stage before it
1284 may access or activate TAPs.
1285 After it leaves this stage, configuration commands may no
1288 @deffn {Config Command} init
1289 This command terminates the configuration stage and
1290 enters the normal command mode. This can be useful to add commands to
1291 the startup scripts and commands such as resetting the target,
1292 programming flash, etc. To reset the CPU upon startup, add "init" and
1293 "reset" at the end of the config script or at the end of the OpenOCD
1294 command line using the @option{-c} command line switch.
1296 If this command does not appear in any startup/configuration file
1297 OpenOCD executes the command for you after processing all
1298 configuration files and/or command line options.
1300 @b{NOTE:} This command normally occurs at or near the end of your
1301 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1302 targets ready. For example: If your openocd.cfg file needs to
1303 read/write memory on your target, @command{init} must occur before
1304 the memory read/write commands. This includes @command{nand probe}.
1307 @anchor{TCP/IP Ports}
1308 @section TCP/IP Ports
1313 The OpenOCD server accepts remote commands in several syntaxes.
1314 Each syntax uses a different TCP/IP port, which you may specify
1315 only during configuration (before those ports are opened).
1317 For reasons including security, you may wish to prevent remote
1318 access using one or more of these ports.
1319 In such cases, just specify the relevant port number as zero.
1320 If you disable all access through TCP/IP, you will need to
1321 use the command line @option{-pipe} option.
1323 @deffn {Command} gdb_port (number)
1325 Specify or query the first port used for incoming GDB connections.
1326 The GDB port for the
1327 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1328 When not specified during the configuration stage,
1329 the port @var{number} defaults to 3333.
1330 When specified as zero, this port is not activated.
1333 @deffn {Command} tcl_port (number)
1334 Specify or query the port used for a simplified RPC
1335 connection that can be used by clients to issue TCL commands and get the
1336 output from the Tcl engine.
1337 Intended as a machine interface.
1338 When not specified during the configuration stage,
1339 the port @var{number} defaults to 6666.
1340 When specified as zero, this port is not activated.
1343 @deffn {Command} telnet_port (number)
1344 Specify or query the
1345 port on which to listen for incoming telnet connections.
1346 This port is intended for interaction with one human through TCL commands.
1347 When not specified during the configuration stage,
1348 the port @var{number} defaults to 4444.
1349 When specified as zero, this port is not activated.
1352 @anchor{GDB Configuration}
1353 @section GDB Configuration
1355 @cindex GDB configuration
1356 You can reconfigure some GDB behaviors if needed.
1357 The ones listed here are static and global.
1358 @xref{Target Configuration}, about configuring individual targets.
1359 @xref{Target Events}, about configuring target-specific event handling.
1361 @anchor{gdb_breakpoint_override}
1362 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1363 Force breakpoint type for gdb @command{break} commands.
1364 This option supports GDB GUIs which don't
1365 distinguish hard versus soft breakpoints, if the default OpenOCD and
1366 GDB behaviour is not sufficient. GDB normally uses hardware
1367 breakpoints if the memory map has been set up for flash regions.
1370 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1371 Configures what OpenOCD will do when GDB detaches from the daemon.
1372 Default behaviour is @option{resume}.
1375 @anchor{gdb_flash_program}
1376 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1377 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1378 vFlash packet is received.
1379 The default behaviour is @option{enable}.
1382 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1383 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1384 requested. GDB will then know when to set hardware breakpoints, and program flash
1385 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1386 for flash programming to work.
1387 Default behaviour is @option{enable}.
1388 @xref{gdb_flash_program}.
1391 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1392 Specifies whether data aborts cause an error to be reported
1393 by GDB memory read packets.
1394 The default behaviour is @option{disable};
1395 use @option{enable} see these errors reported.
1398 @anchor{Event Polling}
1399 @section Event Polling
1401 Hardware debuggers are parts of asynchronous systems,
1402 where significant events can happen at any time.
1403 The OpenOCD server needs to detect some of these events,
1404 so it can report them to through TCL command line
1407 Examples of such events include:
1410 @item One of the targets can stop running ... maybe it triggers
1411 a code breakpoint or data watchpoint, or halts itself.
1412 @item Messages may be sent over ``debug message'' channels ... many
1413 targets support such messages sent over JTAG,
1414 for receipt by the person debugging or tools.
1415 @item Loss of power ... some adapters can detect these events.
1416 @item Resets not issued through JTAG ... such reset sources
1417 can include button presses or other system hardware, sometimes
1418 including the target itself (perhaps through a watchdog).
1419 @item Debug instrumentation sometimes supports event triggering
1420 such as ``trace buffer full'' (so it can quickly be emptied)
1421 or other signals (to correlate with code behavior).
1424 None of those events are signaled through standard JTAG signals.
1425 However, most conventions for JTAG connectors include voltage
1426 level and system reset (SRST) signal detection.
1427 Some connectors also include instrumentation signals, which
1428 can imply events when those signals are inputs.
1430 In general, OpenOCD needs to periodically check for those events,
1431 either by looking at the status of signals on the JTAG connector
1432 or by sending synchronous ``tell me your status'' JTAG requests
1433 to the various active targets.
1434 There is a command to manage and monitor that polling,
1435 which is normally done in the background.
1437 @deffn Command poll [@option{on}|@option{off}]
1438 Poll the current target for its current state.
1439 (Also, @pxref{target curstate}.)
1440 If that target is in debug mode, architecture
1441 specific information about the current state is printed.
1442 An optional parameter
1443 allows background polling to be enabled and disabled.
1445 You could use this from the TCL command shell, or
1446 from GDB using @command{monitor poll} command.
1449 background polling: on
1450 target state: halted
1451 target halted in ARM state due to debug-request, \
1452 current mode: Supervisor
1453 cpsr: 0x800000d3 pc: 0x11081bfc
1454 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1459 @node Interface - Dongle Configuration
1460 @chapter Interface - Dongle Configuration
1461 @cindex config file, interface
1462 @cindex interface config file
1464 JTAG Adapters/Interfaces/Dongles are normally configured
1465 through commands in an interface configuration
1466 file which is sourced by your @file{openocd.cfg} file, or
1467 through a command line @option{-f interface/....cfg} option.
1470 source [find interface/olimex-jtag-tiny.cfg]
1474 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1475 A few cases are so simple that you only need to say what driver to use:
1482 Most adapters need a bit more configuration than that.
1485 @section Interface Configuration
1487 The interface command tells OpenOCD what type of JTAG dongle you are
1488 using. Depending on the type of dongle, you may need to have one or
1489 more additional commands.
1491 @deffn {Config Command} {interface} name
1492 Use the interface driver @var{name} to connect to the
1496 @deffn Command {interface_list}
1497 List the interface drivers that have been built into
1498 the running copy of OpenOCD.
1501 @deffn Command {jtag interface}
1502 Returns the name of the interface driver being used.
1505 @section Interface Drivers
1507 Each of the interface drivers listed here must be explicitly
1508 enabled when OpenOCD is configured, in order to be made
1509 available at run time.
1511 @deffn {Interface Driver} {amt_jtagaccel}
1512 Amontec Chameleon in its JTAG Accelerator configuration,
1513 connected to a PC's EPP mode parallel port.
1514 This defines some driver-specific commands:
1516 @deffn {Config Command} {parport_port} number
1517 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1518 the number of the @file{/dev/parport} device.
1521 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1522 Displays status of RTCK option.
1523 Optionally sets that option first.
1527 @deffn {Interface Driver} {arm-jtag-ew}
1528 Olimex ARM-JTAG-EW USB adapter
1529 This has one driver-specific command:
1531 @deffn Command {armjtagew_info}
1536 @deffn {Interface Driver} {at91rm9200}
1537 Supports bitbanged JTAG from the local system,
1538 presuming that system is an Atmel AT91rm9200
1539 and a specific set of GPIOs is used.
1540 @c command: at91rm9200_device NAME
1541 @c chooses among list of bit configs ... only one option
1544 @deffn {Interface Driver} {dummy}
1545 A dummy software-only driver for debugging.
1548 @deffn {Interface Driver} {ep93xx}
1549 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1552 @deffn {Interface Driver} {ft2232}
1553 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1554 These interfaces have several commands, used to configure the driver
1555 before initializing the JTAG scan chain:
1557 @deffn {Config Command} {ft2232_device_desc} description
1558 Provides the USB device description (the @emph{iProduct string})
1559 of the FTDI FT2232 device. If not
1560 specified, the FTDI default value is used. This setting is only valid
1561 if compiled with FTD2XX support.
1564 @deffn {Config Command} {ft2232_serial} serial-number
1565 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1566 in case the vendor provides unique IDs and more than one FT2232 device
1567 is connected to the host.
1568 If not specified, serial numbers are not considered.
1569 (Note that USB serial numbers can be arbitrary Unicode strings,
1570 and are not restricted to containing only decimal digits.)
1573 @deffn {Config Command} {ft2232_layout} name
1574 Each vendor's FT2232 device can use different GPIO signals
1575 to control output-enables, reset signals, and LEDs.
1576 Currently valid layout @var{name} values include:
1578 @item @b{axm0432_jtag} Axiom AXM-0432
1579 @item @b{comstick} Hitex STR9 comstick
1580 @item @b{cortino} Hitex Cortino JTAG interface
1581 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1582 either for the local Cortex-M3 (SRST only)
1583 or in a passthrough mode (neither SRST nor TRST)
1584 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1585 @item @b{flyswatter} Tin Can Tools Flyswatter
1586 @item @b{icebear} ICEbear JTAG adapter from Section 5
1587 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1588 @item @b{m5960} American Microsystems M5960
1589 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1590 @item @b{oocdlink} OOCDLink
1591 @c oocdlink ~= jtagkey_prototype_v1
1592 @item @b{sheevaplug} Marvell Sheevaplug development kit
1593 @item @b{signalyzer} Xverve Signalyzer
1594 @item @b{stm32stick} Hitex STM32 Performance Stick
1595 @item @b{turtelizer2} egnite Software turtelizer2
1596 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1600 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1601 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1602 default values are used.
1603 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1605 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1609 @deffn {Config Command} {ft2232_latency} ms
1610 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1611 ft2232_read() fails to return the expected number of bytes. This can be caused by
1612 USB communication delays and has proved hard to reproduce and debug. Setting the
1613 FT2232 latency timer to a larger value increases delays for short USB packets but it
1614 also reduces the risk of timeouts before receiving the expected number of bytes.
1615 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1618 For example, the interface config file for a
1619 Turtelizer JTAG Adapter looks something like this:
1623 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1624 ft2232_layout turtelizer2
1625 ft2232_vid_pid 0x0403 0xbdc8
1629 @deffn {Interface Driver} {gw16012}
1630 Gateworks GW16012 JTAG programmer.
1631 This has one driver-specific command:
1633 @deffn {Config Command} {parport_port} number
1634 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1635 the number of the @file{/dev/parport} device.
1639 @deffn {Interface Driver} {jlink}
1640 Segger jlink USB adapter
1641 @c command: jlink_info
1643 @c command: jlink_hw_jtag (2|3)
1644 @c sets version 2 or 3
1647 @deffn {Interface Driver} {parport}
1648 Supports PC parallel port bit-banging cables:
1649 Wigglers, PLD download cable, and more.
1650 These interfaces have several commands, used to configure the driver
1651 before initializing the JTAG scan chain:
1653 @deffn {Config Command} {parport_cable} name
1654 The layout of the parallel port cable used to connect to the target.
1655 Currently valid cable @var{name} values include:
1658 @item @b{altium} Altium Universal JTAG cable.
1659 @item @b{arm-jtag} Same as original wiggler except SRST and
1660 TRST connections reversed and TRST is also inverted.
1661 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1662 in configuration mode. This is only used to
1663 program the Chameleon itself, not a connected target.
1664 @item @b{dlc5} The Xilinx Parallel cable III.
1665 @item @b{flashlink} The ST Parallel cable.
1666 @item @b{lattice} Lattice ispDOWNLOAD Cable
1667 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1669 Amontec's Chameleon Programmer. The new version available from
1670 the website uses the original Wiggler layout ('@var{wiggler}')
1671 @item @b{triton} The parallel port adapter found on the
1672 ``Karo Triton 1 Development Board''.
1673 This is also the layout used by the HollyGates design
1674 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1675 @item @b{wiggler} The original Wiggler layout, also supported by
1676 several clones, such as the Olimex ARM-JTAG
1677 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1678 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1682 @deffn {Config Command} {parport_port} number
1683 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1684 the @file{/dev/parport} device
1686 When using PPDEV to access the parallel port, use the number of the parallel port:
1687 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1688 you may encounter a problem.
1691 @deffn {Config Command} {parport_write_on_exit} (on|off)
1692 This will configure the parallel driver to write a known
1693 cable-specific value to the parallel interface on exiting OpenOCD
1696 For example, the interface configuration file for a
1697 classic ``Wiggler'' cable might look something like this:
1702 parport_cable wiggler
1706 @deffn {Interface Driver} {presto}
1707 ASIX PRESTO USB JTAG programmer.
1708 @c command: presto_serial str
1709 @c sets serial number
1712 @deffn {Interface Driver} {rlink}
1713 Raisonance RLink USB adapter
1716 @deffn {Interface Driver} {usbprog}
1717 usbprog is a freely programmable USB adapter.
1720 @deffn {Interface Driver} {vsllink}
1721 vsllink is part of Versaloon which is a versatile USB programmer.
1724 This defines quite a few driver-specific commands,
1725 which are not currently documented here.
1729 @deffn {Interface Driver} {ZY1000}
1730 This is the Zylin ZY1000 JTAG debugger.
1733 This defines some driver-specific commands,
1734 which are not currently documented here.
1737 @deffn Command power [@option{on}|@option{off}]
1738 Turn power switch to target on/off.
1739 No arguments: print status.
1746 JTAG clock setup is part of system setup.
1747 It @emph{does not belong with interface setup} since any interface
1748 only knows a few of the constraints for the JTAG clock speed.
1749 Sometimes the JTAG speed is
1750 changed during the target initialization process: (1) slow at
1751 reset, (2) program the CPU clocks, (3) run fast.
1752 Both the "slow" and "fast" clock rates are functions of the
1753 oscillators used, the chip, the board design, and sometimes
1754 power management software that may be active.
1756 The speed used during reset can be adjusted using pre_reset
1757 and post_reset event handlers.
1758 @xref{Target Events}.
1760 If your system supports adaptive clocking (RTCK), configuring
1761 JTAG to use that is probably the most robust approach.
1762 However, it introduces delays to synchronize clocks; so it
1763 may not be the fastest solution.
1765 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1766 instead of @command{jtag_khz}.
1768 @deffn {Command} jtag_khz max_speed_kHz
1769 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1770 JTAG interfaces usually support a limited number of
1771 speeds. The speed actually used won't be faster
1772 than the speed specified.
1774 As a rule of thumb, if you specify a clock rate make
1775 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1776 This is especially true for synthesized cores (ARMxxx-S).
1778 Speed 0 (khz) selects RTCK method.
1780 If your system uses RTCK, you won't need to change the
1781 JTAG clocking after setup.
1782 Not all interfaces, boards, or targets support ``rtck''.
1783 If the interface device can not
1784 support it, an error is returned when you try to use RTCK.
1787 @defun jtag_rclk fallback_speed_kHz
1789 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1790 If that fails (maybe the interface, board, or target doesn't
1791 support it), falls back to the specified frequency.
1793 # Fall back to 3mhz if RTCK is not supported
1798 @node Reset Configuration
1799 @chapter Reset Configuration
1800 @cindex Reset Configuration
1802 Every system configuration may require a different reset
1803 configuration. This can also be quite confusing.
1804 Resets also interact with @var{reset-init} event handlers,
1805 which do things like setting up clocks and DRAM, and
1806 JTAG clock rates. (@xref{JTAG Speed}.)
1807 They can also interact with JTAG routers.
1808 Please see the various board files for examples.
1811 To maintainers and integrators:
1812 Reset configuration touches several things at once.
1813 Normally the board configuration file
1814 should define it and assume that the JTAG adapter supports
1815 everything that's wired up to the board's JTAG connector.
1817 However, the target configuration file could also make note
1818 of something the silicon vendor has done inside the chip,
1819 which will be true for most (or all) boards using that chip.
1820 And when the JTAG adapter doesn't support everything, the
1821 user configuration file will need to override parts of
1822 the reset configuration provided by other files.
1825 @section Types of Reset
1827 There are many kinds of reset possible through JTAG, but
1828 they may not all work with a given board and adapter.
1829 That's part of why reset configuration can be error prone.
1833 @emph{System Reset} ... the @emph{SRST} hardware signal
1834 resets all chips connected to the JTAG adapter, such as processors,
1835 power management chips, and I/O controllers. Normally resets triggered
1836 with this signal behave exactly like pressing a RESET button.
1838 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1839 just the TAP controllers connected to the JTAG adapter.
1840 Such resets should not be visible to the rest of the system; resetting a
1841 device's the TAP controller just puts that controller into a known state.
1843 @emph{Emulation Reset} ... many devices can be reset through JTAG
1844 commands. These resets are often distinguishable from system
1845 resets, either explicitly (a "reset reason" register says so)
1846 or implicitly (not all parts of the chip get reset).
1848 @emph{Other Resets} ... system-on-chip devices often support
1849 several other types of reset.
1850 You may need to arrange that a watchdog timer stops
1851 while debugging, preventing a watchdog reset.
1852 There may be individual module resets.
1855 In the best case, OpenOCD can hold SRST, then reset
1856 the TAPs via TRST and send commands through JTAG to halt the
1857 CPU at the reset vector before the 1st instruction is executed.
1858 Then when it finally releases the SRST signal, the system is
1859 halted under debugger control before any code has executed.
1860 This is the behavior required to support the @command{reset halt}
1861 and @command{reset init} commands; after @command{reset init} a
1862 board-specific script might do things like setting up DRAM.
1863 (@xref{Reset Command}.)
1865 @anchor{SRST and TRST Issues}
1866 @section SRST and TRST Issues
1868 Because SRST and TRST are hardware signals, they can have a
1869 variety of system-specific constraints. Some of the most
1874 @item @emph{Signal not available} ... Some boards don't wire
1875 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1876 support such signals even if they are wired up.
1877 Use the @command{reset_config} @var{signals} options to say
1878 when either of those signals is not connected.
1879 When SRST is not available, your code might not be able to rely
1880 on controllers having been fully reset during code startup.
1881 Missing TRST is not a problem, since JTAG level resets can
1882 be triggered using with TMS signaling.
1884 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1885 adapter will connect SRST to TRST, instead of keeping them separate.
1886 Use the @command{reset_config} @var{combination} options to say
1887 when those signals aren't properly independent.
1889 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1890 delay circuit, reset supervisor, or on-chip features can extend
1891 the effect of a JTAG adapter's reset for some time after the adapter
1892 stops issuing the reset. For example, there may be chip or board
1893 requirements that all reset pulses last for at least a
1894 certain amount of time; and reset buttons commonly have
1895 hardware debouncing.
1896 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1897 commands to say when extra delays are needed.
1899 @item @emph{Drive type} ... Reset lines often have a pullup
1900 resistor, letting the JTAG interface treat them as open-drain
1901 signals. But that's not a requirement, so the adapter may need
1902 to use push/pull output drivers.
1903 Also, with weak pullups it may be advisable to drive
1904 signals to both levels (push/pull) to minimize rise times.
1905 Use the @command{reset_config} @var{trst_type} and
1906 @var{srst_type} parameters to say how to drive reset signals.
1908 @item @emph{Special initialization} ... Targets sometimes need
1909 special JTAG initialization sequences to handle chip-specific
1910 issues (not limited to errata).
1911 For example, certain JTAG commands might need to be issued while
1912 the system as a whole is in a reset state (SRST active)
1913 but the JTAG scan chain is usable (TRST inactive).
1914 (@xref{JTAG Commands}, where the @command{jtag_reset}
1915 command is presented.)
1918 There can also be other issues.
1919 Some devices don't fully conform to the JTAG specifications.
1920 Trivial system-specific differences are common, such as
1921 SRST and TRST using slightly different names.
1922 There are also vendors who distribute key JTAG documentation for
1923 their chips only to developers who have signed a Non-Disclosure
1926 Sometimes there are chip-specific extensions like a requirement to use
1927 the normally-optional TRST signal (precluding use of JTAG adapters which
1928 don't pass TRST through), or needing extra steps to complete a TAP reset.
1930 In short, SRST and especially TRST handling may be very finicky,
1931 needing to cope with both architecture and board specific constraints.
1933 @section Commands for Handling Resets
1935 @deffn {Command} jtag_nsrst_delay milliseconds
1936 How long (in milliseconds) OpenOCD should wait after deasserting
1937 nSRST (active-low system reset) before starting new JTAG operations.
1938 When a board has a reset button connected to SRST line it will
1939 probably have hardware debouncing, implying you should use this.
1942 @deffn {Command} jtag_ntrst_delay milliseconds
1943 How long (in milliseconds) OpenOCD should wait after deasserting
1944 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1947 @deffn {Command} reset_config mode_flag ...
1948 This command tells OpenOCD the reset configuration
1949 of your combination of JTAG board and target in target
1950 configuration scripts.
1952 Information earlier in this section describes the kind of problems
1953 the command is intended to address (@pxref{SRST and TRST Issues}).
1954 As a rule this command belongs only in board config files,
1955 describing issues like @emph{board doesn't connect TRST};
1956 or in user config files, addressing limitations derived
1957 from a particular combination of interface and board.
1958 (An unlikely example would be using a TRST-only adapter
1959 with a board that only wires up SRST.)
1961 The @var{mode_flag} options can be specified in any order, but only one
1962 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1963 and @var{srst_type} -- may be specified at a time.
1964 If you don't provide a new value for a given type, its previous
1965 value (perhaps the default) is unchanged.
1966 For example, this means that you don't need to say anything at all about
1967 TRST just to declare that if the JTAG adapter should want to drive SRST,
1968 it must explicitly be driven high (@option{srst_push_pull}).
1970 @var{signals} can specify which of the reset signals are connected.
1971 For example, If the JTAG interface provides SRST, but the board doesn't
1972 connect that signal properly, then OpenOCD can't use it.
1973 Possible values are @option{none} (the default), @option{trst_only},
1974 @option{srst_only} and @option{trst_and_srst}.
1977 If your board provides SRST or TRST through the JTAG connector,
1978 you must declare that or else those signals will not be used.
1981 The @var{combination} is an optional value specifying broken reset
1982 signal implementations.
1983 The default behaviour if no option given is @option{separate},
1984 indicating everything behaves normally.
1985 @option{srst_pulls_trst} states that the
1986 test logic is reset together with the reset of the system (e.g. Philips
1987 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1988 the system is reset together with the test logic (only hypothetical, I
1989 haven't seen hardware with such a bug, and can be worked around).
1990 @option{combined} implies both @option{srst_pulls_trst} and
1991 @option{trst_pulls_srst}.
1993 The optional @var{trst_type} and @var{srst_type} parameters allow the
1994 driver mode of each reset line to be specified. These values only affect
1995 JTAG interfaces with support for different driver modes, like the Amontec
1996 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
1997 relevant signal (TRST or SRST) is not connected.
1999 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2000 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2001 Most boards connect this signal to a pulldown, so the JTAG TAPs
2002 never leave reset unless they are hooked up to a JTAG adapter.
2004 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2005 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2006 Most boards connect this signal to a pullup, and allow the
2007 signal to be pulled low by various events including system
2008 powerup and pressing a reset button.
2012 @node TAP Declaration
2013 @chapter TAP Declaration
2014 @cindex TAP declaration
2015 @cindex TAP configuration
2017 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2018 TAPs serve many roles, including:
2021 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2022 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2023 Others do it indirectly, making a CPU do it.
2024 @item @b{Program Download} Using the same CPU support GDB uses,
2025 you can initialize a DRAM controller, download code to DRAM, and then
2026 start running that code.
2027 @item @b{Boundary Scan} Most chips support boundary scan, which
2028 helps test for board assembly problems like solder bridges
2029 and missing connections
2032 OpenOCD must know about the active TAPs on your board(s).
2033 Setting up the TAPs is the core task of your configuration files.
2034 Once those TAPs are set up, you can pass their names to code
2035 which sets up CPUs and exports them as GDB targets,
2036 probes flash memory, performs low-level JTAG operations, and more.
2038 @section Scan Chains
2041 TAPs are part of a hardware @dfn{scan chain},
2042 which is daisy chain of TAPs.
2043 They also need to be added to
2044 OpenOCD's software mirror of that hardware list,
2045 giving each member a name and associating other data with it.
2046 Simple scan chains, with a single TAP, are common in
2047 systems with a single microcontroller or microprocessor.
2048 More complex chips may have several TAPs internally.
2049 Very complex scan chains might have a dozen or more TAPs:
2050 several in one chip, more in the next, and connecting
2051 to other boards with their own chips and TAPs.
2053 You can display the list with the @command{scan_chain} command.
2054 (Don't confuse this with the list displayed by the @command{targets}
2055 command, presented in the next chapter.
2056 That only displays TAPs for CPUs which are configured as
2058 Here's what the scan chain might look like for a chip more than one TAP:
2061 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2062 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2063 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2064 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2065 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2068 Unfortunately those TAPs can't always be autoconfigured,
2069 because not all devices provide good support for that.
2070 JTAG doesn't require supporting IDCODE instructions, and
2071 chips with JTAG routers may not link TAPs into the chain
2072 until they are told to do so.
2074 The configuration mechanism currently supported by OpenOCD
2075 requires explicit configuration of all TAP devices using
2076 @command{jtag newtap} commands, as detailed later in this chapter.
2077 A command like this would declare one tap and name it @code{chip1.cpu}:
2080 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2083 Each target configuration file lists the TAPs provided
2085 Board configuration files combine all the targets on a board,
2087 Note that @emph{the order in which TAPs are declared is very important.}
2088 It must match the order in the JTAG scan chain, both inside
2089 a single chip and between them.
2090 @xref{FAQ TAP Order}.
2092 For example, the ST Microsystems STR912 chip has
2093 three separate TAPs@footnote{See the ST
2094 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2095 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2096 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2097 To configure those taps, @file{target/str912.cfg}
2098 includes commands something like this:
2101 jtag newtap str912 flash ... params ...
2102 jtag newtap str912 cpu ... params ...
2103 jtag newtap str912 bs ... params ...
2106 Actual config files use a variable instead of literals like
2107 @option{str912}, to support more than one chip of each type.
2108 @xref{Config File Guidelines}.
2110 @deffn Command {jtag names}
2111 Returns the names of all current TAPs in the scan chain.
2112 Use @command{jtag cget} or @command{jtag tapisenabled}
2113 to examine attributes and state of each TAP.
2115 foreach t [jtag names] @{
2116 puts [format "TAP: %s\n" $t]
2121 @deffn Command {scan_chain}
2122 Displays the TAPs in the scan chain configuration,
2124 The set of TAPs listed by this command is fixed by
2125 exiting the OpenOCD configuration stage,
2126 but systems with a JTAG router can
2127 enable or disable TAPs dynamically.
2128 In addition to the enable/disable status, the contents of
2129 each TAP's instruction register can also change.
2132 @c FIXME! "jtag cget" should be able to return all TAP
2133 @c attributes, like "$target_name cget" does for targets.
2135 @c Probably want "jtag eventlist", and a "tap-reset" event
2136 @c (on entry to RESET state).
2141 When TAP objects are declared with @command{jtag newtap},
2142 a @dfn{dotted.name} is created for the TAP, combining the
2143 name of a module (usually a chip) and a label for the TAP.
2144 For example: @code{xilinx.tap}, @code{str912.flash},
2145 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2146 Many other commands use that dotted.name to manipulate or
2147 refer to the TAP. For example, CPU configuration uses the
2148 name, as does declaration of NAND or NOR flash banks.
2150 The components of a dotted name should follow ``C'' symbol
2151 name rules: start with an alphabetic character, then numbers
2152 and underscores are OK; while others (including dots!) are not.
2155 In older code, JTAG TAPs were numbered from 0..N.
2156 This feature is still present.
2157 However its use is highly discouraged, and
2158 should not be relied on; it will be removed by mid-2010.
2159 Update all of your scripts to use TAP names rather than numbers,
2160 by paying attention to the runtime warnings they trigger.
2161 Using TAP numbers in target configuration scripts prevents
2162 reusing those scripts on boards with multiple targets.
2165 @section TAP Declaration Commands
2167 @c shouldn't this be(come) a {Config Command}?
2168 @anchor{jtag newtap}
2169 @deffn Command {jtag newtap} chipname tapname configparams...
2170 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2171 and configured according to the various @var{configparams}.
2173 The @var{chipname} is a symbolic name for the chip.
2174 Conventionally target config files use @code{$_CHIPNAME},
2175 defaulting to the model name given by the chip vendor but
2178 @cindex TAP naming convention
2179 The @var{tapname} reflects the role of that TAP,
2180 and should follow this convention:
2183 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2184 @item @code{cpu} -- The main CPU of the chip, alternatively
2185 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2186 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2187 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2188 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2189 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2190 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2191 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2193 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2194 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2195 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2196 a JTAG TAP; that TAP should be named @code{sdma}.
2199 Every TAP requires at least the following @var{configparams}:
2202 @item @code{-ircapture} @var{NUMBER}
2203 @*The bit pattern loaded by the TAP into the JTAG shift register
2204 on entry to the @sc{ircapture} state, such as 0x01.
2205 JTAG requires the two LSBs of this value to be 01.
2206 The value is used to verify that instruction scans work correctly.
2207 @item @code{-irlen} @var{NUMBER}
2208 @*The length in bits of the
2209 instruction register, such as 4 or 5 bits.
2210 @item @code{-irmask} @var{NUMBER}
2211 @*A mask for the IR register.
2212 For some devices, there are bits in the IR that aren't used.
2213 This lets OpenOCD mask them off when doing IDCODE comparisons.
2214 In general, this should just be all ones for the size of the IR.
2217 A TAP may also provide optional @var{configparams}:
2220 @item @code{-disable} (or @code{-enable})
2221 @*Use the @code{-disable} parameter to flag a TAP which is not
2222 linked in to the scan chain after a reset using either TRST
2223 or the JTAG state machine's @sc{reset} state.
2224 You may use @code{-enable} to highlight the default state
2225 (the TAP is linked in).
2226 @xref{Enabling and Disabling TAPs}.
2227 @item @code{-expected-id} @var{number}
2228 @*A non-zero value represents the expected 32-bit IDCODE
2229 found when the JTAG chain is examined.
2230 These codes are not required by all JTAG devices.
2231 @emph{Repeat the option} as many times as required if more than one
2232 ID code could appear (for example, multiple versions).
2236 @c @deffn Command {jtag arp_init-reset}
2237 @c ... more or less "init" ?
2239 @anchor{Enabling and Disabling TAPs}
2240 @section Enabling and Disabling TAPs
2242 @cindex JTAG Route Controller
2245 In some systems, a @dfn{JTAG Route Controller} (JRC)
2246 is used to enable and/or disable specific JTAG TAPs.
2247 Many ARM based chips from Texas Instruments include
2248 an ``ICEpick'' module, which is a JRC.
2249 Such chips include DaVinci and OMAP3 processors.
2251 A given TAP may not be visible until the JRC has been
2252 told to link it into the scan chain; and if the JRC
2253 has been told to unlink that TAP, it will no longer
2255 Such routers address problems that JTAG ``bypass mode''
2259 @item The scan chain can only go as fast as its slowest TAP.
2260 @item Having many TAPs slows instruction scans, since all
2261 TAPs receive new instructions.
2262 @item TAPs in the scan chain must be powered up, which wastes
2263 power and prevents debugging some power management mechanisms.
2266 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2267 as implied by the existence of JTAG routers.
2268 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2269 does include a kind of JTAG router functionality.
2271 @c (a) currently the event handlers don't seem to be able to
2272 @c fail in a way that could lead to no-change-of-state.
2273 @c (b) eventually non-event configuration should be possible,
2274 @c in which case some this documentation must move.
2276 @deffn Command {jtag cget} dotted.name @option{-event} name
2277 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2278 At this writing this mechanism is used only for event handling,
2279 and the only two events relate to TAP enabling and disabling.
2281 The @code{configure} subcommand assigns an event handler,
2282 a TCL string which is evaluated when the event is triggered.
2283 The @code{cget} subcommand returns that handler.
2284 The two possible values for an event @var{name}
2285 are @option{tap-disable} and @option{tap-enable}.
2287 So for example, when defining a TAP for a CPU connected to
2288 a JTAG router, you should define TAP event handlers using
2289 code that looks something like this:
2292 jtag configure CHIP.cpu -event tap-enable @{
2293 echo "Enabling CPU TAP"
2294 ... jtag operations using CHIP.jrc
2296 jtag configure CHIP.cpu -event tap-disable @{
2297 echo "Disabling CPU TAP"
2298 ... jtag operations using CHIP.jrc
2303 @deffn Command {jtag tapdisable} dotted.name
2304 @deffnx Command {jtag tapenable} dotted.name
2305 @deffnx Command {jtag tapisenabled} dotted.name
2306 These three commands all return the string "1" if the tap
2307 specified by @var{dotted.name} is enabled,
2308 and "0" if it is disbabled.
2309 The @command{tapenable} variant first enables the tap
2310 by sending it a @option{tap-enable} event.
2311 The @command{tapdisable} variant first disables the tap
2312 by sending it a @option{tap-disable} event.
2315 Humans will find the @command{scan_chain} command more helpful
2316 than the script-oriented @command{tapisenabled}
2317 for querying the state of the JTAG taps.
2321 @node CPU Configuration
2322 @chapter CPU Configuration
2325 This chapter discusses how to set up GDB debug targets for CPUs.
2326 You can also access these targets without GDB
2327 (@pxref{Architecture and Core Commands},
2328 and @ref{Target State handling}) and
2329 through various kinds of NAND and NOR flash commands.
2330 If you have multiple CPUs you can have multiple such targets.
2332 We'll start by looking at how to examine the targets you have,
2333 then look at how to add one more target and how to configure it.
2335 @section Target List
2336 @cindex target, current
2337 @cindex target, list
2339 All targets that have been set up are part of a list,
2340 where each member has a name.
2341 That name should normally be the same as the TAP name.
2342 You can display the list with the @command{targets}
2344 This display often has only one CPU; here's what it might
2345 look like with more than one:
2347 TargetName Type Endian TapName State
2348 -- ------------------ ---------- ------ ------------------ ------------
2349 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2350 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2353 One member of that list is the @dfn{current target}, which
2354 is implicitly referenced by many commands.
2355 It's the one marked with a @code{*} near the target name.
2356 In particular, memory addresses often refer to the address
2357 space seen by that current target.
2358 Commands like @command{mdw} (memory display words)
2359 and @command{flash erase_address} (erase NOR flash blocks)
2360 are examples; and there are many more.
2362 Several commands let you examine the list of targets:
2364 @deffn Command {target count}
2365 Returns the number of targets, @math{N}.
2366 The highest numbered target is @math{N - 1}.
2368 set c [target count]
2369 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2370 # Assuming you have created this function
2371 print_target_details $x
2376 @deffn Command {target current}
2377 Returns the name of the current target.
2380 @deffn Command {target names}
2381 Lists the names of all current targets in the list.
2383 foreach t [target names] @{
2384 puts [format "Target: %s\n" $t]
2389 @deffn Command {target number} number
2390 The list of targets is numbered starting at zero.
2391 This command returns the name of the target at index @var{number}.
2393 set thename [target number $x]
2394 puts [format "Target %d is: %s\n" $x $thename]
2398 @c yep, "target list" would have been better.
2399 @c plus maybe "target setdefault".
2401 @deffn Command targets [name]
2402 @emph{Note: the name of this command is plural. Other target
2403 command names are singular.}
2405 With no parameter, this command displays a table of all known
2406 targets in a user friendly form.
2408 With a parameter, this command sets the current target to
2409 the given target with the given @var{name}; this is
2410 only relevant on boards which have more than one target.
2413 @section Target CPU Types and Variants
2418 Each target has a @dfn{CPU type}, as shown in the output of
2419 the @command{targets} command. You need to specify that type
2420 when calling @command{target create}.
2421 The CPU type indicates more than just the instruction set.
2422 It also indicates how that instruction set is implemented,
2423 what kind of debug support it integrates,
2424 whether it has an MMU (and if so, what kind),
2425 what core-specific commands may be available
2426 (@pxref{Architecture and Core Commands}),
2429 For some CPU types, OpenOCD also defines @dfn{variants} which
2430 indicate differences that affect their handling.
2431 For example, a particular implementation bug might need to be
2432 worked around in some chip versions.
2434 It's easy to see what target types are supported,
2435 since there's a command to list them.
2436 However, there is currently no way to list what target variants
2437 are supported (other than by reading the OpenOCD source code).
2439 @anchor{target types}
2440 @deffn Command {target types}
2441 Lists all supported target types.
2442 At this writing, the supported CPU types and variants are:
2445 @item @code{arm11} -- this is a generation of ARMv6 cores
2446 @item @code{arm720t} -- this is an ARMv4 core
2447 @item @code{arm7tdmi} -- this is an ARMv4 core
2448 @item @code{arm920t} -- this is an ARMv5 core
2449 @item @code{arm926ejs} -- this is an ARMv5 core
2450 @item @code{arm966e} -- this is an ARMv5 core
2451 @item @code{arm9tdmi} -- this is an ARMv4 core
2452 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2453 (Support for this is preliminary and incomplete.)
2454 @item @code{cortex_a8} -- this is an ARMv7 core
2455 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2456 compact Thumb2 instruction set. It supports one variant:
2458 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2459 This will cause OpenOCD to use a software reset rather than asserting
2460 SRST, to avoid a issue with clearing the debug registers.
2461 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2462 be detected and the normal reset behaviour used.
2464 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2465 @item @code{feroceon} -- resembles arm926
2466 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2468 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2469 provide a functional SRST line on the EJTAG connector. This causes
2470 OpenOCD to instead use an EJTAG software reset command to reset the
2472 You still need to enable @option{srst} on the @command{reset_config}
2473 command to enable OpenOCD hardware reset functionality.
2475 @item @code{xscale} -- this is actually an architecture,
2476 not a CPU type. It is based on the ARMv5 architecture.
2477 There are several variants defined:
2479 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2480 @code{pxa27x} ... instruction register length is 7 bits
2481 @item @code{pxa250}, @code{pxa255},
2482 @code{pxa26x} ... instruction register length is 5 bits
2487 To avoid being confused by the variety of ARM based cores, remember
2488 this key point: @emph{ARM is a technology licencing company}.
2489 (See: @url{http://www.arm.com}.)
2490 The CPU name used by OpenOCD will reflect the CPU design that was
2491 licenced, not a vendor brand which incorporates that design.
2492 Name prefixes like arm7, arm9, arm11, and cortex
2493 reflect design generations;
2494 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2495 reflect an architecture version implemented by a CPU design.
2497 @anchor{Target Configuration}
2498 @section Target Configuration
2500 Before creating a ``target'', you must have added its TAP to the scan chain.
2501 When you've added that TAP, you will have a @code{dotted.name}
2502 which is used to set up the CPU support.
2503 The chip-specific configuration file will normally configure its CPU(s)
2504 right after it adds all of the chip's TAPs to the scan chain.
2506 Although you can set up a target in one step, it's often clearer if you
2507 use shorter commands and do it in two steps: create it, then configure
2509 All operations on the target after it's created will use a new
2510 command, created as part of target creation.
2512 The two main things to configure after target creation are
2513 a work area, which usually has target-specific defaults even
2514 if the board setup code overrides them later;
2515 and event handlers (@pxref{Target Events}), which tend
2516 to be much more board-specific.
2517 The key steps you use might look something like this
2520 target create MyTarget cortex_m3 -chain-position mychip.cpu
2521 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2522 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2523 $MyTarget configure -event reset-init @{ myboard_reinit @}
2526 You should specify a working area if you can; typically it uses some
2528 Such a working area can speed up many things, including bulk
2529 writes to target memory;
2530 flash operations like checking to see if memory needs to be erased;
2531 GDB memory checksumming;
2535 On more complex chips, the work area can become
2536 inaccessible when application code
2537 (such as an operating system)
2538 enables or disables the MMU.
2539 For example, the particular MMU context used to acess the virtual
2540 address will probably matter ... and that context might not have
2541 easy access to other addresses needed.
2542 At this writing, OpenOCD doesn't have much MMU intelligence.
2545 It's often very useful to define a @code{reset-init} event handler.
2546 For systems that are normally used with a boot loader,
2547 common tasks include updating clocks and initializing memory
2549 That may be needed to let you write the boot loader into flash,
2550 in order to ``de-brick'' your board; or to load programs into
2551 external DDR memory without having run the boot loader.
2553 @deffn Command {target create} target_name type configparams...
2554 This command creates a GDB debug target that refers to a specific JTAG tap.
2555 It enters that target into a list, and creates a new
2556 command (@command{@var{target_name}}) which is used for various
2557 purposes including additional configuration.
2560 @item @var{target_name} ... is the name of the debug target.
2561 By convention this should be the same as the @emph{dotted.name}
2562 of the TAP associated with this target, which must be specified here
2563 using the @code{-chain-position @var{dotted.name}} configparam.
2565 This name is also used to create the target object command,
2566 referred to here as @command{$target_name},
2567 and in other places the target needs to be identified.
2568 @item @var{type} ... specifies the target type. @xref{target types}.
2569 @item @var{configparams} ... all parameters accepted by
2570 @command{$target_name configure} are permitted.
2571 If the target is big-endian, set it here with @code{-endian big}.
2572 If the variant matters, set it here with @code{-variant}.
2574 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2578 @deffn Command {$target_name configure} configparams...
2579 The options accepted by this command may also be
2580 specified as parameters to @command{target create}.
2581 Their values can later be queried one at a time by
2582 using the @command{$target_name cget} command.
2584 @emph{Warning:} changing some of these after setup is dangerous.
2585 For example, moving a target from one TAP to another;
2586 and changing its endianness or variant.
2590 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2591 used to access this target.
2593 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2594 whether the CPU uses big or little endian conventions
2596 @item @code{-event} @var{event_name} @var{event_body} --
2597 @xref{Target Events}.
2598 Note that this updates a list of named event handlers.
2599 Calling this twice with two different event names assigns
2600 two different handlers, but calling it twice with the
2601 same event name assigns only one handler.
2603 @item @code{-variant} @var{name} -- specifies a variant of the target,
2604 which OpenOCD needs to know about.
2606 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2607 whether the work area gets backed up; by default, it doesn't.
2608 When possible, use a working_area that doesn't need to be backed up,
2609 since performing a backup slows down operations.
2611 @item @code{-work-area-size} @var{size} -- specify/set the work area
2613 @item @code{-work-area-phys} @var{address} -- set the work area
2614 base @var{address} to be used when no MMU is active.
2616 @item @code{-work-area-virt} @var{address} -- set the work area
2617 base @var{address} to be used when an MMU is active.
2622 @section Other $target_name Commands
2623 @cindex object command
2625 The Tcl/Tk language has the concept of object commands,
2626 and OpenOCD adopts that same model for targets.
2628 A good Tk example is a on screen button.
2629 Once a button is created a button
2630 has a name (a path in Tk terms) and that name is useable as a first
2631 class command. For example in Tk, one can create a button and later
2632 configure it like this:
2636 button .foobar -background red -command @{ foo @}
2638 .foobar configure -foreground blue
2640 set x [.foobar cget -background]
2642 puts [format "The button is %s" $x]
2645 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2646 button, and its object commands are invoked the same way.
2649 str912.cpu mww 0x1234 0x42
2650 omap3530.cpu mww 0x5555 123
2653 The commands supported by OpenOCD target objects are:
2655 @deffn Command {$target_name arp_examine}
2656 @deffnx Command {$target_name arp_halt}
2657 @deffnx Command {$target_name arp_poll}
2658 @deffnx Command {$target_name arp_reset}
2659 @deffnx Command {$target_name arp_waitstate}
2660 Internal OpenOCD scripts (most notably @file{startup.tcl})
2661 use these to deal with specific reset cases.
2662 They are not otherwise documented here.
2665 @deffn Command {$target_name array2mem} arrayname width address count
2666 @deffnx Command {$target_name mem2array} arrayname width address count
2667 These provide an efficient script-oriented interface to memory.
2668 The @code{array2mem} primitive writes bytes, halfwords, or words;
2669 while @code{mem2array} reads them.
2670 In both cases, the TCL side uses an array, and
2671 the target side uses raw memory.
2673 The efficiency comes from enabling the use of
2674 bulk JTAG data transfer operations.
2675 The script orientation comes from working with data
2676 values that are packaged for use by TCL scripts;
2677 @command{mdw} type primitives only print data they retrieve,
2678 and neither store nor return those values.
2681 @item @var{arrayname} ... is the name of an array variable
2682 @item @var{width} ... is 8/16/32 - indicating the memory access size
2683 @item @var{address} ... is the target memory address
2684 @item @var{count} ... is the number of elements to process
2688 @deffn Command {$target_name cget} queryparm
2689 Each configuration parameter accepted by
2690 @command{$target_name configure}
2691 can be individually queried, to return its current value.
2692 The @var{queryparm} is a parameter name
2693 accepted by that command, such as @code{-work-area-phys}.
2694 There are a few special cases:
2697 @item @code{-event} @var{event_name} -- returns the handler for the
2698 event named @var{event_name}.
2699 This is a special case because setting a handler requires
2701 @item @code{-type} -- returns the target type.
2702 This is a special case because this is set using
2703 @command{target create} and can't be changed
2704 using @command{$target_name configure}.
2707 For example, if you wanted to summarize information about
2708 all the targets you might use something like this:
2711 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2712 set name [target number $x]
2713 set y [$name cget -endian]
2714 set z [$name cget -type]
2715 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2721 @anchor{target curstate}
2722 @deffn Command {$target_name curstate}
2723 Displays the current target state:
2724 @code{debug-running},
2727 @code{running}, or @code{unknown}.
2728 (Also, @pxref{Event Polling}.)
2731 @deffn Command {$target_name eventlist}
2732 Displays a table listing all event handlers
2733 currently associated with this target.
2734 @xref{Target Events}.
2737 @deffn Command {$target_name invoke-event} event_name
2738 Invokes the handler for the event named @var{event_name}.
2739 (This is primarily intended for use by OpenOCD framework
2740 code, for example by the reset code in @file{startup.tcl}.)
2743 @deffn Command {$target_name mdw} addr [count]
2744 @deffnx Command {$target_name mdh} addr [count]
2745 @deffnx Command {$target_name mdb} addr [count]
2746 Display contents of address @var{addr}, as
2747 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2748 or 8-bit bytes (@command{mdb}).
2749 If @var{count} is specified, displays that many units.
2750 (If you want to manipulate the data instead of displaying it,
2751 see the @code{mem2array} primitives.)
2754 @deffn Command {$target_name mww} addr word
2755 @deffnx Command {$target_name mwh} addr halfword
2756 @deffnx Command {$target_name mwb} addr byte
2757 Writes the specified @var{word} (32 bits),
2758 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2759 at the specified address @var{addr}.
2762 @anchor{Target Events}
2763 @section Target Events
2765 At various times, certain things can happen, or you want them to happen.
2768 @item What should happen when GDB connects? Should your target reset?
2769 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2770 @item During reset, do you need to write to certain memory locations
2771 to set up system clocks or
2772 to reconfigure the SDRAM?
2775 All of the above items can be addressed by target event handlers.
2776 These are set up by @command{$target_name configure -event} or
2777 @command{target create ... -event}.
2779 The programmer's model matches the @code{-command} option used in Tcl/Tk
2780 buttons and events. The two examples below act the same, but one creates
2781 and invokes a small procedure while the other inlines it.
2784 proc my_attach_proc @{ @} @{
2788 mychip.cpu configure -event gdb-attach my_attach_proc
2789 mychip.cpu configure -event gdb-attach @{
2795 The following target events are defined:
2798 @item @b{debug-halted}
2799 @* The target has halted for debug reasons (i.e.: breakpoint)
2800 @item @b{debug-resumed}
2801 @* The target has resumed (i.e.: gdb said run)
2802 @item @b{early-halted}
2803 @* Occurs early in the halt process
2805 @item @b{examine-end}
2806 @* Currently not used (goal: when JTAG examine completes)
2807 @item @b{examine-start}
2808 @* Currently not used (goal: when JTAG examine starts)
2810 @item @b{gdb-attach}
2811 @* When GDB connects
2812 @item @b{gdb-detach}
2813 @* When GDB disconnects
2815 @* When the target has halted and GDB is not doing anything (see early halt)
2816 @item @b{gdb-flash-erase-start}
2817 @* Before the GDB flash process tries to erase the flash
2818 @item @b{gdb-flash-erase-end}
2819 @* After the GDB flash process has finished erasing the flash
2820 @item @b{gdb-flash-write-start}
2821 @* Before GDB writes to the flash
2822 @item @b{gdb-flash-write-end}
2823 @* After GDB writes to the flash
2825 @* Before the target steps, gdb is trying to start/resume the target
2827 @* The target has halted
2829 @item @b{old-gdb_program_config}
2830 @* DO NOT USE THIS: Used internally
2831 @item @b{old-pre_resume}
2832 @* DO NOT USE THIS: Used internally
2834 @item @b{reset-assert-pre}
2835 @* Issued as part of @command{reset} processing
2836 after SRST and/or TRST were activated and deactivated,
2837 but before reset is asserted on the tap.
2838 @item @b{reset-assert-post}
2839 @* Issued as part of @command{reset} processing
2840 when reset is asserted on the tap.
2841 @item @b{reset-deassert-pre}
2842 @* Issued as part of @command{reset} processing
2843 when reset is about to be released on the tap.
2845 For some chips, this may be a good place to make sure
2846 the JTAG clock is slow enough to work before the PLL
2847 has been set up to allow faster JTAG speeds.
2848 @item @b{reset-deassert-post}
2849 @* Issued as part of @command{reset} processing
2850 when reset has been released on the tap.
2852 @* Issued as the final step in @command{reset} processing.
2854 @item @b{reset-halt-post}
2855 @* Currently not used
2856 @item @b{reset-halt-pre}
2857 @* Currently not used
2859 @item @b{reset-init}
2860 @* Used by @b{reset init} command for board-specific initialization.
2861 This event fires after @emph{reset-deassert-post}.
2863 This is where you would configure PLLs and clocking, set up DRAM so
2864 you can download programs that don't fit in on-chip SRAM, set up pin
2865 multiplexing, and so on.
2866 @item @b{reset-start}
2867 @* Issued as part of @command{reset} processing
2868 before either SRST or TRST are activated.
2870 @item @b{reset-wait-pos}
2871 @* Currently not used
2872 @item @b{reset-wait-pre}
2873 @* Currently not used
2875 @item @b{resume-start}
2876 @* Before any target is resumed
2877 @item @b{resume-end}
2878 @* After all targets have resumed
2882 @* Target has resumed
2886 @node Flash Commands
2887 @chapter Flash Commands
2889 OpenOCD has different commands for NOR and NAND flash;
2890 the ``flash'' command works with NOR flash, while
2891 the ``nand'' command works with NAND flash.
2892 This partially reflects different hardware technologies:
2893 NOR flash usually supports direct CPU instruction and data bus access,
2894 while data from a NAND flash must be copied to memory before it can be
2895 used. (SPI flash must also be copied to memory before use.)
2896 However, the documentation also uses ``flash'' as a generic term;
2897 for example, ``Put flash configuration in board-specific files''.
2901 @item Configure via the command @command{flash bank}
2902 @* Do this in a board-specific configuration file,
2903 passing parameters as needed by the driver.
2904 @item Operate on the flash via @command{flash subcommand}
2905 @* Often commands to manipulate the flash are typed by a human, or run
2906 via a script in some automated way. Common tasks include writing a
2907 boot loader, operating system, or other data.
2909 @* Flashing via GDB requires the flash be configured via ``flash
2910 bank'', and the GDB flash features be enabled.
2911 @xref{GDB Configuration}.
2914 Many CPUs have the ablity to ``boot'' from the first flash bank.
2915 This means that misprogramming that bank can ``brick'' a system,
2916 so that it can't boot.
2917 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2918 board by (re)installing working boot firmware.
2920 @anchor{NOR Configuration}
2921 @section Flash Configuration Commands
2922 @cindex flash configuration
2924 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2925 Configures a flash bank which provides persistent storage
2926 for addresses from @math{base} to @math{base + size - 1}.
2927 These banks will often be visible to GDB through the target's memory map.
2928 In some cases, configuring a flash bank will activate extra commands;
2929 see the driver-specific documentation.
2932 @item @var{driver} ... identifies the controller driver
2933 associated with the flash bank being declared.
2934 This is usually @code{cfi} for external flash, or else
2935 the name of a microcontroller with embedded flash memory.
2936 @xref{Flash Driver List}.
2937 @item @var{base} ... Base address of the flash chip.
2938 @item @var{size} ... Size of the chip, in bytes.
2939 For some drivers, this value is detected from the hardware.
2940 @item @var{chip_width} ... Width of the flash chip, in bytes;
2941 ignored for most microcontroller drivers.
2942 @item @var{bus_width} ... Width of the data bus used to access the
2943 chip, in bytes; ignored for most microcontroller drivers.
2944 @item @var{target} ... Names the target used to issue
2945 commands to the flash controller.
2946 @comment Actually, it's currently a controller-specific parameter...
2947 @item @var{driver_options} ... drivers may support, or require,
2948 additional parameters. See the driver-specific documentation
2949 for more information.
2952 This command is not available after OpenOCD initialization has completed.
2953 Use it in board specific configuration files, not interactively.
2957 @comment the REAL name for this command is "ocd_flash_banks"
2958 @comment less confusing would be: "flash list" (like "nand list")
2959 @deffn Command {flash banks}
2960 Prints a one-line summary of each device declared
2961 using @command{flash bank}, numbered from zero.
2962 Note that this is the @emph{plural} form;
2963 the @emph{singular} form is a very different command.
2966 @deffn Command {flash probe} num
2967 Identify the flash, or validate the parameters of the configured flash. Operation
2968 depends on the flash type.
2969 The @var{num} parameter is a value shown by @command{flash banks}.
2970 Most flash commands will implicitly @emph{autoprobe} the bank;
2971 flash drivers can distinguish between probing and autoprobing,
2972 but most don't bother.
2975 @section Erasing, Reading, Writing to Flash
2976 @cindex flash erasing
2977 @cindex flash reading
2978 @cindex flash writing
2979 @cindex flash programming
2981 One feature distinguishing NOR flash from NAND or serial flash technologies
2982 is that for read access, it acts exactly like any other addressible memory.
2983 This means you can use normal memory read commands like @command{mdw} or
2984 @command{dump_image} with it, with no special @command{flash} subcommands.
2985 @xref{Memory access}, and @ref{Image access}.
2987 Write access works differently. Flash memory normally needs to be erased
2988 before it's written. Erasing a sector turns all of its bits to ones, and
2989 writing can turn ones into zeroes. This is why there are special commands
2990 for interactive erasing and writing, and why GDB needs to know which parts
2991 of the address space hold NOR flash memory.
2994 Most of these erase and write commands leverage the fact that NOR flash
2995 chips consume target address space. They implicitly refer to the current
2996 JTAG target, and map from an address in that target's address space
2997 back to a flash bank.
2998 @comment In May 2009, those mappings may fail if any bank associated
2999 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3000 A few commands use abstract addressing based on bank and sector numbers,
3001 and don't depend on searching the current target and its address space.
3002 Avoid confusing the two command models.
3005 Some flash chips implement software protection against accidental writes,
3006 since such buggy writes could in some cases ``brick'' a system.
3007 For such systems, erasing and writing may require sector protection to be
3009 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3010 and AT91SAM7 on-chip flash.
3011 @xref{flash protect}.
3013 @anchor{flash erase_sector}
3014 @deffn Command {flash erase_sector} num first last
3015 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3016 @var{last}. Sector numbering starts at 0.
3017 The @var{num} parameter is a value shown by @command{flash banks}.
3020 @deffn Command {flash erase_address} address length
3021 Erase sectors starting at @var{address} for @var{length} bytes.
3022 The flash bank to use is inferred from the @var{address}, and
3023 the specified length must stay within that bank.
3024 As a special case, when @var{length} is zero and @var{address} is
3025 the start of the bank, the whole flash is erased.
3028 @deffn Command {flash fillw} address word length
3029 @deffnx Command {flash fillh} address halfword length
3030 @deffnx Command {flash fillb} address byte length
3031 Fills flash memory with the specified @var{word} (32 bits),
3032 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3033 starting at @var{address} and continuing
3034 for @var{length} units (word/halfword/byte).
3035 No erasure is done before writing; when needed, that must be done
3036 before issuing this command.
3037 Writes are done in blocks of up to 1024 bytes, and each write is
3038 verified by reading back the data and comparing it to what was written.
3039 The flash bank to use is inferred from the @var{address} of
3040 each block, and the specified length must stay within that bank.
3042 @comment no current checks for errors if fill blocks touch multiple banks!
3044 @anchor{flash write_bank}
3045 @deffn Command {flash write_bank} num filename offset
3046 Write the binary @file{filename} to flash bank @var{num},
3047 starting at @var{offset} bytes from the beginning of the bank.
3048 The @var{num} parameter is a value shown by @command{flash banks}.
3051 @anchor{flash write_image}
3052 @deffn Command {flash write_image} [erase] filename [offset] [type]
3053 Write the image @file{filename} to the current target's flash bank(s).
3054 A relocation @var{offset} may be specified, in which case it is added
3055 to the base address for each section in the image.
3056 The file [@var{type}] can be specified
3057 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3058 @option{elf} (ELF file), @option{s19} (Motorola s19).
3059 @option{mem}, or @option{builder}.
3060 The relevant flash sectors will be erased prior to programming
3061 if the @option{erase} parameter is given.
3062 The flash bank to use is inferred from the @var{address} of
3066 @section Other Flash commands
3067 @cindex flash protection
3069 @deffn Command {flash erase_check} num
3070 Check erase state of sectors in flash bank @var{num},
3071 and display that status.
3072 The @var{num} parameter is a value shown by @command{flash banks}.
3073 This is the only operation that
3074 updates the erase state information displayed by @option{flash info}. That means you have
3075 to issue an @command{flash erase_check} command after erasing or programming the device
3076 to get updated information.
3077 (Code execution may have invalidated any state records kept by OpenOCD.)
3080 @deffn Command {flash info} num
3081 Print info about flash bank @var{num}
3082 The @var{num} parameter is a value shown by @command{flash banks}.
3083 The information includes per-sector protect status.
3086 @anchor{flash protect}
3087 @deffn Command {flash protect} num first last (on|off)
3088 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3089 @var{first} to @var{last} of flash bank @var{num}.
3090 The @var{num} parameter is a value shown by @command{flash banks}.
3093 @deffn Command {flash protect_check} num
3094 Check protection state of sectors in flash bank @var{num}.
3095 The @var{num} parameter is a value shown by @command{flash banks}.
3096 @comment @option{flash erase_sector} using the same syntax.
3099 @anchor{Flash Driver List}
3100 @section Flash Drivers, Options, and Commands
3101 As noted above, the @command{flash bank} command requires a driver name,
3102 and allows driver-specific options and behaviors.
3103 Some drivers also activate driver-specific commands.
3105 @subsection External Flash
3107 @deffn {Flash Driver} cfi
3108 @cindex Common Flash Interface
3110 The ``Common Flash Interface'' (CFI) is the main standard for
3111 external NOR flash chips, each of which connects to a
3112 specific external chip select on the CPU.
3113 Frequently the first such chip is used to boot the system.
3114 Your board's @code{reset-init} handler might need to
3115 configure additional chip selects using other commands (like: @command{mww} to
3116 configure a bus and its timings) , or
3117 perhaps configure a GPIO pin that controls the ``write protect'' pin
3119 The CFI driver can use a target-specific working area to significantly
3122 The CFI driver can accept the following optional parameters, in any order:
3125 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3126 like AM29LV010 and similar types.
3127 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3130 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3131 wide on a sixteen bit bus:
3134 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3135 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3137 @c "cfi part_id" disabled
3140 @subsection Internal Flash (Microcontrollers)
3142 @deffn {Flash Driver} aduc702x
3143 The ADUC702x analog microcontrollers from Analog Devices
3144 include internal flash and use ARM7TDMI cores.
3145 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3146 The setup command only requires the @var{target} argument
3147 since all devices in this family have the same memory layout.
3150 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3154 @deffn {Flash Driver} at91sam3
3156 All members of the AT91SAM3 microcontroller family from
3157 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3158 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3159 that the driver was orginaly developed and tested using the
3160 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3161 the family was cribbed from the data sheet. @emph{Note to future
3162 readers/updaters: Please remove this worrysome comment after other
3163 chips are confirmed.}
3165 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3166 have one flash bank. In all cases the flash banks are at
3167 the following fixed locations:
3170 # Flash bank 0 - all chips
3171 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3172 # Flash bank 1 - only 256K chips
3173 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3176 Internally, the AT91SAM3 flash memory is organized as follows.
3177 Unlike the AT91SAM7 chips, these are not used as parameters
3178 to the @command{flash bank} command:
3181 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3182 @item @emph{Bank Size:} 128K/64K Per flash bank
3183 @item @emph{Sectors:} 16 or 8 per bank
3184 @item @emph{SectorSize:} 8K Per Sector
3185 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3188 The AT91SAM3 driver adds some additional commands:
3190 @deffn Command {at91sam3 gpnvm}
3191 @deffnx Command {at91sam3 gpnvm clear} number
3192 @deffnx Command {at91sam3 gpnvm set} number
3193 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3194 With no parameters, @command{show} or @command{show all},
3195 shows the status of all GPNVM bits.
3196 With @command{show} @var{number}, displays that bit.
3198 With @command{set} @var{number} or @command{clear} @var{number},
3199 modifies that GPNVM bit.
3202 @deffn Command {at91sam3 info}
3203 This command attempts to display information about the AT91SAM3
3204 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3205 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3206 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3207 various clock configuration registers and attempts to display how it
3208 believes the chip is configured. By default, the SLOWCLK is assumed to
3209 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3212 @deffn Command {at91sam3 slowclk} [value]
3213 This command shows/sets the slow clock frequency used in the
3214 @command{at91sam3 info} command calculations above.
3218 @deffn {Flash Driver} at91sam7
3219 All members of the AT91SAM7 microcontroller family from Atmel include
3220 internal flash and use ARM7TDMI cores. The driver automatically
3221 recognizes a number of these chips using the chip identification
3222 register, and autoconfigures itself.
3225 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3228 For chips which are not recognized by the controller driver, you must
3229 provide additional parameters in the following order:
3232 @item @var{chip_model} ... label used with @command{flash info}
3234 @item @var{sectors_per_bank}
3235 @item @var{pages_per_sector}
3236 @item @var{pages_size}
3237 @item @var{num_nvm_bits}
3238 @item @var{freq_khz} ... required if an external clock is provided,
3239 optional (but recommended) when the oscillator frequency is known
3242 It is recommended that you provide zeroes for all of those values
3243 except the clock frequency, so that everything except that frequency
3244 will be autoconfigured.
3245 Knowing the frequency helps ensure correct timings for flash access.
3247 The flash controller handles erases automatically on a page (128/256 byte)
3248 basis, so explicit erase commands are not necessary for flash programming.
3249 However, there is an ``EraseAll`` command that can erase an entire flash
3250 plane (of up to 256KB), and it will be used automatically when you issue
3251 @command{flash erase_sector} or @command{flash erase_address} commands.
3253 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3254 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3255 bit for the processor. Each processor has a number of such bits,
3256 used for controlling features such as brownout detection (so they
3257 are not truly general purpose).
3259 This assumes that the first flash bank (number 0) is associated with
3260 the appropriate at91sam7 target.
3265 @deffn {Flash Driver} avr
3266 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3267 @emph{The current implementation is incomplete.}
3268 @comment - defines mass_erase ... pointless given flash_erase_address
3271 @deffn {Flash Driver} ecosflash
3272 @emph{No idea what this is...}
3273 The @var{ecosflash} driver defines one mandatory parameter,
3274 the name of a modules of target code which is downloaded
3278 @deffn {Flash Driver} lpc2000
3279 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3280 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3281 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3282 which must appear in the following order:
3285 @item @var{variant} ... required, may be
3286 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3287 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3288 or @var{lpc1700} (LPC175x and LPC176x)
3289 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3290 at which the core is running
3291 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3292 telling the driver to calculate a valid checksum for the exception vector table.
3295 LPC flashes don't require the chip and bus width to be specified.
3298 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3299 lpc2000_v2 14765 calc_checksum
3302 @deffn {Command} {lpc2000 part_id} bank
3303 Displays the four byte part identifier associated with
3304 the specified flash @var{bank}.
3308 @deffn {Flash Driver} lpc288x
3309 The LPC2888 microcontroller from NXP needs slightly different flash
3310 support from its lpc2000 siblings.
3311 The @var{lpc288x} driver defines one mandatory parameter,
3312 the programming clock rate in Hz.
3313 LPC flashes don't require the chip and bus width to be specified.
3316 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3320 @deffn {Flash Driver} ocl
3321 @emph{No idea what this is, other than using some arm7/arm9 core.}
3324 flash bank ocl 0 0 0 0 $_TARGETNAME
3328 @deffn {Flash Driver} pic32mx
3329 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3330 and integrate flash memory.
3331 @emph{The current implementation is incomplete.}
3334 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3337 @comment numerous *disabled* commands are defined:
3338 @comment - chip_erase ... pointless given flash_erase_address
3339 @comment - lock, unlock ... pointless given protect on/off (yes?)
3340 @comment - pgm_word ... shouldn't bank be deduced from address??
3341 Some pic32mx-specific commands are defined:
3342 @deffn Command {pic32mx pgm_word} address value bank
3343 Programs the specified 32-bit @var{value} at the given @var{address}
3344 in the specified chip @var{bank}.
3348 @deffn {Flash Driver} stellaris
3349 All members of the Stellaris LM3Sxxx microcontroller family from
3351 include internal flash and use ARM Cortex M3 cores.
3352 The driver automatically recognizes a number of these chips using
3353 the chip identification register, and autoconfigures itself.
3354 @footnote{Currently there is a @command{stellaris mass_erase} command.
3355 That seems pointless since the same effect can be had using the
3356 standard @command{flash erase_address} command.}
3359 flash bank stellaris 0 0 0 0 $_TARGETNAME
3363 @deffn {Flash Driver} stm32x
3364 All members of the STM32 microcontroller family from ST Microelectronics
3365 include internal flash and use ARM Cortex M3 cores.
3366 The driver automatically recognizes a number of these chips using
3367 the chip identification register, and autoconfigures itself.
3370 flash bank stm32x 0 0 0 0 $_TARGETNAME
3373 Some stm32x-specific commands
3374 @footnote{Currently there is a @command{stm32x mass_erase} command.
3375 That seems pointless since the same effect can be had using the
3376 standard @command{flash erase_address} command.}
3379 @deffn Command {stm32x lock} num
3380 Locks the entire stm32 device.
3381 The @var{num} parameter is a value shown by @command{flash banks}.
3384 @deffn Command {stm32x unlock} num
3385 Unlocks the entire stm32 device.
3386 The @var{num} parameter is a value shown by @command{flash banks}.
3389 @deffn Command {stm32x options_read} num
3390 Read and display the stm32 option bytes written by
3391 the @command{stm32x options_write} command.
3392 The @var{num} parameter is a value shown by @command{flash banks}.
3395 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3396 Writes the stm32 option byte with the specified values.
3397 The @var{num} parameter is a value shown by @command{flash banks}.
3401 @deffn {Flash Driver} str7x
3402 All members of the STR7 microcontroller family from ST Microelectronics
3403 include internal flash and use ARM7TDMI cores.
3404 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3405 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3408 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3411 @deffn Command {str7x disable_jtag} bank
3412 Activate the Debug/Readout protection mechanism
3413 for the specified flash bank.
3417 @deffn {Flash Driver} str9x
3418 Most members of the STR9 microcontroller family from ST Microelectronics
3419 include internal flash and use ARM966E cores.
3420 The str9 needs the flash controller to be configured using
3421 the @command{str9x flash_config} command prior to Flash programming.
3424 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3425 str9x flash_config 0 4 2 0 0x80000
3428 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3429 Configures the str9 flash controller.
3430 The @var{num} parameter is a value shown by @command{flash banks}.
3433 @item @var{bbsr} - Boot Bank Size register
3434 @item @var{nbbsr} - Non Boot Bank Size register
3435 @item @var{bbadr} - Boot Bank Start Address register
3436 @item @var{nbbadr} - Boot Bank Start Address register
3442 @deffn {Flash Driver} tms470
3443 Most members of the TMS470 microcontroller family from Texas Instruments
3444 include internal flash and use ARM7TDMI cores.
3445 This driver doesn't require the chip and bus width to be specified.
3447 Some tms470-specific commands are defined:
3449 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3450 Saves programming keys in a register, to enable flash erase and write commands.
3453 @deffn Command {tms470 osc_mhz} clock_mhz
3454 Reports the clock speed, which is used to calculate timings.
3457 @deffn Command {tms470 plldis} (0|1)
3458 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3463 @subsection str9xpec driver
3466 Here is some background info to help
3467 you better understand how this driver works. OpenOCD has two flash drivers for
3471 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3472 flash programming as it is faster than the @option{str9xpec} driver.
3474 Direct programming @option{str9xpec} using the flash controller. This is an
3475 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3476 core does not need to be running to program using this flash driver. Typical use
3477 for this driver is locking/unlocking the target and programming the option bytes.
3480 Before we run any commands using the @option{str9xpec} driver we must first disable
3481 the str9 core. This example assumes the @option{str9xpec} driver has been
3482 configured for flash bank 0.
3484 # assert srst, we do not want core running
3485 # while accessing str9xpec flash driver
3487 # turn off target polling
3490 str9xpec enable_turbo 0
3492 str9xpec options_read 0
3493 # re-enable str9 core
3494 str9xpec disable_turbo 0
3498 The above example will read the str9 option bytes.
3499 When performing a unlock remember that you will not be able to halt the str9 - it
3500 has been locked. Halting the core is not required for the @option{str9xpec} driver
3501 as mentioned above, just issue the commands above manually or from a telnet prompt.
3503 @deffn {Flash Driver} str9xpec
3504 Only use this driver for locking/unlocking the device or configuring the option bytes.
3505 Use the standard str9 driver for programming.
3506 Before using the flash commands the turbo mode must be enabled using the
3507 @command{str9xpec enable_turbo} command.
3509 Several str9xpec-specific commands are defined:
3511 @deffn Command {str9xpec disable_turbo} num
3512 Restore the str9 into JTAG chain.
3515 @deffn Command {str9xpec enable_turbo} num
3516 Enable turbo mode, will simply remove the str9 from the chain and talk
3517 directly to the embedded flash controller.
3520 @deffn Command {str9xpec lock} num
3521 Lock str9 device. The str9 will only respond to an unlock command that will
3525 @deffn Command {str9xpec part_id} num
3526 Prints the part identifier for bank @var{num}.
3529 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3530 Configure str9 boot bank.
3533 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3534 Configure str9 lvd source.
3537 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3538 Configure str9 lvd threshold.
3541 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3542 Configure str9 lvd reset warning source.
3545 @deffn Command {str9xpec options_read} num
3546 Read str9 option bytes.
3549 @deffn Command {str9xpec options_write} num
3550 Write str9 option bytes.
3553 @deffn Command {str9xpec unlock} num
3562 @subsection mFlash Configuration
3563 @cindex mFlash Configuration
3565 @deffn {Config Command} {mflash bank} soc base RST_pin target
3566 Configures a mflash for @var{soc} host bank at
3568 The pin number format depends on the host GPIO naming convention.
3569 Currently, the mflash driver supports s3c2440 and pxa270.
3571 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3574 mflash bank s3c2440 0x10000000 1b 0
3577 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3580 mflash bank pxa270 0x08000000 43 0
3584 @subsection mFlash commands
3585 @cindex mFlash commands
3587 @deffn Command {mflash config pll} frequency
3588 Configure mflash PLL.
3589 The @var{frequency} is the mflash input frequency, in Hz.
3590 Issuing this command will erase mflash's whole internal nand and write new pll.
3591 After this command, mflash needs power-on-reset for normal operation.
3592 If pll was newly configured, storage and boot(optional) info also need to be update.
3595 @deffn Command {mflash config boot}
3596 Configure bootable option.
3597 If bootable option is set, mflash offer the first 8 sectors
3601 @deffn Command {mflash config storage}
3602 Configure storage information.
3603 For the normal storage operation, this information must be
3607 @deffn Command {mflash dump} num filename offset size
3608 Dump @var{size} bytes, starting at @var{offset} bytes from the
3609 beginning of the bank @var{num}, to the file named @var{filename}.
3612 @deffn Command {mflash probe}
3616 @deffn Command {mflash write} num filename offset
3617 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3618 @var{offset} bytes from the beginning of the bank.
3621 @node NAND Flash Commands
3622 @chapter NAND Flash Commands
3625 Compared to NOR or SPI flash, NAND devices are inexpensive
3626 and high density. Today's NAND chips, and multi-chip modules,
3627 commonly hold multiple GigaBytes of data.
3629 NAND chips consist of a number of ``erase blocks'' of a given
3630 size (such as 128 KBytes), each of which is divided into a
3631 number of pages (of perhaps 512 or 2048 bytes each). Each
3632 page of a NAND flash has an ``out of band'' (OOB) area to hold
3633 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3634 of OOB for every 512 bytes of page data.
3636 One key characteristic of NAND flash is that its error rate
3637 is higher than that of NOR flash. In normal operation, that
3638 ECC is used to correct and detect errors. However, NAND
3639 blocks can also wear out and become unusable; those blocks
3640 are then marked "bad". NAND chips are even shipped from the
3641 manufacturer with a few bad blocks. The highest density chips
3642 use a technology (MLC) that wears out more quickly, so ECC
3643 support is increasingly important as a way to detect blocks
3644 that have begun to fail, and help to preserve data integrity
3645 with techniques such as wear leveling.
3647 Software is used to manage the ECC. Some controllers don't
3648 support ECC directly; in those cases, software ECC is used.
3649 Other controllers speed up the ECC calculations with hardware.
3650 Single-bit error correction hardware is routine. Controllers
3651 geared for newer MLC chips may correct 4 or more errors for
3652 every 512 bytes of data.
3654 You will need to make sure that any data you write using
3655 OpenOCD includes the apppropriate kind of ECC. For example,
3656 that may mean passing the @code{oob_softecc} flag when
3657 writing NAND data, or ensuring that the correct hardware
3660 The basic steps for using NAND devices include:
3662 @item Declare via the command @command{nand device}
3663 @* Do this in a board-specific configuration file,
3664 passing parameters as needed by the controller.
3665 @item Configure each device using @command{nand probe}.
3666 @* Do this only after the associated target is set up,
3667 such as in its reset-init script or in procures defined
3668 to access that device.
3669 @item Operate on the flash via @command{nand subcommand}
3670 @* Often commands to manipulate the flash are typed by a human, or run
3671 via a script in some automated way. Common task include writing a
3672 boot loader, operating system, or other data needed to initialize or
3676 @b{NOTE:} At the time this text was written, the largest NAND
3677 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3678 This is because the variables used to hold offsets and lengths
3679 are only 32 bits wide.
3680 (Larger chips may work in some cases, unless an offset or length
3681 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3682 Some larger devices will work, since they are actually multi-chip
3683 modules with two smaller chips and individual chipselect lines.
3685 @anchor{NAND Configuration}
3686 @section NAND Configuration Commands
3687 @cindex NAND configuration
3689 NAND chips must be declared in configuration scripts,
3690 plus some additional configuration that's done after
3691 OpenOCD has initialized.
3693 @deffn {Config Command} {nand device} controller target [configparams...]
3694 Declares a NAND device, which can be read and written to
3695 after it has been configured through @command{nand probe}.
3696 In OpenOCD, devices are single chips; this is unlike some
3697 operating systems, which may manage multiple chips as if
3698 they were a single (larger) device.
3699 In some cases, configuring a device will activate extra
3700 commands; see the controller-specific documentation.
3702 @b{NOTE:} This command is not available after OpenOCD
3703 initialization has completed. Use it in board specific
3704 configuration files, not interactively.
3707 @item @var{controller} ... identifies the controller driver
3708 associated with the NAND device being declared.
3709 @xref{NAND Driver List}.
3710 @item @var{target} ... names the target used when issuing
3711 commands to the NAND controller.
3712 @comment Actually, it's currently a controller-specific parameter...
3713 @item @var{configparams} ... controllers may support, or require,
3714 additional parameters. See the controller-specific documentation
3715 for more information.
3719 @deffn Command {nand list}
3720 Prints a one-line summary of each device declared
3721 using @command{nand device}, numbered from zero.
3722 Note that un-probed devices show no details.
3725 @deffn Command {nand probe} num
3726 Probes the specified device to determine key characteristics
3727 like its page and block sizes, and how many blocks it has.
3728 The @var{num} parameter is the value shown by @command{nand list}.
3729 You must (successfully) probe a device before you can use
3730 it with most other NAND commands.
3733 @section Erasing, Reading, Writing to NAND Flash
3735 @deffn Command {nand dump} num filename offset length [oob_option]
3736 @cindex NAND reading
3737 Reads binary data from the NAND device and writes it to the file,
3738 starting at the specified offset.
3739 The @var{num} parameter is the value shown by @command{nand list}.
3741 Use a complete path name for @var{filename}, so you don't depend
3742 on the directory used to start the OpenOCD server.
3744 The @var{offset} and @var{length} must be exact multiples of the
3745 device's page size. They describe a data region; the OOB data
3746 associated with each such page may also be accessed.
3748 @b{NOTE:} At the time this text was written, no error correction
3749 was done on the data that's read, unless raw access was disabled
3750 and the underlying NAND controller driver had a @code{read_page}
3751 method which handled that error correction.
3753 By default, only page data is saved to the specified file.
3754 Use an @var{oob_option} parameter to save OOB data:
3756 @item no oob_* parameter
3757 @*Output file holds only page data; OOB is discarded.
3758 @item @code{oob_raw}
3759 @*Output file interleaves page data and OOB data;
3760 the file will be longer than "length" by the size of the
3761 spare areas associated with each data page.
3762 Note that this kind of "raw" access is different from
3763 what's implied by @command{nand raw_access}, which just
3764 controls whether a hardware-aware access method is used.
3765 @item @code{oob_only}
3766 @*Output file has only raw OOB data, and will
3767 be smaller than "length" since it will contain only the
3768 spare areas associated with each data page.
3772 @deffn Command {nand erase} num offset length
3773 @cindex NAND erasing
3774 @cindex NAND programming
3775 Erases blocks on the specified NAND device, starting at the
3776 specified @var{offset} and continuing for @var{length} bytes.
3777 Both of those values must be exact multiples of the device's
3778 block size, and the region they specify must fit entirely in the chip.
3779 The @var{num} parameter is the value shown by @command{nand list}.
3781 @b{NOTE:} This command will try to erase bad blocks, when told
3782 to do so, which will probably invalidate the manufacturer's bad
3784 For the remainder of the current server session, @command{nand info}
3785 will still report that the block ``is'' bad.
3788 @deffn Command {nand write} num filename offset [option...]
3789 @cindex NAND writing
3790 @cindex NAND programming
3791 Writes binary data from the file into the specified NAND device,
3792 starting at the specified offset. Those pages should already
3793 have been erased; you can't change zero bits to one bits.
3794 The @var{num} parameter is the value shown by @command{nand list}.
3796 Use a complete path name for @var{filename}, so you don't depend
3797 on the directory used to start the OpenOCD server.
3799 The @var{offset} must be an exact multiple of the device's page size.
3800 All data in the file will be written, assuming it doesn't run
3801 past the end of the device.
3802 Only full pages are written, and any extra space in the last
3803 page will be filled with 0xff bytes. (That includes OOB data,
3804 if that's being written.)
3806 @b{NOTE:} At the time this text was written, bad blocks are
3807 ignored. That is, this routine will not skip bad blocks,
3808 but will instead try to write them. This can cause problems.
3810 Provide at most one @var{option} parameter. With some
3811 NAND drivers, the meanings of these parameters may change
3812 if @command{nand raw_access} was used to disable hardware ECC.
3814 @item no oob_* parameter
3815 @*File has only page data, which is written.
3816 If raw acccess is in use, the OOB area will not be written.
3817 Otherwise, if the underlying NAND controller driver has
3818 a @code{write_page} routine, that routine may write the OOB
3819 with hardware-computed ECC data.
3820 @item @code{oob_only}
3821 @*File has only raw OOB data, which is written to the OOB area.
3822 Each page's data area stays untouched. @i{This can be a dangerous
3823 option}, since it can invalidate the ECC data.
3824 You may need to force raw access to use this mode.
3825 @item @code{oob_raw}
3826 @*File interleaves data and OOB data, both of which are written
3827 If raw access is enabled, the data is written first, then the
3829 Otherwise, if the underlying NAND controller driver has
3830 a @code{write_page} routine, that routine may modify the OOB
3831 before it's written, to include hardware-computed ECC data.
3832 @item @code{oob_softecc}
3833 @*File has only page data, which is written.
3834 The OOB area is filled with 0xff, except for a standard 1-bit
3835 software ECC code stored in conventional locations.
3836 You might need to force raw access to use this mode, to prevent
3837 the underlying driver from applying hardware ECC.
3838 @item @code{oob_softecc_kw}
3839 @*File has only page data, which is written.
3840 The OOB area is filled with 0xff, except for a 4-bit software ECC
3841 specific to the boot ROM in Marvell Kirkwood SoCs.
3842 You might need to force raw access to use this mode, to prevent
3843 the underlying driver from applying hardware ECC.
3847 @section Other NAND commands
3848 @cindex NAND other commands
3850 @deffn Command {nand check_bad_blocks} [offset length]
3851 Checks for manufacturer bad block markers on the specified NAND
3852 device. If no parameters are provided, checks the whole
3853 device; otherwise, starts at the specified @var{offset} and
3854 continues for @var{length} bytes.
3855 Both of those values must be exact multiples of the device's
3856 block size, and the region they specify must fit entirely in the chip.
3857 The @var{num} parameter is the value shown by @command{nand list}.
3859 @b{NOTE:} Before using this command you should force raw access
3860 with @command{nand raw_access enable} to ensure that the underlying
3861 driver will not try to apply hardware ECC.
3864 @deffn Command {nand info} num
3865 The @var{num} parameter is the value shown by @command{nand list}.
3866 This prints the one-line summary from "nand list", plus for
3867 devices which have been probed this also prints any known
3868 status for each block.
3871 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
3872 Sets or clears an flag affecting how page I/O is done.
3873 The @var{num} parameter is the value shown by @command{nand list}.
3875 This flag is cleared (disabled) by default, but changing that
3876 value won't affect all NAND devices. The key factor is whether
3877 the underlying driver provides @code{read_page} or @code{write_page}
3878 methods. If it doesn't provide those methods, the setting of
3879 this flag is irrelevant; all access is effectively ``raw''.
3881 When those methods exist, they are normally used when reading
3882 data (@command{nand dump} or reading bad block markers) or
3883 writing it (@command{nand write}). However, enabling
3884 raw access (setting the flag) prevents use of those methods,
3885 bypassing hardware ECC logic.
3886 @i{This can be a dangerous option}, since writing blocks
3887 with the wrong ECC data can cause them to be marked as bad.
3890 @anchor{NAND Driver List}
3891 @section NAND Drivers, Options, and Commands
3892 As noted above, the @command{nand device} command allows
3893 driver-specific options and behaviors.
3894 Some controllers also activate controller-specific commands.
3896 @deffn {NAND Driver} davinci
3897 This driver handles the NAND controllers found on DaVinci family
3898 chips from Texas Instruments.
3899 It takes three extra parameters:
3900 address of the NAND chip;
3901 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3902 address of the AEMIF controller on this processor.
3904 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3906 All DaVinci processors support the single-bit ECC hardware,
3907 and newer ones also support the four-bit ECC hardware.
3908 The @code{write_page} and @code{read_page} methods are used
3909 to implement those ECC modes, unless they are disabled using
3910 the @command{nand raw_access} command.
3913 @deffn {NAND Driver} lpc3180
3914 These controllers require an extra @command{nand device}
3915 parameter: the clock rate used by the controller.
3916 @deffn Command {lpc3180 select} num [mlc|slc]
3917 Configures use of the MLC or SLC controller mode.
3918 MLC implies use of hardware ECC.
3919 The @var{num} parameter is the value shown by @command{nand list}.
3922 At this writing, this driver includes @code{write_page}
3923 and @code{read_page} methods. Using @command{nand raw_access}
3924 to disable those methods will prevent use of hardware ECC
3925 in the MLC controller mode, but won't change SLC behavior.
3927 @comment current lpc3180 code won't issue 5-byte address cycles
3929 @deffn {NAND Driver} orion
3930 These controllers require an extra @command{nand device}
3931 parameter: the address of the controller.
3933 nand device orion 0xd8000000
3935 These controllers don't define any specialized commands.
3936 At this writing, their drivers don't include @code{write_page}
3937 or @code{read_page} methods, so @command{nand raw_access} won't
3938 change any behavior.
3941 @deffn {NAND Driver} s3c2410
3942 @deffnx {NAND Driver} s3c2412
3943 @deffnx {NAND Driver} s3c2440
3944 @deffnx {NAND Driver} s3c2443
3945 These S3C24xx family controllers don't have any special
3946 @command{nand device} options, and don't define any
3947 specialized commands.
3948 At this writing, their drivers don't include @code{write_page}
3949 or @code{read_page} methods, so @command{nand raw_access} won't
3950 change any behavior.
3953 @node PLD/FPGA Commands
3954 @chapter PLD/FPGA Commands
3958 Programmable Logic Devices (PLDs) and the more flexible
3959 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
3960 OpenOCD can support programming them.
3961 Although PLDs are generally restrictive (cells are less functional, and
3962 there are no special purpose cells for memory or computational tasks),
3963 they share the same OpenOCD infrastructure.
3964 Accordingly, both are called PLDs here.
3966 @section PLD/FPGA Configuration and Commands
3968 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
3969 OpenOCD maintains a list of PLDs available for use in various commands.
3970 Also, each such PLD requires a driver.
3972 They are referenced by the number shown by the @command{pld devices} command,
3973 and new PLDs are defined by @command{pld device driver_name}.
3975 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
3976 Defines a new PLD device, supported by driver @var{driver_name},
3977 using the TAP named @var{tap_name}.
3978 The driver may make use of any @var{driver_options} to configure its
3982 @deffn {Command} {pld devices}
3983 Lists the PLDs and their numbers.
3986 @deffn {Command} {pld load} num filename
3987 Loads the file @file{filename} into the PLD identified by @var{num}.
3988 The file format must be inferred by the driver.
3991 @section PLD/FPGA Drivers, Options, and Commands
3993 Drivers may support PLD-specific options to the @command{pld device}
3994 definition command, and may also define commands usable only with
3995 that particular type of PLD.
3997 @deffn {FPGA Driver} virtex2
3998 Virtex-II is a family of FPGAs sold by Xilinx.
3999 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4000 No driver-specific PLD definition options are used,
4001 and one driver-specific command is defined.
4003 @deffn {Command} {virtex2 read_stat} num
4004 Reads and displays the Virtex-II status register (STAT)
4009 @node General Commands
4010 @chapter General Commands
4013 The commands documented in this chapter here are common commands that
4014 you, as a human, may want to type and see the output of. Configuration type
4015 commands are documented elsewhere.
4019 @item @b{Source Of Commands}
4020 @* OpenOCD commands can occur in a configuration script (discussed
4021 elsewhere) or typed manually by a human or supplied programatically,
4022 or via one of several TCP/IP Ports.
4024 @item @b{From the human}
4025 @* A human should interact with the telnet interface (default port: 4444)
4026 or via GDB (default port 3333).
4028 To issue commands from within a GDB session, use the @option{monitor}
4029 command, e.g. use @option{monitor poll} to issue the @option{poll}
4030 command. All output is relayed through the GDB session.
4032 @item @b{Machine Interface}
4033 The Tcl interface's intent is to be a machine interface. The default Tcl
4038 @section Daemon Commands
4040 @deffn {Command} exit
4041 Exits the current telnet session.
4044 @c note EXTREMELY ANNOYING word wrap at column 75
4045 @c even when lines are e.g. 100+ columns ...
4046 @c coded in startup.tcl
4047 @deffn {Command} help [string]
4048 With no parameters, prints help text for all commands.
4049 Otherwise, prints each helptext containing @var{string}.
4050 Not every command provides helptext.
4053 @deffn Command sleep msec [@option{busy}]
4054 Wait for at least @var{msec} milliseconds before resuming.
4055 If @option{busy} is passed, busy-wait instead of sleeping.
4056 (This option is strongly discouraged.)
4057 Useful in connection with script files
4058 (@command{script} command and @command{target_name} configuration).
4061 @deffn Command shutdown
4062 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4065 @anchor{debug_level}
4066 @deffn Command debug_level [n]
4067 @cindex message level
4068 Display debug level.
4069 If @var{n} (from 0..3) is provided, then set it to that level.
4070 This affects the kind of messages sent to the server log.
4071 Level 0 is error messages only;
4072 level 1 adds warnings;
4073 level 2 adds informational messages;
4074 and level 3 adds debugging messages.
4075 The default is level 2, but that can be overridden on
4076 the command line along with the location of that log
4077 file (which is normally the server's standard output).
4081 @deffn Command fast (@option{enable}|@option{disable})
4083 Set default behaviour of OpenOCD to be "fast and dangerous".
4085 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4086 fast memory access, and DCC downloads. Those parameters may still be
4087 individually overridden.
4089 The target specific "dangerous" optimisation tweaking options may come and go
4090 as more robust and user friendly ways are found to ensure maximum throughput
4091 and robustness with a minimum of configuration.
4093 Typically the "fast enable" is specified first on the command line:
4096 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4100 @deffn Command echo message
4101 Logs a message at "user" priority.
4102 Output @var{message} to stdout.
4104 echo "Downloading kernel -- please wait"
4108 @deffn Command log_output [filename]
4109 Redirect logging to @var{filename};
4110 the initial log output channel is stderr.
4113 @anchor{Target State handling}
4114 @section Target State handling
4117 @cindex target initialization
4119 In this section ``target'' refers to a CPU configured as
4120 shown earlier (@pxref{CPU Configuration}).
4121 These commands, like many, implicitly refer to
4122 a current target which is used to perform the
4123 various operations. The current target may be changed
4124 by using @command{targets} command with the name of the
4125 target which should become current.
4127 @deffn Command reg [(number|name) [value]]
4128 Access a single register by @var{number} or by its @var{name}.
4130 @emph{With no arguments}:
4131 list all available registers for the current target,
4132 showing number, name, size, value, and cache status.
4134 @emph{With number/name}: display that register's value.
4136 @emph{With both number/name and value}: set register's value.
4138 Cores may have surprisingly many registers in their
4139 Debug and trace infrastructure:
4143 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4144 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4145 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4147 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4148 0x00000000 (dirty: 0, valid: 0)
4153 @deffn Command halt [ms]
4154 @deffnx Command wait_halt [ms]
4155 The @command{halt} command first sends a halt request to the target,
4156 which @command{wait_halt} doesn't.
4157 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4158 or 5 seconds if there is no parameter, for the target to halt
4159 (and enter debug mode).
4160 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4163 @deffn Command resume [address]
4164 Resume the target at its current code position,
4165 or the optional @var{address} if it is provided.
4166 OpenOCD will wait 5 seconds for the target to resume.
4169 @deffn Command step [address]
4170 Single-step the target at its current code position,
4171 or the optional @var{address} if it is provided.
4174 @anchor{Reset Command}
4175 @deffn Command reset
4176 @deffnx Command {reset run}
4177 @deffnx Command {reset halt}
4178 @deffnx Command {reset init}
4179 Perform as hard a reset as possible, using SRST if possible.
4180 @emph{All defined targets will be reset, and target
4181 events will fire during the reset sequence.}
4183 The optional parameter specifies what should
4184 happen after the reset.
4185 If there is no parameter, a @command{reset run} is executed.
4186 The other options will not work on all systems.
4187 @xref{Reset Configuration}.
4190 @item @b{run} Let the target run
4191 @item @b{halt} Immediately halt the target
4192 @item @b{init} Immediately halt the target, and execute the reset-init script
4196 @deffn Command soft_reset_halt
4197 Requesting target halt and executing a soft reset. This is often used
4198 when a target cannot be reset and halted. The target, after reset is
4199 released begins to execute code. OpenOCD attempts to stop the CPU and
4200 then sets the program counter back to the reset vector. Unfortunately
4201 the code that was executed may have left the hardware in an unknown
4205 @section I/O Utilities
4207 These commands are available when
4208 OpenOCD is built with @option{--enable-ioutil}.
4209 They are mainly useful on embedded targets,
4211 Hosts with operating systems have complementary tools.
4213 @emph{Note:} there are several more such commands.
4215 @deffn Command append_file filename [string]*
4216 Appends the @var{string} parameters to
4217 the text file @file{filename}.
4218 Each string except the last one is followed by one space.
4219 The last string is followed by a newline.
4222 @deffn Command cat filename
4223 Reads and displays the text file @file{filename}.
4226 @deffn Command cp src_filename dest_filename
4227 Copies contents from the file @file{src_filename}
4228 into @file{dest_filename}.
4232 @emph{No description provided.}
4236 @emph{No description provided.}
4240 @emph{No description provided.}
4243 @deffn Command meminfo
4244 Display available RAM memory on OpenOCD host.
4245 Used in OpenOCD regression testing scripts.
4249 @emph{No description provided.}
4253 @emph{No description provided.}
4256 @deffn Command rm filename
4257 @c "rm" has both normal and Jim-level versions??
4258 Unlinks the file @file{filename}.
4261 @deffn Command trunc filename
4262 Removes all data in the file @file{filename}.
4265 @anchor{Memory access}
4266 @section Memory access commands
4267 @cindex memory access
4269 These commands allow accesses of a specific size to the memory
4270 system. Often these are used to configure the current target in some
4271 special way. For example - one may need to write certain values to the
4272 SDRAM controller to enable SDRAM.
4275 @item Use the @command{targets} (plural) command
4276 to change the current target.
4277 @item In system level scripts these commands are deprecated.
4278 Please use their TARGET object siblings to avoid making assumptions
4279 about what TAP is the current target, or about MMU configuration.
4282 @deffn Command mdw addr [count]
4283 @deffnx Command mdh addr [count]
4284 @deffnx Command mdb addr [count]
4285 Display contents of address @var{addr}, as
4286 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4287 or 8-bit bytes (@command{mdb}).
4288 If @var{count} is specified, displays that many units.
4289 (If you want to manipulate the data instead of displaying it,
4290 see the @code{mem2array} primitives.)
4293 @deffn Command mww addr word
4294 @deffnx Command mwh addr halfword
4295 @deffnx Command mwb addr byte
4296 Writes the specified @var{word} (32 bits),
4297 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4298 at the specified address @var{addr}.
4302 @anchor{Image access}
4303 @section Image loading commands
4304 @cindex image loading
4305 @cindex image dumping
4308 @deffn Command {dump_image} filename address size
4309 Dump @var{size} bytes of target memory starting at @var{address} to the
4310 binary file named @var{filename}.
4313 @deffn Command {fast_load}
4314 Loads an image stored in memory by @command{fast_load_image} to the
4315 current target. Must be preceeded by fast_load_image.
4318 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4319 Normally you should be using @command{load_image} or GDB load. However, for
4320 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4321 host), storing the image in memory and uploading the image to the target
4322 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4323 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4324 memory, i.e. does not affect target. This approach is also useful when profiling
4325 target programming performance as I/O and target programming can easily be profiled
4330 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4331 Load image from file @var{filename} to target memory at @var{address}.
4332 The file format may optionally be specified
4333 (@option{bin}, @option{ihex}, or @option{elf})
4336 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4337 Displays image section sizes and addresses
4338 as if @var{filename} were loaded into target memory
4339 starting at @var{address} (defaults to zero).
4340 The file format may optionally be specified
4341 (@option{bin}, @option{ihex}, or @option{elf})
4344 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4345 Verify @var{filename} against target memory starting at @var{address}.
4346 The file format may optionally be specified
4347 (@option{bin}, @option{ihex}, or @option{elf})
4348 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4352 @section Breakpoint and Watchpoint commands
4356 CPUs often make debug modules accessible through JTAG, with
4357 hardware support for a handful of code breakpoints and data
4359 In addition, CPUs almost always support software breakpoints.
4361 @deffn Command {bp} [address len [@option{hw}]]
4362 With no parameters, lists all active breakpoints.
4363 Else sets a breakpoint on code execution starting
4364 at @var{address} for @var{length} bytes.
4365 This is a software breakpoint, unless @option{hw} is specified
4366 in which case it will be a hardware breakpoint.
4368 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4369 for similar mechanisms that do not consume hardware breakpoints.)
4372 @deffn Command {rbp} address
4373 Remove the breakpoint at @var{address}.
4376 @deffn Command {rwp} address
4377 Remove data watchpoint on @var{address}
4380 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4381 With no parameters, lists all active watchpoints.
4382 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4383 The watch point is an "access" watchpoint unless
4384 the @option{r} or @option{w} parameter is provided,
4385 defining it as respectively a read or write watchpoint.
4386 If a @var{value} is provided, that value is used when determining if
4387 the watchpoint should trigger. The value may be first be masked
4388 using @var{mask} to mark ``don't care'' fields.
4391 @section Misc Commands
4394 @deffn Command {profile} seconds filename
4395 Profiling samples the CPU's program counter as quickly as possible,
4396 which is useful for non-intrusive stochastic profiling.
4397 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4400 @deffn Command {version}
4401 Displays a string identifying the version of this OpenOCD server.
4404 @deffn Command {virt2phys} virtual_address
4405 Requests the current target to map the specified @var{virtual_address}
4406 to its corresponding physical address, and displays the result.
4409 @node Architecture and Core Commands
4410 @chapter Architecture and Core Commands
4411 @cindex Architecture Specific Commands
4412 @cindex Core Specific Commands
4414 Most CPUs have specialized JTAG operations to support debugging.
4415 OpenOCD packages most such operations in its standard command framework.
4416 Some of those operations don't fit well in that framework, so they are
4417 exposed here as architecture or implementation (core) specific commands.
4419 @anchor{ARM Hardware Tracing}
4420 @section ARM Hardware Tracing
4425 CPUs based on ARM cores may include standard tracing interfaces,
4426 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4427 address and data bus trace records to a ``Trace Port''.
4431 Development-oriented boards will sometimes provide a high speed
4432 trace connector for collecting that data, when the particular CPU
4433 supports such an interface.
4434 (The standard connector is a 38-pin Mictor, with both JTAG
4435 and trace port support.)
4436 Those trace connectors are supported by higher end JTAG adapters
4437 and some logic analyzer modules; frequently those modules can
4438 buffer several megabytes of trace data.
4439 Configuring an ETM coupled to such an external trace port belongs
4440 in the board-specific configuration file.
4442 If the CPU doesn't provide an external interface, it probably
4443 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4444 dedicated SRAM. 4KBytes is one common ETB size.
4445 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4446 (target) configuration file, since it works the same on all boards.
4449 ETM support in OpenOCD doesn't seem to be widely used yet.
4452 ETM support may be buggy, and at least some @command{etm config}
4453 parameters should be detected by asking the ETM for them.
4454 It seems like a GDB hookup should be possible,
4455 as well as triggering trace on specific events
4456 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4457 There should be GUI tools to manipulate saved trace data and help
4458 analyse it in conjunction with the source code.
4459 It's unclear how much of a common interface is shared
4460 with the current XScale trace support, or should be
4461 shared with eventual Nexus-style trace module support.
4464 @subsection ETM Configuration
4465 ETM setup is coupled with the trace port driver configuration.
4467 @deffn {Config Command} {etm config} target width mode clocking driver
4468 Declares the ETM associated with @var{target}, and associates it
4469 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4471 Several of the parameters must reflect the trace port configuration.
4472 The @var{width} must be either 4, 8, or 16.
4473 The @var{mode} must be @option{normal}, @option{multiplexted},
4474 or @option{demultiplexted}.
4475 The @var{clocking} must be @option{half} or @option{full}.
4478 You can see the ETM registers using the @command{reg} command, although
4479 not all of those possible registers are present in every ETM.
4483 @deffn Command {etm info}
4484 Displays information about the current target's ETM.
4487 @deffn Command {etm status}
4488 Displays status of the current target's ETM:
4489 is the ETM idle, or is it collecting data?
4490 Did trace data overflow?
4494 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4495 Displays what data that ETM will collect.
4496 If arguments are provided, first configures that data.
4497 When the configuration changes, tracing is stopped
4498 and any buffered trace data is invalidated.
4501 @item @var{type} ... one of
4502 @option{none} (save nothing),
4503 @option{data} (save data),
4504 @option{address} (save addresses),
4505 @option{all} (save data and addresses)
4506 @item @var{context_id_bits} ... 0, 8, 16, or 32
4507 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4508 @item @var{branch_output} ... @option{enable} or @option{disable}
4512 @deffn Command {etm trigger_percent} percent
4513 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4516 @subsection ETM Trace Operation
4518 After setting up the ETM, you can use it to collect data.
4519 That data can be exported to files for later analysis.
4520 It can also be parsed with OpenOCD, for basic sanity checking.
4522 @deffn Command {etm analyze}
4523 Reads trace data into memory, if it wasn't already present.
4524 Decodes and prints the data that was collected.
4527 @deffn Command {etm dump} filename
4528 Stores the captured trace data in @file{filename}.
4531 @deffn Command {etm image} filename [base_address] [type]
4532 Opens an image file.
4535 @deffn Command {etm load} filename
4536 Loads captured trace data from @file{filename}.
4539 @deffn Command {etm start}
4540 Starts trace data collection.
4543 @deffn Command {etm stop}
4544 Stops trace data collection.
4547 @anchor{Trace Port Drivers}
4548 @subsection Trace Port Drivers
4550 To use an ETM trace port it must be associated with a driver.
4552 @deffn {Trace Port Driver} dummy
4553 Use the @option{dummy} driver if you are configuring an ETM that's
4554 not connected to anything (on-chip ETB or off-chip trace connector).
4555 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4556 any trace data collection.}
4557 @deffn {Config Command} {etm_dummy config} target
4558 Associates the ETM for @var{target} with a dummy driver.
4562 @deffn {Trace Port Driver} etb
4563 Use the @option{etb} driver if you are configuring an ETM
4564 to use on-chip ETB memory.
4565 @deffn {Config Command} {etb config} target etb_tap
4566 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4567 You can see the ETB registers using the @command{reg} command.
4571 @deffn {Trace Port Driver} oocd_trace
4572 This driver isn't available unless OpenOCD was explicitly configured
4573 with the @option{--enable-oocd_trace} option. You probably don't want
4574 to configure it unless you've built the appropriate prototype hardware;
4575 it's @emph{proof-of-concept} software.
4577 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4578 connected to an off-chip trace connector.
4580 @deffn {Config Command} {oocd_trace config} target tty
4581 Associates the ETM for @var{target} with a trace driver which
4582 collects data through the serial port @var{tty}.
4585 @deffn Command {oocd_trace resync}
4586 Re-synchronizes with the capture clock.
4589 @deffn Command {oocd_trace status}
4590 Reports whether the capture clock is locked or not.
4595 @section ARMv4 and ARMv5 Architecture
4599 These commands are specific to ARM architecture v4 and v5,
4600 including all ARM7 or ARM9 systems and Intel XScale.
4601 They are available in addition to other core-specific
4602 commands that may be available.
4604 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4605 Displays the core_state, optionally changing it to process
4606 either @option{arm} or @option{thumb} instructions.
4607 The target may later be resumed in the currently set core_state.
4608 (Processors may also support the Jazelle state, but
4609 that is not currently supported in OpenOCD.)
4612 @deffn Command {armv4_5 disassemble} address count [thumb]
4614 Disassembles @var{count} instructions starting at @var{address}.
4615 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
4616 else ARM (32-bit) instructions are used.
4617 (Processors may also support the Jazelle state, but
4618 those instructions are not currently understood by OpenOCD.)
4621 @deffn Command {armv4_5 reg}
4622 Display a table of all banked core registers, fetching the current value from every
4623 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4627 @subsection ARM7 and ARM9 specific commands
4631 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4632 ARM9TDMI, ARM920T or ARM926EJ-S.
4633 They are available in addition to the ARMv4/5 commands,
4634 and any other core-specific commands that may be available.
4636 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4637 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4638 instead of breakpoints. This should be
4639 safe for all but ARM7TDMI--S cores (like Philips LPC).
4640 This feature is enabled by default on most ARM9 cores,
4641 including ARM9TDMI, ARM920T, and ARM926EJ-S.
4644 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4646 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4647 amounts of memory. DCC downloads offer a huge speed increase, but might be
4648 unsafe, especially with targets running at very low speeds. This command was introduced
4649 with OpenOCD rev. 60, and requires a few bytes of working area.
4652 @anchor{arm7_9 fast_memory_access}
4653 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4654 Enable or disable memory writes and reads that don't check completion of
4655 the operation. This provides a huge speed increase, especially with USB JTAG
4656 cables (FT2232), but might be unsafe if used with targets running at very low
4657 speeds, like the 32kHz startup clock of an AT91RM9200.
4660 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4661 @emph{This is intended for use while debugging OpenOCD; you probably
4664 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4665 as used in the specified @var{mode}
4666 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4667 the M4..M0 bits of the PSR).
4668 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4669 Register 16 is the mode-specific SPSR,
4670 unless the specified mode is 0xffffffff (32-bit all-ones)
4671 in which case register 16 is the CPSR.
4672 The write goes directly to the CPU, bypassing the register cache.
4675 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4676 @emph{This is intended for use while debugging OpenOCD; you probably
4679 If the second parameter is zero, writes @var{word} to the
4680 Current Program Status register (CPSR).
4681 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4682 In both cases, this bypasses the register cache.
4685 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4686 @emph{This is intended for use while debugging OpenOCD; you probably
4689 Writes eight bits to the CPSR or SPSR,
4690 first rotating them by @math{2*rotate} bits,
4691 and bypassing the register cache.
4692 This has lower JTAG overhead than writing the entire CPSR or SPSR
4693 with @command{arm7_9 write_xpsr}.
4696 @subsection ARM720T specific commands
4699 These commands are available to ARM720T based CPUs,
4700 which are implementations of the ARMv4T architecture
4701 based on the ARM7TDMI-S integer core.
4702 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4704 @deffn Command {arm720t cp15} regnum [value]
4705 Display cp15 register @var{regnum};
4706 else if a @var{value} is provided, that value is written to that register.
4709 @deffn Command {arm720t mdw_phys} addr [count]
4710 @deffnx Command {arm720t mdh_phys} addr [count]
4711 @deffnx Command {arm720t mdb_phys} addr [count]
4712 Display contents of physical address @var{addr}, as
4713 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4714 or 8-bit bytes (@command{mdb_phys}).
4715 If @var{count} is specified, displays that many units.
4718 @deffn Command {arm720t mww_phys} addr word
4719 @deffnx Command {arm720t mwh_phys} addr halfword
4720 @deffnx Command {arm720t mwb_phys} addr byte
4721 Writes the specified @var{word} (32 bits),
4722 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4723 at the specified physical address @var{addr}.
4726 @deffn Command {arm720t virt2phys} va
4727 Translate a virtual address @var{va} to a physical address
4728 and display the result.
4731 @subsection ARM9TDMI specific commands
4734 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
4735 or processors resembling ARM9TDMI, and can use these commands.
4736 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4738 @c 9-june-2009: tried this on arm920t, it didn't work.
4739 @c no-params always lists nothing caught, and that's how it acts.
4741 @anchor{arm9tdmi vector_catch}
4742 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
4743 @cindex vector_catch
4744 Vector Catch hardware provides a sort of dedicated breakpoint
4745 for hardware events such as reset, interrupt, and abort.
4746 You can use this to conserve normal breakpoint resources,
4747 so long as you're not concerned with code that branches directly
4748 to those hardware vectors.
4750 This always finishes by listing the current configuration.
4751 If parameters are provided, it first reconfigures the
4752 vector catch hardware to intercept
4753 @option{all} of the hardware vectors,
4754 @option{none} of them,
4755 or a list with one or more of the following:
4756 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4757 @option{irq} @option{fiq}.
4760 @subsection ARM920T specific commands
4763 These commands are available to ARM920T based CPUs,
4764 which are implementations of the ARMv4T architecture
4765 built using the ARM9TDMI integer core.
4766 They are available in addition to the ARMv4/5, ARM7/ARM9,
4767 and ARM9TDMI commands.
4769 @deffn Command {arm920t cache_info}
4770 Print information about the caches found. This allows to see whether your target
4771 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
4774 @deffn Command {arm920t cp15} regnum [value]
4775 Display cp15 register @var{regnum};
4776 else if a @var{value} is provided, that value is written to that register.
4779 @deffn Command {arm920t cp15i} opcode [value [address]]
4780 Interpreted access using cp15 @var{opcode}.
4781 If no @var{value} is provided, the result is displayed.
4782 Else if that value is written using the specified @var{address},
4783 or using zero if no other address is not provided.
4786 @deffn Command {arm920t mdw_phys} addr [count]
4787 @deffnx Command {arm920t mdh_phys} addr [count]
4788 @deffnx Command {arm920t mdb_phys} addr [count]
4789 Display contents of physical address @var{addr}, as
4790 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4791 or 8-bit bytes (@command{mdb_phys}).
4792 If @var{count} is specified, displays that many units.
4795 @deffn Command {arm920t mww_phys} addr word
4796 @deffnx Command {arm920t mwh_phys} addr halfword
4797 @deffnx Command {arm920t mwb_phys} addr byte
4798 Writes the specified @var{word} (32 bits),
4799 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4800 at the specified physical address @var{addr}.
4803 @deffn Command {arm920t read_cache} filename
4804 Dump the content of ICache and DCache to a file named @file{filename}.
4807 @deffn Command {arm920t read_mmu} filename
4808 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4811 @deffn Command {arm920t virt2phys} va
4812 Translate a virtual address @var{va} to a physical address
4813 and display the result.
4816 @subsection ARM926ej-s specific commands
4819 These commands are available to ARM926ej-s based CPUs,
4820 which are implementations of the ARMv5TEJ architecture
4821 based on the ARM9EJ-S integer core.
4822 They are available in addition to the ARMv4/5, ARM7/ARM9,
4823 and ARM9TDMI commands.
4825 The Feroceon cores also support these commands, although
4826 they are not built from ARM926ej-s designs.
4828 @deffn Command {arm926ejs cache_info}
4829 Print information about the caches found.
4832 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4833 Accesses cp15 register @var{regnum} using
4834 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4835 If a @var{value} is provided, that value is written to that register.
4836 Else that register is read and displayed.
4839 @deffn Command {arm926ejs mdw_phys} addr [count]
4840 @deffnx Command {arm926ejs mdh_phys} addr [count]
4841 @deffnx Command {arm926ejs mdb_phys} addr [count]
4842 Display contents of physical address @var{addr}, as
4843 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4844 or 8-bit bytes (@command{mdb_phys}).
4845 If @var{count} is specified, displays that many units.
4848 @deffn Command {arm926ejs mww_phys} addr word
4849 @deffnx Command {arm926ejs mwh_phys} addr halfword
4850 @deffnx Command {arm926ejs mwb_phys} addr byte
4851 Writes the specified @var{word} (32 bits),
4852 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4853 at the specified physical address @var{addr}.
4856 @deffn Command {arm926ejs virt2phys} va
4857 Translate a virtual address @var{va} to a physical address
4858 and display the result.
4861 @subsection ARM966E specific commands
4864 These commands are available to ARM966 based CPUs,
4865 which are implementations of the ARMv5TE architecture.
4866 They are available in addition to the ARMv4/5, ARM7/ARM9,
4867 and ARM9TDMI commands.
4869 @deffn Command {arm966e cp15} regnum [value]
4870 Display cp15 register @var{regnum};
4871 else if a @var{value} is provided, that value is written to that register.
4874 @subsection XScale specific commands
4877 These commands are available to XScale based CPUs,
4878 which are implementations of the ARMv5TE architecture.
4880 @deffn Command {xscale analyze_trace}
4881 Displays the contents of the trace buffer.
4884 @deffn Command {xscale cache_clean_address} address
4885 Changes the address used when cleaning the data cache.
4888 @deffn Command {xscale cache_info}
4889 Displays information about the CPU caches.
4892 @deffn Command {xscale cp15} regnum [value]
4893 Display cp15 register @var{regnum};
4894 else if a @var{value} is provided, that value is written to that register.
4897 @deffn Command {xscale debug_handler} target address
4898 Changes the address used for the specified target's debug handler.
4901 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
4902 Enables or disable the CPU's data cache.
4905 @deffn Command {xscale dump_trace} filename
4906 Dumps the raw contents of the trace buffer to @file{filename}.
4909 @deffn Command {xscale icache} (@option{enable}|@option{disable})
4910 Enables or disable the CPU's instruction cache.
4913 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
4914 Enables or disable the CPU's memory management unit.
4917 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
4918 Enables or disables the trace buffer,
4919 and controls how it is emptied.
4922 @deffn Command {xscale trace_image} filename [offset [type]]
4923 Opens a trace image from @file{filename}, optionally rebasing
4924 its segment addresses by @var{offset}.
4925 The image @var{type} may be one of
4926 @option{bin} (binary), @option{ihex} (Intel hex),
4927 @option{elf} (ELF file), @option{s19} (Motorola s19),
4928 @option{mem}, or @option{builder}.
4931 @anchor{xscale vector_catch}
4932 @deffn Command {xscale vector_catch} [mask]
4933 @cindex vector_catch
4934 Display a bitmask showing the hardware vectors to catch.
4935 If the optional parameter is provided, first set the bitmask to that value.
4938 @section ARMv6 Architecture
4941 @subsection ARM11 specific commands
4944 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
4945 Read coprocessor register
4948 @deffn Command {arm11 memwrite burst} [value]
4949 Displays the value of the memwrite burst-enable flag,
4950 which is enabled by default.
4951 If @var{value} is defined, first assigns that.
4954 @deffn Command {arm11 memwrite error_fatal} [value]
4955 Displays the value of the memwrite error_fatal flag,
4956 which is enabled by default.
4957 If @var{value} is defined, first assigns that.
4960 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
4961 Write coprocessor register
4964 @deffn Command {arm11 no_increment} [value]
4965 Displays the value of the flag controlling whether
4966 some read or write operations increment the pointer
4967 (the default behavior) or not (acting like a FIFO).
4968 If @var{value} is defined, first assigns that.
4971 @deffn Command {arm11 step_irq_enable} [value]
4972 Displays the value of the flag controlling whether
4973 IRQs are enabled during single stepping;
4974 they is disabled by default.
4975 If @var{value} is defined, first assigns that.
4978 @section ARMv7 Architecture
4981 @subsection ARMv7 Debug Access Port (DAP) specific commands
4982 @cindex Debug Access Port
4984 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
4985 included on cortex-m3 and cortex-a8 systems.
4986 They are available in addition to other core-specific commands that may be available.
4988 @deffn Command {dap info} [num]
4989 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
4992 @deffn Command {dap apsel} [num]
4993 Select AP @var{num}, defaulting to 0.
4996 @deffn Command {dap apid} [num]
4997 Displays id register from AP @var{num},
4998 defaulting to the currently selected AP.
5001 @deffn Command {dap baseaddr} [num]
5002 Displays debug base address from AP @var{num},
5003 defaulting to the currently selected AP.
5006 @deffn Command {dap memaccess} [value]
5007 Displays the number of extra tck for mem-ap memory bus access [0-255].
5008 If @var{value} is defined, first assigns that.
5011 @subsection Cortex-M3 specific commands
5014 @deffn Command {cortex_m3 disassemble} address count
5016 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5019 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5020 Control masking (disabling) interrupts during target step/resume.
5023 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5024 @cindex vector_catch
5025 Vector Catch hardware provides dedicated breakpoints
5026 for certain hardware events.
5028 Parameters request interception of
5029 @option{all} of these hardware event vectors,
5030 @option{none} of them,
5031 or one or more of the following:
5032 @option{hard_err} for a HardFault exception;
5033 @option{mm_err} for a MemManage exception;
5034 @option{bus_err} for a BusFault exception;
5037 @option{chk_err}, or
5038 @option{nocp_err} for various UsageFault exceptions; or
5040 If NVIC setup code does not enable them,
5041 MemManage, BusFault, and UsageFault exceptions
5042 are mapped to HardFault.
5043 UsageFault checks for
5044 divide-by-zero and unaligned access
5045 must also be explicitly enabled.
5047 This finishes by listing the current vector catch configuration.
5050 @anchor{Software Debug Messages and Tracing}
5051 @section Software Debug Messages and Tracing
5052 @cindex Linux-ARM DCC support
5056 OpenOCD can process certain requests from target software. Currently
5057 @command{target_request debugmsgs}
5058 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5059 These messages are received as part of target polling, so
5060 you need to have @command{poll on} active to receive them.
5061 They are intrusive in that they will affect program execution
5062 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5064 See @file{libdcc} in the contrib dir for more details.
5065 In addition to sending strings, characters, and
5066 arrays of various size integers from the target,
5067 @file{libdcc} also exports a software trace point mechanism.
5068 The target being debugged may
5069 issue trace messages which include a 24-bit @dfn{trace point} number.
5070 Trace point support includes two distinct mechanisms,
5071 each supported by a command:
5074 @item @emph{History} ... A circular buffer of trace points
5075 can be set up, and then displayed at any time.
5076 This tracks where code has been, which can be invaluable in
5077 finding out how some fault was triggered.
5079 The buffer may overflow, since it collects records continuously.
5080 It may be useful to use some of the 24 bits to represent a
5081 particular event, and other bits to hold data.
5083 @item @emph{Counting} ... An array of counters can be set up,
5084 and then displayed at any time.
5085 This can help establish code coverage and identify hot spots.
5087 The array of counters is directly indexed by the trace point
5088 number, so trace points with higher numbers are not counted.
5091 Linux-ARM kernels have a ``Kernel low-level debugging
5092 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5093 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5094 deliver messages before a serial console can be activated.
5095 This is not the same format used by @file{libdcc}.
5096 Other software, such as the U-Boot boot loader, sometimes
5097 does the same thing.
5099 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5100 Displays current handling of target DCC message requests.
5101 These messages may be sent to the debugger while the target is running.
5102 The optional @option{enable} and @option{charmsg} parameters
5103 both enable the messages, while @option{disable} disables them.
5105 With @option{charmsg} the DCC words each contain one character,
5106 as used by Linux with CONFIG_DEBUG_ICEDCC;
5107 otherwise the libdcc format is used.
5110 @deffn Command {trace history} (@option{clear}|count)
5111 With no parameter, displays all the trace points that have triggered
5112 in the order they triggered.
5113 With the parameter @option{clear}, erases all current trace history records.
5114 With a @var{count} parameter, allocates space for that many
5118 @deffn Command {trace point} (@option{clear}|identifier)
5119 With no parameter, displays all trace point identifiers and how many times
5120 they have been triggered.
5121 With the parameter @option{clear}, erases all current trace point counters.
5122 With a numeric @var{identifier} parameter, creates a new a trace point counter
5123 and associates it with that identifier.
5125 @emph{Important:} The identifier and the trace point number
5126 are not related except by this command.
5127 These trace point numbers always start at zero (from server startup,
5128 or after @command{trace point clear}) and count up from there.
5133 @chapter JTAG Commands
5134 @cindex JTAG Commands
5135 Most general purpose JTAG commands have been presented earlier.
5136 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5137 Lower level JTAG commands, as presented here,
5138 may be needed to work with targets which require special
5139 attention during operations such as reset or initialization.
5141 To use these commands you will need to understand some
5142 of the basics of JTAG, including:
5145 @item A JTAG scan chain consists of a sequence of individual TAP
5146 devices such as a CPUs.
5147 @item Control operations involve moving each TAP through the same
5148 standard state machine (in parallel)
5149 using their shared TMS and clock signals.
5150 @item Data transfer involves shifting data through the chain of
5151 instruction or data registers of each TAP, writing new register values
5152 while the reading previous ones.
5153 @item Data register sizes are a function of the instruction active in
5154 a given TAP, while instruction register sizes are fixed for each TAP.
5155 All TAPs support a BYPASS instruction with a single bit data register.
5156 @item The way OpenOCD differentiates between TAP devices is by
5157 shifting different instructions into (and out of) their instruction
5161 @section Low Level JTAG Commands
5163 These commands are used by developers who need to access
5164 JTAG instruction or data registers, possibly controlling
5165 the order of TAP state transitions.
5166 If you're not debugging OpenOCD internals, or bringing up a
5167 new JTAG adapter or a new type of TAP device (like a CPU or
5168 JTAG router), you probably won't need to use these commands.
5170 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5171 Loads the data register of @var{tap} with a series of bit fields
5172 that specify the entire register.
5173 Each field is @var{numbits} bits long with
5174 a numeric @var{value} (hexadecimal encouraged).
5175 The return value holds the original value of each
5178 For example, a 38 bit number might be specified as one
5179 field of 32 bits then one of 6 bits.
5180 @emph{For portability, never pass fields which are more
5181 than 32 bits long. Many OpenOCD implementations do not
5182 support 64-bit (or larger) integer values.}
5184 All TAPs other than @var{tap} must be in BYPASS mode.
5185 The single bit in their data registers does not matter.
5187 When @var{tap_state} is specified, the JTAG state machine is left
5189 For example @sc{drpause} might be specified, so that more
5190 instructions can be issued before re-entering the @sc{run/idle} state.
5191 If the end state is not specified, the @sc{run/idle} state is entered.
5194 OpenOCD does not record information about data register lengths,
5195 so @emph{it is important that you get the bit field lengths right}.
5196 Remember that different JTAG instructions refer to different
5197 data registers, which may have different lengths.
5198 Moreover, those lengths may not be fixed;
5199 the SCAN_N instruction can change the length of
5200 the register accessed by the INTEST instruction
5201 (by connecting a different scan chain).
5205 @deffn Command {flush_count}
5206 Returns the number of times the JTAG queue has been flushed.
5207 This may be used for performance tuning.
5209 For example, flushing a queue over USB involves a
5210 minimum latency, often several milliseconds, which does
5211 not change with the amount of data which is written.
5212 You may be able to identify performance problems by finding
5213 tasks which waste bandwidth by flushing small transfers too often,
5214 instead of batching them into larger operations.
5217 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5218 For each @var{tap} listed, loads the instruction register
5219 with its associated numeric @var{instruction}.
5220 (The number of bits in that instruction may be displayed
5221 using the @command{scan_chain} command.)
5222 For other TAPs, a BYPASS instruction is loaded.
5224 When @var{tap_state} is specified, the JTAG state machine is left
5226 For example @sc{irpause} might be specified, so the data register
5227 can be loaded before re-entering the @sc{run/idle} state.
5228 If the end state is not specified, the @sc{run/idle} state is entered.
5231 OpenOCD currently supports only a single field for instruction
5232 register values, unlike data register values.
5233 For TAPs where the instruction register length is more than 32 bits,
5234 portable scripts currently must issue only BYPASS instructions.
5238 @deffn Command {jtag_reset} trst srst
5239 Set values of reset signals.
5240 The @var{trst} and @var{srst} parameter values may be
5241 @option{0}, indicating that reset is inactive (pulled or driven high),
5242 or @option{1}, indicating it is active (pulled or driven low).
5243 The @command{reset_config} command should already have been used
5244 to configure how the board and JTAG adapter treat these two
5245 signals, and to say if either signal is even present.
5246 @xref{Reset Configuration}.
5249 @deffn Command {runtest} @var{num_cycles}
5250 Move to the @sc{run/idle} state, and execute at least
5251 @var{num_cycles} of the JTAG clock (TCK).
5252 Instructions often need some time
5253 to execute before they take effect.
5256 @c tms_sequence (short|long)
5257 @c ... temporary, debug-only, probably gone before 0.2 ships
5259 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5260 Verify values captured during @sc{ircapture} and returned
5261 during IR scans. Default is enabled, but this can be
5262 overridden by @command{verify_jtag}.
5265 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5266 Enables verification of DR and IR scans, to help detect
5267 programming errors. For IR scans, @command{verify_ircapture}
5268 must also be enabled.
5272 @section TAP state names
5273 @cindex TAP state names
5275 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5276 and @command{irscan} commands are:
5279 @item @b{RESET} ... should act as if TRST were active
5280 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5283 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5285 @item @b{DRPAUSE} ... data register ready for update or more shifting
5290 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5292 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5297 Note that only six of those states are fully ``stable'' in the
5298 face of TMS fixed (low except for @sc{reset})
5299 and a free-running JTAG clock. For all the
5300 others, the next TCK transition changes to a new state.
5303 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5304 produce side effects by changing register contents. The values
5305 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5306 may not be as expected.
5307 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5308 choices after @command{drscan} or @command{irscan} commands,
5309 since they are free of JTAG side effects.
5310 However, @sc{run/idle} may have side effects that appear at other
5311 levels, such as advancing the ARM9E-S instruction pipeline.
5312 Consult the documentation for the TAP(s) you are working with.
5315 @node Boundary Scan Commands
5316 @chapter Boundary Scan Commands
5318 One of the original purposes of JTAG was to support
5319 boundary scan based hardware testing.
5320 Although its primary focus is to support On-Chip Debugging,
5321 OpenOCD also includes some boundary scan commands.
5323 @section SVF: Serial Vector Format
5324 @cindex Serial Vector Format
5327 The Serial Vector Format, better known as @dfn{SVF}, is a
5328 way to represent JTAG test patterns in text files.
5329 OpenOCD supports running such test files.
5331 @deffn Command {svf} filename [@option{quiet}]
5332 This issues a JTAG reset (Test-Logic-Reset) and then
5333 runs the SVF script from @file{filename}.
5334 Unless the @option{quiet} option is specified,
5335 each command is logged before it is executed.
5338 @section XSVF: Xilinx Serial Vector Format
5339 @cindex Xilinx Serial Vector Format
5342 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5343 binary representation of SVF which is optimized for use with
5345 OpenOCD supports running such test files.
5347 @quotation Important
5348 Not all XSVF commands are supported.
5351 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5352 This issues a JTAG reset (Test-Logic-Reset) and then
5353 runs the XSVF script from @file{filename}.
5354 When a @var{tapname} is specified, the commands are directed at
5356 When @option{virt2} is specified, the @sc{xruntest} command counts
5357 are interpreted as TCK cycles instead of microseconds.
5358 Unless the @option{quiet} option is specified,
5359 messages are logged for comments and some retries.
5365 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5366 be used to access files on PCs (either the developer's PC or some other PC).
5368 The way this works on the ZY1000 is to prefix a filename by
5369 "/tftp/ip/" and append the TFTP path on the TFTP
5370 server (tftpd). For example,
5373 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5376 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5377 if the file was hosted on the embedded host.
5379 In order to achieve decent performance, you must choose a TFTP server
5380 that supports a packet size bigger than the default packet size (512 bytes). There
5381 are numerous TFTP servers out there (free and commercial) and you will have to do
5382 a bit of googling to find something that fits your requirements.
5384 @node GDB and OpenOCD
5385 @chapter GDB and OpenOCD
5387 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5388 to debug remote targets.
5390 @anchor{Connecting to GDB}
5391 @section Connecting to GDB
5392 @cindex Connecting to GDB
5393 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5394 instance GDB 6.3 has a known bug that produces bogus memory access
5395 errors, which has since been fixed: look up 1836 in
5396 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5398 OpenOCD can communicate with GDB in two ways:
5402 A socket (TCP/IP) connection is typically started as follows:
5404 target remote localhost:3333
5406 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5408 A pipe connection is typically started as follows:
5410 target remote | openocd --pipe
5412 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5413 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5417 To list the available OpenOCD commands type @command{monitor help} on the
5420 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5421 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5422 packet size and the device's memory map.
5424 Previous versions of OpenOCD required the following GDB options to increase
5425 the packet size and speed up GDB communication:
5427 set remote memory-write-packet-size 1024
5428 set remote memory-write-packet-size fixed
5429 set remote memory-read-packet-size 1024
5430 set remote memory-read-packet-size fixed
5432 This is now handled in the @option{qSupported} PacketSize and should not be required.
5434 @section Programming using GDB
5435 @cindex Programming using GDB
5437 By default the target memory map is sent to GDB. This can be disabled by
5438 the following OpenOCD configuration option:
5440 gdb_memory_map disable
5442 For this to function correctly a valid flash configuration must also be set
5443 in OpenOCD. For faster performance you should also configure a valid
5446 Informing GDB of the memory map of the target will enable GDB to protect any
5447 flash areas of the target and use hardware breakpoints by default. This means
5448 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5449 using a memory map. @xref{gdb_breakpoint_override}.
5451 To view the configured memory map in GDB, use the GDB command @option{info mem}
5452 All other unassigned addresses within GDB are treated as RAM.
5454 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5455 This can be changed to the old behaviour by using the following GDB command
5457 set mem inaccessible-by-default off
5460 If @command{gdb_flash_program enable} is also used, GDB will be able to
5461 program any flash memory using the vFlash interface.
5463 GDB will look at the target memory map when a load command is given, if any
5464 areas to be programmed lie within the target flash area the vFlash packets
5467 If the target needs configuring before GDB programming, an event
5468 script can be executed:
5470 $_TARGETNAME configure -event EVENTNAME BODY
5473 To verify any flash programming the GDB command @option{compare-sections}
5476 @node Tcl Scripting API
5477 @chapter Tcl Scripting API
5478 @cindex Tcl Scripting API
5482 The commands are stateless. E.g. the telnet command line has a concept
5483 of currently active target, the Tcl API proc's take this sort of state
5484 information as an argument to each proc.
5486 There are three main types of return values: single value, name value
5487 pair list and lists.
5489 Name value pair. The proc 'foo' below returns a name/value pair
5495 > set foo(you) Oyvind
5496 > set foo(mouse) Micky
5497 > set foo(duck) Donald
5505 me Duane you Oyvind mouse Micky duck Donald
5507 Thus, to get the names of the associative array is easy:
5509 foreach { name value } [set foo] {
5510 puts "Name: $name, Value: $value"
5514 Lists returned must be relatively small. Otherwise a range
5515 should be passed in to the proc in question.
5517 @section Internal low-level Commands
5519 By low-level, the intent is a human would not directly use these commands.
5521 Low-level commands are (should be) prefixed with "ocd_", e.g.
5522 @command{ocd_flash_banks}
5523 is the low level API upon which @command{flash banks} is implemented.
5526 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5528 Read memory and return as a Tcl array for script processing
5529 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5531 Convert a Tcl array to memory locations and write the values
5532 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
5534 Return information about the flash banks
5537 OpenOCD commands can consist of two words, e.g. "flash banks". The
5538 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
5539 called "flash_banks".
5541 @section OpenOCD specific Global Variables
5545 Real Tcl has ::tcl_platform(), and platform::identify, and many other
5546 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
5547 holds one of the following values:
5550 @item @b{winxx} Built using Microsoft Visual Studio
5551 @item @b{linux} Linux is the underlying operating sytem
5552 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
5553 @item @b{cygwin} Running under Cygwin
5554 @item @b{mingw32} Running under MingW32
5555 @item @b{other} Unknown, none of the above.
5558 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5561 We should add support for a variable like Tcl variable
5562 @code{tcl_platform(platform)}, it should be called
5563 @code{jim_platform} (because it
5564 is jim, not real tcl).
5568 @chapter Deprecated/Removed Commands
5569 @cindex Deprecated/Removed Commands
5570 Certain OpenOCD commands have been deprecated or
5571 removed during the various revisions.
5573 Upgrade your scripts as soon as possible.
5574 These descriptions for old commands may be removed
5575 a year after the command itself was removed.
5576 This means that in January 2010 this chapter may
5577 become much shorter.
5580 @item @b{arm7_9 fast_writes}
5581 @cindex arm7_9 fast_writes
5582 @*Use @command{arm7_9 fast_memory_access} instead.
5583 @xref{arm7_9 fast_memory_access}.
5586 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5587 @item @b{arm7_9 force_hw_bkpts}
5588 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5589 for flash if the GDB memory map has been set up(default when flash is declared in
5590 target configuration). @xref{gdb_breakpoint_override}.
5591 @item @b{arm7_9 sw_bkpts}
5592 @*On by default. @xref{gdb_breakpoint_override}.
5593 @item @b{daemon_startup}
5594 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5595 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5596 and @option{target cortex_m3 little reset_halt 0}.
5597 @item @b{dump_binary}
5598 @*use @option{dump_image} command with same args. @xref{dump_image}.
5599 @item @b{flash erase}
5600 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5601 @item @b{flash write}
5602 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5603 @item @b{flash write_binary}
5604 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5605 @item @b{flash auto_erase}
5606 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5608 @item @b{jtag_device}
5609 @*use the @command{jtag newtap} command, converting from positional syntax
5610 to named prefixes, and naming the TAP.
5612 Note that if you try to use the old command, a message will tell you the
5613 right new command to use; and that the fourth parameter in the old syntax
5614 was never actually used.
5616 OLD: jtag_device 8 0x01 0xe3 0xfe
5617 NEW: jtag newtap CHIPNAME TAPNAME \
5618 -irlen 8 -ircapture 0x01 -irmask 0xe3
5621 @item @b{jtag_speed} value
5622 @*@xref{JTAG Speed}.
5623 Usually, a value of zero means maximum
5624 speed. The actual effect of this option depends on the JTAG interface used.
5626 @item wiggler: maximum speed / @var{number}
5627 @item ft2232: 6MHz / (@var{number}+1)
5628 @item amt jtagaccel: 8 / 2**@var{number}
5629 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5630 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5631 @comment end speed list.
5634 @item @b{load_binary}
5635 @*use @option{load_image} command with same args. @xref{load_image}.
5636 @item @b{run_and_halt_time}
5637 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5644 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5645 @*use the create subcommand of @option{target}.
5646 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5647 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5648 @item @b{working_area}
5649 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5657 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5659 @cindex adaptive clocking
5662 In digital circuit design it is often refered to as ``clock
5663 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5664 operating at some speed, your target is operating at another. The two
5665 clocks are not synchronised, they are ``asynchronous''
5667 In order for the two to work together they must be synchronised. Otherwise
5668 the two systems will get out of sync with each other and nothing will
5669 work. There are 2 basic options:
5672 Use a special circuit.
5674 One clock must be some multiple slower than the other.
5677 @b{Does this really matter?} For some chips and some situations, this
5678 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
5679 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
5680 program/enable the oscillators and eventually the main clock. It is in
5681 those critical times you must slow the JTAG clock to sometimes 1 to
5684 Imagine debugging a 500MHz ARM926 hand held battery powered device
5685 that ``deep sleeps'' at 32kHz between every keystroke. It can be
5688 @b{Solution #1 - A special circuit}
5690 In order to make use of this, your JTAG dongle must support the RTCK
5691 feature. Not all dongles support this - keep reading!
5693 The RTCK signal often found in some ARM chips is used to help with
5694 this problem. ARM has a good description of the problem described at
5695 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
5696 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
5697 work? / how does adaptive clocking work?''.
5699 The nice thing about adaptive clocking is that ``battery powered hand
5700 held device example'' - the adaptiveness works perfectly all the
5701 time. One can set a break point or halt the system in the deep power
5702 down code, slow step out until the system speeds up.
5704 Note that adaptive clocking may also need to work at the board level,
5705 when a board-level scan chain has multiple chips.
5706 Parallel clock voting schemes are good way to implement this,
5707 both within and between chips, and can easily be implemented
5709 It's not difficult to have logic fan a module's input TCK signal out
5710 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
5711 back with the right polarity before changing the output RTCK signal.
5712 Texas Instruments makes some clock voting logic available
5713 for free (with no support) in VHDL form; see
5714 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
5716 @b{Solution #2 - Always works - but may be slower}
5718 Often this is a perfectly acceptable solution.
5720 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
5721 the target clock speed. But what that ``magic division'' is varies
5722 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
5723 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
5724 1/12 the clock speed.
5726 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
5728 You can still debug the 'low power' situations - you just need to
5729 manually adjust the clock speed at every step. While painful and
5730 tedious, it is not always practical.
5732 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
5733 have a special debug mode in your application that does a ``high power
5734 sleep''. If you are careful - 98% of your problems can be debugged
5737 To set the JTAG frequency use the command:
5745 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
5747 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
5748 around Windows filenames.
5761 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
5763 Make sure you have Cygwin installed, or at least a version of OpenOCD that
5764 claims to come with all the necessary DLLs. When using Cygwin, try launching
5765 OpenOCD from the Cygwin shell.
5767 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
5768 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
5769 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
5771 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
5772 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
5773 software breakpoints consume one of the two available hardware breakpoints.
5775 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
5777 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
5778 clock at the time you're programming the flash. If you've specified the crystal's
5779 frequency, make sure the PLL is disabled. If you've specified the full core speed
5780 (e.g. 60MHz), make sure the PLL is enabled.
5782 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
5783 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
5784 out while waiting for end of scan, rtck was disabled".
5786 Make sure your PC's parallel port operates in EPP mode. You might have to try several
5787 settings in your PC BIOS (ECP, EPP, and different versions of those).
5789 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
5790 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
5791 memory read caused data abort".
5793 The errors are non-fatal, and are the result of GDB trying to trace stack frames
5794 beyond the last valid frame. It might be possible to prevent this by setting up
5795 a proper "initial" stack frame, if you happen to know what exactly has to
5796 be done, feel free to add this here.
5798 @b{Simple:} In your startup code - push 8 registers of zeros onto the
5799 stack before calling main(). What GDB is doing is ``climbing'' the run
5800 time stack by reading various values on the stack using the standard
5801 call frame for the target. GDB keeps going - until one of 2 things
5802 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
5803 stackframes have been processed. By pushing zeros on the stack, GDB
5806 @b{Debugging Interrupt Service Routines} - In your ISR before you call
5807 your C code, do the same - artifically push some zeros onto the stack,
5808 remember to pop them off when the ISR is done.
5810 @b{Also note:} If you have a multi-threaded operating system, they
5811 often do not @b{in the intrest of saving memory} waste these few
5815 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
5816 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
5818 This warning doesn't indicate any serious problem, as long as you don't want to
5819 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
5820 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
5821 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
5822 independently. With this setup, it's not possible to halt the core right out of
5823 reset, everything else should work fine.
5825 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
5826 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
5827 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
5828 quit with an error message. Is there a stability issue with OpenOCD?
5830 No, this is not a stability issue concerning OpenOCD. Most users have solved
5831 this issue by simply using a self-powered USB hub, which they connect their
5832 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
5833 supply stable enough for the Amontec JTAGkey to be operated.
5835 @b{Laptops running on battery have this problem too...}
5837 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
5838 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
5839 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
5840 What does that mean and what might be the reason for this?
5842 First of all, the reason might be the USB power supply. Try using a self-powered
5843 hub instead of a direct connection to your computer. Secondly, the error code 4
5844 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
5845 chip ran into some sort of error - this points us to a USB problem.
5847 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
5848 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
5849 What does that mean and what might be the reason for this?
5851 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
5852 has closed the connection to OpenOCD. This might be a GDB issue.
5854 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
5855 are described, there is a parameter for specifying the clock frequency
5856 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
5857 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
5858 specified in kilohertz. However, I do have a quartz crystal of a
5859 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
5860 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
5863 No. The clock frequency specified here must be given as an integral number.
5864 However, this clock frequency is used by the In-Application-Programming (IAP)
5865 routines of the LPC2000 family only, which seems to be very tolerant concerning
5866 the given clock frequency, so a slight difference between the specified clock
5867 frequency and the actual clock frequency will not cause any trouble.
5869 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
5871 Well, yes and no. Commands can be given in arbitrary order, yet the
5872 devices listed for the JTAG scan chain must be given in the right
5873 order (jtag newdevice), with the device closest to the TDO-Pin being
5874 listed first. In general, whenever objects of the same type exist
5875 which require an index number, then these objects must be given in the
5876 right order (jtag newtap, targets and flash banks - a target
5877 references a jtag newtap and a flash bank references a target).
5879 You can use the ``scan_chain'' command to verify and display the tap order.
5881 Also, some commands can't execute until after @command{init} has been
5882 processed. Such commands include @command{nand probe} and everything
5883 else that needs to write to controller registers, perhaps for setting
5884 up DRAM and loading it with code.
5886 @anchor{FAQ TAP Order}
5887 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
5890 Yes; whenever you have more than one, you must declare them in
5891 the same order used by the hardware.
5893 Many newer devices have multiple JTAG TAPs. For example: ST
5894 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
5895 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
5896 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
5897 connected to the boundary scan TAP, which then connects to the
5898 Cortex-M3 TAP, which then connects to the TDO pin.
5900 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
5901 (2) The boundary scan TAP. If your board includes an additional JTAG
5902 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
5903 place it before or after the STM32 chip in the chain. For example:
5906 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
5907 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
5908 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
5909 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
5910 @item Xilinx TDO Pin -> OpenOCD TDO (input)
5913 The ``jtag device'' commands would thus be in the order shown below. Note:
5916 @item jtag newtap Xilinx tap -irlen ...
5917 @item jtag newtap stm32 cpu -irlen ...
5918 @item jtag newtap stm32 bs -irlen ...
5919 @item # Create the debug target and say where it is
5920 @item target create stm32.cpu -chain-position stm32.cpu ...
5924 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
5925 log file, I can see these error messages: Error: arm7_9_common.c:561
5926 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
5932 @node Tcl Crash Course
5933 @chapter Tcl Crash Course
5936 Not everyone knows Tcl - this is not intended to be a replacement for
5937 learning Tcl, the intent of this chapter is to give you some idea of
5938 how the Tcl scripts work.
5940 This chapter is written with two audiences in mind. (1) OpenOCD users
5941 who need to understand a bit more of how JIM-Tcl works so they can do
5942 something useful, and (2) those that want to add a new command to
5945 @section Tcl Rule #1
5946 There is a famous joke, it goes like this:
5948 @item Rule #1: The wife is always correct
5949 @item Rule #2: If you think otherwise, See Rule #1
5952 The Tcl equal is this:
5955 @item Rule #1: Everything is a string
5956 @item Rule #2: If you think otherwise, See Rule #1
5959 As in the famous joke, the consequences of Rule #1 are profound. Once
5960 you understand Rule #1, you will understand Tcl.
5962 @section Tcl Rule #1b
5963 There is a second pair of rules.
5965 @item Rule #1: Control flow does not exist. Only commands
5966 @* For example: the classic FOR loop or IF statement is not a control
5967 flow item, they are commands, there is no such thing as control flow
5969 @item Rule #2: If you think otherwise, See Rule #1
5970 @* Actually what happens is this: There are commands that by
5971 convention, act like control flow key words in other languages. One of
5972 those commands is the word ``for'', another command is ``if''.
5975 @section Per Rule #1 - All Results are strings
5976 Every Tcl command results in a string. The word ``result'' is used
5977 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
5978 Everything is a string}
5980 @section Tcl Quoting Operators
5981 In life of a Tcl script, there are two important periods of time, the
5982 difference is subtle.
5985 @item Evaluation Time
5988 The two key items here are how ``quoted things'' work in Tcl. Tcl has
5989 three primary quoting constructs, the [square-brackets] the
5990 @{curly-braces@} and ``double-quotes''
5992 By now you should know $VARIABLES always start with a $DOLLAR
5993 sign. BTW: To set a variable, you actually use the command ``set'', as
5994 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
5995 = 1'' statement, but without the equal sign.
5998 @item @b{[square-brackets]}
5999 @* @b{[square-brackets]} are command substitutions. It operates much
6000 like Unix Shell `back-ticks`. The result of a [square-bracket]
6001 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6002 string}. These two statements are roughly identical:
6006 echo "The Date is: $X"
6009 puts "The Date is: $X"
6011 @item @b{``double-quoted-things''}
6012 @* @b{``double-quoted-things''} are just simply quoted
6013 text. $VARIABLES and [square-brackets] are expanded in place - the
6014 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6018 puts "It is now \"[date]\", $x is in 1 hour"
6020 @item @b{@{Curly-Braces@}}
6021 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6022 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6023 'single-quote' operators in BASH shell scripts, with the added
6024 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6025 nested 3 times@}@}@} NOTE: [date] is a bad example;
6026 at this writing, Jim/OpenOCD does not have a date command.
6029 @section Consequences of Rule 1/2/3/4
6031 The consequences of Rule 1 are profound.
6033 @subsection Tokenisation & Execution.
6035 Of course, whitespace, blank lines and #comment lines are handled in
6038 As a script is parsed, each (multi) line in the script file is
6039 tokenised and according to the quoting rules. After tokenisation, that
6040 line is immedatly executed.
6042 Multi line statements end with one or more ``still-open''
6043 @{curly-braces@} which - eventually - closes a few lines later.
6045 @subsection Command Execution
6047 Remember earlier: There are no ``control flow''
6048 statements in Tcl. Instead there are COMMANDS that simply act like
6049 control flow operators.
6051 Commands are executed like this:
6054 @item Parse the next line into (argc) and (argv[]).
6055 @item Look up (argv[0]) in a table and call its function.
6056 @item Repeat until End Of File.
6059 It sort of works like this:
6062 ReadAndParse( &argc, &argv );
6064 cmdPtr = LookupCommand( argv[0] );
6066 (*cmdPtr->Execute)( argc, argv );
6070 When the command ``proc'' is parsed (which creates a procedure
6071 function) it gets 3 parameters on the command line. @b{1} the name of
6072 the proc (function), @b{2} the list of parameters, and @b{3} the body
6073 of the function. Not the choice of words: LIST and BODY. The PROC
6074 command stores these items in a table somewhere so it can be found by
6077 @subsection The FOR command
6079 The most interesting command to look at is the FOR command. In Tcl,
6080 the FOR command is normally implemented in C. Remember, FOR is a
6081 command just like any other command.
6083 When the ascii text containing the FOR command is parsed, the parser
6084 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6088 @item The ascii text 'for'
6089 @item The start text
6090 @item The test expression
6095 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6096 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6097 Often many of those parameters are in @{curly-braces@} - thus the
6098 variables inside are not expanded or replaced until later.
6100 Remember that every Tcl command looks like the classic ``main( argc,
6101 argv )'' function in C. In JimTCL - they actually look like this:
6105 MyCommand( Jim_Interp *interp,
6107 Jim_Obj * const *argvs );
6110 Real Tcl is nearly identical. Although the newer versions have
6111 introduced a byte-code parser and intepreter, but at the core, it
6112 still operates in the same basic way.
6114 @subsection FOR command implementation
6116 To understand Tcl it is perhaps most helpful to see the FOR
6117 command. Remember, it is a COMMAND not a control flow structure.
6119 In Tcl there are two underlying C helper functions.
6121 Remember Rule #1 - You are a string.
6123 The @b{first} helper parses and executes commands found in an ascii
6124 string. Commands can be seperated by semicolons, or newlines. While
6125 parsing, variables are expanded via the quoting rules.
6127 The @b{second} helper evaluates an ascii string as a numerical
6128 expression and returns a value.
6130 Here is an example of how the @b{FOR} command could be
6131 implemented. The pseudo code below does not show error handling.
6133 void Execute_AsciiString( void *interp, const char *string );
6135 int Evaluate_AsciiExpression( void *interp, const char *string );
6138 MyForCommand( void *interp,
6143 SetResult( interp, "WRONG number of parameters");
6147 // argv[0] = the ascii string just like C
6149 // Execute the start statement.
6150 Execute_AsciiString( interp, argv[1] );
6154 i = Evaluate_AsciiExpression(interp, argv[2]);
6159 Execute_AsciiString( interp, argv[3] );
6161 // Execute the LOOP part
6162 Execute_AsciiString( interp, argv[4] );
6166 SetResult( interp, "" );
6171 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6172 in the same basic way.
6174 @section OpenOCD Tcl Usage
6176 @subsection source and find commands
6177 @b{Where:} In many configuration files
6178 @* Example: @b{ source [find FILENAME] }
6179 @*Remember the parsing rules
6181 @item The FIND command is in square brackets.
6182 @* The FIND command is executed with the parameter FILENAME. It should
6183 find the full path to the named file. The RESULT is a string, which is
6184 substituted on the orginal command line.
6185 @item The command source is executed with the resulting filename.
6186 @* SOURCE reads a file and executes as a script.
6188 @subsection format command
6189 @b{Where:} Generally occurs in numerous places.
6190 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6196 puts [format "The answer: %d" [expr $x * $y]]
6199 @item The SET command creates 2 variables, X and Y.
6200 @item The double [nested] EXPR command performs math
6201 @* The EXPR command produces numerical result as a string.
6203 @item The format command is executed, producing a single string
6204 @* Refer to Rule #1.
6205 @item The PUTS command outputs the text.
6207 @subsection Body or Inlined Text
6208 @b{Where:} Various TARGET scripts.
6211 proc someproc @{@} @{
6212 ... multiple lines of stuff ...
6214 $_TARGETNAME configure -event FOO someproc
6215 #2 Good - no variables
6216 $_TARGETNAME confgure -event foo "this ; that;"
6217 #3 Good Curly Braces
6218 $_TARGETNAME configure -event FOO @{
6221 #4 DANGER DANGER DANGER
6222 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6225 @item The $_TARGETNAME is an OpenOCD variable convention.
6226 @*@b{$_TARGETNAME} represents the last target created, the value changes
6227 each time a new target is created. Remember the parsing rules. When
6228 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6229 the name of the target which happens to be a TARGET (object)
6231 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6232 @*There are 4 examples:
6234 @item The TCLBODY is a simple string that happens to be a proc name
6235 @item The TCLBODY is several simple commands seperated by semicolons
6236 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6237 @item The TCLBODY is a string with variables that get expanded.
6240 In the end, when the target event FOO occurs the TCLBODY is
6241 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6242 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6244 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6245 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6246 and the text is evaluated. In case #4, they are replaced before the
6247 ``Target Object Command'' is executed. This occurs at the same time
6248 $_TARGETNAME is replaced. In case #4 the date will never
6249 change. @{BTW: [date] is a bad example; at this writing,
6250 Jim/OpenOCD does not have a date command@}
6252 @subsection Global Variables
6253 @b{Where:} You might discover this when writing your own procs @* In
6254 simple terms: Inside a PROC, if you need to access a global variable
6255 you must say so. See also ``upvar''. Example:
6257 proc myproc @{ @} @{
6258 set y 0 #Local variable Y
6259 global x #Global variable X
6260 puts [format "X=%d, Y=%d" $x $y]
6263 @section Other Tcl Hacks
6264 @b{Dynamic variable creation}
6266 # Dynamically create a bunch of variables.
6267 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6269 set vn [format "BIT%d" $x]
6273 set $vn [expr (1 << $x)]
6276 @b{Dynamic proc/command creation}
6278 # One "X" function - 5 uart functions.
6279 foreach who @{A B C D E@}
6280 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6284 @node Target Library
6285 @chapter Target Library
6286 @cindex Target Library
6288 OpenOCD comes with a target configuration script library. These scripts can be
6289 used as-is or serve as a starting point.
6291 The target library is published together with the OpenOCD executable and
6292 the path to the target library is in the OpenOCD script search path.
6293 Similarly there are example scripts for configuring the JTAG interface.
6295 The command line below uses the example parport configuration script
6296 that ship with OpenOCD, then configures the str710.cfg target and
6297 finally issues the init and reset commands. The communication speed
6298 is set to 10kHz for reset and 8MHz for post reset.
6301 openocd -f interface/parport.cfg -f target/str710.cfg \
6302 -c "init" -c "reset"
6305 To list the target scripts available:
6308 $ ls /usr/local/lib/openocd/target
6310 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6311 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6312 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6313 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6318 @node OpenOCD Concept Index
6319 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6320 @comment case issue with ``Index.html'' and ``index.html''
6321 @comment Occurs when creating ``--html --no-split'' output
6322 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6323 @unnumbered OpenOCD Concept Index
6327 @node Command and Driver Index
6328 @unnumbered Command and Driver Index