1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (openocd)
27 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (openocd) version @value{VERSION}, @value{UPDATED}.
45 * About:: About Openocd.
46 * Developers:: Openocd developers
47 * Building:: Building Openocd
48 * Running:: Running Openocd
49 * Configuration:: Openocd Configuration.
50 * Commands:: Openocd Commands
51 * Sample Scripts:: Sample Target Scripts
52 * GDB and Openocd:: Using GDB and Openocd
53 * Upgrading:: Deprecated/Removed Commands
54 * FAQ:: Frequently Asked Questions
55 * License:: GNU Free Documentation License
63 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
64 and boundary-scan testing for embedded target devices. The targets are interfaced
65 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
66 connection types in the future.
68 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
69 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
70 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
71 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
73 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
74 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
75 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
81 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
82 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
83 Others interested in improving the state of free and open debug and testing technology
84 are welcome to participate.
86 Other developers have contributed support for additional targets and flashes as well
87 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
91 @cindex building openocd
93 You can download the current SVN version with SVN client of your choice from the
94 following repositories:
96 (@uref{svn://svn.berlios.de/openocd/trunk})
100 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
102 Using the SVN command line client, you could use the following command to fetch the
103 latest version (make sure there is no (non-svn) directory called "openocd" in the
107 svn checkout svn://svn.berlios.de/openocd/trunk openocd
110 Building the OpenOCD requires a recent version of the GNU autotools.
111 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
112 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
113 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
114 paths, resulting in obscure dependency errors (This is an observation I've gathered
115 from the logs of one user - correct me if I'm wrong).
117 You further need the appropriate driver files, if you want to build support for
118 a FTDI FT2232 based interface:
120 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
121 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
122 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
123 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
126 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
127 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
129 In general, the D2XX driver provides superior performance (several times as fast),
130 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
131 a kernel module, only a user space library.
133 To build OpenOCD (on both Linux and Cygwin), use the following commands:
137 Bootstrap generates the configure script, and prepares building on your system.
141 Configure generates the Makefiles used to build OpenOCD.
145 Make builds the OpenOCD, and places the final executable in ./src/.
147 The configure script takes several options, specifying which JTAG interfaces
152 @option{--enable-parport}
154 @option{--enable-parport_ppdev}
156 @option{--enable-parport_giveio}
158 @option{--enable-amtjtagaccel}
160 @option{--enable-ft2232_ftd2xx}
161 @footnote{Using the latest D2XX drivers from FTDI and following their installation
162 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
165 @option{--enable-ft2232_libftdi}
167 @option{--with-ftd2xx=/path/to/d2xx/}
169 @option{--enable-gw16012}
171 @option{--enable-usbprog}
173 @option{--enable-presto_libftdi}
175 @option{--enable-presto_ftd2xx}
178 If you want to access the parallel port using the PPDEV interface you have to specify
179 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
180 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
181 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
183 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
184 absolute path containing no spaces.
186 Linux users should copy the various parts of the D2XX package to the appropriate
187 locations, i.e. /usr/include, /usr/lib.
191 @cindex running openocd
193 @cindex --debug_level
196 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
197 Run with @option{--help} or @option{-h} to view the available command line arguments.
199 It reads its configuration by default from the file openocd.cfg located in the current
200 working directory. This may be overwritten with the @option{-f <configfile>} command line
203 To enable debug output (when reporting problems or working on OpenOCD itself), use
204 the @option{-d} command line switch. This sets the debug_level to "3", outputting
205 the most information, including debug messages. The default setting is "2", outputting
206 only informational messages, warnings and errors. You can also change this setting
207 from within a telnet or gdb session (@option{debug_level <n>}).
209 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
211 Search paths for config/script files can be added to openocd by using
212 the @option{-s <search>} switch.
215 @chapter Configuration
216 @cindex configuration
217 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
218 by default from the file openocd.cfg in the current directory. A different configuration
219 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
221 The configuration file is used to specify on which ports the daemon listens for new
222 connections, the JTAG interface used to connect to the target, the layout of the JTAG
223 chain, the targets that should be debugged, and connected flashes.
225 @section Daemon configuration
228 @item @b{telnet_port} <@var{number}>
230 Port on which to listen for incoming telnet connections
231 @item @b{gdb_port} <@var{number}>
233 First port on which to listen for incoming GDB connections. The GDB port for the
234 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
235 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
237 Configures what openocd will do when gdb detaches from the daeman.
238 Default behaviour is <@var{resume}>
239 @item @b{gdb_memory_map} <@var{enable|disable}>
240 @cindex gdb_memory_map
241 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
242 requested. gdb will then know when to set hardware breakpoints, and program flash
243 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
244 for flash programming to work.
245 Default behaviour is <@var{disable}>
246 @item @b{gdb_flash_program} <@var{enable|disable}>
247 @cindex gdb_flash_program
248 Set to <@var{enable}> so that openocd will program the flash memory when a
249 vFlash packet is received.
250 Default behaviour is <@var{disable}>
251 @item @b{daemon_startup} <@var{mode}>
252 @cindex daemon_startup
253 @option{mode} can either @option{attach} or @option{reset}
254 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
255 if it should just attach to the target.
258 @section JTAG interface configuration
261 @item @b{interface} <@var{name}>
263 Use the interface driver <@var{name}> to connect to the target. Currently supported
267 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
270 @item @b{amt_jtagaccel}
271 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
276 FTDI FT2232 based devices using either the open-source libftdi or the binary only
277 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
278 platform. The libftdi uses libusb, and should be portable to all systems that provide
283 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
287 ASIX PRESTO USB JTAG programmer.
291 usbprog is a freely programmable USB adapter.
295 Gateworks GW16012 JTAG programmer.
300 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
302 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
303 speed. The actual effect of this option depends on the JTAG interface used. Reset
304 speed is used during reset and post reset speed after reset. post reset speed
305 is optional, in which case the reset speed is used.
308 @item wiggler: maximum speed / @var{number}
309 @item ft2232: 6MHz / (@var{number}+1)
310 @item amt jtagaccel: 8 / 2**@var{number}
313 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
314 especially true for synthesized cores (-S).
316 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
318 Same as jtag_speed, except that the speed is specified in maximum kHz. If
319 the device can not support the rate asked for, or can not translate from
320 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
321 is not supported, then an error is reported.
323 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
325 The configuration of the reset signals available on the JTAG interface AND the target.
326 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
327 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
328 @option{srst_only} or @option{trst_and_srst}.
330 [@var{combination}] is an optional value specifying broken reset signal implementations.
331 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
332 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
333 that the system is reset together with the test logic (only hypothetical, I haven't
334 seen hardware with such a bug, and can be worked around).
335 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
336 The default behaviour if no option given is @option{separate}.
338 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
339 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
340 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
341 (default) and @option{srst_push_pull} for the system reset. These values only affect
342 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
344 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
346 Describes the devices that form the JTAG daisy chain, with the first device being
347 the one closest to TDO. The parameters are the length of the instruction register
348 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
349 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
350 The IDCODE instruction will in future be used to query devices for their JTAG
351 identification code. This line is the same for all ARM7 and ARM9 devices.
352 Other devices, like CPLDs, require different parameters. An example configuration
353 line for a Xilinx XC9500 CPLD would look like this:
355 jtag_device 8 0x01 0x0e3 0xfe
357 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
358 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
359 The IDCODE instruction is 0xfe.
361 @item @b{jtag_nsrst_delay} <@var{ms}>
362 @cindex jtag_nsrst_delay
363 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
364 starting new JTAG operations.
365 @item @b{jtag_ntrst_delay} <@var{ms}>
366 @cindex jtag_ntrst_delay
367 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
368 starting new JTAG operations.
370 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
371 or on-chip features) keep a reset line asserted for some time after the external reset
375 @section parport options
378 @item @b{parport_port} <@var{number}>
380 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
381 the @file{/dev/parport} device
383 When using PPDEV to access the parallel port, use the number of the parallel port:
384 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
385 you may encounter a problem.
386 @item @b{parport_cable} <@var{name}>
387 @cindex parport_cable
388 The layout of the parallel port cable used to connect to the target.
389 Currently supported cables are
393 Original Wiggler layout, also supported by several clones, such
394 as the Olimex ARM-JTAG
395 @item @b{old_amt_wiggler}
396 @cindex old_amt_wiggler
397 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
398 version available from the website uses the original Wiggler layout ('@var{wiggler}')
401 Describes the connection of the Amontec Chameleon's CPLD when operated in
402 configuration mode. This is only used to program the Chameleon itself, not
406 Xilinx Parallel cable III.
409 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
410 This is also the layout used by the HollyGates design
411 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
416 @item @b{parport_write_on_exit} <@var{on|off}>
417 @cindex parport_write_on_exit
418 This will configure the parallel driver to write a known value to the parallel
419 interface on exiting openocd
422 @section amt_jtagaccel options
424 @item @b{parport_port} <@var{number}>
426 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
427 @file{/dev/parport} device
429 @section ft2232 options
432 @item @b{ft2232_device_desc} <@var{description}>
433 @cindex ft2232_device_desc
434 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
435 default value is used. This setting is only valid if compiled with FTD2XX support.
436 @item @b{ft2232_layout} <@var{name}>
437 @cindex ft2232_layout
438 The layout of the FT2232 GPIO signals used to control output-enables and reset
439 signals. Valid layouts are
442 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
444 Amontec JTAGkey and JTAGkey-tiny
447 @item @b{olimex-jtag}
450 American Microsystems M5960
451 @item @b{evb_lm3s811}
452 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
453 SRST signals on external connector
457 Hitex STM32 Performance Stick
459 Tin Can Tools Flyswatter
460 @item @b{turtelizer2}
461 egnite Software turtelizer2
466 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
467 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
468 default values are used. This command is not available on Windows.
469 @item @b{ft2232_latency} <@var{ms}>
470 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
471 ft2232_read() fails to return the expected number of bytes. This can be caused by
472 USB communication delays and has proved hard to reproduce and debug. Setting the
473 FT2232 latency timer to a larger value increases delays for short USB packages but it
474 also reduces the risk of timeouts before receiving the expected number of bytes.
475 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
478 @section ep93xx options
479 @cindex ep93xx options
480 Currently, there are no options available for the ep93xx interface.
483 @section Target configuration
486 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
489 Defines a target that should be debugged. Currently supported types are:
503 If you want to use a target board that is not on this list, see Adding a new
506 Endianess may be @option{little} or @option{big}.
508 The reset_mode specifies what should happen to the target when a reset occurs:
512 Immediately request a target halt after reset. This allows targets to be debugged
513 from the very first instruction. This is only possible with targets and JTAG
514 interfaces that correctly implement the reset signals.
517 Similar to @option{reset_halt}, but executes the script file defined to handle the
518 'reset' event for the target. Like @option{reset_halt} this only works with
519 correct reset implementations.
522 Simply let the target run after a reset.
523 @item @b{run_and_halt}
525 Let the target run for some time (default: 1s), and then request halt.
526 @item @b{run_and_init}
528 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
529 to run for some time, then halted, and the @option{reset} event script is executed.
532 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
533 completely independent (like the LPC2000 series), or where the JTAG interface is
534 unavailable for some time during startup (like the STR7 series), you can't use
535 @option{reset_halt} or @option{reset_init}.
537 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
538 @cindex target_script
539 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
541 TODO: describe exact semantic of events
542 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
543 @cindex run_and_halt_time
544 The amount of time the debugger should wait after releasing reset before it asserts
545 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
547 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
548 <@var{backup}|@var{nobackup}>
550 Specifies a working area for the debugger to use. This may be used to speed-up
551 downloads to target memory and flash operations, or to perform otherwise unavailable
552 operations (some coprocessor operations on ARM7/9 systems, for example). The last
553 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
554 a working_area that doesn't need to be backed up, as that slows down operation.
557 @subsection arm7tdmi options
558 @cindex arm7tdmi options
559 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
560 The arm7tdmi target definition requires at least one additional argument, specifying
561 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
562 The optional [@var{variant}] parameter has been removed in recent versions.
563 The correct feature set is determined at runtime.
565 @subsection arm720t options
566 @cindex arm720t options
567 ARM720t options are similar to ARM7TDMI options.
569 @subsection arm9tdmi options
570 @cindex arm9tdmi options
571 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
572 @option{arm920t}, @option{arm922t} and @option{arm940t}.
573 This enables the hardware single-stepping support found on these cores.
575 @subsection arm920t options
576 @cindex arm920t options
577 ARM920t options are similar to ARM9TDMI options.
579 @subsection arm966e options
580 @cindex arm966e options
581 ARM966e options are similar to ARM9TDMI options.
583 @subsection xscale options
584 @cindex xscale options
585 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
586 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
588 @section Flash configuration
589 @cindex Flash configuration
592 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
593 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
595 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
596 and <@var{bus_width}> bytes using the selected flash <driver>.
598 @item @b{flash auto_erase} <@option{on}|@option{off}>
599 @cindex flash auto_erase
600 auto erase flash banks prior to writing. Currently only works when using
601 @option{flash write_image} command. Default is @option{off}.
604 @subsection lpc2000 options
605 @cindex lpc2000 options
607 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
608 <@var{clock}> [@var{calc_checksum}]
609 LPC flashes don't require the chip and bus width to be specified. Additional
610 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
611 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
612 of the target this flash belongs to (first is 0), the frequency at which the core
613 is currently running (in kHz - must be an integral number), and the optional keyword
614 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
617 @subsection cfi options
620 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
622 CFI flashes require the number of the target they're connected to as an additional
623 argument. The CFI driver makes use of a working area (specified for the target)
624 to significantly speed up operation.
626 @var{chip_width} and @var{bus_width} are specified in bytes.
628 @subsection at91sam7 options
629 @cindex at91sam7 options
631 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
632 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
633 reading the chip-id and type.
635 @subsection str7 options
638 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
639 variant can be either STR71x, STR73x or STR75x.
641 @subsection str9 options
644 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
645 The str9 needs the flash controller to be configured prior to Flash programming, eg.
647 str9x flash_config 0 4 2 0 0x80000
649 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
651 @subsection str9 options (str9xpec driver)
653 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
654 Before using the flash commands the turbo mode will need enabling using str9xpec
655 @option{enable_turbo} <@var{num>.}
657 Only use this driver for locking/unlocking the device or configuring the option bytes.
658 Use the standard str9 driver for programming.
660 @subsection stellaris (LM3Sxxx) options
661 @cindex stellaris (LM3Sxxx) options
663 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
664 stellaris flash plugin only require the @var{target#}.
666 @subsection stm32x options
667 @cindex stm32x options
669 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
670 stm32x flash plugin only require the @var{target#}.
676 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
677 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
678 is available from both the telnet interface and a GDB session. To issue commands to the
679 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
680 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
686 @item @b{sleep} <@var{msec}>
688 Wait for n milliseconds before resuming. Useful in connection with script files
689 (@var{script} command and @var{target_script} configuration).
693 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
695 @item @b{debug_level} [@var{n}]
697 Display or adjust debug level to n<0-3>
699 @item @b{log_output} <@var{file}>
701 Redirect logging to <file> (default: stderr)
703 @item @b{script} <@var{file}>
705 Execute commands from <file>
709 @subsection Target state handling
711 @item @b{poll} [@option{on}|@option{off}]
713 Poll the target for its current state. If the target is in debug mode, architecture
714 specific information about the current state are printed. An optional parameter
715 allows continuous polling to be enabled and disabled.
717 @item @b{halt} [@option{ms}]
719 Send a halt request to the target and waits for it to halt for [@option{ms}].
720 Default [@option{ms}] is 5 seconds if no arg given.
721 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
722 will stop openocd from waiting.
724 @item @b{wait_halt} [@option{ms}]
726 Wait for the target to enter debug mode. Optional [@option{ms}] is
727 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
730 @item @b{resume} [@var{address}]
732 Resume the target at its current code position, or at an optional address.
733 Openocd will wait 5 seconds for the target to resume.
735 @item @b{step} [@var{address}]
737 Single-step the target at its current code position, or at an optional address.
739 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
740 |@option{run_and_init}]
742 Do a hard-reset. The optional parameter specifies what should happen after the reset.
743 This optional parameter overwrites the setting specified in the configuration file,
744 making the new behaviour the default for the @option{reset} command.
751 Immediately halt the target (works only with certain configurations).
754 Immediately halt the target, and execute the reset script (works only with certain
756 @item @b{run_and_halt}
757 @cindex reset run_and_halt
758 Let the target run for a certain amount of time, then request a halt.
759 @item @b{run_and_init}
760 @cindex reset run_and_init
761 Let the target run for a certain amount of time, then request a halt. Execute the
762 reset script once the target entered debug mode.
766 @subsection Memory access commands
767 These commands allow accesses of a specific size to the memory system:
769 @item @b{mdw} <@var{addr}> [@var{count}]
772 @item @b{mdh} <@var{addr}> [@var{count}]
774 display memory half-words
775 @item @b{mdb} <@var{addr}> [@var{count}]
778 @item @b{mww} <@var{addr}> <@var{value}>
781 @item @b{mwh} <@var{addr}> <@var{value}>
783 write memory half-word
784 @item @b{mwb} <@var{addr}> <@var{value}>
788 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
790 Load image <@var{file}> to target memory at <@var{address}>
791 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
793 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
794 (binary) <@var{file}>.
795 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
797 Verify <@var{file}> to target memory starting at <@var{address}>.
798 This will first attempt using a crc checksum, if this fails it will try a binary compare.
801 @subsection Flash commands
802 @cindex Flash commands
804 @item @b{flash banks}
806 List configured flash banks
807 @item @b{flash info} <@var{num}>
809 Print info about flash bank <@option{num}>
810 @item @b{flash probe} <@var{num}>
812 Identify the flash, or validate the parameters of the configured flash. Operation
813 depends on the flash type.
814 @item @b{flash erase_check} <@var{num}>
815 @cindex flash erase_check
816 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
817 updates the erase state information displayed by @option{flash info}. That means you have
818 to issue an @option{erase_check} command after erasing or programming the device to get
820 @item @b{flash protect_check} <@var{num}>
821 @cindex flash protect_check
822 Check protection state of sectors in flash bank <num>.
823 @option{flash erase_sector} using the same syntax.
824 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
825 @cindex flash erase_sector
826 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
827 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
828 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
830 @item @b{flash erase_address} <@var{address}> <@var{length}>
831 @cindex flash erase_address
832 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
833 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
834 @cindex flash write_bank
835 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
836 <@option{offset}> bytes from the beginning of the bank.
837 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
838 @cindex flash write_image
839 Write the image <@var{file}> to the current target's flash bank(s). A relocation
840 [@var{offset}] can be specified and the file [@var{type}] can be specified
841 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
842 (ELF file) or @option{s19} (Motorola s19).
843 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
844 @cindex flash protect
845 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
846 <@var{last}> of @option{flash bank} <@var{num}>.
847 @item @b{flash auto_erase} <@var{on}|@var{off}>
848 @cindex flash auto_erase
849 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
850 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
854 @section Target Specific Commands
855 @cindex Target Specific Commands
857 @subsection AT91SAM7 specific commands
858 @cindex AT91SAM7 specific commands
859 The flash configuration is deduced from the chip identification register. The flash
860 controller handles erases automatically on a page (128/265 byte) basis so erase is
861 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
862 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
863 that can be erased separatly.Only an EraseAll command is supported by the controller
864 for each flash plane and this is called with
866 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
867 bulk erase flash planes first_plane to last_plane.
868 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
869 @cindex at91sam7 gpnvm
870 set or clear a gpnvm bit for the processor
873 @subsection STR9 specific commands
874 @cindex STR9 specific commands
875 These are flash specific commands when using the str9xpec driver.
877 @item @b{str9xpec enable_turbo} <@var{num}>
878 @cindex str9xpec enable_turbo
879 enable turbo mode, simply this will remove the str9 from the chain and talk
880 directly to the embedded flash controller.
881 @item @b{str9xpec disable_turbo} <@var{num}>
882 @cindex str9xpec disable_turbo
883 restore the str9 into jtag chain.
884 @item @b{str9xpec lock} <@var{num}>
885 @cindex str9xpec lock
886 lock str9 device. The str9 will only respond to an unlock command that will
888 @item @b{str9xpec unlock} <@var{num}>
889 @cindex str9xpec unlock
891 @item @b{str9xpec options_read} <@var{num}>
892 @cindex str9xpec options_read
893 read str9 option bytes.
894 @item @b{str9xpec options_write} <@var{num}>
895 @cindex str9xpec options_write
896 write str9 option bytes.
899 @subsection STR9 configuration
900 @cindex STR9 configuration
902 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
903 <@var{BBADR}> <@var{NBBADR}>
904 @cindex str9x flash_config
905 Configure str9 flash controller.
907 eg. str9x flash_config 0 4 2 0 0x80000
909 BBSR - Boot Bank Size register
910 NBBSR - Non Boot Bank Size register
911 BBADR - Boot Bank Start Address register
912 NBBADR - Boot Bank Start Address register
916 @subsection STR9 option byte configuration
917 @cindex STR9 option byte configuration
919 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
920 @cindex str9xpec options_cmap
921 configure str9 boot bank.
922 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
923 @cindex str9xpec options_lvdthd
924 configure str9 lvd threshold.
925 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
926 @cindex str9xpec options_lvdsel
927 configure str9 lvd source.
928 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
929 @cindex str9xpec options_lvdwarn
930 configure str9 lvd reset warning source.
933 @subsection STM32x specific commands
934 @cindex STM32x specific commands
936 These are flash specific commands when using the stm32x driver.
938 @item @b{stm32x lock} <@var{num}>
941 @item @b{stm32x unlock} <@var{num}>
942 @cindex stm32x unlock
944 @item @b{stm32x options_read} <@var{num}>
945 @cindex stm32x options_read
946 read stm32 option bytes.
947 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
948 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
949 @cindex stm32x options_write
950 write stm32 option bytes.
951 @item @b{stm32x mass_erase} <@var{num}>
952 @cindex stm32x mass_erase
953 mass erase flash memory.
957 @section Architecture Specific Commands
958 @cindex Architecture Specific Commands
960 @subsection ARMV4/5 specific commands
961 @cindex ARMV4/5 specific commands
963 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
964 or Intel XScale (XScale isn't supported yet).
966 @item @b{armv4_5 reg}
968 Display a list of all banked core registers, fetching the current value from every
969 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
971 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
972 @cindex armv4_5 core_mode
973 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
974 The target is resumed in the currently set @option{core_mode}.
977 @subsection ARM7/9 specific commands
978 @cindex ARM7/9 specific commands
980 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
981 ARM920t or ARM926EJ-S.
983 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
984 @cindex arm7_9 sw_bkpts
985 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
986 one of the watchpoint registers to implement software breakpoints. Disabling
987 SW Bkpts frees that register again.
988 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
989 @cindex arm7_9 force_hw_bkpts
990 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
991 breakpoints are turned into hardware breakpoints.
992 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
994 Enable use of the DBGRQ bit to force entry into debug mode. This should be
995 safe for all but ARM7TDMI--S cores (like Philips LPC).
996 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
997 @cindex arm7_9 fast_memory_access
998 Allow the OpenOCD to read and write memory without checking completion of
999 the operation. This provides a huge speed increase, especially with USB JTAG
1000 cables (FT2232), but might be unsafe if used with targets running at a very low
1001 speed, like the 32kHz startup clock of an AT91RM9200.
1002 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1003 @cindex arm7_9 dcc_downloads
1004 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1005 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1006 unsafe, especially with targets running at a very low speed. This command was introduced
1007 with OpenOCD rev. 60.
1010 @subsection ARM720T specific commands
1011 @cindex ARM720T specific commands
1014 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1015 @cindex arm720t cp15
1016 display/modify cp15 register <@option{num}> [@option{value}].
1017 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1018 @cindex arm720t md<bhw>_phys
1019 Display memory at physical address addr.
1020 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1021 @cindex arm720t mw<bhw>_phys
1022 Write memory at physical address addr.
1023 @item @b{arm720t virt2phys} <@var{va}>
1024 @cindex arm720t virt2phys
1025 Translate a virtual address to a physical address.
1028 @subsection ARM9TDMI specific commands
1029 @cindex ARM9TDMI specific commands
1032 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1033 @cindex arm9tdmi vector_catch
1034 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1035 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1036 @option{irq} @option{fiq}.
1038 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1041 @subsection ARM966E specific commands
1042 @cindex ARM966E specific commands
1045 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1046 @cindex arm966e cp15
1047 display/modify cp15 register <@option{num}> [@option{value}].
1050 @subsection ARM920T specific commands
1051 @cindex ARM920T specific commands
1054 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1055 @cindex arm920t cp15
1056 display/modify cp15 register <@option{num}> [@option{value}].
1057 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1058 @cindex arm920t cp15i
1059 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1060 @item @b{arm920t cache_info}
1061 @cindex arm920t cache_info
1062 Print information about the caches found. This allows you to see if your target
1063 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1064 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1065 @cindex arm920t md<bhw>_phys
1066 Display memory at physical address addr.
1067 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1068 @cindex arm920t mw<bhw>_phys
1069 Write memory at physical address addr.
1070 @item @b{arm920t read_cache} <@var{filename}>
1071 @cindex arm920t read_cache
1072 Dump the content of ICache and DCache to a file.
1073 @item @b{arm920t read_mmu} <@var{filename}>
1074 @cindex arm920t read_mmu
1075 Dump the content of the ITLB and DTLB to a file.
1076 @item @b{arm920t virt2phys} <@var{va}>
1077 @cindex arm920t virt2phys
1078 Translate a virtual address to a physical address.
1081 @subsection ARM926EJS specific commands
1082 @cindex ARM926EJS specific commands
1085 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1086 @cindex arm926ejs cp15
1087 display/modify cp15 register <@option{num}> [@option{value}].
1088 @item @b{arm926ejs cache_info}
1089 @cindex arm926ejs cache_info
1090 Print information about the caches found.
1091 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1092 @cindex arm926ejs md<bhw>_phys
1093 Display memory at physical address addr.
1094 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1095 @cindex arm926ejs mw<bhw>_phys
1096 Write memory at physical address addr.
1097 @item @b{arm926ejs virt2phys} <@var{va}>
1098 @cindex arm926ejs virt2phys
1099 Translate a virtual address to a physical address.
1103 @section Debug commands
1104 @cindex Debug commands
1105 The following commands give direct access to the core, and are most likely
1106 only useful while debugging the OpenOCD.
1108 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1109 @cindex arm7_9 write_xpsr
1110 Immediately write either the current program status register (CPSR) or the saved
1111 program status register (SPSR), without changing the register cache (as displayed
1112 by the @option{reg} and @option{armv4_5 reg} commands).
1113 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1114 <@var{0=cpsr},@var{1=spsr}>
1115 @cindex arm7_9 write_xpsr_im8
1116 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1117 operation (similar to @option{write_xpsr}).
1118 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1119 @cindex arm7_9 write_core_reg
1120 Write a core register, without changing the register cache (as displayed by the
1121 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1122 encoding of the [M4:M0] bits of the PSR.
1126 @section JTAG commands
1127 @cindex JTAG commands
1129 @item @b{scan_chain}
1131 Print current scan chain configuration.
1132 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1135 @item @b{endstate} <@var{tap_state}>
1137 Finish JTAG operations in <@var{tap_state}>.
1138 @item @b{runtest} <@var{num_cycles}>
1140 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1141 @item @b{statemove} [@var{tap_state}]
1143 Move to current endstate or [@var{tap_state}]
1144 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1146 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1147 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1149 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1150 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1151 @cindex verify_ircapture
1152 Verify value captured during Capture-IR. Default is enabled.
1153 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1155 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1156 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1158 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1162 @section Target Requests
1163 @cindex Target Requests
1164 Openocd can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1165 See libdcc in the contrib dir for more details.
1167 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1168 @cindex target_request debugmsgs
1169 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1172 @node Sample Scripts
1173 @chapter Sample Scripts
1176 This page will collect some script examples for different CPUs.
1178 The configuration script can be divided in the following section:
1180 @item daemon configuration
1182 @item jtag scan chain
1183 @item target configuration
1184 @item flash configuration
1187 Detailed information about each section can be found at OpenOCD configuration
1189 @section OMAP5912 Flash Debug
1190 @cindex OMAP5912 Flash Debug
1191 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1192 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1193 - (@uref{http://www.spectrumdigital.com}).
1194 @subsection Openocd config
1196 #daemon configuration
1203 parport_cable wiggler
1206 #use combined on interfaces or targets that can't set TRST/SRST separately
1207 reset_config trst_and_srst
1210 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1211 jtag_device 38 0x0 0x0 0x0
1212 jtag_device 4 0x1 0x0 0xe
1213 jtag_device 8 0x0 0x0 0x0
1215 #target configuration
1216 daemon_startup reset
1218 #target <type> <endianness> <reset mode> <chainpos> <variant>
1219 target arm926ejs little run_and_init 1 arm926ejs
1220 target_script 0 reset omap5912_osk.init
1221 run_and_halt_time 0 30
1223 # omap5912 lcd frame buffer as working area
1224 working_area 0 0x20000000 0x3e800 nobackup
1226 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1227 flash bank cfi 0x00000000 0x1000000 2 2 0
1230 @subsection Openocd init
1242 mww 0xfffec808 0x000000f5
1243 mww 0xfffec808 0x000000a0
1245 mww 0xfffeb048 0x0000aaaa
1247 mww 0xfffeb048 0x00005555
1256 @section STR71x Script
1257 @cindex STR71x Script
1258 The following script was used with an Amontec JTAGkey and a STR710 / STR711 CPU:
1260 #daemon configuration
1266 ft2232_device_desc "Amontec JTAGkey A"
1267 ft2232_layout jtagkey
1268 ft2232_vid_pid 0x0403 0xcff8
1271 #use combined on interfaces or targets that can't set TRST/SRST separately
1272 reset_config trst_and_srst srst_pulls_trst
1275 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1276 jtag_device 4 0x1 0xf 0xe
1278 #target configuration
1279 daemon_startup reset
1281 #target <type> <startup mode>
1282 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1283 target arm7tdmi little run_and_halt 0 arm7tdmi
1284 run_and_halt_time 0 30
1286 working_area 0 0x2000C000 0x4000 nobackup
1288 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1289 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1292 @section STR750 Script
1293 @cindex STR750 Script
1294 The following script was used with an Amontec JTAGkey and a STR750 CPU:
1296 #daemon configuration
1302 ft2232_device_desc "Amontec JTAGkey A"
1303 ft2232_layout jtagkey
1304 ft2232_vid_pid 0x0403 0xcff8
1307 #use combined on interfaces or targets that can't set TRST/SRST separately
1308 #reset_config trst_and_srst srst_pulls_trst
1309 reset_config trst_and_srst srst_pulls_trst
1312 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1313 jtag_device 4 0x1 0xf 0xe
1315 #jtag nTRST and nSRST delay
1316 jtag_nsrst_delay 500
1317 jtag_ntrst_delay 500
1319 #target configuration
1320 daemon_startup reset
1322 #target <type> <startup mode>
1323 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1324 target arm7tdmi little run_and_halt 0 arm7tdmi
1325 run_and_halt_time 0 30
1327 working_area 0 0x40000000 0x4000 nobackup
1329 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1330 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1333 @section STR912 Script
1334 @cindex STR912 Script
1335 The following script was used with an Amontec JTAGkey and a STR912 CPU:
1337 #daemon configuration
1343 ft2232_device_desc "Amontec JTAGkey A"
1344 ft2232_layout jtagkey
1347 #use combined on interfaces or targets that can't set TRST/SRST separately
1348 reset_config trst_and_srst
1351 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1352 jtag_device 8 0x1 0x1 0xfe
1353 jtag_device 4 0x1 0xf 0xe
1354 jtag_device 5 0x1 0x1 0x1e
1356 #target configuration
1357 daemon_startup reset
1359 #target <type> <startup mode>
1360 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1361 target arm966e little reset_halt 1 arm966e
1362 run_and_halt_time 0 30
1364 working_area 0 0x50000000 16384 nobackup
1366 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1367 flash bank str9x 0x00000000 0x00080000 0 0 0
1370 @section STR912 comstick
1371 @cindex STR912 comstick Script
1372 The following script was used with a Hitex STR9 Comstick:
1374 #daemon configuration
1380 ft2232_device_desc "STR9-comStick A"
1381 ft2232_layout comstick
1384 jtag_nsrst_delay 100
1385 jtag_ntrst_delay 100
1387 #use combined on interfaces or targets that can't set TRST/SRST separately
1388 reset_config trst_and_srst
1391 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1392 jtag_device 8 0x1 0x1 0xfe
1393 jtag_device 4 0x1 0xf 0xe
1394 jtag_device 5 0x1 0x1 0x1e
1396 #target configuration
1397 daemon_startup reset
1399 #target <type> <startup mode>
1400 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1401 target arm966e little reset_halt 1 arm966e
1402 run_and_halt_time 0 30
1404 working_area 0 0x50000000 16384 nobackup
1406 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1407 flash bank str9x 0x00000000 0x00080000 0 0 0
1410 @section STM32x Script
1411 @cindex STM32x Script
1412 The following script was used with an Amontec JTAGkey and a STM32x CPU:
1414 #daemon configuration
1420 ft2232_device_desc "Amontec JTAGkey A"
1421 ft2232_layout jtagkey
1424 jtag_nsrst_delay 100
1425 jtag_ntrst_delay 100
1427 #use combined on interfaces or targets that can't set TRST/SRST separately
1428 reset_config trst_and_srst
1431 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1432 jtag_device 4 0x1 0xf 0xe
1433 jtag_device 5 0x1 0x1 0x1e
1435 #target configuration
1436 daemon_startup reset
1438 #target <type> <startup mode>
1439 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1440 target cortex_m3 little run_and_halt 0
1441 run_and_halt_time 0 30
1443 working_area 0 0x20000000 16384 nobackup
1445 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1446 flash bank stm32x 0x08000000 0x00020000 0 0 0
1449 @section STM32x Performance Stick
1450 @cindex STM32x Performance Stick Script
1451 The following script was used with the Hitex STM32 Performance Stick
1453 #daemon configuration
1459 ft2232_device_desc "STM32-PerformanceStick A"
1460 ft2232_layout stm32stick
1463 jtag_nsrst_delay 100
1464 jtag_ntrst_delay 100
1466 #use combined on interfaces or targets that can't set TRST/SRST separately
1467 reset_config trst_and_srst
1470 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1471 jtag_device 4 0x1 0xf 0xe
1472 jtag_device 5 0x1 0x1 0x1e
1473 jtag_device 4 0x1 0xf 0xe
1475 #target configuration
1476 daemon_startup reset
1478 #target <type> <startup mode>
1479 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1480 target cortex_m3 little run_and_halt 0
1481 run_and_halt_time 0 30
1483 working_area 0 0x20000000 16384 nobackup
1485 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1486 flash bank stm32x 0x08000000 0x00020000 0 0 0
1489 @section LPC2129 Script
1490 @cindex LPC2129 Script
1491 The following script was used with an wiggler PP and a LPC-2129 CPU:
1493 #daemon configuration
1500 parport_cable wiggler
1503 #use combined on interfaces or targets that can't set TRST/SRST separately
1504 reset_config trst_and_srst srst_pulls_trst
1507 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1508 jtag_device 4 0x1 0xf 0xe
1510 #target configuration
1511 daemon_startup reset
1513 #target <type> <startup mode>
1514 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1515 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1516 run_and_halt_time 0 30
1518 working_area 0 0x40000000 0x4000 nobackup
1520 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1521 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1524 @section LPC2148 Script
1525 @cindex LPC2148 Script
1526 The following script was used with an Amontec JTAGkey and a LPC2148 CPU:
1528 #daemon configuration
1534 ft2232_device_desc "Amontec JTAGkey A"
1535 ft2232_layout jtagkey
1536 ft2232_vid_pid 0x0403 0xcff8
1539 #use combined on interfaces or targets that can't set TRST/SRST separately
1540 reset_config trst_and_srst srst_pulls_trst
1543 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1544 jtag_device 4 0x1 0xf 0xe
1546 #target configuration
1547 daemon_startup reset
1549 #target <type> <startup mode>
1550 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1551 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1552 run_and_halt_time 0 30
1554 working_area 0 0x40000000 0x8000 nobackup
1556 #flash configuration
1557 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1560 @section LPC2294 Script
1561 @cindex LPC2294 Script
1562 The following script was used with an Amontec JTAGkey and a LPC2294 CPU:
1564 #daemon configuration
1570 ft2232_device_desc "Amontec JTAGkey A"
1571 ft2232_layout jtagkey
1572 ft2232_vid_pid 0x0403 0xcff8
1575 #use combined on interfaces or targets that can't set TRST/SRST separately
1576 reset_config trst_and_srst srst_pulls_trst
1579 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1580 jtag_device 4 0x1 0xf 0xe
1582 #target configuration
1583 daemon_startup reset
1585 #target <type> <startup mode>
1586 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1587 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1588 run_and_halt_time 0 30
1590 working_area 0 0x40000000 0x4000 nobackup
1592 #flash configuration
1593 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1596 @section AT91R40008 Script
1597 @cindex AT91R40008 Script
1598 The following script was used with an Amontec JTAGkey and a AT91R40008 CPU:
1600 #daemon configuration
1606 ft2232_device_desc "Amontec JTAGkey A"
1607 ft2232_layout jtagkey
1608 ft2232_vid_pid 0x0403 0xcff8
1610 jtag_nsrst_delay 200
1611 jtag_ntrst_delay 200
1613 #use combined on interfaces or targets that can't set TRST/SRST separately
1614 reset_config srst_only srst_pulls_trst
1617 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1618 jtag_device 4 0x1 0xf 0xe
1620 #target configuration
1621 daemon_startup reset
1623 #target <type> <startup mode>
1624 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1625 target arm7tdmi little run_and_halt 0 arm7tdmi
1626 run_and_halt_time 0 30
1629 @section AT91SAM7s Script
1630 @cindex AT91SAM7s Script
1631 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 CPU:
1633 #daemon configuration
1639 ft2232_device_desc "Olimex OpenOCD JTAG A"
1640 ft2232_layout olimex-jtag
1641 ft2232_vid_pid 0x15BA 0x0003
1643 jtag_nsrst_delay 200
1644 jtag_ntrst_delay 200
1646 #use combined on interfaces or targets that can't set TRST/SRST separately
1647 reset_config srst_only srst_pulls_trst
1650 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1651 jtag_device 4 0x1 0xf 0xe
1653 #target configuration
1654 daemon_startup reset
1656 #target <type> <startup mode>
1657 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1658 target arm7tdmi little run_and_halt 0 arm7tdmi
1659 run_and_halt_time 0 30
1661 # flash-options AT91
1662 working_area 0 0x00200000 0x4000 nobackup
1663 flash bank at91sam7 0 0 0 0 0
1666 # erase command (telnet-interface) for complete flash:
1667 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1668 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1669 # set/clear NVM-Bits:
1670 # at91sam7 gpnvm <num> <bit> <set|clear>
1671 # disable locking from SAM-BA:
1672 # flash protect 0 0 1 off
1675 @section XSCALE IXP42x Script
1676 @cindex XSCALE IXP42x Script
1677 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x CPU:
1679 #daemon configuration
1685 ft2232_device_desc "Amontec JTAGkey A"
1686 ft2232_layout jtagkey
1687 ft2232_vid_pid 0x0403 0xcff8
1689 jtag_nsrst_delay 200
1690 jtag_ntrst_delay 200
1692 #use combined on interfaces or targets that can't set TRST/SRST separately
1693 reset_config srst_only srst_pulls_trst
1696 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1697 jtag_device 7 0x1 0x7f 0x7e
1699 #target configuration
1700 daemon_startup reset
1702 #target <type> <startup mode>
1703 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1704 target xscale big run_and_halt 0 IXP42x
1705 run_and_halt_time 0 30
1708 @section Cirrus Logic EP9301 Script
1709 @cindex Cirrus Logic EP9301 Script
1710 The following script was used with FT2232 based JTAG interfaces and a
1711 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1713 #daemon configuration
1721 #ft2232_device_desc "Olimex OpenOCD JTAG"
1722 #ft2232_layout olimex-jtag
1723 #ft2232_vid_pid 0x15ba 0x0003
1725 #Amontec JTAGkey (and JTAGkey-Tiny)
1726 #Serial is only necessary if more than one JTAGkey is connected
1727 ft2232_device_desc "Amontec JTAGkey A"
1728 #ft2232_serial AMTJKV31
1729 #ft2232_serial T1P3S2W8
1730 ft2232_layout jtagkey
1731 ft2232_vid_pid 0x0403 0xcff8
1733 #wiggler/parallel port interface
1736 #parport_cable wiggler
1739 reset_config trst_and_srst
1742 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1743 jtag_device 4 0x1 0xf 0xe
1745 jtag_nsrst_delay 100
1746 jtag_ntrst_delay 100
1748 #target configuration
1749 daemon_startup attach
1751 #target <type> <endianess> <reset mode>
1752 target arm920t little reset_halt 0
1753 working_area 0 0x80014000 0x1000 backup
1755 #flash configuration
1756 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1757 flash bank cfi 0x60000000 0x1000000 2 2 0
1760 @section Hilscher netX 100 / 500 Script
1761 @cindex Hilscher netX 100 / 500 Script
1762 The following script was used with an Amontec JTAGkey and a Hilscher
1765 #daemon configuration
1771 ft2232_device_desc "Amontec JTAGkey A"
1772 ft2232_layout jtagkey
1773 ft2232_vid_pid 0x0403 0xcff8
1776 #use combined on interfaces or targets that can't set TRST/SRST separately
1777 reset_config trst_and_srst
1780 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1781 jtag_device 4 0x1 0xf 0xe
1783 jtag_nsrst_delay 100
1784 jtag_ntrst_delay 100
1786 #target configuration
1787 daemon_startup reset
1789 #target <type> <endianness> <startup mode> <chainpos> <variant>
1790 target arm926ejs little run_and_halt 0 arm926ejs
1791 run_and_halt_time 0 500
1794 @section Marvell/Intel PXA270 Script
1795 @cindex Marvell/Intel PXA270 Script
1797 # config for Intel PXA270
1798 # not, as of 2007-06-22, openocd only works with the
1799 # libftd2xx library from ftdi. libftdi does not work.
1805 ft2232_layout olimex-jtag
1806 ft2232_vid_pid 0x15BA 0x0003
1807 ft2232_device_desc "Olimex OpenOCD JTAG"
1809 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1810 # the rest of the needed delays are built into the openocd program
1811 jtag_nsrst_delay 260
1812 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1813 # the rest of the needed delays are built into the openocd program
1816 #use combined on interfaces or targets that can't set TRST/SRST separately
1817 reset_config trst_and_srst separate
1820 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1821 jtag_device 7 0x1 0x7f 0x7e
1823 #target configuration
1824 daemon_startup reset
1826 target xscale little reset_halt 0 pxa27x
1828 # maps to PXA internal RAM. If you are using a PXA255
1829 # you must initialize SDRAM or leave this option off
1830 working_area 0 0x5c000000 0x10000 nobackup
1832 run_and_halt_time 0 30
1834 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1835 # works for P30 flash
1836 flash bank cfi 0x00000000 0x1000000 2 4 0
1839 @node GDB and Openocd
1840 @chapter GDB and Openocd
1841 @cindex GDB and Openocd
1842 Openocd complies with the remote gdbserver protocol, and as such can be used
1843 to debug remote targets.
1845 @section Connecting to gdb
1846 @cindex Connecting to gdb
1847 A connection is typically started as follows:
1849 target remote localhost:3333
1851 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1853 To see a list of available openocd commands type @option{monitor help} on the
1856 Openocd supports the gdb @option{qSupported} packet, this enables information
1857 to be sent by the gdb server (openocd) to gdb. Typical information includes
1858 packet size and device memory map.
1860 Previous versions of openocd required the following gdb options to increase
1861 the packet size and speed up gdb communication.
1863 set remote memory-write-packet-size 1024
1864 set remote memory-write-packet-size fixed
1865 set remote memory-read-packet-size 1024
1866 set remote memory-read-packet-size fixed
1868 This is now handled in the @option{qSupported} PacketSize.
1870 @section Programming using gdb
1871 @cindex Programming using gdb
1873 By default the target memory map is not sent to gdb, this can be enabled by
1874 the following openocd config option:
1876 gdb_memory_map enable
1878 For this to function correctly a valid flash config must also be configured
1879 in openocd. For speed also configure a valid working area.
1881 Informing gdb of the memory map of the target will enable gdb to protect any
1882 flash area of the target and use hardware breakpoints by default. This means
1883 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1886 To view the configured memory map in gdb, use the gdb command @option{info mem}
1887 All other unasigned addresses within gdb are treated as RAM.
1889 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1890 this can be changed to the old behaviour by using the following gdb command.
1892 set mem inaccessible-by-default off
1895 If @option{gdb_flash_program enable} is also used, gdb will be able to
1896 program any flash memory using the vFlash interface.
1898 gdb will look at the target memory map when a load command is given, if any
1899 areas to be programmed lie within the target flash area the vFlash packets
1902 Incase the target needs configuring before gdb programming, a script can be executed.
1904 target_script 0 gdb_program_config config.script
1907 To verify any flash programming the gdb command @option{compare-sections}
1911 @chapter Deprecated/Removed Commands
1912 @cindex Deprecated/Removed Commands
1913 Certain openocd commands have been deprecated/removed during the various revisions.
1916 @item @b{load_binary}
1918 use @option{load_image} command with same args
1919 @item @b{dump_binary}
1921 use @option{dump_image} command with same args
1922 @item @b{flash erase}
1924 use @option{flash erase_sector} command with same args
1925 @item @b{flash write}
1927 use @option{flash write_bank} command with same args
1928 @item @b{flash write_binary}
1929 @cindex flash write_binary
1930 use @option{flash write_bank} command with same args
1931 @item @b{arm7_9 fast_writes}
1932 @cindex arm7_9 fast_writes
1933 use @option{arm7_9 fast_memory_access} command with same args
1940 @item OpenOCD complains about a missing cygwin1.dll.
1942 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1943 claims to come with all the necessary dlls. When using Cygwin, try launching
1944 the OpenOCD from the Cygwin shell.
1946 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1947 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1948 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1950 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1951 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1952 software breakpoints consume one of the two available hardware breakpoints,
1953 and are therefore disabled by default. If your code is running from RAM, you
1954 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1955 your code resides in Flash, you can't use software breakpoints, but you can force
1956 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1958 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1959 and works sometimes fine.
1961 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1962 clock at the time you're programming the flash. If you've specified the crystal's
1963 frequency, make sure the PLL is disabled, if you've specified the full core speed
1964 (e.g. 60MHz), make sure the PLL is enabled.
1966 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1967 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1968 out while waiting for end of scan, rtck was disabled".
1970 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1971 settings in your PC BIOS (ECP, EPP, and different versions of those).
1973 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1974 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1975 memory read caused data abort".
1977 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1978 beyond the last valid frame. It might be possible to prevent this by setting up
1979 a proper "initial" stack frame, if you happen to know what exactly has to
1980 be done, feel free to add this here.
1982 @item I get the following message in the OpenOCD console (or log file):
1983 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1985 This warning doesn't indicate any serious problem, as long as you don't want to
1986 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1987 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1988 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1989 independently. With this setup, it's not possible to halt the core right out of
1990 reset, everything else should work fine.
1992 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1993 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1994 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1995 quit with an error message. Is there a stability issue with OpenOCD?
1997 No, this is not a stability issue concerning OpenOCD. Most users have solved
1998 this issue by simply using a self-powered USB hub, which they connect their
1999 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
2000 supply stable enough for the Amontec JTAGkey to be operated.
2002 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
2003 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
2004 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
2005 What does that mean and what might be the reason for this?
2007 First of all, the reason might be the USB power supply. Try using a self-powered
2008 hub instead of a direct connection to your computer. Secondly, the error code 4
2009 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
2010 chip ran into some sort of error - this points us to a USB problem.
2012 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
2013 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
2014 What does that mean and what might be the reason for this?
2016 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
2017 has closed the connection to OpenOCD. This might be a GDB issue.
2019 @item In the configuration file in the section where flash device configurations
2020 are described, there is a parameter for specifying the clock frequency for
2021 LPC2000 internal flash devices (e.g.
2022 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
2023 which must be specified in kilohertz. However, I do have a quartz crystal of a
2024 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
2025 Is it possible to specify real numbers for the clock frequency?
2027 No. The clock frequency specified here must be given as an integral number.
2028 However, this clock frequency is used by the In-Application-Programming (IAP)
2029 routines of the LPC2000 family only, which seems to be very tolerant concerning
2030 the given clock frequency, so a slight difference between the specified clock
2031 frequency and the actual clock frequency will not cause any trouble.
2033 @item Do I have to keep a specific order for the commands in the configuration file?
2035 Well, yes and no. Commands can be given in arbitrary order, yet the devices
2036 listed for the JTAG scan chain must be given in the right order (jtag_device),
2037 with the device closest to the TDO-Pin being listed first. In general,
2038 whenever objects of the same type exist which require an index number, then
2039 these objects must be given in the right order (jtag_devices, targets and flash
2040 banks - a target references a jtag_device and a flash bank references a target).
2042 @item Sometimes my debugging session terminates with an error. When I look into the
2043 log file, I can see these error messages: Error: arm7_9_common.c:561
2044 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP