1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are three things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
257 @item @b{Connection} Printer Ports - Does your computer have one?
258 @item @b{Connection} Is that long printer bit-bang cable practical?
259 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
262 @section Stand alone Systems
264 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
265 dongle, but a standalone box. The ZY1000 has the advantage that it does
266 not require any drivers installed on the developer PC. It also has
267 a built in web interface. It supports RTCK/RCLK or adaptive clocking
268 and has a built in relay to power cycle targets remotely.
270 @section USB FT2232 Based
272 There are many USB JTAG dongles on the market, many of them are based
273 on a chip from ``Future Technology Devices International'' (FTDI)
274 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
275 See: @url{http://www.ftdichip.com} for more information.
276 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
277 chips are starting to become available in JTAG adapters.
281 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
283 @* See: @url{http://www.amontec.com/jtagkey.shtml}
285 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
287 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
289 @* See: @url{http://www.signalyzer.com}
290 @item @b{evb_lm3s811}
291 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
292 @item @b{luminary_icdi}
293 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
294 @item @b{olimex-jtag}
295 @* See: @url{http://www.olimex.com}
297 @* See: @url{http://www.tincantools.com}
298 @item @b{turtelizer2}
300 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
301 @url{http://www.ethernut.de}
303 @* Link: @url{http://www.hitex.com/index.php?id=383}
305 @* Link @url{http://www.hitex.com/stm32-stick}
306 @item @b{axm0432_jtag}
307 @* Axiom AXM-0432 Link @url{http://www.axman.com}
309 @* Link @url{http://www.hitex.com/index.php?id=cortino}
312 @section USB JLINK based
313 There are several OEM versions of the Segger @b{JLINK} adapter. It is
314 an example of a micro controller based JTAG adapter, it uses an
315 AT91SAM764 internally.
318 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
319 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
320 @item @b{SEGGER JLINK}
321 @* Link: @url{http://www.segger.com/jlink.html}
323 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
326 @section USB RLINK based
327 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
330 @item @b{Raisonance RLink}
331 @* Link: @url{http://www.raisonance.com/products/RLink.php}
332 @item @b{STM32 Primer}
333 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
334 @item @b{STM32 Primer2}
335 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
341 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
343 @item @b{USB - Presto}
344 @* Link: @url{http://tools.asix.net/prg_presto.htm}
346 @item @b{Versaloon-Link}
347 @* Link: @url{http://www.simonqian.com/en/Versaloon}
349 @item @b{ARM-JTAG-EW}
350 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
353 @section IBM PC Parallel Printer Port Based
355 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
356 and the MacGraigor Wiggler. There are many clones and variations of
361 @item @b{Wiggler} - There are many clones of this.
362 @* Link: @url{http://www.macraigor.com/wiggler.htm}
364 @item @b{DLC5} - From XILINX - There are many clones of this
365 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
366 produced, PDF schematics are easily found and it is easy to make.
368 @item @b{Amontec - JTAG Accelerator}
369 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
372 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
375 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
376 Improved parallel-port wiggler-style JTAG adapter}
378 @item @b{Wiggler_ntrst_inverted}
379 @* Yet another variation - See the source code, src/jtag/parport.c
381 @item @b{old_amt_wiggler}
382 @* Unknown - probably not on the market today
385 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
388 @* Link: @url{http://www.amontec.com/chameleon.shtml}
394 @* ispDownload from Lattice Semiconductor
395 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
398 @* From ST Microsystems;
399 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
400 FlashLINK JTAG programing cable for PSD and uPSD}
408 @* An EP93xx based Linux machine using the GPIO pins directly.
411 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
416 @chapter About JIM-Tcl
420 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
421 This programming language provides a simple and extensible
424 All commands presented in this Guide are extensions to JIM-Tcl.
425 You can use them as simple commands, without needing to learn
426 much of anything about Tcl.
427 Alternatively, can write Tcl programs with them.
429 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
432 @item @b{JIM vs. Tcl}
433 @* JIM-TCL is a stripped down version of the well known Tcl language,
434 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
435 fewer features. JIM-Tcl is a single .C file and a single .H file and
436 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
437 4.2 MB .zip file containing 1540 files.
439 @item @b{Missing Features}
440 @* Our practice has been: Add/clone the real Tcl feature if/when
441 needed. We welcome JIM Tcl improvements, not bloat.
444 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
445 command interpreter today is a mixture of (newer)
446 JIM-Tcl commands, and (older) the orginal command interpreter.
449 @* At the OpenOCD telnet command line (or via the GDB mon command) one
450 can type a Tcl for() loop, set variables, etc.
451 Some of the commands documented in this guide are implemented
452 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
454 @item @b{Historical Note}
455 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
457 @item @b{Need a crash course in Tcl?}
458 @*@xref{Tcl Crash Course}.
463 @cindex command line options
465 @cindex directory search
467 The @option{--help} option shows:
471 --help | -h display this help
472 --version | -v display OpenOCD version
473 --file | -f use configuration file <name>
474 --search | -s dir to search for config files and scripts
475 --debug | -d set debug level <0-3>
476 --log_output | -l redirect log output to file <name>
477 --command | -c run <command>
478 --pipe | -p use pipes when talking to gdb
481 By default OpenOCD reads the file configuration file ``openocd.cfg''
482 in the current directory. To specify a different (or multiple)
483 configuration file, you can use the ``-f'' option. For example:
486 openocd -f config1.cfg -f config2.cfg -f config3.cfg
489 Once started, OpenOCD runs as a daemon, waiting for connections from
490 clients (Telnet, GDB, Other).
492 If you are having problems, you can enable internal debug messages via
495 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
496 @option{-c} command line switch.
498 To enable debug output (when reporting problems or working on OpenOCD
499 itself), use the @option{-d} command line switch. This sets the
500 @option{debug_level} to "3", outputting the most information,
501 including debug messages. The default setting is "2", outputting only
502 informational messages, warnings and errors. You can also change this
503 setting from within a telnet or gdb session using @command{debug_level
504 <n>} (@pxref{debug_level}).
506 You can redirect all output from the daemon to a file using the
507 @option{-l <logfile>} switch.
509 Search paths for config/script files can be added to OpenOCD by using
510 the @option{-s <search>} switch. The current directory and the OpenOCD
511 target library is in the search path by default.
513 For details on the @option{-p} option. @xref{Connecting to GDB}.
515 Note! OpenOCD will launch the GDB & telnet server even if it can not
516 establish a connection with the target. In general, it is possible for
517 the JTAG controller to be unresponsive until the target is set up
518 correctly via e.g. GDB monitor commands in a GDB init script.
520 @node OpenOCD Project Setup
521 @chapter OpenOCD Project Setup
523 To use OpenOCD with your development projects, you need to do more than
524 just connecting the JTAG adapter hardware (dongle) to your development board
525 and then starting the OpenOCD server.
526 You also need to configure that server so that it knows
527 about that adapter and board, and helps your work.
529 @section Hooking up the JTAG Adapter
531 Today's most common case is a dongle with a JTAG cable on one side
532 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
533 and a USB cable on the other.
534 Instead of USB, some cables use Ethernet;
535 older ones may use a PC parallel port, or even a serial port.
538 @item @emph{Start with power to your target board turned off},
539 and nothing connected to your JTAG adapter.
540 If you're particularly paranoid, unplug power to the board.
541 It's important to have the ground signal properly set up,
542 unless you are using a JTAG adapter which provides
543 galvanic isolation between the target board and the
546 @item @emph{Be sure it's the right kind of JTAG connector.}
547 If your dongle has a 20-pin ARM connector, you need some kind
548 of adapter (or octopus, see below) to hook it up to
549 boards using 14-pin or 10-pin connectors ... or to 20-pin
550 connectors which don't use ARM's pinout.
552 In the same vein, make sure the voltage levels are compatible.
553 Not all JTAG adapters have the level shifters needed to work
554 with 1.2 Volt boards.
556 @item @emph{Be certain the cable is properly oriented} or you might
557 damage your board. In most cases there are only two possible
558 ways to connect the cable.
559 Connect the JTAG cable from your adapter to the board.
560 Be sure it's firmly connected.
562 In the best case, the connector is keyed to physically
563 prevent you from inserting it wrong.
564 This is most often done using a slot on the board's male connector
565 housing, which must match a key on the JTAG cable's female connector.
566 If there's no housing, then you must look carefully and
567 make sure pin 1 on the cable hooks up to pin 1 on the board.
568 Ribbon cables are frequently all grey except for a wire on one
569 edge, which is red. The red wire is pin 1.
571 Sometimes dongles provide cables where one end is an ``octopus'' of
572 color coded single-wire connectors, instead of a connector block.
573 These are great when converting from one JTAG pinout to another,
574 but are tedious to set up.
575 Use these with connector pinout diagrams to help you match up the
576 adapter signals to the right board pins.
578 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
579 A USB, parallel, or serial port connector will go to the host which
580 you are using to run OpenOCD.
581 For Ethernet, consult the documentation and your network administrator.
583 For USB based JTAG adapters you have an easy sanity check at this point:
584 does the host operating system see the JTAG adapter?
586 @item @emph{Connect the adapter's power supply, if needed.}
587 This step is primarily for non-USB adapters,
588 but sometimes USB adapters need extra power.
590 @item @emph{Power up the target board.}
591 Unless you just let the magic smoke escape,
592 you're now ready to set up the OpenOCD server
593 so you can use JTAG to work with that board.
597 Talk with the OpenOCD server using
598 telnet (@code{telnet localhost 4444} on many systems) or GDB.
599 @xref{GDB and OpenOCD}.
601 @section Project Directory
603 There are many ways you can configure OpenOCD and start it up.
605 A simple way to organize them all involves keeping a
606 single directory for your work with a given board.
607 When you start OpenOCD from that directory,
608 it searches there first for configuration files, scripts,
609 and for code you upload to the target board.
610 It is also the natural place to write files,
611 such as log files and data you download from the board.
613 @section Configuration Basics
615 There are two basic ways of configuring OpenOCD, and
616 a variety of ways you can mix them.
617 Think of the difference as just being how you start the server:
620 @item Many @option{-f file} or @option{-c command} options on the command line
621 @item No options, but a @dfn{user config file}
622 in the current directory named @file{openocd.cfg}
625 Here is an example @file{openocd.cfg} file for a setup
626 using a Signalyzer FT2232-based JTAG adapter to talk to
627 a board with an Atmel AT91SAM7X256 microcontroller:
630 source [find interface/signalyzer.cfg]
632 # GDB can also flash my flash!
633 gdb_memory_map enable
634 gdb_flash_program enable
636 source [find target/sam7x256.cfg]
639 Here is the command line equivalent of that configuration:
642 openocd -f interface/signalyzer.cfg \
643 -c "gdb_memory_map enable" \
644 -c "gdb_flash_program enable" \
645 -f target/sam7x256.cfg
648 You could wrap such long command lines in shell scripts,
649 each supporting a different development task.
650 One might re-flash the board with a specific firmware version.
651 Another might set up a particular debugging or run-time environment.
653 Here we will focus on the simpler solution: one user config
654 file, including basic configuration plus any TCL procedures
655 to simplify your work.
657 @section User Config Files
658 @cindex config file, user
659 @cindex user config file
660 @cindex config file, overview
662 A user configuration file ties together all the parts of a project
664 One of the following will match your situation best:
667 @item Ideally almost everything comes from configuration files
668 provided by someone else.
669 For example, OpenOCD distributes a @file{scripts} directory
670 (probably in @file{/usr/share/openocd/scripts} on Linux).
671 Board and tool vendors can provide these too, as can individual
672 user sites; the @option{-s} command line option lets you say
673 where to find these files. (@xref{Running}.)
674 The AT91SAM7X256 example above works this way.
676 Three main types of non-user configuration file each have their
677 own subdirectory in the @file{scripts} directory:
680 @item @b{interface} -- one for each kind of JTAG adapter/dongle
681 @item @b{board} -- one for each different board
682 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
685 Best case: include just two files, and they handle everything else.
686 The first is an interface config file.
687 The second is board-specific, and it sets up the JTAG TAPs and
688 their GDB targets (by deferring to some @file{target.cfg} file),
689 declares all flash memory, and leaves you nothing to do except
693 source [find interface/olimex-jtag-tiny.cfg]
694 source [find board/csb337.cfg]
697 Boards with a single microcontroller often won't need more
698 than the target config file, as in the AT91SAM7X256 example.
699 That's because there is no external memory (flash, DDR RAM), and
700 the board differences are encapsulated by application code.
702 @item You can often reuse some standard config files but
703 need to write a few new ones, probably a @file{board.cfg} file.
704 You will be using commands described later in this User's Guide,
705 and working with the guidelines in the next chapter.
707 For example, there may be configuration files for your JTAG adapter
708 and target chip, but you need a new board-specific config file
709 giving access to your particular flash chips.
710 Or you might need to write another target chip configuration file
711 for a new chip built around the Cortex M3 core.
714 When you write new configuration files, please submit
715 them for inclusion in the next OpenOCD release.
716 For example, a @file{board/newboard.cfg} file will help the
717 next users of that board, and a @file{target/newcpu.cfg}
718 will help support users of any board using that chip.
722 You may may need to write some C code.
723 It may be as simple as a supporting a new ft2232 or parport
724 based dongle; a bit more involved, like a NAND or NOR flash
725 controller driver; or a big piece of work like supporting
726 a new chip architecture.
729 Reuse the existing config files when you can.
730 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
731 You may find a board configuration that's a good example to follow.
733 When you write config files, separate the reusable parts
734 (things every user of that interface, chip, or board needs)
735 from ones specific to your environment and debugging approach.
739 For example, a @code{gdb-attach} event handler that invokes
740 the @command{reset init} command will interfere with debugging
741 early boot code, which performs some of the same actions
742 that the @code{reset-init} event handler does.
745 Likewise, the @command{arm9tdmi vector_catch} command (or
747 its siblings @command{xscale vector_catch}
748 and @command{cortex_m3 vector_catch}) can be a timesaver
749 during some debug sessions, but don't make everyone use that either.
750 Keep those kinds of debugging aids in your user config file,
751 along with messaging and tracing setup.
752 (@xref{Software Debug Messages and Tracing}.)
755 You might need to override some defaults.
756 For example, you might need to move, shrink, or back up the target's
757 work area if your application needs much SRAM.
760 TCP/IP port configuration is another example of something which
761 is environment-specific, and should only appear in
762 a user config file. @xref{TCP/IP Ports}.
765 @section Project-Specific Utilities
767 A few project-specific utility
768 routines may well speed up your work.
769 Write them, and keep them in your project's user config file.
771 For example, if you are making a boot loader work on a
772 board, it's nice to be able to debug the ``after it's
773 loaded to RAM'' parts separately from the finicky early
774 code which sets up the DDR RAM controller and clocks.
775 A script like this one, or a more GDB-aware sibling,
779 proc ramboot @{ @} @{
780 # Reset, running the target's "reset-init" scripts
781 # to initialize clocks and the DDR RAM controller.
782 # Leave the CPU halted.
785 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
786 load_image u-boot.bin 0x20000000
793 Then once that code is working you will need to make it
794 boot from NOR flash; a different utility would help.
795 Alternatively, some developers write to flash using GDB.
796 (You might use a similar script if you're working with a flash
797 based microcontroller application instead of a boot loader.)
800 proc newboot @{ @} @{
801 # Reset, leaving the CPU halted. The "reset-init" event
802 # proc gives faster access to the CPU and to NOR flash;
803 # "reset halt" would be slower.
806 # Write standard version of U-Boot into the first two
807 # sectors of NOR flash ... the standard version should
808 # do the same lowlevel init as "reset-init".
809 flash protect 0 0 1 off
810 flash erase_sector 0 0 1
811 flash write_bank 0 u-boot.bin 0x0
812 flash protect 0 0 1 on
814 # Reboot from scratch using that new boot loader.
819 You may need more complicated utility procedures when booting
821 That often involves an extra bootloader stage,
822 running from on-chip SRAM to perform DDR RAM setup so it can load
823 the main bootloader code (which won't fit into that SRAM).
825 Other helper scripts might be used to write production system images,
826 involving considerably more than just a three stage bootloader.
829 @node Config File Guidelines
830 @chapter Config File Guidelines
832 This chapter is aimed at any user who needs to write a config file,
833 including developers and integrators of OpenOCD and any user who
834 needs to get a new board working smoothly.
835 It provides guidelines for creating those files.
837 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
840 @item @file{interface} ...
841 think JTAG Dongle. Files that configure JTAG adapters go here.
842 @item @file{board} ...
843 think Circuit Board, PWA, PCB, they go by many names. Board files
844 contain initialization items that are specific to a board. For
845 example, the SDRAM initialization sequence for the board, or the type
846 of external flash and what address it uses. Any initialization
847 sequence to enable that external flash or SDRAM should be found in the
848 board file. Boards may also contain multiple targets: two CPUs; or
849 a CPU and an FPGA or CPLD.
850 @item @file{target} ...
851 think chip. The ``target'' directory represents the JTAG TAPs
853 which OpenOCD should control, not a board. Two common types of targets
854 are ARM chips and FPGA or CPLD chips.
855 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
856 the target config file defines all of them.
859 The @file{openocd.cfg} user config
860 file may override features in any of the above files by
861 setting variables before sourcing the target file, or by adding
862 commands specific to their situation.
864 @section Interface Config Files
867 should be able to source one of these files with a command like this:
870 source [find interface/FOOBAR.cfg]
873 A preconfigured interface file should exist for every interface in use
874 today, that said, perhaps some interfaces have only been used by the
875 sole developer who created it.
877 A separate chapter gives information about how to set these up.
878 @xref{Interface - Dongle Configuration}.
879 Read the OpenOCD source code if you have a new kind of hardware interface
880 and need to provide a driver for it.
882 @section Board Config Files
883 @cindex config file, board
884 @cindex board config file
887 should be able to source one of these files with a command like this:
890 source [find board/FOOBAR.cfg]
893 The point of a board config file is to package everything
894 about a given board that user config files need to know.
895 In summary the board files should contain (if present)
898 @item One or more @command{source [target/...cfg]} statements
899 @item NOR flash configuration (@pxref{NOR Configuration})
900 @item NAND flash configuration (@pxref{NAND Configuration})
901 @item Target @code{reset} handlers for SDRAM and I/O configuration
902 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
903 @item All things that are not ``inside a chip''
906 Generic things inside target chips belong in target config files,
907 not board config files. So for example a @code{reset-init} event
908 handler should know board-specific oscillator and PLL parameters,
909 which it passes to target-specific utility code.
911 The most complex task of a board config file is creating such a
912 @code{reset-init} event handler.
913 Define those handlers last, after you verify the rest of the board
916 @subsection Communication Between Config files
918 In addition to target-specific utility code, another way that
919 board and target config files communicate is by following a
920 convention on how to use certain variables.
922 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
923 Thus the rule we follow in OpenOCD is this: Variables that begin with
924 a leading underscore are temporary in nature, and can be modified and
925 used at will within a target configuration file.
927 Complex board config files can do the things like this,
928 for a board with three chips:
931 # Chip #1: PXA270 for network side, big endian
934 source [find target/pxa270.cfg]
935 # on return: _TARGETNAME = network.cpu
936 # other commands can refer to the "network.cpu" target.
937 $_TARGETNAME configure .... events for this CPU..
939 # Chip #2: PXA270 for video side, little endian
942 source [find target/pxa270.cfg]
943 # on return: _TARGETNAME = video.cpu
944 # other commands can refer to the "video.cpu" target.
945 $_TARGETNAME configure .... events for this CPU..
947 # Chip #3: Xilinx FPGA for glue logic
950 source [find target/spartan3.cfg]
953 That example is oversimplified because it doesn't show any flash memory,
954 or the @code{reset-init} event handlers to initialize external DRAM
955 or (assuming it needs it) load a configuration into the FPGA.
956 Such features are usually needed for low-level work with many boards,
957 where ``low level'' implies that the board initialization software may
958 not be working. (That's a common reason to need JTAG tools. Another
959 is to enable working with microcontroller-based systems, which often
960 have no debugging support except a JTAG connector.)
962 Target config files may also export utility functions to board and user
963 config files. Such functions should use name prefixes, to help avoid
966 Board files could also accept input variables from user config files.
967 For example, there might be a @code{J4_JUMPER} setting used to identify
968 what kind of flash memory a development board is using, or how to set
969 up other clocks and peripherals.
971 @subsection Variable Naming Convention
972 @cindex variable names
974 Most boards have only one instance of a chip.
975 However, it should be easy to create a board with more than
976 one such chip (as shown above).
977 Accordingly, we encourage these conventions for naming
978 variables associated with different @file{target.cfg} files,
979 to promote consistency and
980 so that board files can override target defaults.
982 Inputs to target config files include:
985 @item @code{CHIPNAME} ...
986 This gives a name to the overall chip, and is used as part of
987 tap identifier dotted names.
988 While the default is normally provided by the chip manufacturer,
989 board files may need to distinguish between instances of a chip.
990 @item @code{ENDIAN} ...
991 By default @option{little} - although chips may hard-wire @option{big}.
992 Chips that can't change endianness don't need to use this variable.
993 @item @code{CPUTAPID} ...
994 When OpenOCD examines the JTAG chain, it can be told verify the
995 chips against the JTAG IDCODE register.
996 The target file will hold one or more defaults, but sometimes the
997 chip in a board will use a different ID (perhaps a newer revision).
1000 Outputs from target config files include:
1003 @item @code{_TARGETNAME} ...
1004 By convention, this variable is created by the target configuration
1005 script. The board configuration file may make use of this variable to
1006 configure things like a ``reset init'' script, or other things
1007 specific to that board and that target.
1008 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1009 @code{_TARGETNAME1}, ... etc.
1012 @subsection The reset-init Event Handler
1013 @cindex event, reset-init
1014 @cindex reset-init handler
1016 Board config files run in the OpenOCD configuration stage;
1017 they can't use TAPs or targets, since they haven't been
1019 This means you can't write memory or access chip registers;
1020 you can't even verify that a flash chip is present.
1021 That's done later in event handlers, of which the target @code{reset-init}
1022 handler is one of the most important.
1024 Except on microcontrollers, the basic job of @code{reset-init} event
1025 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1026 Microcontrollers rarely use boot loaders; they run right out of their
1027 on-chip flash and SRAM memory. But they may want to use one of these
1028 handlers too, if just for developer convenience.
1031 Because this is so very board-specific, and chip-specific, no examples
1033 Instead, look at the board config files distributed with OpenOCD.
1034 If you have a boot loader, its source code may also be useful.
1037 Some of this code could probably be shared between different boards.
1038 For example, setting up a DRAM controller often doesn't differ by
1039 much except the bus width (16 bits or 32?) and memory timings, so a
1040 reusable TCL procedure loaded by the @file{target.cfg} file might take
1041 those as parameters.
1042 Similarly with oscillator, PLL, and clock setup;
1043 and disabling the watchdog.
1044 Structure the code cleanly, and provide comments to help
1045 the next developer doing such work.
1046 (@emph{You might be that next person} trying to reuse init code!)
1048 The last thing normally done in a @code{reset-init} handler is probing
1049 whatever flash memory was configured. For most chips that needs to be
1050 done while the associated target is halted, either because JTAG memory
1051 access uses the CPU or to prevent conflicting CPU access.
1053 @subsection JTAG Clock Rate
1055 Before your @code{reset-init} handler has set up
1056 the PLLs and clocking, you may need to use
1057 a low JTAG clock rate; then you'd increase it later.
1058 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1059 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1060 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1061 Consult chip documentation to determine the peak JTAG clock rate,
1062 which might be less than that.
1065 On most ARMs, JTAG clock detection is coupled to the core clock, so
1066 software using a @option{wait for interrupt} operation blocks JTAG access.
1067 Adaptive clocking provides a partial workaround, but a more complete
1068 solution just avoids using that instruction with JTAG debuggers.
1071 If the board supports adaptive clocking, use the @command{jtag_rclk}
1072 command, in case your board is used with JTAG adapter which
1073 also supports it. Otherwise use @command{jtag_khz}.
1074 Set the slow rate at the beginning of the reset sequence,
1075 and the faster rate as soon as the clocks are at full speed.
1077 @section Target Config Files
1078 @cindex config file, target
1079 @cindex target config file
1081 Board config files communicate with target config files using
1082 naming conventions as described above, and may source one or
1083 more target config files like this:
1086 source [find target/FOOBAR.cfg]
1089 The point of a target config file is to package everything
1090 about a given chip that board config files need to know.
1091 In summary the target files should contain
1095 @item Add TAPs to the scan chain
1096 @item Add CPU targets (includes GDB support)
1097 @item CPU/Chip/CPU-Core specific features
1101 As a rule of thumb, a target file sets up only one chip.
1102 For a microcontroller, that will often include a single TAP,
1103 which is a CPU needing a GDB target, and its on-chip flash.
1105 More complex chips may include multiple TAPs, and the target
1106 config file may need to define them all before OpenOCD
1107 can talk to the chip.
1108 For example, some phone chips have JTAG scan chains that include
1109 an ARM core for operating system use, a DSP,
1110 another ARM core embedded in an image processing engine,
1111 and other processing engines.
1113 @subsection Default Value Boiler Plate Code
1115 All target configuration files should start with code like this,
1116 letting board config files express environment-specific
1117 differences in how things should be set up.
1120 # Boards may override chip names, perhaps based on role,
1121 # but the default should match what the vendor uses
1122 if @{ [info exists CHIPNAME] @} @{
1123 set _CHIPNAME $CHIPNAME
1125 set _CHIPNAME sam7x256
1128 # ONLY use ENDIAN with targets that can change it.
1129 if @{ [info exists ENDIAN] @} @{
1135 # TAP identifiers may change as chips mature, for example with
1136 # new revision fields (the "3" here). Pick a good default; you
1137 # can pass several such identifiers to the "jtag newtap" command.
1138 if @{ [info exists CPUTAPID ] @} @{
1139 set _CPUTAPID $CPUTAPID
1141 set _CPUTAPID 0x3f0f0f0f
1144 @c but 0x3f0f0f0f is for an str73x part ...
1146 @emph{Remember:} Board config files may include multiple target
1147 config files, or the same target file multiple times
1148 (changing at least @code{CHIPNAME}).
1150 Likewise, the target configuration file should define
1151 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1152 use it later on when defining debug targets:
1155 set _TARGETNAME $_CHIPNAME.cpu
1156 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1159 @subsection Adding TAPs to the Scan Chain
1160 After the ``defaults'' are set up,
1161 add the TAPs on each chip to the JTAG scan chain.
1162 @xref{TAP Declaration}, and the naming convention
1165 In the simplest case the chip has only one TAP,
1166 probably for a CPU or FPGA.
1167 The config file for the Atmel AT91SAM7X256
1168 looks (in part) like this:
1171 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1172 -expected-id $_CPUTAPID
1175 A board with two such at91sam7 chips would be able
1176 to source such a config file twice, with different
1177 values for @code{CHIPNAME}, so
1178 it adds a different TAP each time.
1180 If there are one or more nonzero @option{-expected-id} values,
1181 OpenOCD attempts to verify the actual tap id against those values.
1182 It will issue error messages if there is mismatch, which
1183 can help to pinpoint problems in OpenOCD configurations.
1186 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1187 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1188 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1189 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1190 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1193 There are more complex examples too, with chips that have
1194 multiple TAPs. Ones worth looking at include:
1197 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1198 plus a JRC to enable them
1199 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1200 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1201 is not currently used)
1204 @subsection Add CPU targets
1206 After adding a TAP for a CPU, you should set it up so that
1207 GDB and other commands can use it.
1208 @xref{CPU Configuration}.
1209 For the at91sam7 example above, the command can look like this;
1210 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1211 to little endian, and this chip doesn't support changing that.
1214 set _TARGETNAME $_CHIPNAME.cpu
1215 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1218 Work areas are small RAM areas associated with CPU targets.
1219 They are used by OpenOCD to speed up downloads,
1220 and to download small snippets of code to program flash chips.
1221 If the chip includes a form of ``on-chip-ram'' - and many do - define
1222 a work area if you can.
1223 Again using the at91sam7 as an example, this can look like:
1226 $_TARGETNAME configure -work-area-phys 0x00200000 \
1227 -work-area-size 0x4000 -work-area-backup 0
1230 @subsection Chip Reset Setup
1232 As a rule, you should put the @command{reset_config} command
1233 into the board file. Most things you think you know about a
1234 chip can be tweaked by the board.
1236 Some chips have specific ways the TRST and SRST signals are
1237 managed. In the unusual case that these are @emph{chip specific}
1238 and can never be changed by board wiring, they could go here.
1240 Some chips need special attention during reset handling if
1241 they're going to be used with JTAG.
1242 An example might be needing to send some commands right
1243 after the target's TAP has been reset, providing a
1244 @code{reset-deassert-post} event handler that writes a chip
1245 register to report that JTAG debugging is being done.
1247 @subsection ARM Core Specific Hacks
1249 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1250 special high speed download features - enable it.
1252 If present, the MMU, the MPU and the CACHE should be disabled.
1254 Some ARM cores are equipped with trace support, which permits
1255 examination of the instruction and data bus activity. Trace
1256 activity is controlled through an ``Embedded Trace Module'' (ETM)
1257 on one of the core's scan chains. The ETM emits voluminous data
1258 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1259 If you are using an external trace port,
1260 configure it in your board config file.
1261 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1262 configure it in your target config file.
1265 etm config $_TARGETNAME 16 normal full etb
1266 etb config $_TARGETNAME $_CHIPNAME.etb
1269 @subsection Internal Flash Configuration
1271 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1273 @b{Never ever} in the ``target configuration file'' define any type of
1274 flash that is external to the chip. (For example a BOOT flash on
1275 Chip Select 0.) Such flash information goes in a board file - not
1276 the TARGET (chip) file.
1280 @item at91sam7x256 - has 256K flash YES enable it.
1281 @item str912 - has flash internal YES enable it.
1282 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1283 @item pxa270 - again - CS0 flash - it goes in the board file.
1286 @node Daemon Configuration
1287 @chapter Daemon Configuration
1288 @cindex initialization
1289 The commands here are commonly found in the openocd.cfg file and are
1290 used to specify what TCP/IP ports are used, and how GDB should be
1293 @section Configuration Stage
1294 @cindex configuration stage
1295 @cindex config command
1297 When the OpenOCD server process starts up, it enters a
1298 @emph{configuration stage} which is the only time that
1299 certain commands, @emph{configuration commands}, may be issued.
1300 In this manual, the definition of a configuration command is
1301 presented as a @emph{Config Command}, not as a @emph{Command}
1302 which may be issued interactively.
1304 Those configuration commands include declaration of TAPs,
1306 the interface used for JTAG communication,
1307 and other basic setup.
1308 The server must leave the configuration stage before it
1309 may access or activate TAPs.
1310 After it leaves this stage, configuration commands may no
1313 @deffn {Config Command} init
1314 This command terminates the configuration stage and
1315 enters the normal command mode. This can be useful to add commands to
1316 the startup scripts and commands such as resetting the target,
1317 programming flash, etc. To reset the CPU upon startup, add "init" and
1318 "reset" at the end of the config script or at the end of the OpenOCD
1319 command line using the @option{-c} command line switch.
1321 If this command does not appear in any startup/configuration file
1322 OpenOCD executes the command for you after processing all
1323 configuration files and/or command line options.
1325 @b{NOTE:} This command normally occurs at or near the end of your
1326 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1327 targets ready. For example: If your openocd.cfg file needs to
1328 read/write memory on your target, @command{init} must occur before
1329 the memory read/write commands. This includes @command{nand probe}.
1332 @anchor{TCP/IP Ports}
1333 @section TCP/IP Ports
1338 The OpenOCD server accepts remote commands in several syntaxes.
1339 Each syntax uses a different TCP/IP port, which you may specify
1340 only during configuration (before those ports are opened).
1342 For reasons including security, you may wish to prevent remote
1343 access using one or more of these ports.
1344 In such cases, just specify the relevant port number as zero.
1345 If you disable all access through TCP/IP, you will need to
1346 use the command line @option{-pipe} option.
1348 @deffn {Command} gdb_port (number)
1350 Specify or query the first port used for incoming GDB connections.
1351 The GDB port for the
1352 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1353 When not specified during the configuration stage,
1354 the port @var{number} defaults to 3333.
1355 When specified as zero, this port is not activated.
1358 @deffn {Command} tcl_port (number)
1359 Specify or query the port used for a simplified RPC
1360 connection that can be used by clients to issue TCL commands and get the
1361 output from the Tcl engine.
1362 Intended as a machine interface.
1363 When not specified during the configuration stage,
1364 the port @var{number} defaults to 6666.
1365 When specified as zero, this port is not activated.
1368 @deffn {Command} telnet_port (number)
1369 Specify or query the
1370 port on which to listen for incoming telnet connections.
1371 This port is intended for interaction with one human through TCL commands.
1372 When not specified during the configuration stage,
1373 the port @var{number} defaults to 4444.
1374 When specified as zero, this port is not activated.
1377 @anchor{GDB Configuration}
1378 @section GDB Configuration
1380 @cindex GDB configuration
1381 You can reconfigure some GDB behaviors if needed.
1382 The ones listed here are static and global.
1383 @xref{Target Configuration}, about configuring individual targets.
1384 @xref{Target Events}, about configuring target-specific event handling.
1386 @anchor{gdb_breakpoint_override}
1387 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1388 Force breakpoint type for gdb @command{break} commands.
1389 This option supports GDB GUIs which don't
1390 distinguish hard versus soft breakpoints, if the default OpenOCD and
1391 GDB behaviour is not sufficient. GDB normally uses hardware
1392 breakpoints if the memory map has been set up for flash regions.
1395 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1396 Configures what OpenOCD will do when GDB detaches from the daemon.
1397 Default behaviour is @option{resume}.
1400 @anchor{gdb_flash_program}
1401 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1402 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1403 vFlash packet is received.
1404 The default behaviour is @option{enable}.
1407 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1408 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1409 requested. GDB will then know when to set hardware breakpoints, and program flash
1410 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1411 for flash programming to work.
1412 Default behaviour is @option{enable}.
1413 @xref{gdb_flash_program}.
1416 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1417 Specifies whether data aborts cause an error to be reported
1418 by GDB memory read packets.
1419 The default behaviour is @option{disable};
1420 use @option{enable} see these errors reported.
1423 @anchor{Event Polling}
1424 @section Event Polling
1426 Hardware debuggers are parts of asynchronous systems,
1427 where significant events can happen at any time.
1428 The OpenOCD server needs to detect some of these events,
1429 so it can report them to through TCL command line
1432 Examples of such events include:
1435 @item One of the targets can stop running ... maybe it triggers
1436 a code breakpoint or data watchpoint, or halts itself.
1437 @item Messages may be sent over ``debug message'' channels ... many
1438 targets support such messages sent over JTAG,
1439 for receipt by the person debugging or tools.
1440 @item Loss of power ... some adapters can detect these events.
1441 @item Resets not issued through JTAG ... such reset sources
1442 can include button presses or other system hardware, sometimes
1443 including the target itself (perhaps through a watchdog).
1444 @item Debug instrumentation sometimes supports event triggering
1445 such as ``trace buffer full'' (so it can quickly be emptied)
1446 or other signals (to correlate with code behavior).
1449 None of those events are signaled through standard JTAG signals.
1450 However, most conventions for JTAG connectors include voltage
1451 level and system reset (SRST) signal detection.
1452 Some connectors also include instrumentation signals, which
1453 can imply events when those signals are inputs.
1455 In general, OpenOCD needs to periodically check for those events,
1456 either by looking at the status of signals on the JTAG connector
1457 or by sending synchronous ``tell me your status'' JTAG requests
1458 to the various active targets.
1459 There is a command to manage and monitor that polling,
1460 which is normally done in the background.
1462 @deffn Command poll [@option{on}|@option{off}]
1463 Poll the current target for its current state.
1464 (Also, @pxref{target curstate}.)
1465 If that target is in debug mode, architecture
1466 specific information about the current state is printed.
1467 An optional parameter
1468 allows background polling to be enabled and disabled.
1470 You could use this from the TCL command shell, or
1471 from GDB using @command{monitor poll} command.
1474 background polling: on
1475 target state: halted
1476 target halted in ARM state due to debug-request, \
1477 current mode: Supervisor
1478 cpsr: 0x800000d3 pc: 0x11081bfc
1479 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1484 @node Interface - Dongle Configuration
1485 @chapter Interface - Dongle Configuration
1486 @cindex config file, interface
1487 @cindex interface config file
1489 JTAG Adapters/Interfaces/Dongles are normally configured
1490 through commands in an interface configuration
1491 file which is sourced by your @file{openocd.cfg} file, or
1492 through a command line @option{-f interface/....cfg} option.
1495 source [find interface/olimex-jtag-tiny.cfg]
1499 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1500 A few cases are so simple that you only need to say what driver to use:
1507 Most adapters need a bit more configuration than that.
1510 @section Interface Configuration
1512 The interface command tells OpenOCD what type of JTAG dongle you are
1513 using. Depending on the type of dongle, you may need to have one or
1514 more additional commands.
1516 @deffn {Config Command} {interface} name
1517 Use the interface driver @var{name} to connect to the
1521 @deffn Command {interface_list}
1522 List the interface drivers that have been built into
1523 the running copy of OpenOCD.
1526 @deffn Command {jtag interface}
1527 Returns the name of the interface driver being used.
1530 @section Interface Drivers
1532 Each of the interface drivers listed here must be explicitly
1533 enabled when OpenOCD is configured, in order to be made
1534 available at run time.
1536 @deffn {Interface Driver} {amt_jtagaccel}
1537 Amontec Chameleon in its JTAG Accelerator configuration,
1538 connected to a PC's EPP mode parallel port.
1539 This defines some driver-specific commands:
1541 @deffn {Config Command} {parport_port} number
1542 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1543 the number of the @file{/dev/parport} device.
1546 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1547 Displays status of RTCK option.
1548 Optionally sets that option first.
1552 @deffn {Interface Driver} {arm-jtag-ew}
1553 Olimex ARM-JTAG-EW USB adapter
1554 This has one driver-specific command:
1556 @deffn Command {armjtagew_info}
1561 @deffn {Interface Driver} {at91rm9200}
1562 Supports bitbanged JTAG from the local system,
1563 presuming that system is an Atmel AT91rm9200
1564 and a specific set of GPIOs is used.
1565 @c command: at91rm9200_device NAME
1566 @c chooses among list of bit configs ... only one option
1569 @deffn {Interface Driver} {dummy}
1570 A dummy software-only driver for debugging.
1573 @deffn {Interface Driver} {ep93xx}
1574 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1577 @deffn {Interface Driver} {ft2232}
1578 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1579 These interfaces have several commands, used to configure the driver
1580 before initializing the JTAG scan chain:
1582 @deffn {Config Command} {ft2232_device_desc} description
1583 Provides the USB device description (the @emph{iProduct string})
1584 of the FTDI FT2232 device. If not
1585 specified, the FTDI default value is used. This setting is only valid
1586 if compiled with FTD2XX support.
1589 @deffn {Config Command} {ft2232_serial} serial-number
1590 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1591 in case the vendor provides unique IDs and more than one FT2232 device
1592 is connected to the host.
1593 If not specified, serial numbers are not considered.
1594 (Note that USB serial numbers can be arbitrary Unicode strings,
1595 and are not restricted to containing only decimal digits.)
1598 @deffn {Config Command} {ft2232_layout} name
1599 Each vendor's FT2232 device can use different GPIO signals
1600 to control output-enables, reset signals, and LEDs.
1601 Currently valid layout @var{name} values include:
1603 @item @b{axm0432_jtag} Axiom AXM-0432
1604 @item @b{comstick} Hitex STR9 comstick
1605 @item @b{cortino} Hitex Cortino JTAG interface
1606 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1607 either for the local Cortex-M3 (SRST only)
1608 or in a passthrough mode (neither SRST nor TRST)
1609 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1610 @item @b{flyswatter} Tin Can Tools Flyswatter
1611 @item @b{icebear} ICEbear JTAG adapter from Section 5
1612 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1613 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1614 @item @b{m5960} American Microsystems M5960
1615 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1616 @item @b{oocdlink} OOCDLink
1617 @c oocdlink ~= jtagkey_prototype_v1
1618 @item @b{sheevaplug} Marvell Sheevaplug development kit
1619 @item @b{signalyzer} Xverve Signalyzer
1620 @item @b{stm32stick} Hitex STM32 Performance Stick
1621 @item @b{turtelizer2} egnite Software turtelizer2
1622 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1626 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1627 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1628 default values are used.
1629 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1631 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1635 @deffn {Config Command} {ft2232_latency} ms
1636 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1637 ft2232_read() fails to return the expected number of bytes. This can be caused by
1638 USB communication delays and has proved hard to reproduce and debug. Setting the
1639 FT2232 latency timer to a larger value increases delays for short USB packets but it
1640 also reduces the risk of timeouts before receiving the expected number of bytes.
1641 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1644 For example, the interface config file for a
1645 Turtelizer JTAG Adapter looks something like this:
1649 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1650 ft2232_layout turtelizer2
1651 ft2232_vid_pid 0x0403 0xbdc8
1655 @deffn {Interface Driver} {gw16012}
1656 Gateworks GW16012 JTAG programmer.
1657 This has one driver-specific command:
1659 @deffn {Config Command} {parport_port} number
1660 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1661 the number of the @file{/dev/parport} device.
1665 @deffn {Interface Driver} {jlink}
1666 Segger jlink USB adapter
1667 @c command: jlink_info
1669 @c command: jlink_hw_jtag (2|3)
1670 @c sets version 2 or 3
1673 @deffn {Interface Driver} {parport}
1674 Supports PC parallel port bit-banging cables:
1675 Wigglers, PLD download cable, and more.
1676 These interfaces have several commands, used to configure the driver
1677 before initializing the JTAG scan chain:
1679 @deffn {Config Command} {parport_cable} name
1680 The layout of the parallel port cable used to connect to the target.
1681 Currently valid cable @var{name} values include:
1684 @item @b{altium} Altium Universal JTAG cable.
1685 @item @b{arm-jtag} Same as original wiggler except SRST and
1686 TRST connections reversed and TRST is also inverted.
1687 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1688 in configuration mode. This is only used to
1689 program the Chameleon itself, not a connected target.
1690 @item @b{dlc5} The Xilinx Parallel cable III.
1691 @item @b{flashlink} The ST Parallel cable.
1692 @item @b{lattice} Lattice ispDOWNLOAD Cable
1693 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1695 Amontec's Chameleon Programmer. The new version available from
1696 the website uses the original Wiggler layout ('@var{wiggler}')
1697 @item @b{triton} The parallel port adapter found on the
1698 ``Karo Triton 1 Development Board''.
1699 This is also the layout used by the HollyGates design
1700 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1701 @item @b{wiggler} The original Wiggler layout, also supported by
1702 several clones, such as the Olimex ARM-JTAG
1703 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1704 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1708 @deffn {Config Command} {parport_port} number
1709 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1710 the @file{/dev/parport} device
1712 When using PPDEV to access the parallel port, use the number of the parallel port:
1713 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1714 you may encounter a problem.
1717 @deffn {Config Command} {parport_write_on_exit} (on|off)
1718 This will configure the parallel driver to write a known
1719 cable-specific value to the parallel interface on exiting OpenOCD
1722 For example, the interface configuration file for a
1723 classic ``Wiggler'' cable might look something like this:
1728 parport_cable wiggler
1732 @deffn {Interface Driver} {presto}
1733 ASIX PRESTO USB JTAG programmer.
1734 @c command: presto_serial str
1735 @c sets serial number
1738 @deffn {Interface Driver} {rlink}
1739 Raisonance RLink USB adapter
1742 @deffn {Interface Driver} {usbprog}
1743 usbprog is a freely programmable USB adapter.
1746 @deffn {Interface Driver} {vsllink}
1747 vsllink is part of Versaloon which is a versatile USB programmer.
1750 This defines quite a few driver-specific commands,
1751 which are not currently documented here.
1755 @deffn {Interface Driver} {ZY1000}
1756 This is the Zylin ZY1000 JTAG debugger.
1759 This defines some driver-specific commands,
1760 which are not currently documented here.
1763 @deffn Command power [@option{on}|@option{off}]
1764 Turn power switch to target on/off.
1765 No arguments: print status.
1772 JTAG clock setup is part of system setup.
1773 It @emph{does not belong with interface setup} since any interface
1774 only knows a few of the constraints for the JTAG clock speed.
1775 Sometimes the JTAG speed is
1776 changed during the target initialization process: (1) slow at
1777 reset, (2) program the CPU clocks, (3) run fast.
1778 Both the "slow" and "fast" clock rates are functions of the
1779 oscillators used, the chip, the board design, and sometimes
1780 power management software that may be active.
1782 The speed used during reset can be adjusted using pre_reset
1783 and post_reset event handlers.
1784 @xref{Target Events}.
1786 If your system supports adaptive clocking (RTCK), configuring
1787 JTAG to use that is probably the most robust approach.
1788 However, it introduces delays to synchronize clocks; so it
1789 may not be the fastest solution.
1791 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1792 instead of @command{jtag_khz}.
1794 @deffn {Command} jtag_khz max_speed_kHz
1795 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1796 JTAG interfaces usually support a limited number of
1797 speeds. The speed actually used won't be faster
1798 than the speed specified.
1800 Chip data sheets generally include a top JTAG clock rate.
1801 The actual rate is often a function of a CPU core clock,
1802 and is normally less than that peak rate.
1803 For example, most ARM cores accept at most one sixth of the CPU clock.
1805 Speed 0 (khz) selects RTCK method.
1807 If your system uses RTCK, you won't need to change the
1808 JTAG clocking after setup.
1809 Not all interfaces, boards, or targets support ``rtck''.
1810 If the interface device can not
1811 support it, an error is returned when you try to use RTCK.
1814 @defun jtag_rclk fallback_speed_kHz
1815 @cindex adaptive clocking
1817 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1818 If that fails (maybe the interface, board, or target doesn't
1819 support it), falls back to the specified frequency.
1821 # Fall back to 3mhz if RTCK is not supported
1826 @node Reset Configuration
1827 @chapter Reset Configuration
1828 @cindex Reset Configuration
1830 Every system configuration may require a different reset
1831 configuration. This can also be quite confusing.
1832 Resets also interact with @var{reset-init} event handlers,
1833 which do things like setting up clocks and DRAM, and
1834 JTAG clock rates. (@xref{JTAG Speed}.)
1835 They can also interact with JTAG routers.
1836 Please see the various board files for examples.
1839 To maintainers and integrators:
1840 Reset configuration touches several things at once.
1841 Normally the board configuration file
1842 should define it and assume that the JTAG adapter supports
1843 everything that's wired up to the board's JTAG connector.
1845 However, the target configuration file could also make note
1846 of something the silicon vendor has done inside the chip,
1847 which will be true for most (or all) boards using that chip.
1848 And when the JTAG adapter doesn't support everything, the
1849 user configuration file will need to override parts of
1850 the reset configuration provided by other files.
1853 @section Types of Reset
1855 There are many kinds of reset possible through JTAG, but
1856 they may not all work with a given board and adapter.
1857 That's part of why reset configuration can be error prone.
1861 @emph{System Reset} ... the @emph{SRST} hardware signal
1862 resets all chips connected to the JTAG adapter, such as processors,
1863 power management chips, and I/O controllers. Normally resets triggered
1864 with this signal behave exactly like pressing a RESET button.
1866 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1867 just the TAP controllers connected to the JTAG adapter.
1868 Such resets should not be visible to the rest of the system; resetting a
1869 device's the TAP controller just puts that controller into a known state.
1871 @emph{Emulation Reset} ... many devices can be reset through JTAG
1872 commands. These resets are often distinguishable from system
1873 resets, either explicitly (a "reset reason" register says so)
1874 or implicitly (not all parts of the chip get reset).
1876 @emph{Other Resets} ... system-on-chip devices often support
1877 several other types of reset.
1878 You may need to arrange that a watchdog timer stops
1879 while debugging, preventing a watchdog reset.
1880 There may be individual module resets.
1883 In the best case, OpenOCD can hold SRST, then reset
1884 the TAPs via TRST and send commands through JTAG to halt the
1885 CPU at the reset vector before the 1st instruction is executed.
1886 Then when it finally releases the SRST signal, the system is
1887 halted under debugger control before any code has executed.
1888 This is the behavior required to support the @command{reset halt}
1889 and @command{reset init} commands; after @command{reset init} a
1890 board-specific script might do things like setting up DRAM.
1891 (@xref{Reset Command}.)
1893 @anchor{SRST and TRST Issues}
1894 @section SRST and TRST Issues
1896 Because SRST and TRST are hardware signals, they can have a
1897 variety of system-specific constraints. Some of the most
1902 @item @emph{Signal not available} ... Some boards don't wire
1903 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1904 support such signals even if they are wired up.
1905 Use the @command{reset_config} @var{signals} options to say
1906 when either of those signals is not connected.
1907 When SRST is not available, your code might not be able to rely
1908 on controllers having been fully reset during code startup.
1909 Missing TRST is not a problem, since JTAG level resets can
1910 be triggered using with TMS signaling.
1912 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1913 adapter will connect SRST to TRST, instead of keeping them separate.
1914 Use the @command{reset_config} @var{combination} options to say
1915 when those signals aren't properly independent.
1917 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1918 delay circuit, reset supervisor, or on-chip features can extend
1919 the effect of a JTAG adapter's reset for some time after the adapter
1920 stops issuing the reset. For example, there may be chip or board
1921 requirements that all reset pulses last for at least a
1922 certain amount of time; and reset buttons commonly have
1923 hardware debouncing.
1924 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1925 commands to say when extra delays are needed.
1927 @item @emph{Drive type} ... Reset lines often have a pullup
1928 resistor, letting the JTAG interface treat them as open-drain
1929 signals. But that's not a requirement, so the adapter may need
1930 to use push/pull output drivers.
1931 Also, with weak pullups it may be advisable to drive
1932 signals to both levels (push/pull) to minimize rise times.
1933 Use the @command{reset_config} @var{trst_type} and
1934 @var{srst_type} parameters to say how to drive reset signals.
1936 @item @emph{Special initialization} ... Targets sometimes need
1937 special JTAG initialization sequences to handle chip-specific
1938 issues (not limited to errata).
1939 For example, certain JTAG commands might need to be issued while
1940 the system as a whole is in a reset state (SRST active)
1941 but the JTAG scan chain is usable (TRST inactive).
1942 (@xref{JTAG Commands}, where the @command{jtag_reset}
1943 command is presented.)
1946 There can also be other issues.
1947 Some devices don't fully conform to the JTAG specifications.
1948 Trivial system-specific differences are common, such as
1949 SRST and TRST using slightly different names.
1950 There are also vendors who distribute key JTAG documentation for
1951 their chips only to developers who have signed a Non-Disclosure
1954 Sometimes there are chip-specific extensions like a requirement to use
1955 the normally-optional TRST signal (precluding use of JTAG adapters which
1956 don't pass TRST through), or needing extra steps to complete a TAP reset.
1958 In short, SRST and especially TRST handling may be very finicky,
1959 needing to cope with both architecture and board specific constraints.
1961 @section Commands for Handling Resets
1963 @deffn {Command} jtag_nsrst_delay milliseconds
1964 How long (in milliseconds) OpenOCD should wait after deasserting
1965 nSRST (active-low system reset) before starting new JTAG operations.
1966 When a board has a reset button connected to SRST line it will
1967 probably have hardware debouncing, implying you should use this.
1970 @deffn {Command} jtag_ntrst_delay milliseconds
1971 How long (in milliseconds) OpenOCD should wait after deasserting
1972 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1975 @deffn {Command} reset_config mode_flag ...
1976 This command tells OpenOCD the reset configuration
1977 of your combination of JTAG board and target in target
1978 configuration scripts.
1980 Information earlier in this section describes the kind of problems
1981 the command is intended to address (@pxref{SRST and TRST Issues}).
1982 As a rule this command belongs only in board config files,
1983 describing issues like @emph{board doesn't connect TRST};
1984 or in user config files, addressing limitations derived
1985 from a particular combination of interface and board.
1986 (An unlikely example would be using a TRST-only adapter
1987 with a board that only wires up SRST.)
1989 The @var{mode_flag} options can be specified in any order, but only one
1990 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1991 and @var{srst_type} -- may be specified at a time.
1992 If you don't provide a new value for a given type, its previous
1993 value (perhaps the default) is unchanged.
1994 For example, this means that you don't need to say anything at all about
1995 TRST just to declare that if the JTAG adapter should want to drive SRST,
1996 it must explicitly be driven high (@option{srst_push_pull}).
1998 @var{signals} can specify which of the reset signals are connected.
1999 For example, If the JTAG interface provides SRST, but the board doesn't
2000 connect that signal properly, then OpenOCD can't use it.
2001 Possible values are @option{none} (the default), @option{trst_only},
2002 @option{srst_only} and @option{trst_and_srst}.
2005 If your board provides SRST or TRST through the JTAG connector,
2006 you must declare that or else those signals will not be used.
2009 The @var{combination} is an optional value specifying broken reset
2010 signal implementations.
2011 The default behaviour if no option given is @option{separate},
2012 indicating everything behaves normally.
2013 @option{srst_pulls_trst} states that the
2014 test logic is reset together with the reset of the system (e.g. Philips
2015 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2016 the system is reset together with the test logic (only hypothetical, I
2017 haven't seen hardware with such a bug, and can be worked around).
2018 @option{combined} implies both @option{srst_pulls_trst} and
2019 @option{trst_pulls_srst}.
2021 @option{srst_gates_jtag} indicates that asserting SRST gates the
2022 JTAG clock. This means that no communication can happen on JTAG
2023 while SRST is asserted.
2025 The optional @var{trst_type} and @var{srst_type} parameters allow the
2026 driver mode of each reset line to be specified. These values only affect
2027 JTAG interfaces with support for different driver modes, like the Amontec
2028 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2029 relevant signal (TRST or SRST) is not connected.
2031 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2032 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2033 Most boards connect this signal to a pulldown, so the JTAG TAPs
2034 never leave reset unless they are hooked up to a JTAG adapter.
2036 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2037 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2038 Most boards connect this signal to a pullup, and allow the
2039 signal to be pulled low by various events including system
2040 powerup and pressing a reset button.
2044 @node TAP Declaration
2045 @chapter TAP Declaration
2046 @cindex TAP declaration
2047 @cindex TAP configuration
2049 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2050 TAPs serve many roles, including:
2053 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2054 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2055 Others do it indirectly, making a CPU do it.
2056 @item @b{Program Download} Using the same CPU support GDB uses,
2057 you can initialize a DRAM controller, download code to DRAM, and then
2058 start running that code.
2059 @item @b{Boundary Scan} Most chips support boundary scan, which
2060 helps test for board assembly problems like solder bridges
2061 and missing connections
2064 OpenOCD must know about the active TAPs on your board(s).
2065 Setting up the TAPs is the core task of your configuration files.
2066 Once those TAPs are set up, you can pass their names to code
2067 which sets up CPUs and exports them as GDB targets,
2068 probes flash memory, performs low-level JTAG operations, and more.
2070 @section Scan Chains
2073 TAPs are part of a hardware @dfn{scan chain},
2074 which is daisy chain of TAPs.
2075 They also need to be added to
2076 OpenOCD's software mirror of that hardware list,
2077 giving each member a name and associating other data with it.
2078 Simple scan chains, with a single TAP, are common in
2079 systems with a single microcontroller or microprocessor.
2080 More complex chips may have several TAPs internally.
2081 Very complex scan chains might have a dozen or more TAPs:
2082 several in one chip, more in the next, and connecting
2083 to other boards with their own chips and TAPs.
2085 You can display the list with the @command{scan_chain} command.
2086 (Don't confuse this with the list displayed by the @command{targets}
2087 command, presented in the next chapter.
2088 That only displays TAPs for CPUs which are configured as
2090 Here's what the scan chain might look like for a chip more than one TAP:
2093 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2094 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2095 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2096 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2097 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2100 Unfortunately those TAPs can't always be autoconfigured,
2101 because not all devices provide good support for that.
2102 JTAG doesn't require supporting IDCODE instructions, and
2103 chips with JTAG routers may not link TAPs into the chain
2104 until they are told to do so.
2106 The configuration mechanism currently supported by OpenOCD
2107 requires explicit configuration of all TAP devices using
2108 @command{jtag newtap} commands, as detailed later in this chapter.
2109 A command like this would declare one tap and name it @code{chip1.cpu}:
2112 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2115 Each target configuration file lists the TAPs provided
2117 Board configuration files combine all the targets on a board,
2119 Note that @emph{the order in which TAPs are declared is very important.}
2120 It must match the order in the JTAG scan chain, both inside
2121 a single chip and between them.
2122 @xref{FAQ TAP Order}.
2124 For example, the ST Microsystems STR912 chip has
2125 three separate TAPs@footnote{See the ST
2126 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2127 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2128 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2129 To configure those taps, @file{target/str912.cfg}
2130 includes commands something like this:
2133 jtag newtap str912 flash ... params ...
2134 jtag newtap str912 cpu ... params ...
2135 jtag newtap str912 bs ... params ...
2138 Actual config files use a variable instead of literals like
2139 @option{str912}, to support more than one chip of each type.
2140 @xref{Config File Guidelines}.
2142 @deffn Command {jtag names}
2143 Returns the names of all current TAPs in the scan chain.
2144 Use @command{jtag cget} or @command{jtag tapisenabled}
2145 to examine attributes and state of each TAP.
2147 foreach t [jtag names] @{
2148 puts [format "TAP: %s\n" $t]
2153 @deffn Command {scan_chain}
2154 Displays the TAPs in the scan chain configuration,
2156 The set of TAPs listed by this command is fixed by
2157 exiting the OpenOCD configuration stage,
2158 but systems with a JTAG router can
2159 enable or disable TAPs dynamically.
2160 In addition to the enable/disable status, the contents of
2161 each TAP's instruction register can also change.
2164 @c FIXME! "jtag cget" should be able to return all TAP
2165 @c attributes, like "$target_name cget" does for targets.
2167 @c Probably want "jtag eventlist", and a "tap-reset" event
2168 @c (on entry to RESET state).
2173 When TAP objects are declared with @command{jtag newtap},
2174 a @dfn{dotted.name} is created for the TAP, combining the
2175 name of a module (usually a chip) and a label for the TAP.
2176 For example: @code{xilinx.tap}, @code{str912.flash},
2177 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2178 Many other commands use that dotted.name to manipulate or
2179 refer to the TAP. For example, CPU configuration uses the
2180 name, as does declaration of NAND or NOR flash banks.
2182 The components of a dotted name should follow ``C'' symbol
2183 name rules: start with an alphabetic character, then numbers
2184 and underscores are OK; while others (including dots!) are not.
2187 In older code, JTAG TAPs were numbered from 0..N.
2188 This feature is still present.
2189 However its use is highly discouraged, and
2190 should not be relied on; it will be removed by mid-2010.
2191 Update all of your scripts to use TAP names rather than numbers,
2192 by paying attention to the runtime warnings they trigger.
2193 Using TAP numbers in target configuration scripts prevents
2194 reusing those scripts on boards with multiple targets.
2197 @section TAP Declaration Commands
2199 @c shouldn't this be(come) a {Config Command}?
2200 @anchor{jtag newtap}
2201 @deffn Command {jtag newtap} chipname tapname configparams...
2202 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2203 and configured according to the various @var{configparams}.
2205 The @var{chipname} is a symbolic name for the chip.
2206 Conventionally target config files use @code{$_CHIPNAME},
2207 defaulting to the model name given by the chip vendor but
2210 @cindex TAP naming convention
2211 The @var{tapname} reflects the role of that TAP,
2212 and should follow this convention:
2215 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2216 @item @code{cpu} -- The main CPU of the chip, alternatively
2217 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2218 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2219 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2220 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2221 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2222 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2223 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2225 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2226 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2227 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2228 a JTAG TAP; that TAP should be named @code{sdma}.
2231 Every TAP requires at least the following @var{configparams}:
2234 @item @code{-ircapture} @var{NUMBER}
2235 @*The bit pattern loaded by the TAP into the JTAG shift register
2236 on entry to the @sc{ircapture} state, such as 0x01.
2237 JTAG requires the two LSBs of this value to be 01.
2238 The value is used to verify that instruction scans work correctly.
2239 @item @code{-irlen} @var{NUMBER}
2240 @*The length in bits of the
2241 instruction register, such as 4 or 5 bits.
2242 @item @code{-irmask} @var{NUMBER}
2243 @*A mask for the IR register.
2244 For some devices, there are bits in the IR that aren't used.
2245 This lets OpenOCD mask them off when doing IDCODE comparisons.
2246 In general, this should just be all ones for the size of the IR.
2249 A TAP may also provide optional @var{configparams}:
2252 @item @code{-disable} (or @code{-enable})
2253 @*Use the @code{-disable} parameter to flag a TAP which is not
2254 linked in to the scan chain after a reset using either TRST
2255 or the JTAG state machine's @sc{reset} state.
2256 You may use @code{-enable} to highlight the default state
2257 (the TAP is linked in).
2258 @xref{Enabling and Disabling TAPs}.
2259 @item @code{-expected-id} @var{number}
2260 @*A non-zero value represents the expected 32-bit IDCODE
2261 found when the JTAG chain is examined.
2262 These codes are not required by all JTAG devices.
2263 @emph{Repeat the option} as many times as required if more than one
2264 ID code could appear (for example, multiple versions).
2268 @c @deffn Command {jtag arp_init-reset}
2269 @c ... more or less "init" ?
2271 @anchor{Enabling and Disabling TAPs}
2272 @section Enabling and Disabling TAPs
2274 @cindex JTAG Route Controller
2277 In some systems, a @dfn{JTAG Route Controller} (JRC)
2278 is used to enable and/or disable specific JTAG TAPs.
2279 Many ARM based chips from Texas Instruments include
2280 an ``ICEpick'' module, which is a JRC.
2281 Such chips include DaVinci and OMAP3 processors.
2283 A given TAP may not be visible until the JRC has been
2284 told to link it into the scan chain; and if the JRC
2285 has been told to unlink that TAP, it will no longer
2287 Such routers address problems that JTAG ``bypass mode''
2291 @item The scan chain can only go as fast as its slowest TAP.
2292 @item Having many TAPs slows instruction scans, since all
2293 TAPs receive new instructions.
2294 @item TAPs in the scan chain must be powered up, which wastes
2295 power and prevents debugging some power management mechanisms.
2298 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2299 as implied by the existence of JTAG routers.
2300 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2301 does include a kind of JTAG router functionality.
2303 @c (a) currently the event handlers don't seem to be able to
2304 @c fail in a way that could lead to no-change-of-state.
2305 @c (b) eventually non-event configuration should be possible,
2306 @c in which case some this documentation must move.
2308 @deffn Command {jtag cget} dotted.name @option{-event} name
2309 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2310 At this writing this mechanism is used only for event handling.
2311 Three events are available. Two events relate to TAP enabling
2312 and disabling, one to post reset handling.
2314 The @code{configure} subcommand assigns an event handler,
2315 a TCL string which is evaluated when the event is triggered.
2316 The @code{cget} subcommand returns that handler.
2317 The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
2319 So for example, when defining a TAP for a CPU connected to
2320 a JTAG router, you should define TAP event handlers using
2321 code that looks something like this:
2324 jtag configure CHIP.cpu -event tap-enable @{
2325 echo "Enabling CPU TAP"
2326 ... jtag operations using CHIP.jrc
2328 jtag configure CHIP.cpu -event tap-disable @{
2329 echo "Disabling CPU TAP"
2330 ... jtag operations using CHIP.jrc
2334 If you need some post reset action, you can do:
2337 jtag configure CHIP.cpu -event post-reset @{
2339 ... jtag operations to be done after reset
2344 @deffn Command {jtag tapdisable} dotted.name
2345 @deffnx Command {jtag tapenable} dotted.name
2346 @deffnx Command {jtag tapisenabled} dotted.name
2347 These three commands all return the string "1" if the tap
2348 specified by @var{dotted.name} is enabled,
2349 and "0" if it is disbabled.
2350 The @command{tapenable} variant first enables the tap
2351 by sending it a @option{tap-enable} event.
2352 The @command{tapdisable} variant first disables the tap
2353 by sending it a @option{tap-disable} event.
2356 Humans will find the @command{scan_chain} command more helpful
2357 than the script-oriented @command{tapisenabled}
2358 for querying the state of the JTAG taps.
2362 @node CPU Configuration
2363 @chapter CPU Configuration
2366 This chapter discusses how to set up GDB debug targets for CPUs.
2367 You can also access these targets without GDB
2368 (@pxref{Architecture and Core Commands},
2369 and @ref{Target State handling}) and
2370 through various kinds of NAND and NOR flash commands.
2371 If you have multiple CPUs you can have multiple such targets.
2373 We'll start by looking at how to examine the targets you have,
2374 then look at how to add one more target and how to configure it.
2376 @section Target List
2377 @cindex target, current
2378 @cindex target, list
2380 All targets that have been set up are part of a list,
2381 where each member has a name.
2382 That name should normally be the same as the TAP name.
2383 You can display the list with the @command{targets}
2385 This display often has only one CPU; here's what it might
2386 look like with more than one:
2388 TargetName Type Endian TapName State
2389 -- ------------------ ---------- ------ ------------------ ------------
2390 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2391 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2394 One member of that list is the @dfn{current target}, which
2395 is implicitly referenced by many commands.
2396 It's the one marked with a @code{*} near the target name.
2397 In particular, memory addresses often refer to the address
2398 space seen by that current target.
2399 Commands like @command{mdw} (memory display words)
2400 and @command{flash erase_address} (erase NOR flash blocks)
2401 are examples; and there are many more.
2403 Several commands let you examine the list of targets:
2405 @deffn Command {target count}
2406 @emph{Note: target numbers are deprecated; don't use them.
2407 They will be removed shortly after August 2010, including this command.
2408 Iterate target using @command{target names}, not by counting.}
2410 Returns the number of targets, @math{N}.
2411 The highest numbered target is @math{N - 1}.
2413 set c [target count]
2414 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2415 # Assuming you have created this function
2416 print_target_details $x
2421 @deffn Command {target current}
2422 Returns the name of the current target.
2425 @deffn Command {target names}
2426 Lists the names of all current targets in the list.
2428 foreach t [target names] @{
2429 puts [format "Target: %s\n" $t]
2434 @deffn Command {target number} number
2435 @emph{Note: target numbers are deprecated; don't use them.
2436 They will be removed shortly after August 2010, including this command.}
2438 The list of targets is numbered starting at zero.
2439 This command returns the name of the target at index @var{number}.
2441 set thename [target number $x]
2442 puts [format "Target %d is: %s\n" $x $thename]
2446 @c yep, "target list" would have been better.
2447 @c plus maybe "target setdefault".
2449 @deffn Command targets [name]
2450 @emph{Note: the name of this command is plural. Other target
2451 command names are singular.}
2453 With no parameter, this command displays a table of all known
2454 targets in a user friendly form.
2456 With a parameter, this command sets the current target to
2457 the given target with the given @var{name}; this is
2458 only relevant on boards which have more than one target.
2461 @section Target CPU Types and Variants
2466 Each target has a @dfn{CPU type}, as shown in the output of
2467 the @command{targets} command. You need to specify that type
2468 when calling @command{target create}.
2469 The CPU type indicates more than just the instruction set.
2470 It also indicates how that instruction set is implemented,
2471 what kind of debug support it integrates,
2472 whether it has an MMU (and if so, what kind),
2473 what core-specific commands may be available
2474 (@pxref{Architecture and Core Commands}),
2477 For some CPU types, OpenOCD also defines @dfn{variants} which
2478 indicate differences that affect their handling.
2479 For example, a particular implementation bug might need to be
2480 worked around in some chip versions.
2482 It's easy to see what target types are supported,
2483 since there's a command to list them.
2484 However, there is currently no way to list what target variants
2485 are supported (other than by reading the OpenOCD source code).
2487 @anchor{target types}
2488 @deffn Command {target types}
2489 Lists all supported target types.
2490 At this writing, the supported CPU types and variants are:
2493 @item @code{arm11} -- this is a generation of ARMv6 cores
2494 @item @code{arm720t} -- this is an ARMv4 core
2495 @item @code{arm7tdmi} -- this is an ARMv4 core
2496 @item @code{arm920t} -- this is an ARMv5 core
2497 @item @code{arm926ejs} -- this is an ARMv5 core
2498 @item @code{arm966e} -- this is an ARMv5 core
2499 @item @code{arm9tdmi} -- this is an ARMv4 core
2500 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2501 (Support for this is preliminary and incomplete.)
2502 @item @code{cortex_a8} -- this is an ARMv7 core
2503 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2504 compact Thumb2 instruction set. It supports one variant:
2506 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2507 This will cause OpenOCD to use a software reset rather than asserting
2508 SRST, to avoid a issue with clearing the debug registers.
2509 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2510 be detected and the normal reset behaviour used.
2512 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2513 @item @code{feroceon} -- resembles arm926
2514 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2516 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2517 provide a functional SRST line on the EJTAG connector. This causes
2518 OpenOCD to instead use an EJTAG software reset command to reset the
2520 You still need to enable @option{srst} on the @command{reset_config}
2521 command to enable OpenOCD hardware reset functionality.
2523 @item @code{xscale} -- this is actually an architecture,
2524 not a CPU type. It is based on the ARMv5 architecture.
2525 There are several variants defined:
2527 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2528 @code{pxa27x} ... instruction register length is 7 bits
2529 @item @code{pxa250}, @code{pxa255},
2530 @code{pxa26x} ... instruction register length is 5 bits
2535 To avoid being confused by the variety of ARM based cores, remember
2536 this key point: @emph{ARM is a technology licencing company}.
2537 (See: @url{http://www.arm.com}.)
2538 The CPU name used by OpenOCD will reflect the CPU design that was
2539 licenced, not a vendor brand which incorporates that design.
2540 Name prefixes like arm7, arm9, arm11, and cortex
2541 reflect design generations;
2542 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2543 reflect an architecture version implemented by a CPU design.
2545 @anchor{Target Configuration}
2546 @section Target Configuration
2548 Before creating a ``target'', you must have added its TAP to the scan chain.
2549 When you've added that TAP, you will have a @code{dotted.name}
2550 which is used to set up the CPU support.
2551 The chip-specific configuration file will normally configure its CPU(s)
2552 right after it adds all of the chip's TAPs to the scan chain.
2554 Although you can set up a target in one step, it's often clearer if you
2555 use shorter commands and do it in two steps: create it, then configure
2557 All operations on the target after it's created will use a new
2558 command, created as part of target creation.
2560 The two main things to configure after target creation are
2561 a work area, which usually has target-specific defaults even
2562 if the board setup code overrides them later;
2563 and event handlers (@pxref{Target Events}), which tend
2564 to be much more board-specific.
2565 The key steps you use might look something like this
2568 target create MyTarget cortex_m3 -chain-position mychip.cpu
2569 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2570 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2571 $MyTarget configure -event reset-init @{ myboard_reinit @}
2574 You should specify a working area if you can; typically it uses some
2576 Such a working area can speed up many things, including bulk
2577 writes to target memory;
2578 flash operations like checking to see if memory needs to be erased;
2579 GDB memory checksumming;
2583 On more complex chips, the work area can become
2584 inaccessible when application code
2585 (such as an operating system)
2586 enables or disables the MMU.
2587 For example, the particular MMU context used to acess the virtual
2588 address will probably matter ... and that context might not have
2589 easy access to other addresses needed.
2590 At this writing, OpenOCD doesn't have much MMU intelligence.
2593 It's often very useful to define a @code{reset-init} event handler.
2594 For systems that are normally used with a boot loader,
2595 common tasks include updating clocks and initializing memory
2597 That may be needed to let you write the boot loader into flash,
2598 in order to ``de-brick'' your board; or to load programs into
2599 external DDR memory without having run the boot loader.
2601 @deffn Command {target create} target_name type configparams...
2602 This command creates a GDB debug target that refers to a specific JTAG tap.
2603 It enters that target into a list, and creates a new
2604 command (@command{@var{target_name}}) which is used for various
2605 purposes including additional configuration.
2608 @item @var{target_name} ... is the name of the debug target.
2609 By convention this should be the same as the @emph{dotted.name}
2610 of the TAP associated with this target, which must be specified here
2611 using the @code{-chain-position @var{dotted.name}} configparam.
2613 This name is also used to create the target object command,
2614 referred to here as @command{$target_name},
2615 and in other places the target needs to be identified.
2616 @item @var{type} ... specifies the target type. @xref{target types}.
2617 @item @var{configparams} ... all parameters accepted by
2618 @command{$target_name configure} are permitted.
2619 If the target is big-endian, set it here with @code{-endian big}.
2620 If the variant matters, set it here with @code{-variant}.
2622 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2626 @deffn Command {$target_name configure} configparams...
2627 The options accepted by this command may also be
2628 specified as parameters to @command{target create}.
2629 Their values can later be queried one at a time by
2630 using the @command{$target_name cget} command.
2632 @emph{Warning:} changing some of these after setup is dangerous.
2633 For example, moving a target from one TAP to another;
2634 and changing its endianness or variant.
2638 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2639 used to access this target.
2641 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2642 whether the CPU uses big or little endian conventions
2644 @item @code{-event} @var{event_name} @var{event_body} --
2645 @xref{Target Events}.
2646 Note that this updates a list of named event handlers.
2647 Calling this twice with two different event names assigns
2648 two different handlers, but calling it twice with the
2649 same event name assigns only one handler.
2651 @item @code{-variant} @var{name} -- specifies a variant of the target,
2652 which OpenOCD needs to know about.
2654 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2655 whether the work area gets backed up; by default,
2656 @emph{it is not backed up.}
2657 When possible, use a working_area that doesn't need to be backed up,
2658 since performing a backup slows down operations.
2659 For example, the beginning of an SRAM block is likely to
2660 be used by most build systems, but the end is often unused.
2662 @item @code{-work-area-size} @var{size} -- specify/set the work area
2664 @item @code{-work-area-phys} @var{address} -- set the work area
2665 base @var{address} to be used when no MMU is active.
2667 @item @code{-work-area-virt} @var{address} -- set the work area
2668 base @var{address} to be used when an MMU is active.
2673 @section Other $target_name Commands
2674 @cindex object command
2676 The Tcl/Tk language has the concept of object commands,
2677 and OpenOCD adopts that same model for targets.
2679 A good Tk example is a on screen button.
2680 Once a button is created a button
2681 has a name (a path in Tk terms) and that name is useable as a first
2682 class command. For example in Tk, one can create a button and later
2683 configure it like this:
2687 button .foobar -background red -command @{ foo @}
2689 .foobar configure -foreground blue
2691 set x [.foobar cget -background]
2693 puts [format "The button is %s" $x]
2696 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2697 button, and its object commands are invoked the same way.
2700 str912.cpu mww 0x1234 0x42
2701 omap3530.cpu mww 0x5555 123
2704 The commands supported by OpenOCD target objects are:
2706 @deffn Command {$target_name arp_examine}
2707 @deffnx Command {$target_name arp_halt}
2708 @deffnx Command {$target_name arp_poll}
2709 @deffnx Command {$target_name arp_reset}
2710 @deffnx Command {$target_name arp_waitstate}
2711 Internal OpenOCD scripts (most notably @file{startup.tcl})
2712 use these to deal with specific reset cases.
2713 They are not otherwise documented here.
2716 @deffn Command {$target_name array2mem} arrayname width address count
2717 @deffnx Command {$target_name mem2array} arrayname width address count
2718 These provide an efficient script-oriented interface to memory.
2719 The @code{array2mem} primitive writes bytes, halfwords, or words;
2720 while @code{mem2array} reads them.
2721 In both cases, the TCL side uses an array, and
2722 the target side uses raw memory.
2724 The efficiency comes from enabling the use of
2725 bulk JTAG data transfer operations.
2726 The script orientation comes from working with data
2727 values that are packaged for use by TCL scripts;
2728 @command{mdw} type primitives only print data they retrieve,
2729 and neither store nor return those values.
2732 @item @var{arrayname} ... is the name of an array variable
2733 @item @var{width} ... is 8/16/32 - indicating the memory access size
2734 @item @var{address} ... is the target memory address
2735 @item @var{count} ... is the number of elements to process
2739 @deffn Command {$target_name cget} queryparm
2740 Each configuration parameter accepted by
2741 @command{$target_name configure}
2742 can be individually queried, to return its current value.
2743 The @var{queryparm} is a parameter name
2744 accepted by that command, such as @code{-work-area-phys}.
2745 There are a few special cases:
2748 @item @code{-event} @var{event_name} -- returns the handler for the
2749 event named @var{event_name}.
2750 This is a special case because setting a handler requires
2752 @item @code{-type} -- returns the target type.
2753 This is a special case because this is set using
2754 @command{target create} and can't be changed
2755 using @command{$target_name configure}.
2758 For example, if you wanted to summarize information about
2759 all the targets you might use something like this:
2762 foreach name [target names] @{
2763 set y [$name cget -endian]
2764 set z [$name cget -type]
2765 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2771 @anchor{target curstate}
2772 @deffn Command {$target_name curstate}
2773 Displays the current target state:
2774 @code{debug-running},
2777 @code{running}, or @code{unknown}.
2778 (Also, @pxref{Event Polling}.)
2781 @deffn Command {$target_name eventlist}
2782 Displays a table listing all event handlers
2783 currently associated with this target.
2784 @xref{Target Events}.
2787 @deffn Command {$target_name invoke-event} event_name
2788 Invokes the handler for the event named @var{event_name}.
2789 (This is primarily intended for use by OpenOCD framework
2790 code, for example by the reset code in @file{startup.tcl}.)
2793 @deffn Command {$target_name mdw} addr [count]
2794 @deffnx Command {$target_name mdh} addr [count]
2795 @deffnx Command {$target_name mdb} addr [count]
2796 Display contents of address @var{addr}, as
2797 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2798 or 8-bit bytes (@command{mdb}).
2799 If @var{count} is specified, displays that many units.
2800 (If you want to manipulate the data instead of displaying it,
2801 see the @code{mem2array} primitives.)
2804 @deffn Command {$target_name mww} addr word
2805 @deffnx Command {$target_name mwh} addr halfword
2806 @deffnx Command {$target_name mwb} addr byte
2807 Writes the specified @var{word} (32 bits),
2808 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2809 at the specified address @var{addr}.
2812 @anchor{Target Events}
2813 @section Target Events
2815 At various times, certain things can happen, or you want them to happen.
2818 @item What should happen when GDB connects? Should your target reset?
2819 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2820 @item During reset, do you need to write to certain memory locations
2821 to set up system clocks or
2822 to reconfigure the SDRAM?
2825 All of the above items can be addressed by target event handlers.
2826 These are set up by @command{$target_name configure -event} or
2827 @command{target create ... -event}.
2829 The programmer's model matches the @code{-command} option used in Tcl/Tk
2830 buttons and events. The two examples below act the same, but one creates
2831 and invokes a small procedure while the other inlines it.
2834 proc my_attach_proc @{ @} @{
2838 mychip.cpu configure -event gdb-attach my_attach_proc
2839 mychip.cpu configure -event gdb-attach @{
2845 The following target events are defined:
2848 @item @b{debug-halted}
2849 @* The target has halted for debug reasons (i.e.: breakpoint)
2850 @item @b{debug-resumed}
2851 @* The target has resumed (i.e.: gdb said run)
2852 @item @b{early-halted}
2853 @* Occurs early in the halt process
2855 @item @b{examine-end}
2856 @* Currently not used (goal: when JTAG examine completes)
2857 @item @b{examine-start}
2858 @* Currently not used (goal: when JTAG examine starts)
2860 @item @b{gdb-attach}
2861 @* When GDB connects
2862 @item @b{gdb-detach}
2863 @* When GDB disconnects
2865 @* When the target has halted and GDB is not doing anything (see early halt)
2866 @item @b{gdb-flash-erase-start}
2867 @* Before the GDB flash process tries to erase the flash
2868 @item @b{gdb-flash-erase-end}
2869 @* After the GDB flash process has finished erasing the flash
2870 @item @b{gdb-flash-write-start}
2871 @* Before GDB writes to the flash
2872 @item @b{gdb-flash-write-end}
2873 @* After GDB writes to the flash
2875 @* Before the target steps, gdb is trying to start/resume the target
2877 @* The target has halted
2879 @item @b{old-gdb_program_config}
2880 @* DO NOT USE THIS: Used internally
2881 @item @b{old-pre_resume}
2882 @* DO NOT USE THIS: Used internally
2884 @item @b{reset-assert-pre}
2885 @* Issued as part of @command{reset} processing
2886 after SRST and/or TRST were activated and deactivated,
2887 but before reset is asserted on the tap.
2888 @item @b{reset-assert-post}
2889 @* Issued as part of @command{reset} processing
2890 when reset is asserted on the tap.
2891 @item @b{reset-deassert-pre}
2892 @* Issued as part of @command{reset} processing
2893 when reset is about to be released on the tap.
2895 For some chips, this may be a good place to make sure
2896 the JTAG clock is slow enough to work before the PLL
2897 has been set up to allow faster JTAG speeds.
2898 @item @b{reset-deassert-post}
2899 @* Issued as part of @command{reset} processing
2900 when reset has been released on the tap.
2902 @* Issued as the final step in @command{reset} processing.
2904 @item @b{reset-halt-post}
2905 @* Currently not used
2906 @item @b{reset-halt-pre}
2907 @* Currently not used
2909 @item @b{reset-init}
2910 @* Used by @b{reset init} command for board-specific initialization.
2911 This event fires after @emph{reset-deassert-post}.
2913 This is where you would configure PLLs and clocking, set up DRAM so
2914 you can download programs that don't fit in on-chip SRAM, set up pin
2915 multiplexing, and so on.
2916 @item @b{reset-start}
2917 @* Issued as part of @command{reset} processing
2918 before either SRST or TRST are activated.
2920 @item @b{reset-wait-pos}
2921 @* Currently not used
2922 @item @b{reset-wait-pre}
2923 @* Currently not used
2925 @item @b{resume-start}
2926 @* Before any target is resumed
2927 @item @b{resume-end}
2928 @* After all targets have resumed
2932 @* Target has resumed
2936 @node Flash Commands
2937 @chapter Flash Commands
2939 OpenOCD has different commands for NOR and NAND flash;
2940 the ``flash'' command works with NOR flash, while
2941 the ``nand'' command works with NAND flash.
2942 This partially reflects different hardware technologies:
2943 NOR flash usually supports direct CPU instruction and data bus access,
2944 while data from a NAND flash must be copied to memory before it can be
2945 used. (SPI flash must also be copied to memory before use.)
2946 However, the documentation also uses ``flash'' as a generic term;
2947 for example, ``Put flash configuration in board-specific files''.
2951 @item Configure via the command @command{flash bank}
2952 @* Do this in a board-specific configuration file,
2953 passing parameters as needed by the driver.
2954 @item Operate on the flash via @command{flash subcommand}
2955 @* Often commands to manipulate the flash are typed by a human, or run
2956 via a script in some automated way. Common tasks include writing a
2957 boot loader, operating system, or other data.
2959 @* Flashing via GDB requires the flash be configured via ``flash
2960 bank'', and the GDB flash features be enabled.
2961 @xref{GDB Configuration}.
2964 Many CPUs have the ablity to ``boot'' from the first flash bank.
2965 This means that misprogramming that bank can ``brick'' a system,
2966 so that it can't boot.
2967 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2968 board by (re)installing working boot firmware.
2970 @anchor{NOR Configuration}
2971 @section Flash Configuration Commands
2972 @cindex flash configuration
2974 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2975 Configures a flash bank which provides persistent storage
2976 for addresses from @math{base} to @math{base + size - 1}.
2977 These banks will often be visible to GDB through the target's memory map.
2978 In some cases, configuring a flash bank will activate extra commands;
2979 see the driver-specific documentation.
2982 @item @var{driver} ... identifies the controller driver
2983 associated with the flash bank being declared.
2984 This is usually @code{cfi} for external flash, or else
2985 the name of a microcontroller with embedded flash memory.
2986 @xref{Flash Driver List}.
2987 @item @var{base} ... Base address of the flash chip.
2988 @item @var{size} ... Size of the chip, in bytes.
2989 For some drivers, this value is detected from the hardware.
2990 @item @var{chip_width} ... Width of the flash chip, in bytes;
2991 ignored for most microcontroller drivers.
2992 @item @var{bus_width} ... Width of the data bus used to access the
2993 chip, in bytes; ignored for most microcontroller drivers.
2994 @item @var{target} ... Names the target used to issue
2995 commands to the flash controller.
2996 @comment Actually, it's currently a controller-specific parameter...
2997 @item @var{driver_options} ... drivers may support, or require,
2998 additional parameters. See the driver-specific documentation
2999 for more information.
3002 This command is not available after OpenOCD initialization has completed.
3003 Use it in board specific configuration files, not interactively.
3007 @comment the REAL name for this command is "ocd_flash_banks"
3008 @comment less confusing would be: "flash list" (like "nand list")
3009 @deffn Command {flash banks}
3010 Prints a one-line summary of each device declared
3011 using @command{flash bank}, numbered from zero.
3012 Note that this is the @emph{plural} form;
3013 the @emph{singular} form is a very different command.
3016 @deffn Command {flash probe} num
3017 Identify the flash, or validate the parameters of the configured flash. Operation
3018 depends on the flash type.
3019 The @var{num} parameter is a value shown by @command{flash banks}.
3020 Most flash commands will implicitly @emph{autoprobe} the bank;
3021 flash drivers can distinguish between probing and autoprobing,
3022 but most don't bother.
3025 @section Erasing, Reading, Writing to Flash
3026 @cindex flash erasing
3027 @cindex flash reading
3028 @cindex flash writing
3029 @cindex flash programming
3031 One feature distinguishing NOR flash from NAND or serial flash technologies
3032 is that for read access, it acts exactly like any other addressible memory.
3033 This means you can use normal memory read commands like @command{mdw} or
3034 @command{dump_image} with it, with no special @command{flash} subcommands.
3035 @xref{Memory access}, and @ref{Image access}.
3037 Write access works differently. Flash memory normally needs to be erased
3038 before it's written. Erasing a sector turns all of its bits to ones, and
3039 writing can turn ones into zeroes. This is why there are special commands
3040 for interactive erasing and writing, and why GDB needs to know which parts
3041 of the address space hold NOR flash memory.
3044 Most of these erase and write commands leverage the fact that NOR flash
3045 chips consume target address space. They implicitly refer to the current
3046 JTAG target, and map from an address in that target's address space
3047 back to a flash bank.
3048 @comment In May 2009, those mappings may fail if any bank associated
3049 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3050 A few commands use abstract addressing based on bank and sector numbers,
3051 and don't depend on searching the current target and its address space.
3052 Avoid confusing the two command models.
3055 Some flash chips implement software protection against accidental writes,
3056 since such buggy writes could in some cases ``brick'' a system.
3057 For such systems, erasing and writing may require sector protection to be
3059 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3060 and AT91SAM7 on-chip flash.
3061 @xref{flash protect}.
3063 @anchor{flash erase_sector}
3064 @deffn Command {flash erase_sector} num first last
3065 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3066 @var{last}. Sector numbering starts at 0.
3067 The @var{num} parameter is a value shown by @command{flash banks}.
3070 @deffn Command {flash erase_address} address length
3071 Erase sectors starting at @var{address} for @var{length} bytes.
3072 The flash bank to use is inferred from the @var{address}, and
3073 the specified length must stay within that bank.
3074 As a special case, when @var{length} is zero and @var{address} is
3075 the start of the bank, the whole flash is erased.
3078 @deffn Command {flash fillw} address word length
3079 @deffnx Command {flash fillh} address halfword length
3080 @deffnx Command {flash fillb} address byte length
3081 Fills flash memory with the specified @var{word} (32 bits),
3082 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3083 starting at @var{address} and continuing
3084 for @var{length} units (word/halfword/byte).
3085 No erasure is done before writing; when needed, that must be done
3086 before issuing this command.
3087 Writes are done in blocks of up to 1024 bytes, and each write is
3088 verified by reading back the data and comparing it to what was written.
3089 The flash bank to use is inferred from the @var{address} of
3090 each block, and the specified length must stay within that bank.
3092 @comment no current checks for errors if fill blocks touch multiple banks!
3094 @anchor{flash write_bank}
3095 @deffn Command {flash write_bank} num filename offset
3096 Write the binary @file{filename} to flash bank @var{num},
3097 starting at @var{offset} bytes from the beginning of the bank.
3098 The @var{num} parameter is a value shown by @command{flash banks}.
3101 @anchor{flash write_image}
3102 @deffn Command {flash write_image} [erase] filename [offset] [type]
3103 Write the image @file{filename} to the current target's flash bank(s).
3104 A relocation @var{offset} may be specified, in which case it is added
3105 to the base address for each section in the image.
3106 The file [@var{type}] can be specified
3107 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3108 @option{elf} (ELF file), @option{s19} (Motorola s19).
3109 @option{mem}, or @option{builder}.
3110 The relevant flash sectors will be erased prior to programming
3111 if the @option{erase} parameter is given.
3112 The flash bank to use is inferred from the @var{address} of
3116 @section Other Flash commands
3117 @cindex flash protection
3119 @deffn Command {flash erase_check} num
3120 Check erase state of sectors in flash bank @var{num},
3121 and display that status.
3122 The @var{num} parameter is a value shown by @command{flash banks}.
3123 This is the only operation that
3124 updates the erase state information displayed by @option{flash info}. That means you have
3125 to issue an @command{flash erase_check} command after erasing or programming the device
3126 to get updated information.
3127 (Code execution may have invalidated any state records kept by OpenOCD.)
3130 @deffn Command {flash info} num
3131 Print info about flash bank @var{num}
3132 The @var{num} parameter is a value shown by @command{flash banks}.
3133 The information includes per-sector protect status.
3136 @anchor{flash protect}
3137 @deffn Command {flash protect} num first last (on|off)
3138 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3139 @var{first} to @var{last} of flash bank @var{num}.
3140 The @var{num} parameter is a value shown by @command{flash banks}.
3143 @deffn Command {flash protect_check} num
3144 Check protection state of sectors in flash bank @var{num}.
3145 The @var{num} parameter is a value shown by @command{flash banks}.
3146 @comment @option{flash erase_sector} using the same syntax.
3149 @anchor{Flash Driver List}
3150 @section Flash Drivers, Options, and Commands
3151 As noted above, the @command{flash bank} command requires a driver name,
3152 and allows driver-specific options and behaviors.
3153 Some drivers also activate driver-specific commands.
3155 @subsection External Flash
3157 @deffn {Flash Driver} cfi
3158 @cindex Common Flash Interface
3160 The ``Common Flash Interface'' (CFI) is the main standard for
3161 external NOR flash chips, each of which connects to a
3162 specific external chip select on the CPU.
3163 Frequently the first such chip is used to boot the system.
3164 Your board's @code{reset-init} handler might need to
3165 configure additional chip selects using other commands (like: @command{mww} to
3166 configure a bus and its timings) , or
3167 perhaps configure a GPIO pin that controls the ``write protect'' pin
3169 The CFI driver can use a target-specific working area to significantly
3172 The CFI driver can accept the following optional parameters, in any order:
3175 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3176 like AM29LV010 and similar types.
3177 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3180 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3181 wide on a sixteen bit bus:
3184 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3185 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3187 @c "cfi part_id" disabled
3190 @subsection Internal Flash (Microcontrollers)
3192 @deffn {Flash Driver} aduc702x
3193 The ADUC702x analog microcontrollers from Analog Devices
3194 include internal flash and use ARM7TDMI cores.
3195 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3196 The setup command only requires the @var{target} argument
3197 since all devices in this family have the same memory layout.
3200 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3204 @deffn {Flash Driver} at91sam3
3206 All members of the AT91SAM3 microcontroller family from
3207 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3208 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3209 that the driver was orginaly developed and tested using the
3210 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3211 the family was cribbed from the data sheet. @emph{Note to future
3212 readers/updaters: Please remove this worrysome comment after other
3213 chips are confirmed.}
3215 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3216 have one flash bank. In all cases the flash banks are at
3217 the following fixed locations:
3220 # Flash bank 0 - all chips
3221 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3222 # Flash bank 1 - only 256K chips
3223 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3226 Internally, the AT91SAM3 flash memory is organized as follows.
3227 Unlike the AT91SAM7 chips, these are not used as parameters
3228 to the @command{flash bank} command:
3231 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3232 @item @emph{Bank Size:} 128K/64K Per flash bank
3233 @item @emph{Sectors:} 16 or 8 per bank
3234 @item @emph{SectorSize:} 8K Per Sector
3235 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3238 The AT91SAM3 driver adds some additional commands:
3240 @deffn Command {at91sam3 gpnvm}
3241 @deffnx Command {at91sam3 gpnvm clear} number
3242 @deffnx Command {at91sam3 gpnvm set} number
3243 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3244 With no parameters, @command{show} or @command{show all},
3245 shows the status of all GPNVM bits.
3246 With @command{show} @var{number}, displays that bit.
3248 With @command{set} @var{number} or @command{clear} @var{number},
3249 modifies that GPNVM bit.
3252 @deffn Command {at91sam3 info}
3253 This command attempts to display information about the AT91SAM3
3254 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3255 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3256 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3257 various clock configuration registers and attempts to display how it
3258 believes the chip is configured. By default, the SLOWCLK is assumed to
3259 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3262 @deffn Command {at91sam3 slowclk} [value]
3263 This command shows/sets the slow clock frequency used in the
3264 @command{at91sam3 info} command calculations above.
3268 @deffn {Flash Driver} at91sam7
3269 All members of the AT91SAM7 microcontroller family from Atmel include
3270 internal flash and use ARM7TDMI cores. The driver automatically
3271 recognizes a number of these chips using the chip identification
3272 register, and autoconfigures itself.
3275 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3278 For chips which are not recognized by the controller driver, you must
3279 provide additional parameters in the following order:
3282 @item @var{chip_model} ... label used with @command{flash info}
3284 @item @var{sectors_per_bank}
3285 @item @var{pages_per_sector}
3286 @item @var{pages_size}
3287 @item @var{num_nvm_bits}
3288 @item @var{freq_khz} ... required if an external clock is provided,
3289 optional (but recommended) when the oscillator frequency is known
3292 It is recommended that you provide zeroes for all of those values
3293 except the clock frequency, so that everything except that frequency
3294 will be autoconfigured.
3295 Knowing the frequency helps ensure correct timings for flash access.
3297 The flash controller handles erases automatically on a page (128/256 byte)
3298 basis, so explicit erase commands are not necessary for flash programming.
3299 However, there is an ``EraseAll`` command that can erase an entire flash
3300 plane (of up to 256KB), and it will be used automatically when you issue
3301 @command{flash erase_sector} or @command{flash erase_address} commands.
3303 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3304 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3305 bit for the processor. Each processor has a number of such bits,
3306 used for controlling features such as brownout detection (so they
3307 are not truly general purpose).
3309 This assumes that the first flash bank (number 0) is associated with
3310 the appropriate at91sam7 target.
3315 @deffn {Flash Driver} avr
3316 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3317 @emph{The current implementation is incomplete.}
3318 @comment - defines mass_erase ... pointless given flash_erase_address
3321 @deffn {Flash Driver} ecosflash
3322 @emph{No idea what this is...}
3323 The @var{ecosflash} driver defines one mandatory parameter,
3324 the name of a modules of target code which is downloaded
3328 @deffn {Flash Driver} lpc2000
3329 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3330 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3333 There are LPC2000 devices which are not supported by the @var{lpc2000}
3335 The LPC2888 is supported by the @var{lpc288x} driver.
3336 The LPC29xx family is supported by the @var{lpc2900} driver.
3339 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3340 which must appear in the following order:
3343 @item @var{variant} ... required, may be
3344 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3345 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3346 or @var{lpc1700} (LPC175x and LPC176x)
3347 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3348 at which the core is running
3349 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3350 telling the driver to calculate a valid checksum for the exception vector table.
3353 LPC flashes don't require the chip and bus width to be specified.
3356 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3357 lpc2000_v2 14765 calc_checksum
3360 @deffn {Command} {lpc2000 part_id} bank
3361 Displays the four byte part identifier associated with
3362 the specified flash @var{bank}.
3366 @deffn {Flash Driver} lpc288x
3367 The LPC2888 microcontroller from NXP needs slightly different flash
3368 support from its lpc2000 siblings.
3369 The @var{lpc288x} driver defines one mandatory parameter,
3370 the programming clock rate in Hz.
3371 LPC flashes don't require the chip and bus width to be specified.
3374 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3378 @deffn {Flash Driver} lpc2900
3379 This driver supports the LPC29xx ARM968E based microcontroller family
3382 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3383 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3384 sector layout are auto-configured by the driver.
3385 The driver has one additional mandatory parameter: The CPU clock rate
3386 (in kHz) at the time the flash operations will take place. Most of the time this
3387 will not be the crystal frequency, but a higher PLL frequency. The
3388 @code{reset-init} event handler in the board script is usually the place where
3391 The driver rejects flashless devices (currently the LPC2930).
3393 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3394 It must be handled much more like NAND flash memory, and will therefore be
3395 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3397 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3398 sector needs to be erased or programmed, it is automatically unprotected.
3399 What is shown as protection status in the @code{flash info} command, is
3400 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3401 sector from ever being erased or programmed again. As this is an irreversible
3402 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3403 and not by the standard @code{flash protect} command.
3405 Example for a 125 MHz clock frequency:
3407 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3410 Some @code{lpc2900}-specific commands are defined. In the following command list,
3411 the @var{bank} parameter is the bank number as obtained by the
3412 @code{flash banks} command.
3414 @deffn Command {lpc2900 signature} bank
3415 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3416 content. This is a hardware feature of the flash block, hence the calculation is
3417 very fast. You may use this to verify the content of a programmed device against
3422 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3426 @deffn Command {lpc2900 read_custom} bank filename
3427 Reads the 912 bytes of customer information from the flash index sector, and
3428 saves it to a file in binary format.
3431 lpc2900 read_custom 0 /path_to/customer_info.bin
3435 The index sector of the flash is a @emph{write-only} sector. It cannot be
3436 erased! In order to guard against unintentional write access, all following
3437 commands need to be preceeded by a successful call to the @code{password}
3440 @deffn Command {lpc2900 password} bank password
3441 You need to use this command right before each of the following commands:
3442 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3443 @code{lpc2900 secure_jtag}.
3445 The password string is fixed to "I_know_what_I_am_doing".
3448 lpc2900 password 0 I_know_what_I_am_doing
3449 Potentially dangerous operation allowed in next command!
3453 @deffn Command {lpc2900 write_custom} bank filename type
3454 Writes the content of the file into the customer info space of the flash index
3455 sector. The filetype can be specified with the @var{type} field. Possible values
3456 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3457 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3458 contain a single section, and the contained data length must be exactly
3460 @quotation Attention
3461 This cannot be reverted! Be careful!
3465 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3469 @deffn Command {lpc2900 secure_sector} bank first last
3470 Secures the sector range from @var{first} to @var{last} (including) against
3471 further program and erase operations. The sector security will be effective
3472 after the next power cycle.
3473 @quotation Attention
3474 This cannot be reverted! Be careful!
3476 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3479 lpc2900 secure_sector 0 1 1
3481 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3482 # 0: 0x00000000 (0x2000 8kB) not protected
3483 # 1: 0x00002000 (0x2000 8kB) protected
3484 # 2: 0x00004000 (0x2000 8kB) not protected
3488 @deffn Command {lpc2900 secure_jtag} bank
3489 Irreversibly disable the JTAG port. The new JTAG security setting will be
3490 effective after the next power cycle.
3491 @quotation Attention
3492 This cannot be reverted! Be careful!
3496 lpc2900 secure_jtag 0
3501 @deffn {Flash Driver} ocl
3502 @emph{No idea what this is, other than using some arm7/arm9 core.}
3505 flash bank ocl 0 0 0 0 $_TARGETNAME
3509 @deffn {Flash Driver} pic32mx
3510 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3511 and integrate flash memory.
3512 @emph{The current implementation is incomplete.}
3515 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3518 @comment numerous *disabled* commands are defined:
3519 @comment - chip_erase ... pointless given flash_erase_address
3520 @comment - lock, unlock ... pointless given protect on/off (yes?)
3521 @comment - pgm_word ... shouldn't bank be deduced from address??
3522 Some pic32mx-specific commands are defined:
3523 @deffn Command {pic32mx pgm_word} address value bank
3524 Programs the specified 32-bit @var{value} at the given @var{address}
3525 in the specified chip @var{bank}.
3529 @deffn {Flash Driver} stellaris
3530 All members of the Stellaris LM3Sxxx microcontroller family from
3532 include internal flash and use ARM Cortex M3 cores.
3533 The driver automatically recognizes a number of these chips using
3534 the chip identification register, and autoconfigures itself.
3535 @footnote{Currently there is a @command{stellaris mass_erase} command.
3536 That seems pointless since the same effect can be had using the
3537 standard @command{flash erase_address} command.}
3540 flash bank stellaris 0 0 0 0 $_TARGETNAME
3544 @deffn {Flash Driver} stm32x
3545 All members of the STM32 microcontroller family from ST Microelectronics
3546 include internal flash and use ARM Cortex M3 cores.
3547 The driver automatically recognizes a number of these chips using
3548 the chip identification register, and autoconfigures itself.
3551 flash bank stm32x 0 0 0 0 $_TARGETNAME
3554 Some stm32x-specific commands
3555 @footnote{Currently there is a @command{stm32x mass_erase} command.
3556 That seems pointless since the same effect can be had using the
3557 standard @command{flash erase_address} command.}
3560 @deffn Command {stm32x lock} num
3561 Locks the entire stm32 device.
3562 The @var{num} parameter is a value shown by @command{flash banks}.
3565 @deffn Command {stm32x unlock} num
3566 Unlocks the entire stm32 device.
3567 The @var{num} parameter is a value shown by @command{flash banks}.
3570 @deffn Command {stm32x options_read} num
3571 Read and display the stm32 option bytes written by
3572 the @command{stm32x options_write} command.
3573 The @var{num} parameter is a value shown by @command{flash banks}.
3576 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3577 Writes the stm32 option byte with the specified values.
3578 The @var{num} parameter is a value shown by @command{flash banks}.
3582 @deffn {Flash Driver} str7x
3583 All members of the STR7 microcontroller family from ST Microelectronics
3584 include internal flash and use ARM7TDMI cores.
3585 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3586 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3589 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3592 @deffn Command {str7x disable_jtag} bank
3593 Activate the Debug/Readout protection mechanism
3594 for the specified flash bank.
3598 @deffn {Flash Driver} str9x
3599 Most members of the STR9 microcontroller family from ST Microelectronics
3600 include internal flash and use ARM966E cores.
3601 The str9 needs the flash controller to be configured using
3602 the @command{str9x flash_config} command prior to Flash programming.
3605 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3606 str9x flash_config 0 4 2 0 0x80000
3609 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3610 Configures the str9 flash controller.
3611 The @var{num} parameter is a value shown by @command{flash banks}.
3614 @item @var{bbsr} - Boot Bank Size register
3615 @item @var{nbbsr} - Non Boot Bank Size register
3616 @item @var{bbadr} - Boot Bank Start Address register
3617 @item @var{nbbadr} - Boot Bank Start Address register
3623 @deffn {Flash Driver} tms470
3624 Most members of the TMS470 microcontroller family from Texas Instruments
3625 include internal flash and use ARM7TDMI cores.
3626 This driver doesn't require the chip and bus width to be specified.
3628 Some tms470-specific commands are defined:
3630 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3631 Saves programming keys in a register, to enable flash erase and write commands.
3634 @deffn Command {tms470 osc_mhz} clock_mhz
3635 Reports the clock speed, which is used to calculate timings.
3638 @deffn Command {tms470 plldis} (0|1)
3639 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3644 @subsection str9xpec driver
3647 Here is some background info to help
3648 you better understand how this driver works. OpenOCD has two flash drivers for
3652 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3653 flash programming as it is faster than the @option{str9xpec} driver.
3655 Direct programming @option{str9xpec} using the flash controller. This is an
3656 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3657 core does not need to be running to program using this flash driver. Typical use
3658 for this driver is locking/unlocking the target and programming the option bytes.
3661 Before we run any commands using the @option{str9xpec} driver we must first disable
3662 the str9 core. This example assumes the @option{str9xpec} driver has been
3663 configured for flash bank 0.
3665 # assert srst, we do not want core running
3666 # while accessing str9xpec flash driver
3668 # turn off target polling
3671 str9xpec enable_turbo 0
3673 str9xpec options_read 0
3674 # re-enable str9 core
3675 str9xpec disable_turbo 0
3679 The above example will read the str9 option bytes.
3680 When performing a unlock remember that you will not be able to halt the str9 - it
3681 has been locked. Halting the core is not required for the @option{str9xpec} driver
3682 as mentioned above, just issue the commands above manually or from a telnet prompt.
3684 @deffn {Flash Driver} str9xpec
3685 Only use this driver for locking/unlocking the device or configuring the option bytes.
3686 Use the standard str9 driver for programming.
3687 Before using the flash commands the turbo mode must be enabled using the
3688 @command{str9xpec enable_turbo} command.
3690 Several str9xpec-specific commands are defined:
3692 @deffn Command {str9xpec disable_turbo} num
3693 Restore the str9 into JTAG chain.
3696 @deffn Command {str9xpec enable_turbo} num
3697 Enable turbo mode, will simply remove the str9 from the chain and talk
3698 directly to the embedded flash controller.
3701 @deffn Command {str9xpec lock} num
3702 Lock str9 device. The str9 will only respond to an unlock command that will
3706 @deffn Command {str9xpec part_id} num
3707 Prints the part identifier for bank @var{num}.
3710 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3711 Configure str9 boot bank.
3714 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3715 Configure str9 lvd source.
3718 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3719 Configure str9 lvd threshold.
3722 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3723 Configure str9 lvd reset warning source.
3726 @deffn Command {str9xpec options_read} num
3727 Read str9 option bytes.
3730 @deffn Command {str9xpec options_write} num
3731 Write str9 option bytes.
3734 @deffn Command {str9xpec unlock} num
3743 @subsection mFlash Configuration
3744 @cindex mFlash Configuration
3746 @deffn {Config Command} {mflash bank} soc base RST_pin target
3747 Configures a mflash for @var{soc} host bank at
3749 The pin number format depends on the host GPIO naming convention.
3750 Currently, the mflash driver supports s3c2440 and pxa270.
3752 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3755 mflash bank s3c2440 0x10000000 1b 0
3758 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3761 mflash bank pxa270 0x08000000 43 0
3765 @subsection mFlash commands
3766 @cindex mFlash commands
3768 @deffn Command {mflash config pll} frequency
3769 Configure mflash PLL.
3770 The @var{frequency} is the mflash input frequency, in Hz.
3771 Issuing this command will erase mflash's whole internal nand and write new pll.
3772 After this command, mflash needs power-on-reset for normal operation.
3773 If pll was newly configured, storage and boot(optional) info also need to be update.
3776 @deffn Command {mflash config boot}
3777 Configure bootable option.
3778 If bootable option is set, mflash offer the first 8 sectors
3782 @deffn Command {mflash config storage}
3783 Configure storage information.
3784 For the normal storage operation, this information must be
3788 @deffn Command {mflash dump} num filename offset size
3789 Dump @var{size} bytes, starting at @var{offset} bytes from the
3790 beginning of the bank @var{num}, to the file named @var{filename}.
3793 @deffn Command {mflash probe}
3797 @deffn Command {mflash write} num filename offset
3798 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3799 @var{offset} bytes from the beginning of the bank.
3802 @node NAND Flash Commands
3803 @chapter NAND Flash Commands
3806 Compared to NOR or SPI flash, NAND devices are inexpensive
3807 and high density. Today's NAND chips, and multi-chip modules,
3808 commonly hold multiple GigaBytes of data.
3810 NAND chips consist of a number of ``erase blocks'' of a given
3811 size (such as 128 KBytes), each of which is divided into a
3812 number of pages (of perhaps 512 or 2048 bytes each). Each
3813 page of a NAND flash has an ``out of band'' (OOB) area to hold
3814 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3815 of OOB for every 512 bytes of page data.
3817 One key characteristic of NAND flash is that its error rate
3818 is higher than that of NOR flash. In normal operation, that
3819 ECC is used to correct and detect errors. However, NAND
3820 blocks can also wear out and become unusable; those blocks
3821 are then marked "bad". NAND chips are even shipped from the
3822 manufacturer with a few bad blocks. The highest density chips
3823 use a technology (MLC) that wears out more quickly, so ECC
3824 support is increasingly important as a way to detect blocks
3825 that have begun to fail, and help to preserve data integrity
3826 with techniques such as wear leveling.
3828 Software is used to manage the ECC. Some controllers don't
3829 support ECC directly; in those cases, software ECC is used.
3830 Other controllers speed up the ECC calculations with hardware.
3831 Single-bit error correction hardware is routine. Controllers
3832 geared for newer MLC chips may correct 4 or more errors for
3833 every 512 bytes of data.
3835 You will need to make sure that any data you write using
3836 OpenOCD includes the apppropriate kind of ECC. For example,
3837 that may mean passing the @code{oob_softecc} flag when
3838 writing NAND data, or ensuring that the correct hardware
3841 The basic steps for using NAND devices include:
3843 @item Declare via the command @command{nand device}
3844 @* Do this in a board-specific configuration file,
3845 passing parameters as needed by the controller.
3846 @item Configure each device using @command{nand probe}.
3847 @* Do this only after the associated target is set up,
3848 such as in its reset-init script or in procures defined
3849 to access that device.
3850 @item Operate on the flash via @command{nand subcommand}
3851 @* Often commands to manipulate the flash are typed by a human, or run
3852 via a script in some automated way. Common task include writing a
3853 boot loader, operating system, or other data needed to initialize or
3857 @b{NOTE:} At the time this text was written, the largest NAND
3858 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3859 This is because the variables used to hold offsets and lengths
3860 are only 32 bits wide.
3861 (Larger chips may work in some cases, unless an offset or length
3862 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3863 Some larger devices will work, since they are actually multi-chip
3864 modules with two smaller chips and individual chipselect lines.
3866 @anchor{NAND Configuration}
3867 @section NAND Configuration Commands
3868 @cindex NAND configuration
3870 NAND chips must be declared in configuration scripts,
3871 plus some additional configuration that's done after
3872 OpenOCD has initialized.
3874 @deffn {Config Command} {nand device} controller target [configparams...]
3875 Declares a NAND device, which can be read and written to
3876 after it has been configured through @command{nand probe}.
3877 In OpenOCD, devices are single chips; this is unlike some
3878 operating systems, which may manage multiple chips as if
3879 they were a single (larger) device.
3880 In some cases, configuring a device will activate extra
3881 commands; see the controller-specific documentation.
3883 @b{NOTE:} This command is not available after OpenOCD
3884 initialization has completed. Use it in board specific
3885 configuration files, not interactively.
3888 @item @var{controller} ... identifies the controller driver
3889 associated with the NAND device being declared.
3890 @xref{NAND Driver List}.
3891 @item @var{target} ... names the target used when issuing
3892 commands to the NAND controller.
3893 @comment Actually, it's currently a controller-specific parameter...
3894 @item @var{configparams} ... controllers may support, or require,
3895 additional parameters. See the controller-specific documentation
3896 for more information.
3900 @deffn Command {nand list}
3901 Prints a summary of each device declared
3902 using @command{nand device}, numbered from zero.
3903 Note that un-probed devices show no details.
3906 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3907 blocksize: 131072, blocks: 8192
3908 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3909 blocksize: 131072, blocks: 8192
3914 @deffn Command {nand probe} num
3915 Probes the specified device to determine key characteristics
3916 like its page and block sizes, and how many blocks it has.
3917 The @var{num} parameter is the value shown by @command{nand list}.
3918 You must (successfully) probe a device before you can use
3919 it with most other NAND commands.
3922 @section Erasing, Reading, Writing to NAND Flash
3924 @deffn Command {nand dump} num filename offset length [oob_option]
3925 @cindex NAND reading
3926 Reads binary data from the NAND device and writes it to the file,
3927 starting at the specified offset.
3928 The @var{num} parameter is the value shown by @command{nand list}.
3930 Use a complete path name for @var{filename}, so you don't depend
3931 on the directory used to start the OpenOCD server.
3933 The @var{offset} and @var{length} must be exact multiples of the
3934 device's page size. They describe a data region; the OOB data
3935 associated with each such page may also be accessed.
3937 @b{NOTE:} At the time this text was written, no error correction
3938 was done on the data that's read, unless raw access was disabled
3939 and the underlying NAND controller driver had a @code{read_page}
3940 method which handled that error correction.
3942 By default, only page data is saved to the specified file.
3943 Use an @var{oob_option} parameter to save OOB data:
3945 @item no oob_* parameter
3946 @*Output file holds only page data; OOB is discarded.
3947 @item @code{oob_raw}
3948 @*Output file interleaves page data and OOB data;
3949 the file will be longer than "length" by the size of the
3950 spare areas associated with each data page.
3951 Note that this kind of "raw" access is different from
3952 what's implied by @command{nand raw_access}, which just
3953 controls whether a hardware-aware access method is used.
3954 @item @code{oob_only}
3955 @*Output file has only raw OOB data, and will
3956 be smaller than "length" since it will contain only the
3957 spare areas associated with each data page.
3961 @deffn Command {nand erase} num [offset length]
3962 @cindex NAND erasing
3963 @cindex NAND programming
3964 Erases blocks on the specified NAND device, starting at the
3965 specified @var{offset} and continuing for @var{length} bytes.
3966 Both of those values must be exact multiples of the device's
3967 block size, and the region they specify must fit entirely in the chip.
3968 If those parameters are not specified,
3969 the whole NAND chip will be erased.
3970 The @var{num} parameter is the value shown by @command{nand list}.
3972 @b{NOTE:} This command will try to erase bad blocks, when told
3973 to do so, which will probably invalidate the manufacturer's bad
3975 For the remainder of the current server session, @command{nand info}
3976 will still report that the block ``is'' bad.
3979 @deffn Command {nand write} num filename offset [option...]
3980 @cindex NAND writing
3981 @cindex NAND programming
3982 Writes binary data from the file into the specified NAND device,
3983 starting at the specified offset. Those pages should already
3984 have been erased; you can't change zero bits to one bits.
3985 The @var{num} parameter is the value shown by @command{nand list}.
3987 Use a complete path name for @var{filename}, so you don't depend
3988 on the directory used to start the OpenOCD server.
3990 The @var{offset} must be an exact multiple of the device's page size.
3991 All data in the file will be written, assuming it doesn't run
3992 past the end of the device.
3993 Only full pages are written, and any extra space in the last
3994 page will be filled with 0xff bytes. (That includes OOB data,
3995 if that's being written.)
3997 @b{NOTE:} At the time this text was written, bad blocks are
3998 ignored. That is, this routine will not skip bad blocks,
3999 but will instead try to write them. This can cause problems.
4001 Provide at most one @var{option} parameter. With some
4002 NAND drivers, the meanings of these parameters may change
4003 if @command{nand raw_access} was used to disable hardware ECC.
4005 @item no oob_* parameter
4006 @*File has only page data, which is written.
4007 If raw acccess is in use, the OOB area will not be written.
4008 Otherwise, if the underlying NAND controller driver has
4009 a @code{write_page} routine, that routine may write the OOB
4010 with hardware-computed ECC data.
4011 @item @code{oob_only}
4012 @*File has only raw OOB data, which is written to the OOB area.
4013 Each page's data area stays untouched. @i{This can be a dangerous
4014 option}, since it can invalidate the ECC data.
4015 You may need to force raw access to use this mode.
4016 @item @code{oob_raw}
4017 @*File interleaves data and OOB data, both of which are written
4018 If raw access is enabled, the data is written first, then the
4020 Otherwise, if the underlying NAND controller driver has
4021 a @code{write_page} routine, that routine may modify the OOB
4022 before it's written, to include hardware-computed ECC data.
4023 @item @code{oob_softecc}
4024 @*File has only page data, which is written.
4025 The OOB area is filled with 0xff, except for a standard 1-bit
4026 software ECC code stored in conventional locations.
4027 You might need to force raw access to use this mode, to prevent
4028 the underlying driver from applying hardware ECC.
4029 @item @code{oob_softecc_kw}
4030 @*File has only page data, which is written.
4031 The OOB area is filled with 0xff, except for a 4-bit software ECC
4032 specific to the boot ROM in Marvell Kirkwood SoCs.
4033 You might need to force raw access to use this mode, to prevent
4034 the underlying driver from applying hardware ECC.
4038 @section Other NAND commands
4039 @cindex NAND other commands
4041 @deffn Command {nand check_bad_blocks} [offset length]
4042 Checks for manufacturer bad block markers on the specified NAND
4043 device. If no parameters are provided, checks the whole
4044 device; otherwise, starts at the specified @var{offset} and
4045 continues for @var{length} bytes.
4046 Both of those values must be exact multiples of the device's
4047 block size, and the region they specify must fit entirely in the chip.
4048 The @var{num} parameter is the value shown by @command{nand list}.
4050 @b{NOTE:} Before using this command you should force raw access
4051 with @command{nand raw_access enable} to ensure that the underlying
4052 driver will not try to apply hardware ECC.
4055 @deffn Command {nand info} num
4056 The @var{num} parameter is the value shown by @command{nand list}.
4057 This prints the one-line summary from "nand list", plus for
4058 devices which have been probed this also prints any known
4059 status for each block.
4062 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4063 Sets or clears an flag affecting how page I/O is done.
4064 The @var{num} parameter is the value shown by @command{nand list}.
4066 This flag is cleared (disabled) by default, but changing that
4067 value won't affect all NAND devices. The key factor is whether
4068 the underlying driver provides @code{read_page} or @code{write_page}
4069 methods. If it doesn't provide those methods, the setting of
4070 this flag is irrelevant; all access is effectively ``raw''.
4072 When those methods exist, they are normally used when reading
4073 data (@command{nand dump} or reading bad block markers) or
4074 writing it (@command{nand write}). However, enabling
4075 raw access (setting the flag) prevents use of those methods,
4076 bypassing hardware ECC logic.
4077 @i{This can be a dangerous option}, since writing blocks
4078 with the wrong ECC data can cause them to be marked as bad.
4081 @anchor{NAND Driver List}
4082 @section NAND Drivers, Options, and Commands
4083 As noted above, the @command{nand device} command allows
4084 driver-specific options and behaviors.
4085 Some controllers also activate controller-specific commands.
4087 @deffn {NAND Driver} davinci
4088 This driver handles the NAND controllers found on DaVinci family
4089 chips from Texas Instruments.
4090 It takes three extra parameters:
4091 address of the NAND chip;
4092 hardware ECC mode to use (@option{hwecc1},
4093 @option{hwecc4}, @option{hwecc4_infix});
4094 address of the AEMIF controller on this processor.
4096 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4098 All DaVinci processors support the single-bit ECC hardware,
4099 and newer ones also support the four-bit ECC hardware.
4100 The @code{write_page} and @code{read_page} methods are used
4101 to implement those ECC modes, unless they are disabled using
4102 the @command{nand raw_access} command.
4105 @deffn {NAND Driver} lpc3180
4106 These controllers require an extra @command{nand device}
4107 parameter: the clock rate used by the controller.
4108 @deffn Command {lpc3180 select} num [mlc|slc]
4109 Configures use of the MLC or SLC controller mode.
4110 MLC implies use of hardware ECC.
4111 The @var{num} parameter is the value shown by @command{nand list}.
4114 At this writing, this driver includes @code{write_page}
4115 and @code{read_page} methods. Using @command{nand raw_access}
4116 to disable those methods will prevent use of hardware ECC
4117 in the MLC controller mode, but won't change SLC behavior.
4119 @comment current lpc3180 code won't issue 5-byte address cycles
4121 @deffn {NAND Driver} orion
4122 These controllers require an extra @command{nand device}
4123 parameter: the address of the controller.
4125 nand device orion 0xd8000000
4127 These controllers don't define any specialized commands.
4128 At this writing, their drivers don't include @code{write_page}
4129 or @code{read_page} methods, so @command{nand raw_access} won't
4130 change any behavior.
4133 @deffn {NAND Driver} s3c2410
4134 @deffnx {NAND Driver} s3c2412
4135 @deffnx {NAND Driver} s3c2440
4136 @deffnx {NAND Driver} s3c2443
4137 These S3C24xx family controllers don't have any special
4138 @command{nand device} options, and don't define any
4139 specialized commands.
4140 At this writing, their drivers don't include @code{write_page}
4141 or @code{read_page} methods, so @command{nand raw_access} won't
4142 change any behavior.
4145 @node PLD/FPGA Commands
4146 @chapter PLD/FPGA Commands
4150 Programmable Logic Devices (PLDs) and the more flexible
4151 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4152 OpenOCD can support programming them.
4153 Although PLDs are generally restrictive (cells are less functional, and
4154 there are no special purpose cells for memory or computational tasks),
4155 they share the same OpenOCD infrastructure.
4156 Accordingly, both are called PLDs here.
4158 @section PLD/FPGA Configuration and Commands
4160 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4161 OpenOCD maintains a list of PLDs available for use in various commands.
4162 Also, each such PLD requires a driver.
4164 They are referenced by the number shown by the @command{pld devices} command,
4165 and new PLDs are defined by @command{pld device driver_name}.
4167 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4168 Defines a new PLD device, supported by driver @var{driver_name},
4169 using the TAP named @var{tap_name}.
4170 The driver may make use of any @var{driver_options} to configure its
4174 @deffn {Command} {pld devices}
4175 Lists the PLDs and their numbers.
4178 @deffn {Command} {pld load} num filename
4179 Loads the file @file{filename} into the PLD identified by @var{num}.
4180 The file format must be inferred by the driver.
4183 @section PLD/FPGA Drivers, Options, and Commands
4185 Drivers may support PLD-specific options to the @command{pld device}
4186 definition command, and may also define commands usable only with
4187 that particular type of PLD.
4189 @deffn {FPGA Driver} virtex2
4190 Virtex-II is a family of FPGAs sold by Xilinx.
4191 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4192 No driver-specific PLD definition options are used,
4193 and one driver-specific command is defined.
4195 @deffn {Command} {virtex2 read_stat} num
4196 Reads and displays the Virtex-II status register (STAT)
4201 @node General Commands
4202 @chapter General Commands
4205 The commands documented in this chapter here are common commands that
4206 you, as a human, may want to type and see the output of. Configuration type
4207 commands are documented elsewhere.
4211 @item @b{Source Of Commands}
4212 @* OpenOCD commands can occur in a configuration script (discussed
4213 elsewhere) or typed manually by a human or supplied programatically,
4214 or via one of several TCP/IP Ports.
4216 @item @b{From the human}
4217 @* A human should interact with the telnet interface (default port: 4444)
4218 or via GDB (default port 3333).
4220 To issue commands from within a GDB session, use the @option{monitor}
4221 command, e.g. use @option{monitor poll} to issue the @option{poll}
4222 command. All output is relayed through the GDB session.
4224 @item @b{Machine Interface}
4225 The Tcl interface's intent is to be a machine interface. The default Tcl
4230 @section Daemon Commands
4232 @deffn {Command} exit
4233 Exits the current telnet session.
4236 @c note EXTREMELY ANNOYING word wrap at column 75
4237 @c even when lines are e.g. 100+ columns ...
4238 @c coded in startup.tcl
4239 @deffn {Command} help [string]
4240 With no parameters, prints help text for all commands.
4241 Otherwise, prints each helptext containing @var{string}.
4242 Not every command provides helptext.
4245 @deffn Command sleep msec [@option{busy}]
4246 Wait for at least @var{msec} milliseconds before resuming.
4247 If @option{busy} is passed, busy-wait instead of sleeping.
4248 (This option is strongly discouraged.)
4249 Useful in connection with script files
4250 (@command{script} command and @command{target_name} configuration).
4253 @deffn Command shutdown
4254 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4257 @anchor{debug_level}
4258 @deffn Command debug_level [n]
4259 @cindex message level
4260 Display debug level.
4261 If @var{n} (from 0..3) is provided, then set it to that level.
4262 This affects the kind of messages sent to the server log.
4263 Level 0 is error messages only;
4264 level 1 adds warnings;
4265 level 2 adds informational messages;
4266 and level 3 adds debugging messages.
4267 The default is level 2, but that can be overridden on
4268 the command line along with the location of that log
4269 file (which is normally the server's standard output).
4273 @deffn Command fast (@option{enable}|@option{disable})
4275 Set default behaviour of OpenOCD to be "fast and dangerous".
4277 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4278 fast memory access, and DCC downloads. Those parameters may still be
4279 individually overridden.
4281 The target specific "dangerous" optimisation tweaking options may come and go
4282 as more robust and user friendly ways are found to ensure maximum throughput
4283 and robustness with a minimum of configuration.
4285 Typically the "fast enable" is specified first on the command line:
4288 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4292 @deffn Command echo message
4293 Logs a message at "user" priority.
4294 Output @var{message} to stdout.
4296 echo "Downloading kernel -- please wait"
4300 @deffn Command log_output [filename]
4301 Redirect logging to @var{filename};
4302 the initial log output channel is stderr.
4305 @anchor{Target State handling}
4306 @section Target State handling
4309 @cindex target initialization
4311 In this section ``target'' refers to a CPU configured as
4312 shown earlier (@pxref{CPU Configuration}).
4313 These commands, like many, implicitly refer to
4314 a current target which is used to perform the
4315 various operations. The current target may be changed
4316 by using @command{targets} command with the name of the
4317 target which should become current.
4319 @deffn Command reg [(number|name) [value]]
4320 Access a single register by @var{number} or by its @var{name}.
4322 @emph{With no arguments}:
4323 list all available registers for the current target,
4324 showing number, name, size, value, and cache status.
4326 @emph{With number/name}: display that register's value.
4328 @emph{With both number/name and value}: set register's value.
4330 Cores may have surprisingly many registers in their
4331 Debug and trace infrastructure:
4335 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4336 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4337 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4339 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4340 0x00000000 (dirty: 0, valid: 0)
4345 @deffn Command halt [ms]
4346 @deffnx Command wait_halt [ms]
4347 The @command{halt} command first sends a halt request to the target,
4348 which @command{wait_halt} doesn't.
4349 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4350 or 5 seconds if there is no parameter, for the target to halt
4351 (and enter debug mode).
4352 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4355 On ARM cores, software using the @emph{wait for interrupt} operation
4356 often blocks the JTAG access needed by a @command{halt} command.
4357 This is because that operation also puts the core into a low
4358 power mode by gating the core clock;
4359 but the core clock is needed to detect JTAG clock transitions.
4361 One partial workaround uses adaptive clocking: when the core is
4362 interrupted the operation completes, then JTAG clocks are accepted
4363 at least until the interrupt handler completes.
4364 However, this workaround is often unusable since the processor, board,
4365 and JTAG adapter must all support adaptive JTAG clocking.
4366 Also, it can't work until an interrupt is issued.
4368 A more complete workaround is to not use that operation while you
4369 work with a JTAG debugger.
4370 Tasking environments generaly have idle loops where the body is the
4371 @emph{wait for interrupt} operation.
4372 (On older cores, it is a coprocessor action;
4373 newer cores have a @option{wfi} instruction.)
4374 Such loops can just remove that operation, at the cost of higher
4375 power consumption (because the CPU is needlessly clocked).
4380 @deffn Command resume [address]
4381 Resume the target at its current code position,
4382 or the optional @var{address} if it is provided.
4383 OpenOCD will wait 5 seconds for the target to resume.
4386 @deffn Command step [address]
4387 Single-step the target at its current code position,
4388 or the optional @var{address} if it is provided.
4391 @anchor{Reset Command}
4392 @deffn Command reset
4393 @deffnx Command {reset run}
4394 @deffnx Command {reset halt}
4395 @deffnx Command {reset init}
4396 Perform as hard a reset as possible, using SRST if possible.
4397 @emph{All defined targets will be reset, and target
4398 events will fire during the reset sequence.}
4400 The optional parameter specifies what should
4401 happen after the reset.
4402 If there is no parameter, a @command{reset run} is executed.
4403 The other options will not work on all systems.
4404 @xref{Reset Configuration}.
4407 @item @b{run} Let the target run
4408 @item @b{halt} Immediately halt the target
4409 @item @b{init} Immediately halt the target, and execute the reset-init script
4413 @deffn Command soft_reset_halt
4414 Requesting target halt and executing a soft reset. This is often used
4415 when a target cannot be reset and halted. The target, after reset is
4416 released begins to execute code. OpenOCD attempts to stop the CPU and
4417 then sets the program counter back to the reset vector. Unfortunately
4418 the code that was executed may have left the hardware in an unknown
4422 @section I/O Utilities
4424 These commands are available when
4425 OpenOCD is built with @option{--enable-ioutil}.
4426 They are mainly useful on embedded targets,
4428 Hosts with operating systems have complementary tools.
4430 @emph{Note:} there are several more such commands.
4432 @deffn Command append_file filename [string]*
4433 Appends the @var{string} parameters to
4434 the text file @file{filename}.
4435 Each string except the last one is followed by one space.
4436 The last string is followed by a newline.
4439 @deffn Command cat filename
4440 Reads and displays the text file @file{filename}.
4443 @deffn Command cp src_filename dest_filename
4444 Copies contents from the file @file{src_filename}
4445 into @file{dest_filename}.
4449 @emph{No description provided.}
4453 @emph{No description provided.}
4457 @emph{No description provided.}
4460 @deffn Command meminfo
4461 Display available RAM memory on OpenOCD host.
4462 Used in OpenOCD regression testing scripts.
4466 @emph{No description provided.}
4470 @emph{No description provided.}
4473 @deffn Command rm filename
4474 @c "rm" has both normal and Jim-level versions??
4475 Unlinks the file @file{filename}.
4478 @deffn Command trunc filename
4479 Removes all data in the file @file{filename}.
4482 @anchor{Memory access}
4483 @section Memory access commands
4484 @cindex memory access
4486 These commands allow accesses of a specific size to the memory
4487 system. Often these are used to configure the current target in some
4488 special way. For example - one may need to write certain values to the
4489 SDRAM controller to enable SDRAM.
4492 @item Use the @command{targets} (plural) command
4493 to change the current target.
4494 @item In system level scripts these commands are deprecated.
4495 Please use their TARGET object siblings to avoid making assumptions
4496 about what TAP is the current target, or about MMU configuration.
4499 @deffn Command mdw addr [count]
4500 @deffnx Command mdh addr [count]
4501 @deffnx Command mdb addr [count]
4502 Display contents of address @var{addr}, as
4503 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4504 or 8-bit bytes (@command{mdb}).
4505 If @var{count} is specified, displays that many units.
4506 (If you want to manipulate the data instead of displaying it,
4507 see the @code{mem2array} primitives.)
4510 @deffn Command mww addr word
4511 @deffnx Command mwh addr halfword
4512 @deffnx Command mwb addr byte
4513 Writes the specified @var{word} (32 bits),
4514 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4515 at the specified address @var{addr}.
4519 @anchor{Image access}
4520 @section Image loading commands
4521 @cindex image loading
4522 @cindex image dumping
4525 @deffn Command {dump_image} filename address size
4526 Dump @var{size} bytes of target memory starting at @var{address} to the
4527 binary file named @var{filename}.
4530 @deffn Command {fast_load}
4531 Loads an image stored in memory by @command{fast_load_image} to the
4532 current target. Must be preceeded by fast_load_image.
4535 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4536 Normally you should be using @command{load_image} or GDB load. However, for
4537 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4538 host), storing the image in memory and uploading the image to the target
4539 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4540 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4541 memory, i.e. does not affect target. This approach is also useful when profiling
4542 target programming performance as I/O and target programming can easily be profiled
4547 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4548 Load image from file @var{filename} to target memory at @var{address}.
4549 The file format may optionally be specified
4550 (@option{bin}, @option{ihex}, or @option{elf})
4553 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4554 Displays image section sizes and addresses
4555 as if @var{filename} were loaded into target memory
4556 starting at @var{address} (defaults to zero).
4557 The file format may optionally be specified
4558 (@option{bin}, @option{ihex}, or @option{elf})
4561 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4562 Verify @var{filename} against target memory starting at @var{address}.
4563 The file format may optionally be specified
4564 (@option{bin}, @option{ihex}, or @option{elf})
4565 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4569 @section Breakpoint and Watchpoint commands
4573 CPUs often make debug modules accessible through JTAG, with
4574 hardware support for a handful of code breakpoints and data
4576 In addition, CPUs almost always support software breakpoints.
4578 @deffn Command {bp} [address len [@option{hw}]]
4579 With no parameters, lists all active breakpoints.
4580 Else sets a breakpoint on code execution starting
4581 at @var{address} for @var{length} bytes.
4582 This is a software breakpoint, unless @option{hw} is specified
4583 in which case it will be a hardware breakpoint.
4585 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4586 for similar mechanisms that do not consume hardware breakpoints.)
4589 @deffn Command {rbp} address
4590 Remove the breakpoint at @var{address}.
4593 @deffn Command {rwp} address
4594 Remove data watchpoint on @var{address}
4597 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4598 With no parameters, lists all active watchpoints.
4599 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4600 The watch point is an "access" watchpoint unless
4601 the @option{r} or @option{w} parameter is provided,
4602 defining it as respectively a read or write watchpoint.
4603 If a @var{value} is provided, that value is used when determining if
4604 the watchpoint should trigger. The value may be first be masked
4605 using @var{mask} to mark ``don't care'' fields.
4608 @section Misc Commands
4611 @deffn Command {profile} seconds filename
4612 Profiling samples the CPU's program counter as quickly as possible,
4613 which is useful for non-intrusive stochastic profiling.
4614 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4617 @deffn Command {version}
4618 Displays a string identifying the version of this OpenOCD server.
4621 @deffn Command {virt2phys} virtual_address
4622 Requests the current target to map the specified @var{virtual_address}
4623 to its corresponding physical address, and displays the result.
4626 @node Architecture and Core Commands
4627 @chapter Architecture and Core Commands
4628 @cindex Architecture Specific Commands
4629 @cindex Core Specific Commands
4631 Most CPUs have specialized JTAG operations to support debugging.
4632 OpenOCD packages most such operations in its standard command framework.
4633 Some of those operations don't fit well in that framework, so they are
4634 exposed here as architecture or implementation (core) specific commands.
4636 @anchor{ARM Hardware Tracing}
4637 @section ARM Hardware Tracing
4642 CPUs based on ARM cores may include standard tracing interfaces,
4643 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4644 address and data bus trace records to a ``Trace Port''.
4648 Development-oriented boards will sometimes provide a high speed
4649 trace connector for collecting that data, when the particular CPU
4650 supports such an interface.
4651 (The standard connector is a 38-pin Mictor, with both JTAG
4652 and trace port support.)
4653 Those trace connectors are supported by higher end JTAG adapters
4654 and some logic analyzer modules; frequently those modules can
4655 buffer several megabytes of trace data.
4656 Configuring an ETM coupled to such an external trace port belongs
4657 in the board-specific configuration file.
4659 If the CPU doesn't provide an external interface, it probably
4660 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4661 dedicated SRAM. 4KBytes is one common ETB size.
4662 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4663 (target) configuration file, since it works the same on all boards.
4666 ETM support in OpenOCD doesn't seem to be widely used yet.
4669 ETM support may be buggy, and at least some @command{etm config}
4670 parameters should be detected by asking the ETM for them.
4671 It seems like a GDB hookup should be possible,
4672 as well as triggering trace on specific events
4673 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4674 There should be GUI tools to manipulate saved trace data and help
4675 analyse it in conjunction with the source code.
4676 It's unclear how much of a common interface is shared
4677 with the current XScale trace support, or should be
4678 shared with eventual Nexus-style trace module support.
4681 @subsection ETM Configuration
4682 ETM setup is coupled with the trace port driver configuration.
4684 @deffn {Config Command} {etm config} target width mode clocking driver
4685 Declares the ETM associated with @var{target}, and associates it
4686 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4688 Several of the parameters must reflect the trace port configuration.
4689 The @var{width} must be either 4, 8, or 16.
4690 The @var{mode} must be @option{normal}, @option{multiplexted},
4691 or @option{demultiplexted}.
4692 The @var{clocking} must be @option{half} or @option{full}.
4695 You can see the ETM registers using the @command{reg} command, although
4696 not all of those possible registers are present in every ETM.
4700 @deffn Command {etm info}
4701 Displays information about the current target's ETM.
4704 @deffn Command {etm status}
4705 Displays status of the current target's ETM:
4706 is the ETM idle, or is it collecting data?
4707 Did trace data overflow?
4711 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4712 Displays what data that ETM will collect.
4713 If arguments are provided, first configures that data.
4714 When the configuration changes, tracing is stopped
4715 and any buffered trace data is invalidated.
4718 @item @var{type} ... one of
4719 @option{none} (save nothing),
4720 @option{data} (save data),
4721 @option{address} (save addresses),
4722 @option{all} (save data and addresses)
4723 @item @var{context_id_bits} ... 0, 8, 16, or 32
4724 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4725 @item @var{branch_output} ... @option{enable} or @option{disable}
4729 @deffn Command {etm trigger_percent} percent
4730 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4733 @subsection ETM Trace Operation
4735 After setting up the ETM, you can use it to collect data.
4736 That data can be exported to files for later analysis.
4737 It can also be parsed with OpenOCD, for basic sanity checking.
4739 @deffn Command {etm analyze}
4740 Reads trace data into memory, if it wasn't already present.
4741 Decodes and prints the data that was collected.
4744 @deffn Command {etm dump} filename
4745 Stores the captured trace data in @file{filename}.
4748 @deffn Command {etm image} filename [base_address] [type]
4749 Opens an image file.
4752 @deffn Command {etm load} filename
4753 Loads captured trace data from @file{filename}.
4756 @deffn Command {etm start}
4757 Starts trace data collection.
4760 @deffn Command {etm stop}
4761 Stops trace data collection.
4764 @anchor{Trace Port Drivers}
4765 @subsection Trace Port Drivers
4767 To use an ETM trace port it must be associated with a driver.
4769 @deffn {Trace Port Driver} dummy
4770 Use the @option{dummy} driver if you are configuring an ETM that's
4771 not connected to anything (on-chip ETB or off-chip trace connector).
4772 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4773 any trace data collection.}
4774 @deffn {Config Command} {etm_dummy config} target
4775 Associates the ETM for @var{target} with a dummy driver.
4779 @deffn {Trace Port Driver} etb
4780 Use the @option{etb} driver if you are configuring an ETM
4781 to use on-chip ETB memory.
4782 @deffn {Config Command} {etb config} target etb_tap
4783 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4784 You can see the ETB registers using the @command{reg} command.
4788 @deffn {Trace Port Driver} oocd_trace
4789 This driver isn't available unless OpenOCD was explicitly configured
4790 with the @option{--enable-oocd_trace} option. You probably don't want
4791 to configure it unless you've built the appropriate prototype hardware;
4792 it's @emph{proof-of-concept} software.
4794 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4795 connected to an off-chip trace connector.
4797 @deffn {Config Command} {oocd_trace config} target tty
4798 Associates the ETM for @var{target} with a trace driver which
4799 collects data through the serial port @var{tty}.
4802 @deffn Command {oocd_trace resync}
4803 Re-synchronizes with the capture clock.
4806 @deffn Command {oocd_trace status}
4807 Reports whether the capture clock is locked or not.
4812 @section ARMv4 and ARMv5 Architecture
4816 These commands are specific to ARM architecture v4 and v5,
4817 including all ARM7 or ARM9 systems and Intel XScale.
4818 They are available in addition to other core-specific
4819 commands that may be available.
4821 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4822 Displays the core_state, optionally changing it to process
4823 either @option{arm} or @option{thumb} instructions.
4824 The target may later be resumed in the currently set core_state.
4825 (Processors may also support the Jazelle state, but
4826 that is not currently supported in OpenOCD.)
4829 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
4831 Disassembles @var{count} instructions starting at @var{address}.
4832 If @var{count} is not specified, a single instruction is disassembled.
4833 If @option{thumb} is specified, or the low bit of the address is set,
4834 Thumb (16-bit) instructions are used;
4835 else ARM (32-bit) instructions are used.
4836 (Processors may also support the Jazelle state, but
4837 those instructions are not currently understood by OpenOCD.)
4840 @deffn Command {armv4_5 reg}
4841 Display a table of all banked core registers, fetching the current value from every
4842 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4846 @subsection ARM7 and ARM9 specific commands
4850 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4851 ARM9TDMI, ARM920T or ARM926EJ-S.
4852 They are available in addition to the ARMv4/5 commands,
4853 and any other core-specific commands that may be available.
4855 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4856 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4857 instead of breakpoints. This should be
4858 safe for all but ARM7TDMI--S cores (like Philips LPC).
4859 This feature is enabled by default on most ARM9 cores,
4860 including ARM9TDMI, ARM920T, and ARM926EJ-S.
4863 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4865 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4866 amounts of memory. DCC downloads offer a huge speed increase, but might be
4867 unsafe, especially with targets running at very low speeds. This command was introduced
4868 with OpenOCD rev. 60, and requires a few bytes of working area.
4871 @anchor{arm7_9 fast_memory_access}
4872 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4873 Enable or disable memory writes and reads that don't check completion of
4874 the operation. This provides a huge speed increase, especially with USB JTAG
4875 cables (FT2232), but might be unsafe if used with targets running at very low
4876 speeds, like the 32kHz startup clock of an AT91RM9200.
4879 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4880 @emph{This is intended for use while debugging OpenOCD; you probably
4883 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4884 as used in the specified @var{mode}
4885 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4886 the M4..M0 bits of the PSR).
4887 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4888 Register 16 is the mode-specific SPSR,
4889 unless the specified mode is 0xffffffff (32-bit all-ones)
4890 in which case register 16 is the CPSR.
4891 The write goes directly to the CPU, bypassing the register cache.
4894 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4895 @emph{This is intended for use while debugging OpenOCD; you probably
4898 If the second parameter is zero, writes @var{word} to the
4899 Current Program Status register (CPSR).
4900 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4901 In both cases, this bypasses the register cache.
4904 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4905 @emph{This is intended for use while debugging OpenOCD; you probably
4908 Writes eight bits to the CPSR or SPSR,
4909 first rotating them by @math{2*rotate} bits,
4910 and bypassing the register cache.
4911 This has lower JTAG overhead than writing the entire CPSR or SPSR
4912 with @command{arm7_9 write_xpsr}.
4915 @subsection ARM720T specific commands
4918 These commands are available to ARM720T based CPUs,
4919 which are implementations of the ARMv4T architecture
4920 based on the ARM7TDMI-S integer core.
4921 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4923 @deffn Command {arm720t cp15} regnum [value]
4924 Display cp15 register @var{regnum};
4925 else if a @var{value} is provided, that value is written to that register.
4928 @deffn Command {arm720t mdw_phys} addr [count]
4929 @deffnx Command {arm720t mdh_phys} addr [count]
4930 @deffnx Command {arm720t mdb_phys} addr [count]
4931 Display contents of physical address @var{addr}, as
4932 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4933 or 8-bit bytes (@command{mdb_phys}).
4934 If @var{count} is specified, displays that many units.
4937 @deffn Command {arm720t mww_phys} addr word
4938 @deffnx Command {arm720t mwh_phys} addr halfword
4939 @deffnx Command {arm720t mwb_phys} addr byte
4940 Writes the specified @var{word} (32 bits),
4941 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4942 at the specified physical address @var{addr}.
4945 @deffn Command {arm720t virt2phys} va
4946 Translate a virtual address @var{va} to a physical address
4947 and display the result.
4950 @subsection ARM9 specific commands
4953 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
4955 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4957 For historical reasons, one command shared by these cores starts
4958 with the @command{arm9tdmi} prefix.
4959 This is true even for ARM9E based processors, which implement the
4960 ARMv5TE architecture instead of ARMv4T.
4962 @c 9-june-2009: tried this on arm920t, it didn't work.
4963 @c no-params always lists nothing caught, and that's how it acts.
4965 @anchor{arm9tdmi vector_catch}
4966 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
4967 @cindex vector_catch
4968 Vector Catch hardware provides a sort of dedicated breakpoint
4969 for hardware events such as reset, interrupt, and abort.
4970 You can use this to conserve normal breakpoint resources,
4971 so long as you're not concerned with code that branches directly
4972 to those hardware vectors.
4974 This always finishes by listing the current configuration.
4975 If parameters are provided, it first reconfigures the
4976 vector catch hardware to intercept
4977 @option{all} of the hardware vectors,
4978 @option{none} of them,
4979 or a list with one or more of the following:
4980 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4981 @option{irq} @option{fiq}.
4984 @subsection ARM920T specific commands
4987 These commands are available to ARM920T based CPUs,
4988 which are implementations of the ARMv4T architecture
4989 built using the ARM9TDMI integer core.
4990 They are available in addition to the ARMv4/5, ARM7/ARM9,
4991 and ARM9TDMI commands.
4993 @deffn Command {arm920t cache_info}
4994 Print information about the caches found. This allows to see whether your target
4995 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
4998 @deffn Command {arm920t cp15} regnum [value]
4999 Display cp15 register @var{regnum};
5000 else if a @var{value} is provided, that value is written to that register.
5003 @deffn Command {arm920t cp15i} opcode [value [address]]
5004 Interpreted access using cp15 @var{opcode}.
5005 If no @var{value} is provided, the result is displayed.
5006 Else if that value is written using the specified @var{address},
5007 or using zero if no other address is not provided.
5010 @deffn Command {arm920t mdw_phys} addr [count]
5011 @deffnx Command {arm920t mdh_phys} addr [count]
5012 @deffnx Command {arm920t mdb_phys} addr [count]
5013 Display contents of physical address @var{addr}, as
5014 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5015 or 8-bit bytes (@command{mdb_phys}).
5016 If @var{count} is specified, displays that many units.
5019 @deffn Command {arm920t mww_phys} addr word
5020 @deffnx Command {arm920t mwh_phys} addr halfword
5021 @deffnx Command {arm920t mwb_phys} addr byte
5022 Writes the specified @var{word} (32 bits),
5023 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5024 at the specified physical address @var{addr}.
5027 @deffn Command {arm920t read_cache} filename
5028 Dump the content of ICache and DCache to a file named @file{filename}.
5031 @deffn Command {arm920t read_mmu} filename
5032 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5035 @deffn Command {arm920t virt2phys} va
5036 Translate a virtual address @var{va} to a physical address
5037 and display the result.
5040 @subsection ARM926ej-s specific commands
5043 These commands are available to ARM926ej-s based CPUs,
5044 which are implementations of the ARMv5TEJ architecture
5045 based on the ARM9EJ-S integer core.
5046 They are available in addition to the ARMv4/5, ARM7/ARM9,
5047 and ARM9TDMI commands.
5049 The Feroceon cores also support these commands, although
5050 they are not built from ARM926ej-s designs.
5052 @deffn Command {arm926ejs cache_info}
5053 Print information about the caches found.
5056 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5057 Accesses cp15 register @var{regnum} using
5058 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5059 If a @var{value} is provided, that value is written to that register.
5060 Else that register is read and displayed.
5063 @deffn Command {arm926ejs mdw_phys} addr [count]
5064 @deffnx Command {arm926ejs mdh_phys} addr [count]
5065 @deffnx Command {arm926ejs mdb_phys} addr [count]
5066 Display contents of physical address @var{addr}, as
5067 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5068 or 8-bit bytes (@command{mdb_phys}).
5069 If @var{count} is specified, displays that many units.
5072 @deffn Command {arm926ejs mww_phys} addr word
5073 @deffnx Command {arm926ejs mwh_phys} addr halfword
5074 @deffnx Command {arm926ejs mwb_phys} addr byte
5075 Writes the specified @var{word} (32 bits),
5076 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5077 at the specified physical address @var{addr}.
5080 @deffn Command {arm926ejs virt2phys} va
5081 Translate a virtual address @var{va} to a physical address
5082 and display the result.
5085 @subsection ARM966E specific commands
5088 These commands are available to ARM966 based CPUs,
5089 which are implementations of the ARMv5TE architecture.
5090 They are available in addition to the ARMv4/5, ARM7/ARM9,
5091 and ARM9TDMI commands.
5093 @deffn Command {arm966e cp15} regnum [value]
5094 Display cp15 register @var{regnum};
5095 else if a @var{value} is provided, that value is written to that register.
5098 @subsection XScale specific commands
5101 Some notes about the debug implementation on the XScale CPUs:
5103 The XScale CPU provides a special debug-only mini-instruction cache
5104 (mini-IC) in which exception vectors and target-resident debug handler
5105 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5106 must point vector 0 (the reset vector) to the entry of the debug
5107 handler. However, this means that the complete first cacheline in the
5108 mini-IC is marked valid, which makes the CPU fetch all exception
5109 handlers from the mini-IC, ignoring the code in RAM.
5111 OpenOCD currently does not sync the mini-IC entries with the RAM
5112 contents (which would fail anyway while the target is running), so
5113 the user must provide appropriate values using the @code{xscale
5114 vector_table} command.
5116 It is recommended to place a pc-relative indirect branch in the vector
5117 table, and put the branch destination somewhere in memory. Doing so
5118 makes sure the code in the vector table stays constant regardless of
5119 code layout in memory:
5122 ldr pc,[pc,#0x100-8]
5123 ldr pc,[pc,#0x100-8]
5124 ldr pc,[pc,#0x100-8]
5125 ldr pc,[pc,#0x100-8]
5126 ldr pc,[pc,#0x100-8]
5127 ldr pc,[pc,#0x100-8]
5128 ldr pc,[pc,#0x100-8]
5129 ldr pc,[pc,#0x100-8]
5131 .long real_reset_vector
5132 .long real_ui_handler
5133 .long real_swi_handler
5135 .long real_data_abort
5136 .long 0 /* unused */
5137 .long real_irq_handler
5138 .long real_fiq_handler
5141 The debug handler must be placed somewhere in the address space using
5142 the @code{xscale debug_handler} command. The allowed locations for the
5143 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5144 0xfffff800). The default value is 0xfe000800.
5147 These commands are available to XScale based CPUs,
5148 which are implementations of the ARMv5TE architecture.
5150 @deffn Command {xscale analyze_trace}
5151 Displays the contents of the trace buffer.
5154 @deffn Command {xscale cache_clean_address} address
5155 Changes the address used when cleaning the data cache.
5158 @deffn Command {xscale cache_info}
5159 Displays information about the CPU caches.
5162 @deffn Command {xscale cp15} regnum [value]
5163 Display cp15 register @var{regnum};
5164 else if a @var{value} is provided, that value is written to that register.
5167 @deffn Command {xscale debug_handler} target address
5168 Changes the address used for the specified target's debug handler.
5171 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5172 Enables or disable the CPU's data cache.
5175 @deffn Command {xscale dump_trace} filename
5176 Dumps the raw contents of the trace buffer to @file{filename}.
5179 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5180 Enables or disable the CPU's instruction cache.
5183 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5184 Enables or disable the CPU's memory management unit.
5187 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5188 Enables or disables the trace buffer,
5189 and controls how it is emptied.
5192 @deffn Command {xscale trace_image} filename [offset [type]]
5193 Opens a trace image from @file{filename}, optionally rebasing
5194 its segment addresses by @var{offset}.
5195 The image @var{type} may be one of
5196 @option{bin} (binary), @option{ihex} (Intel hex),
5197 @option{elf} (ELF file), @option{s19} (Motorola s19),
5198 @option{mem}, or @option{builder}.
5201 @anchor{xscale vector_catch}
5202 @deffn Command {xscale vector_catch} [mask]
5203 @cindex vector_catch
5204 Display a bitmask showing the hardware vectors to catch.
5205 If the optional parameter is provided, first set the bitmask to that value.
5207 The mask bits correspond with bit 16..23 in the DCSR:
5210 0x02 Trap Undefined Instructions
5211 0x04 Trap Software Interrupt
5212 0x08 Trap Prefetch Abort
5213 0x10 Trap Data Abort
5220 @anchor{xscale vector_table}
5221 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5222 @cindex vector_table
5224 Set an entry in the mini-IC vector table. There are two tables: one for
5225 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5226 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5227 points to the debug handler entry and can not be overwritten.
5228 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5230 Without arguments, the current settings are displayed.
5234 @section ARMv6 Architecture
5237 @subsection ARM11 specific commands
5240 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5241 Write @var{value} to a coprocessor @var{pX} register
5242 passing parameters @var{CRn},
5243 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5244 and the MCR instruction.
5245 (The difference beween this and the MCR2 instruction is
5246 one bit in the encoding, effecively a fifth parameter.)
5249 @deffn Command {arm11 memwrite burst} [value]
5250 Displays the value of the memwrite burst-enable flag,
5251 which is enabled by default.
5252 If @var{value} is defined, first assigns that.
5255 @deffn Command {arm11 memwrite error_fatal} [value]
5256 Displays the value of the memwrite error_fatal flag,
5257 which is enabled by default.
5258 If @var{value} is defined, first assigns that.
5261 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5262 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5263 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5264 and the MRC instruction.
5265 (The difference beween this and the MRC2 instruction is
5266 one bit in the encoding, effecively a fifth parameter.)
5267 Displays the result.
5270 @deffn Command {arm11 no_increment} [value]
5271 Displays the value of the flag controlling whether
5272 some read or write operations increment the pointer
5273 (the default behavior) or not (acting like a FIFO).
5274 If @var{value} is defined, first assigns that.
5277 @deffn Command {arm11 step_irq_enable} [value]
5278 Displays the value of the flag controlling whether
5279 IRQs are enabled during single stepping;
5280 they is disabled by default.
5281 If @var{value} is defined, first assigns that.
5284 @section ARMv7 Architecture
5287 @subsection ARMv7 Debug Access Port (DAP) specific commands
5288 @cindex Debug Access Port
5290 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5291 included on cortex-m3 and cortex-a8 systems.
5292 They are available in addition to other core-specific commands that may be available.
5294 @deffn Command {dap info} [num]
5295 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5298 @deffn Command {dap apsel} [num]
5299 Select AP @var{num}, defaulting to 0.
5302 @deffn Command {dap apid} [num]
5303 Displays id register from AP @var{num},
5304 defaulting to the currently selected AP.
5307 @deffn Command {dap baseaddr} [num]
5308 Displays debug base address from AP @var{num},
5309 defaulting to the currently selected AP.
5312 @deffn Command {dap memaccess} [value]
5313 Displays the number of extra tck for mem-ap memory bus access [0-255].
5314 If @var{value} is defined, first assigns that.
5317 @subsection ARMv7-A specific commands
5320 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5322 Disassembles @var{count} instructions starting at @var{address}.
5323 If @var{count} is not specified, a single instruction is disassembled.
5324 If @option{thumb} is specified, or the low bit of the address is set,
5325 Thumb2 (mixed 16/32-bit) instructions are used;
5326 else ARM (32-bit) instructions are used.
5327 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5328 ThumbEE disassembly currently has no explicit support.
5329 (Processors may also support the Jazelle state, but
5330 those instructions are not currently understood by OpenOCD.)
5334 @subsection Cortex-M3 specific commands
5337 @deffn Command {cortex_m3 disassemble} address [count]
5339 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5340 If @var{count} is not specified, a single instruction is disassembled.
5343 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5344 Control masking (disabling) interrupts during target step/resume.
5347 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5348 @cindex vector_catch
5349 Vector Catch hardware provides dedicated breakpoints
5350 for certain hardware events.
5352 Parameters request interception of
5353 @option{all} of these hardware event vectors,
5354 @option{none} of them,
5355 or one or more of the following:
5356 @option{hard_err} for a HardFault exception;
5357 @option{mm_err} for a MemManage exception;
5358 @option{bus_err} for a BusFault exception;
5361 @option{chk_err}, or
5362 @option{nocp_err} for various UsageFault exceptions; or
5364 If NVIC setup code does not enable them,
5365 MemManage, BusFault, and UsageFault exceptions
5366 are mapped to HardFault.
5367 UsageFault checks for
5368 divide-by-zero and unaligned access
5369 must also be explicitly enabled.
5371 This finishes by listing the current vector catch configuration.
5374 @anchor{Software Debug Messages and Tracing}
5375 @section Software Debug Messages and Tracing
5376 @cindex Linux-ARM DCC support
5380 OpenOCD can process certain requests from target software. Currently
5381 @command{target_request debugmsgs}
5382 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5383 These messages are received as part of target polling, so
5384 you need to have @command{poll on} active to receive them.
5385 They are intrusive in that they will affect program execution
5386 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5388 See @file{libdcc} in the contrib dir for more details.
5389 In addition to sending strings, characters, and
5390 arrays of various size integers from the target,
5391 @file{libdcc} also exports a software trace point mechanism.
5392 The target being debugged may
5393 issue trace messages which include a 24-bit @dfn{trace point} number.
5394 Trace point support includes two distinct mechanisms,
5395 each supported by a command:
5398 @item @emph{History} ... A circular buffer of trace points
5399 can be set up, and then displayed at any time.
5400 This tracks where code has been, which can be invaluable in
5401 finding out how some fault was triggered.
5403 The buffer may overflow, since it collects records continuously.
5404 It may be useful to use some of the 24 bits to represent a
5405 particular event, and other bits to hold data.
5407 @item @emph{Counting} ... An array of counters can be set up,
5408 and then displayed at any time.
5409 This can help establish code coverage and identify hot spots.
5411 The array of counters is directly indexed by the trace point
5412 number, so trace points with higher numbers are not counted.
5415 Linux-ARM kernels have a ``Kernel low-level debugging
5416 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5417 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5418 deliver messages before a serial console can be activated.
5419 This is not the same format used by @file{libdcc}.
5420 Other software, such as the U-Boot boot loader, sometimes
5421 does the same thing.
5423 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5424 Displays current handling of target DCC message requests.
5425 These messages may be sent to the debugger while the target is running.
5426 The optional @option{enable} and @option{charmsg} parameters
5427 both enable the messages, while @option{disable} disables them.
5429 With @option{charmsg} the DCC words each contain one character,
5430 as used by Linux with CONFIG_DEBUG_ICEDCC;
5431 otherwise the libdcc format is used.
5434 @deffn Command {trace history} (@option{clear}|count)
5435 With no parameter, displays all the trace points that have triggered
5436 in the order they triggered.
5437 With the parameter @option{clear}, erases all current trace history records.
5438 With a @var{count} parameter, allocates space for that many
5442 @deffn Command {trace point} (@option{clear}|identifier)
5443 With no parameter, displays all trace point identifiers and how many times
5444 they have been triggered.
5445 With the parameter @option{clear}, erases all current trace point counters.
5446 With a numeric @var{identifier} parameter, creates a new a trace point counter
5447 and associates it with that identifier.
5449 @emph{Important:} The identifier and the trace point number
5450 are not related except by this command.
5451 These trace point numbers always start at zero (from server startup,
5452 or after @command{trace point clear}) and count up from there.
5457 @chapter JTAG Commands
5458 @cindex JTAG Commands
5459 Most general purpose JTAG commands have been presented earlier.
5460 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5461 Lower level JTAG commands, as presented here,
5462 may be needed to work with targets which require special
5463 attention during operations such as reset or initialization.
5465 To use these commands you will need to understand some
5466 of the basics of JTAG, including:
5469 @item A JTAG scan chain consists of a sequence of individual TAP
5470 devices such as a CPUs.
5471 @item Control operations involve moving each TAP through the same
5472 standard state machine (in parallel)
5473 using their shared TMS and clock signals.
5474 @item Data transfer involves shifting data through the chain of
5475 instruction or data registers of each TAP, writing new register values
5476 while the reading previous ones.
5477 @item Data register sizes are a function of the instruction active in
5478 a given TAP, while instruction register sizes are fixed for each TAP.
5479 All TAPs support a BYPASS instruction with a single bit data register.
5480 @item The way OpenOCD differentiates between TAP devices is by
5481 shifting different instructions into (and out of) their instruction
5485 @section Low Level JTAG Commands
5487 These commands are used by developers who need to access
5488 JTAG instruction or data registers, possibly controlling
5489 the order of TAP state transitions.
5490 If you're not debugging OpenOCD internals, or bringing up a
5491 new JTAG adapter or a new type of TAP device (like a CPU or
5492 JTAG router), you probably won't need to use these commands.
5494 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5495 Loads the data register of @var{tap} with a series of bit fields
5496 that specify the entire register.
5497 Each field is @var{numbits} bits long with
5498 a numeric @var{value} (hexadecimal encouraged).
5499 The return value holds the original value of each
5502 For example, a 38 bit number might be specified as one
5503 field of 32 bits then one of 6 bits.
5504 @emph{For portability, never pass fields which are more
5505 than 32 bits long. Many OpenOCD implementations do not
5506 support 64-bit (or larger) integer values.}
5508 All TAPs other than @var{tap} must be in BYPASS mode.
5509 The single bit in their data registers does not matter.
5511 When @var{tap_state} is specified, the JTAG state machine is left
5513 For example @sc{drpause} might be specified, so that more
5514 instructions can be issued before re-entering the @sc{run/idle} state.
5515 If the end state is not specified, the @sc{run/idle} state is entered.
5518 OpenOCD does not record information about data register lengths,
5519 so @emph{it is important that you get the bit field lengths right}.
5520 Remember that different JTAG instructions refer to different
5521 data registers, which may have different lengths.
5522 Moreover, those lengths may not be fixed;
5523 the SCAN_N instruction can change the length of
5524 the register accessed by the INTEST instruction
5525 (by connecting a different scan chain).
5529 @deffn Command {flush_count}
5530 Returns the number of times the JTAG queue has been flushed.
5531 This may be used for performance tuning.
5533 For example, flushing a queue over USB involves a
5534 minimum latency, often several milliseconds, which does
5535 not change with the amount of data which is written.
5536 You may be able to identify performance problems by finding
5537 tasks which waste bandwidth by flushing small transfers too often,
5538 instead of batching them into larger operations.
5541 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5542 For each @var{tap} listed, loads the instruction register
5543 with its associated numeric @var{instruction}.
5544 (The number of bits in that instruction may be displayed
5545 using the @command{scan_chain} command.)
5546 For other TAPs, a BYPASS instruction is loaded.
5548 When @var{tap_state} is specified, the JTAG state machine is left
5550 For example @sc{irpause} might be specified, so the data register
5551 can be loaded before re-entering the @sc{run/idle} state.
5552 If the end state is not specified, the @sc{run/idle} state is entered.
5555 OpenOCD currently supports only a single field for instruction
5556 register values, unlike data register values.
5557 For TAPs where the instruction register length is more than 32 bits,
5558 portable scripts currently must issue only BYPASS instructions.
5562 @deffn Command {jtag_reset} trst srst
5563 Set values of reset signals.
5564 The @var{trst} and @var{srst} parameter values may be
5565 @option{0}, indicating that reset is inactive (pulled or driven high),
5566 or @option{1}, indicating it is active (pulled or driven low).
5567 The @command{reset_config} command should already have been used
5568 to configure how the board and JTAG adapter treat these two
5569 signals, and to say if either signal is even present.
5570 @xref{Reset Configuration}.
5573 @deffn Command {runtest} @var{num_cycles}
5574 Move to the @sc{run/idle} state, and execute at least
5575 @var{num_cycles} of the JTAG clock (TCK).
5576 Instructions often need some time
5577 to execute before they take effect.
5580 @c tms_sequence (short|long)
5581 @c ... temporary, debug-only, probably gone before 0.2 ships
5583 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5584 Verify values captured during @sc{ircapture} and returned
5585 during IR scans. Default is enabled, but this can be
5586 overridden by @command{verify_jtag}.
5589 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5590 Enables verification of DR and IR scans, to help detect
5591 programming errors. For IR scans, @command{verify_ircapture}
5592 must also be enabled.
5596 @section TAP state names
5597 @cindex TAP state names
5599 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5600 and @command{irscan} commands are:
5603 @item @b{RESET} ... should act as if TRST were active
5604 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5607 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5609 @item @b{DRPAUSE} ... data register ready for update or more shifting
5614 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5616 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5621 Note that only six of those states are fully ``stable'' in the
5622 face of TMS fixed (low except for @sc{reset})
5623 and a free-running JTAG clock. For all the
5624 others, the next TCK transition changes to a new state.
5627 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5628 produce side effects by changing register contents. The values
5629 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5630 may not be as expected.
5631 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5632 choices after @command{drscan} or @command{irscan} commands,
5633 since they are free of JTAG side effects.
5634 However, @sc{run/idle} may have side effects that appear at other
5635 levels, such as advancing the ARM9E-S instruction pipeline.
5636 Consult the documentation for the TAP(s) you are working with.
5639 @node Boundary Scan Commands
5640 @chapter Boundary Scan Commands
5642 One of the original purposes of JTAG was to support
5643 boundary scan based hardware testing.
5644 Although its primary focus is to support On-Chip Debugging,
5645 OpenOCD also includes some boundary scan commands.
5647 @section SVF: Serial Vector Format
5648 @cindex Serial Vector Format
5651 The Serial Vector Format, better known as @dfn{SVF}, is a
5652 way to represent JTAG test patterns in text files.
5653 OpenOCD supports running such test files.
5655 @deffn Command {svf} filename [@option{quiet}]
5656 This issues a JTAG reset (Test-Logic-Reset) and then
5657 runs the SVF script from @file{filename}.
5658 Unless the @option{quiet} option is specified,
5659 each command is logged before it is executed.
5662 @section XSVF: Xilinx Serial Vector Format
5663 @cindex Xilinx Serial Vector Format
5666 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5667 binary representation of SVF which is optimized for use with
5669 OpenOCD supports running such test files.
5671 @quotation Important
5672 Not all XSVF commands are supported.
5675 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5676 This issues a JTAG reset (Test-Logic-Reset) and then
5677 runs the XSVF script from @file{filename}.
5678 When a @var{tapname} is specified, the commands are directed at
5680 When @option{virt2} is specified, the @sc{xruntest} command counts
5681 are interpreted as TCK cycles instead of microseconds.
5682 Unless the @option{quiet} option is specified,
5683 messages are logged for comments and some retries.
5689 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5690 be used to access files on PCs (either the developer's PC or some other PC).
5692 The way this works on the ZY1000 is to prefix a filename by
5693 "/tftp/ip/" and append the TFTP path on the TFTP
5694 server (tftpd). For example,
5697 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5700 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5701 if the file was hosted on the embedded host.
5703 In order to achieve decent performance, you must choose a TFTP server
5704 that supports a packet size bigger than the default packet size (512 bytes). There
5705 are numerous TFTP servers out there (free and commercial) and you will have to do
5706 a bit of googling to find something that fits your requirements.
5708 @node GDB and OpenOCD
5709 @chapter GDB and OpenOCD
5711 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5712 to debug remote targets.
5714 @anchor{Connecting to GDB}
5715 @section Connecting to GDB
5716 @cindex Connecting to GDB
5717 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5718 instance GDB 6.3 has a known bug that produces bogus memory access
5719 errors, which has since been fixed: look up 1836 in
5720 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5722 OpenOCD can communicate with GDB in two ways:
5726 A socket (TCP/IP) connection is typically started as follows:
5728 target remote localhost:3333
5730 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5732 A pipe connection is typically started as follows:
5734 target remote | openocd --pipe
5736 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5737 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5741 To list the available OpenOCD commands type @command{monitor help} on the
5744 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5745 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5746 packet size and the device's memory map.
5748 Previous versions of OpenOCD required the following GDB options to increase
5749 the packet size and speed up GDB communication:
5751 set remote memory-write-packet-size 1024
5752 set remote memory-write-packet-size fixed
5753 set remote memory-read-packet-size 1024
5754 set remote memory-read-packet-size fixed
5756 This is now handled in the @option{qSupported} PacketSize and should not be required.
5758 @section Programming using GDB
5759 @cindex Programming using GDB
5761 By default the target memory map is sent to GDB. This can be disabled by
5762 the following OpenOCD configuration option:
5764 gdb_memory_map disable
5766 For this to function correctly a valid flash configuration must also be set
5767 in OpenOCD. For faster performance you should also configure a valid
5770 Informing GDB of the memory map of the target will enable GDB to protect any
5771 flash areas of the target and use hardware breakpoints by default. This means
5772 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5773 using a memory map. @xref{gdb_breakpoint_override}.
5775 To view the configured memory map in GDB, use the GDB command @option{info mem}
5776 All other unassigned addresses within GDB are treated as RAM.
5778 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5779 This can be changed to the old behaviour by using the following GDB command
5781 set mem inaccessible-by-default off
5784 If @command{gdb_flash_program enable} is also used, GDB will be able to
5785 program any flash memory using the vFlash interface.
5787 GDB will look at the target memory map when a load command is given, if any
5788 areas to be programmed lie within the target flash area the vFlash packets
5791 If the target needs configuring before GDB programming, an event
5792 script can be executed:
5794 $_TARGETNAME configure -event EVENTNAME BODY
5797 To verify any flash programming the GDB command @option{compare-sections}
5800 @node Tcl Scripting API
5801 @chapter Tcl Scripting API
5802 @cindex Tcl Scripting API
5806 The commands are stateless. E.g. the telnet command line has a concept
5807 of currently active target, the Tcl API proc's take this sort of state
5808 information as an argument to each proc.
5810 There are three main types of return values: single value, name value
5811 pair list and lists.
5813 Name value pair. The proc 'foo' below returns a name/value pair
5819 > set foo(you) Oyvind
5820 > set foo(mouse) Micky
5821 > set foo(duck) Donald
5829 me Duane you Oyvind mouse Micky duck Donald
5831 Thus, to get the names of the associative array is easy:
5833 foreach { name value } [set foo] {
5834 puts "Name: $name, Value: $value"
5838 Lists returned must be relatively small. Otherwise a range
5839 should be passed in to the proc in question.
5841 @section Internal low-level Commands
5843 By low-level, the intent is a human would not directly use these commands.
5845 Low-level commands are (should be) prefixed with "ocd_", e.g.
5846 @command{ocd_flash_banks}
5847 is the low level API upon which @command{flash banks} is implemented.
5850 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5852 Read memory and return as a Tcl array for script processing
5853 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5855 Convert a Tcl array to memory locations and write the values
5856 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
5858 Return information about the flash banks
5861 OpenOCD commands can consist of two words, e.g. "flash banks". The
5862 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
5863 called "flash_banks".
5865 @section OpenOCD specific Global Variables
5869 Real Tcl has ::tcl_platform(), and platform::identify, and many other
5870 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
5871 holds one of the following values:
5874 @item @b{winxx} Built using Microsoft Visual Studio
5875 @item @b{linux} Linux is the underlying operating sytem
5876 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
5877 @item @b{cygwin} Running under Cygwin
5878 @item @b{mingw32} Running under MingW32
5879 @item @b{other} Unknown, none of the above.
5882 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5885 We should add support for a variable like Tcl variable
5886 @code{tcl_platform(platform)}, it should be called
5887 @code{jim_platform} (because it
5888 is jim, not real tcl).
5892 @chapter Deprecated/Removed Commands
5893 @cindex Deprecated/Removed Commands
5894 Certain OpenOCD commands have been deprecated or
5895 removed during the various revisions.
5897 Upgrade your scripts as soon as possible.
5898 These descriptions for old commands may be removed
5899 a year after the command itself was removed.
5900 This means that in January 2010 this chapter may
5901 become much shorter.
5904 @item @b{arm7_9 fast_writes}
5905 @cindex arm7_9 fast_writes
5906 @*Use @command{arm7_9 fast_memory_access} instead.
5907 @xref{arm7_9 fast_memory_access}.
5910 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5911 @item @b{arm7_9 force_hw_bkpts}
5912 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5913 for flash if the GDB memory map has been set up(default when flash is declared in
5914 target configuration). @xref{gdb_breakpoint_override}.
5915 @item @b{arm7_9 sw_bkpts}
5916 @*On by default. @xref{gdb_breakpoint_override}.
5917 @item @b{daemon_startup}
5918 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5919 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5920 and @option{target cortex_m3 little reset_halt 0}.
5921 @item @b{dump_binary}
5922 @*use @option{dump_image} command with same args. @xref{dump_image}.
5923 @item @b{flash erase}
5924 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5925 @item @b{flash write}
5926 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5927 @item @b{flash write_binary}
5928 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5929 @item @b{flash auto_erase}
5930 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5932 @item @b{jtag_device}
5933 @*use the @command{jtag newtap} command, converting from positional syntax
5934 to named prefixes, and naming the TAP.
5936 Note that if you try to use the old command, a message will tell you the
5937 right new command to use; and that the fourth parameter in the old syntax
5938 was never actually used.
5940 OLD: jtag_device 8 0x01 0xe3 0xfe
5941 NEW: jtag newtap CHIPNAME TAPNAME \
5942 -irlen 8 -ircapture 0x01 -irmask 0xe3
5945 @item @b{jtag_speed} value
5946 @*@xref{JTAG Speed}.
5947 Usually, a value of zero means maximum
5948 speed. The actual effect of this option depends on the JTAG interface used.
5950 @item wiggler: maximum speed / @var{number}
5951 @item ft2232: 6MHz / (@var{number}+1)
5952 @item amt jtagaccel: 8 / 2**@var{number}
5953 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5954 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5955 @comment end speed list.
5958 @item @b{load_binary}
5959 @*use @option{load_image} command with same args. @xref{load_image}.
5960 @item @b{run_and_halt_time}
5961 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5968 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5969 @*use the create subcommand of @option{target}.
5970 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5971 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5972 @item @b{working_area}
5973 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5981 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5983 @cindex adaptive clocking
5986 In digital circuit design it is often refered to as ``clock
5987 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5988 operating at some speed, your target is operating at another. The two
5989 clocks are not synchronised, they are ``asynchronous''
5991 In order for the two to work together they must be synchronised. Otherwise
5992 the two systems will get out of sync with each other and nothing will
5993 work. There are 2 basic options:
5996 Use a special circuit.
5998 One clock must be some multiple slower than the other.
6001 @b{Does this really matter?} For some chips and some situations, this
6002 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6003 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6004 program/enable the oscillators and eventually the main clock. It is in
6005 those critical times you must slow the JTAG clock to sometimes 1 to
6008 Imagine debugging a 500MHz ARM926 hand held battery powered device
6009 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6012 @b{Solution #1 - A special circuit}
6014 In order to make use of this, your JTAG dongle must support the RTCK
6015 feature. Not all dongles support this - keep reading!
6017 The RTCK signal often found in some ARM chips is used to help with
6018 this problem. ARM has a good description of the problem described at
6019 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6020 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6021 work? / how does adaptive clocking work?''.
6023 The nice thing about adaptive clocking is that ``battery powered hand
6024 held device example'' - the adaptiveness works perfectly all the
6025 time. One can set a break point or halt the system in the deep power
6026 down code, slow step out until the system speeds up.
6028 Note that adaptive clocking may also need to work at the board level,
6029 when a board-level scan chain has multiple chips.
6030 Parallel clock voting schemes are good way to implement this,
6031 both within and between chips, and can easily be implemented
6033 It's not difficult to have logic fan a module's input TCK signal out
6034 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6035 back with the right polarity before changing the output RTCK signal.
6036 Texas Instruments makes some clock voting logic available
6037 for free (with no support) in VHDL form; see
6038 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6040 @b{Solution #2 - Always works - but may be slower}
6042 Often this is a perfectly acceptable solution.
6044 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6045 the target clock speed. But what that ``magic division'' is varies
6046 depending on the chips on your board.
6047 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6048 ARM11 cores use an 8:1 division.
6049 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6051 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6053 You can still debug the 'low power' situations - you just need to
6054 manually adjust the clock speed at every step. While painful and
6055 tedious, it is not always practical.
6057 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6058 have a special debug mode in your application that does a ``high power
6059 sleep''. If you are careful - 98% of your problems can be debugged
6062 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6063 operation in your idle loops even if you don't otherwise change the CPU
6065 That operation gates the CPU clock, and thus the JTAG clock; which
6066 prevents JTAG access. One consequence is not being able to @command{halt}
6067 cores which are executing that @emph{wait for interrupt} operation.
6069 To set the JTAG frequency use the command:
6077 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6079 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6080 around Windows filenames.
6093 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6095 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6096 claims to come with all the necessary DLLs. When using Cygwin, try launching
6097 OpenOCD from the Cygwin shell.
6099 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6100 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6101 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6103 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6104 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6105 software breakpoints consume one of the two available hardware breakpoints.
6107 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6109 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6110 clock at the time you're programming the flash. If you've specified the crystal's
6111 frequency, make sure the PLL is disabled. If you've specified the full core speed
6112 (e.g. 60MHz), make sure the PLL is enabled.
6114 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6115 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6116 out while waiting for end of scan, rtck was disabled".
6118 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6119 settings in your PC BIOS (ECP, EPP, and different versions of those).
6121 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6122 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6123 memory read caused data abort".
6125 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6126 beyond the last valid frame. It might be possible to prevent this by setting up
6127 a proper "initial" stack frame, if you happen to know what exactly has to
6128 be done, feel free to add this here.
6130 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6131 stack before calling main(). What GDB is doing is ``climbing'' the run
6132 time stack by reading various values on the stack using the standard
6133 call frame for the target. GDB keeps going - until one of 2 things
6134 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6135 stackframes have been processed. By pushing zeros on the stack, GDB
6138 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6139 your C code, do the same - artifically push some zeros onto the stack,
6140 remember to pop them off when the ISR is done.
6142 @b{Also note:} If you have a multi-threaded operating system, they
6143 often do not @b{in the intrest of saving memory} waste these few
6147 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6148 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6150 This warning doesn't indicate any serious problem, as long as you don't want to
6151 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6152 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6153 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6154 independently. With this setup, it's not possible to halt the core right out of
6155 reset, everything else should work fine.
6157 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6158 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6159 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6160 quit with an error message. Is there a stability issue with OpenOCD?
6162 No, this is not a stability issue concerning OpenOCD. Most users have solved
6163 this issue by simply using a self-powered USB hub, which they connect their
6164 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6165 supply stable enough for the Amontec JTAGkey to be operated.
6167 @b{Laptops running on battery have this problem too...}
6169 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6170 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6171 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6172 What does that mean and what might be the reason for this?
6174 First of all, the reason might be the USB power supply. Try using a self-powered
6175 hub instead of a direct connection to your computer. Secondly, the error code 4
6176 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6177 chip ran into some sort of error - this points us to a USB problem.
6179 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6180 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6181 What does that mean and what might be the reason for this?
6183 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6184 has closed the connection to OpenOCD. This might be a GDB issue.
6186 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6187 are described, there is a parameter for specifying the clock frequency
6188 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6189 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6190 specified in kilohertz. However, I do have a quartz crystal of a
6191 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6192 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6195 No. The clock frequency specified here must be given as an integral number.
6196 However, this clock frequency is used by the In-Application-Programming (IAP)
6197 routines of the LPC2000 family only, which seems to be very tolerant concerning
6198 the given clock frequency, so a slight difference between the specified clock
6199 frequency and the actual clock frequency will not cause any trouble.
6201 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6203 Well, yes and no. Commands can be given in arbitrary order, yet the
6204 devices listed for the JTAG scan chain must be given in the right
6205 order (jtag newdevice), with the device closest to the TDO-Pin being
6206 listed first. In general, whenever objects of the same type exist
6207 which require an index number, then these objects must be given in the
6208 right order (jtag newtap, targets and flash banks - a target
6209 references a jtag newtap and a flash bank references a target).
6211 You can use the ``scan_chain'' command to verify and display the tap order.
6213 Also, some commands can't execute until after @command{init} has been
6214 processed. Such commands include @command{nand probe} and everything
6215 else that needs to write to controller registers, perhaps for setting
6216 up DRAM and loading it with code.
6218 @anchor{FAQ TAP Order}
6219 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6222 Yes; whenever you have more than one, you must declare them in
6223 the same order used by the hardware.
6225 Many newer devices have multiple JTAG TAPs. For example: ST
6226 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6227 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6228 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6229 connected to the boundary scan TAP, which then connects to the
6230 Cortex-M3 TAP, which then connects to the TDO pin.
6232 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6233 (2) The boundary scan TAP. If your board includes an additional JTAG
6234 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6235 place it before or after the STM32 chip in the chain. For example:
6238 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6239 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6240 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6241 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6242 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6245 The ``jtag device'' commands would thus be in the order shown below. Note:
6248 @item jtag newtap Xilinx tap -irlen ...
6249 @item jtag newtap stm32 cpu -irlen ...
6250 @item jtag newtap stm32 bs -irlen ...
6251 @item # Create the debug target and say where it is
6252 @item target create stm32.cpu -chain-position stm32.cpu ...
6256 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6257 log file, I can see these error messages: Error: arm7_9_common.c:561
6258 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6264 @node Tcl Crash Course
6265 @chapter Tcl Crash Course
6268 Not everyone knows Tcl - this is not intended to be a replacement for
6269 learning Tcl, the intent of this chapter is to give you some idea of
6270 how the Tcl scripts work.
6272 This chapter is written with two audiences in mind. (1) OpenOCD users
6273 who need to understand a bit more of how JIM-Tcl works so they can do
6274 something useful, and (2) those that want to add a new command to
6277 @section Tcl Rule #1
6278 There is a famous joke, it goes like this:
6280 @item Rule #1: The wife is always correct
6281 @item Rule #2: If you think otherwise, See Rule #1
6284 The Tcl equal is this:
6287 @item Rule #1: Everything is a string
6288 @item Rule #2: If you think otherwise, See Rule #1
6291 As in the famous joke, the consequences of Rule #1 are profound. Once
6292 you understand Rule #1, you will understand Tcl.
6294 @section Tcl Rule #1b
6295 There is a second pair of rules.
6297 @item Rule #1: Control flow does not exist. Only commands
6298 @* For example: the classic FOR loop or IF statement is not a control
6299 flow item, they are commands, there is no such thing as control flow
6301 @item Rule #2: If you think otherwise, See Rule #1
6302 @* Actually what happens is this: There are commands that by
6303 convention, act like control flow key words in other languages. One of
6304 those commands is the word ``for'', another command is ``if''.
6307 @section Per Rule #1 - All Results are strings
6308 Every Tcl command results in a string. The word ``result'' is used
6309 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6310 Everything is a string}
6312 @section Tcl Quoting Operators
6313 In life of a Tcl script, there are two important periods of time, the
6314 difference is subtle.
6317 @item Evaluation Time
6320 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6321 three primary quoting constructs, the [square-brackets] the
6322 @{curly-braces@} and ``double-quotes''
6324 By now you should know $VARIABLES always start with a $DOLLAR
6325 sign. BTW: To set a variable, you actually use the command ``set'', as
6326 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6327 = 1'' statement, but without the equal sign.
6330 @item @b{[square-brackets]}
6331 @* @b{[square-brackets]} are command substitutions. It operates much
6332 like Unix Shell `back-ticks`. The result of a [square-bracket]
6333 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6334 string}. These two statements are roughly identical:
6338 echo "The Date is: $X"
6341 puts "The Date is: $X"
6343 @item @b{``double-quoted-things''}
6344 @* @b{``double-quoted-things''} are just simply quoted
6345 text. $VARIABLES and [square-brackets] are expanded in place - the
6346 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6350 puts "It is now \"[date]\", $x is in 1 hour"
6352 @item @b{@{Curly-Braces@}}
6353 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6354 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6355 'single-quote' operators in BASH shell scripts, with the added
6356 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6357 nested 3 times@}@}@} NOTE: [date] is a bad example;
6358 at this writing, Jim/OpenOCD does not have a date command.
6361 @section Consequences of Rule 1/2/3/4
6363 The consequences of Rule 1 are profound.
6365 @subsection Tokenisation & Execution.
6367 Of course, whitespace, blank lines and #comment lines are handled in
6370 As a script is parsed, each (multi) line in the script file is
6371 tokenised and according to the quoting rules. After tokenisation, that
6372 line is immedatly executed.
6374 Multi line statements end with one or more ``still-open''
6375 @{curly-braces@} which - eventually - closes a few lines later.
6377 @subsection Command Execution
6379 Remember earlier: There are no ``control flow''
6380 statements in Tcl. Instead there are COMMANDS that simply act like
6381 control flow operators.
6383 Commands are executed like this:
6386 @item Parse the next line into (argc) and (argv[]).
6387 @item Look up (argv[0]) in a table and call its function.
6388 @item Repeat until End Of File.
6391 It sort of works like this:
6394 ReadAndParse( &argc, &argv );
6396 cmdPtr = LookupCommand( argv[0] );
6398 (*cmdPtr->Execute)( argc, argv );
6402 When the command ``proc'' is parsed (which creates a procedure
6403 function) it gets 3 parameters on the command line. @b{1} the name of
6404 the proc (function), @b{2} the list of parameters, and @b{3} the body
6405 of the function. Not the choice of words: LIST and BODY. The PROC
6406 command stores these items in a table somewhere so it can be found by
6409 @subsection The FOR command
6411 The most interesting command to look at is the FOR command. In Tcl,
6412 the FOR command is normally implemented in C. Remember, FOR is a
6413 command just like any other command.
6415 When the ascii text containing the FOR command is parsed, the parser
6416 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6420 @item The ascii text 'for'
6421 @item The start text
6422 @item The test expression
6427 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6428 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6429 Often many of those parameters are in @{curly-braces@} - thus the
6430 variables inside are not expanded or replaced until later.
6432 Remember that every Tcl command looks like the classic ``main( argc,
6433 argv )'' function in C. In JimTCL - they actually look like this:
6437 MyCommand( Jim_Interp *interp,
6439 Jim_Obj * const *argvs );
6442 Real Tcl is nearly identical. Although the newer versions have
6443 introduced a byte-code parser and intepreter, but at the core, it
6444 still operates in the same basic way.
6446 @subsection FOR command implementation
6448 To understand Tcl it is perhaps most helpful to see the FOR
6449 command. Remember, it is a COMMAND not a control flow structure.
6451 In Tcl there are two underlying C helper functions.
6453 Remember Rule #1 - You are a string.
6455 The @b{first} helper parses and executes commands found in an ascii
6456 string. Commands can be seperated by semicolons, or newlines. While
6457 parsing, variables are expanded via the quoting rules.
6459 The @b{second} helper evaluates an ascii string as a numerical
6460 expression and returns a value.
6462 Here is an example of how the @b{FOR} command could be
6463 implemented. The pseudo code below does not show error handling.
6465 void Execute_AsciiString( void *interp, const char *string );
6467 int Evaluate_AsciiExpression( void *interp, const char *string );
6470 MyForCommand( void *interp,
6475 SetResult( interp, "WRONG number of parameters");
6479 // argv[0] = the ascii string just like C
6481 // Execute the start statement.
6482 Execute_AsciiString( interp, argv[1] );
6486 i = Evaluate_AsciiExpression(interp, argv[2]);
6491 Execute_AsciiString( interp, argv[3] );
6493 // Execute the LOOP part
6494 Execute_AsciiString( interp, argv[4] );
6498 SetResult( interp, "" );
6503 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6504 in the same basic way.
6506 @section OpenOCD Tcl Usage
6508 @subsection source and find commands
6509 @b{Where:} In many configuration files
6510 @* Example: @b{ source [find FILENAME] }
6511 @*Remember the parsing rules
6513 @item The FIND command is in square brackets.
6514 @* The FIND command is executed with the parameter FILENAME. It should
6515 find the full path to the named file. The RESULT is a string, which is
6516 substituted on the orginal command line.
6517 @item The command source is executed with the resulting filename.
6518 @* SOURCE reads a file and executes as a script.
6520 @subsection format command
6521 @b{Where:} Generally occurs in numerous places.
6522 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6528 puts [format "The answer: %d" [expr $x * $y]]
6531 @item The SET command creates 2 variables, X and Y.
6532 @item The double [nested] EXPR command performs math
6533 @* The EXPR command produces numerical result as a string.
6535 @item The format command is executed, producing a single string
6536 @* Refer to Rule #1.
6537 @item The PUTS command outputs the text.
6539 @subsection Body or Inlined Text
6540 @b{Where:} Various TARGET scripts.
6543 proc someproc @{@} @{
6544 ... multiple lines of stuff ...
6546 $_TARGETNAME configure -event FOO someproc
6547 #2 Good - no variables
6548 $_TARGETNAME confgure -event foo "this ; that;"
6549 #3 Good Curly Braces
6550 $_TARGETNAME configure -event FOO @{
6553 #4 DANGER DANGER DANGER
6554 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6557 @item The $_TARGETNAME is an OpenOCD variable convention.
6558 @*@b{$_TARGETNAME} represents the last target created, the value changes
6559 each time a new target is created. Remember the parsing rules. When
6560 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6561 the name of the target which happens to be a TARGET (object)
6563 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6564 @*There are 4 examples:
6566 @item The TCLBODY is a simple string that happens to be a proc name
6567 @item The TCLBODY is several simple commands seperated by semicolons
6568 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6569 @item The TCLBODY is a string with variables that get expanded.
6572 In the end, when the target event FOO occurs the TCLBODY is
6573 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6574 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6576 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6577 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6578 and the text is evaluated. In case #4, they are replaced before the
6579 ``Target Object Command'' is executed. This occurs at the same time
6580 $_TARGETNAME is replaced. In case #4 the date will never
6581 change. @{BTW: [date] is a bad example; at this writing,
6582 Jim/OpenOCD does not have a date command@}
6584 @subsection Global Variables
6585 @b{Where:} You might discover this when writing your own procs @* In
6586 simple terms: Inside a PROC, if you need to access a global variable
6587 you must say so. See also ``upvar''. Example:
6589 proc myproc @{ @} @{
6590 set y 0 #Local variable Y
6591 global x #Global variable X
6592 puts [format "X=%d, Y=%d" $x $y]
6595 @section Other Tcl Hacks
6596 @b{Dynamic variable creation}
6598 # Dynamically create a bunch of variables.
6599 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6601 set vn [format "BIT%d" $x]
6605 set $vn [expr (1 << $x)]
6608 @b{Dynamic proc/command creation}
6610 # One "X" function - 5 uart functions.
6611 foreach who @{A B C D E@}
6612 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6616 @node Target Library
6617 @chapter Target Library
6618 @cindex Target Library
6620 OpenOCD comes with a target configuration script library. These scripts can be
6621 used as-is or serve as a starting point.
6623 The target library is published together with the OpenOCD executable and
6624 the path to the target library is in the OpenOCD script search path.
6625 Similarly there are example scripts for configuring the JTAG interface.
6627 The command line below uses the example parport configuration script
6628 that ship with OpenOCD, then configures the str710.cfg target and
6629 finally issues the init and reset commands. The communication speed
6630 is set to 10kHz for reset and 8MHz for post reset.
6633 openocd -f interface/parport.cfg -f target/str710.cfg \
6634 -c "init" -c "reset"
6637 To list the target scripts available:
6640 $ ls /usr/local/lib/openocd/target
6642 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6643 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6644 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6645 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6650 @node OpenOCD Concept Index
6651 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6652 @comment case issue with ``Index.html'' and ``index.html''
6653 @comment Occurs when creating ``--html --no-split'' output
6654 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6655 @unnumbered OpenOCD Concept Index
6659 @node Command and Driver Index
6660 @unnumbered Command and Driver Index