1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are several things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
257 Does your dongle support it? You might need a level converter.
258 @item @b{Pinout} What pinout does your target board use?
259 Does your dongle support it? You may be able to use jumper
260 wires, or an "octopus" connector, to convert pinouts.
261 @item @b{Connection} Does your computer have the USB, printer, or
262 Ethernet port needed?
263 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
266 @section Stand alone Systems
268 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
269 dongle, but a standalone box. The ZY1000 has the advantage that it does
270 not require any drivers installed on the developer PC. It also has
271 a built in web interface. It supports RTCK/RCLK or adaptive clocking
272 and has a built in relay to power cycle targets remotely.
274 @section USB FT2232 Based
276 There are many USB JTAG dongles on the market, many of them are based
277 on a chip from ``Future Technology Devices International'' (FTDI)
278 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
279 See: @url{http://www.ftdichip.com} for more information.
280 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
281 chips are starting to become available in JTAG adapters.
285 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
287 @* See: @url{http://www.amontec.com/jtagkey.shtml}
289 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
291 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
293 @* See: @url{http://www.signalyzer.com}
294 @item @b{evb_lm3s811}
295 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
296 @item @b{luminary_icdi}
297 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
304 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
305 @url{http://www.ethernut.de}
307 @* Link: @url{http://www.hitex.com/index.php?id=383}
309 @* Link @url{http://www.hitex.com/stm32-stick}
310 @item @b{axm0432_jtag}
311 @* Axiom AXM-0432 Link @url{http://www.axman.com}
313 @* Link @url{http://www.hitex.com/index.php?id=cortino}
316 @section USB JLINK based
317 There are several OEM versions of the Segger @b{JLINK} adapter. It is
318 an example of a micro controller based JTAG adapter, it uses an
319 AT91SAM764 internally.
322 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
323 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
324 @item @b{SEGGER JLINK}
325 @* Link: @url{http://www.segger.com/jlink.html}
327 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
330 @section USB RLINK based
331 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
334 @item @b{Raisonance RLink}
335 @* Link: @url{http://www.raisonance.com/products/RLink.php}
336 @item @b{STM32 Primer}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
338 @item @b{STM32 Primer2}
339 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
345 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
347 @item @b{USB - Presto}
348 @* Link: @url{http://tools.asix.net/prg_presto.htm}
350 @item @b{Versaloon-Link}
351 @* Link: @url{http://www.simonqian.com/en/Versaloon}
353 @item @b{ARM-JTAG-EW}
354 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
357 @section IBM PC Parallel Printer Port Based
359 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
360 and the MacGraigor Wiggler. There are many clones and variations of
363 Note that parallel ports are becoming much less common, so if you
364 have the choice you should probably avoid these adapters in favor
369 @item @b{Wiggler} - There are many clones of this.
370 @* Link: @url{http://www.macraigor.com/wiggler.htm}
372 @item @b{DLC5} - From XILINX - There are many clones of this
373 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
374 produced, PDF schematics are easily found and it is easy to make.
376 @item @b{Amontec - JTAG Accelerator}
377 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
380 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
383 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
384 Improved parallel-port wiggler-style JTAG adapter}
386 @item @b{Wiggler_ntrst_inverted}
387 @* Yet another variation - See the source code, src/jtag/parport.c
389 @item @b{old_amt_wiggler}
390 @* Unknown - probably not on the market today
393 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
396 @* Link: @url{http://www.amontec.com/chameleon.shtml}
402 @* ispDownload from Lattice Semiconductor
403 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
406 @* From ST Microsystems;
407 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
408 FlashLINK JTAG programing cable for PSD and uPSD}
416 @* An EP93xx based Linux machine using the GPIO pins directly.
419 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
424 @chapter About JIM-Tcl
428 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
429 This programming language provides a simple and extensible
432 All commands presented in this Guide are extensions to JIM-Tcl.
433 You can use them as simple commands, without needing to learn
434 much of anything about Tcl.
435 Alternatively, can write Tcl programs with them.
437 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
440 @item @b{JIM vs. Tcl}
441 @* JIM-TCL is a stripped down version of the well known Tcl language,
442 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
443 fewer features. JIM-Tcl is a single .C file and a single .H file and
444 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
445 4.2 MB .zip file containing 1540 files.
447 @item @b{Missing Features}
448 @* Our practice has been: Add/clone the real Tcl feature if/when
449 needed. We welcome JIM Tcl improvements, not bloat.
452 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
453 command interpreter today is a mixture of (newer)
454 JIM-Tcl commands, and (older) the orginal command interpreter.
457 @* At the OpenOCD telnet command line (or via the GDB mon command) one
458 can type a Tcl for() loop, set variables, etc.
459 Some of the commands documented in this guide are implemented
460 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
462 @item @b{Historical Note}
463 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
465 @item @b{Need a crash course in Tcl?}
466 @*@xref{Tcl Crash Course}.
471 @cindex command line options
473 @cindex directory search
475 The @option{--help} option shows:
479 --help | -h display this help
480 --version | -v display OpenOCD version
481 --file | -f use configuration file <name>
482 --search | -s dir to search for config files and scripts
483 --debug | -d set debug level <0-3>
484 --log_output | -l redirect log output to file <name>
485 --command | -c run <command>
486 --pipe | -p use pipes when talking to gdb
489 By default OpenOCD reads the file configuration file ``openocd.cfg''
490 in the current directory. To specify a different (or multiple)
491 configuration file, you can use the ``-f'' option. For example:
494 openocd -f config1.cfg -f config2.cfg -f config3.cfg
497 Once started, OpenOCD runs as a daemon, waiting for connections from
498 clients (Telnet, GDB, Other).
500 If you are having problems, you can enable internal debug messages via
503 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
504 @option{-c} command line switch.
506 To enable debug output (when reporting problems or working on OpenOCD
507 itself), use the @option{-d} command line switch. This sets the
508 @option{debug_level} to "3", outputting the most information,
509 including debug messages. The default setting is "2", outputting only
510 informational messages, warnings and errors. You can also change this
511 setting from within a telnet or gdb session using @command{debug_level
512 <n>} (@pxref{debug_level}).
514 You can redirect all output from the daemon to a file using the
515 @option{-l <logfile>} switch.
517 Search paths for config/script files can be added to OpenOCD by using
518 the @option{-s <search>} switch. The current directory and the OpenOCD
519 target library is in the search path by default.
521 For details on the @option{-p} option. @xref{Connecting to GDB}.
523 Note! OpenOCD will launch the GDB & telnet server even if it can not
524 establish a connection with the target. In general, it is possible for
525 the JTAG controller to be unresponsive until the target is set up
526 correctly via e.g. GDB monitor commands in a GDB init script.
528 @node OpenOCD Project Setup
529 @chapter OpenOCD Project Setup
531 To use OpenOCD with your development projects, you need to do more than
532 just connecting the JTAG adapter hardware (dongle) to your development board
533 and then starting the OpenOCD server.
534 You also need to configure that server so that it knows
535 about that adapter and board, and helps your work.
537 @section Hooking up the JTAG Adapter
539 Today's most common case is a dongle with a JTAG cable on one side
540 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
541 and a USB cable on the other.
542 Instead of USB, some cables use Ethernet;
543 older ones may use a PC parallel port, or even a serial port.
546 @item @emph{Start with power to your target board turned off},
547 and nothing connected to your JTAG adapter.
548 If you're particularly paranoid, unplug power to the board.
549 It's important to have the ground signal properly set up,
550 unless you are using a JTAG adapter which provides
551 galvanic isolation between the target board and the
554 @item @emph{Be sure it's the right kind of JTAG connector.}
555 If your dongle has a 20-pin ARM connector, you need some kind
556 of adapter (or octopus, see below) to hook it up to
557 boards using 14-pin or 10-pin connectors ... or to 20-pin
558 connectors which don't use ARM's pinout.
560 In the same vein, make sure the voltage levels are compatible.
561 Not all JTAG adapters have the level shifters needed to work
562 with 1.2 Volt boards.
564 @item @emph{Be certain the cable is properly oriented} or you might
565 damage your board. In most cases there are only two possible
566 ways to connect the cable.
567 Connect the JTAG cable from your adapter to the board.
568 Be sure it's firmly connected.
570 In the best case, the connector is keyed to physically
571 prevent you from inserting it wrong.
572 This is most often done using a slot on the board's male connector
573 housing, which must match a key on the JTAG cable's female connector.
574 If there's no housing, then you must look carefully and
575 make sure pin 1 on the cable hooks up to pin 1 on the board.
576 Ribbon cables are frequently all grey except for a wire on one
577 edge, which is red. The red wire is pin 1.
579 Sometimes dongles provide cables where one end is an ``octopus'' of
580 color coded single-wire connectors, instead of a connector block.
581 These are great when converting from one JTAG pinout to another,
582 but are tedious to set up.
583 Use these with connector pinout diagrams to help you match up the
584 adapter signals to the right board pins.
586 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
587 A USB, parallel, or serial port connector will go to the host which
588 you are using to run OpenOCD.
589 For Ethernet, consult the documentation and your network administrator.
591 For USB based JTAG adapters you have an easy sanity check at this point:
592 does the host operating system see the JTAG adapter?
594 @item @emph{Connect the adapter's power supply, if needed.}
595 This step is primarily for non-USB adapters,
596 but sometimes USB adapters need extra power.
598 @item @emph{Power up the target board.}
599 Unless you just let the magic smoke escape,
600 you're now ready to set up the OpenOCD server
601 so you can use JTAG to work with that board.
605 Talk with the OpenOCD server using
606 telnet (@code{telnet localhost 4444} on many systems) or GDB.
607 @xref{GDB and OpenOCD}.
609 @section Project Directory
611 There are many ways you can configure OpenOCD and start it up.
613 A simple way to organize them all involves keeping a
614 single directory for your work with a given board.
615 When you start OpenOCD from that directory,
616 it searches there first for configuration files, scripts,
617 and for code you upload to the target board.
618 It is also the natural place to write files,
619 such as log files and data you download from the board.
621 @section Configuration Basics
623 There are two basic ways of configuring OpenOCD, and
624 a variety of ways you can mix them.
625 Think of the difference as just being how you start the server:
628 @item Many @option{-f file} or @option{-c command} options on the command line
629 @item No options, but a @dfn{user config file}
630 in the current directory named @file{openocd.cfg}
633 Here is an example @file{openocd.cfg} file for a setup
634 using a Signalyzer FT2232-based JTAG adapter to talk to
635 a board with an Atmel AT91SAM7X256 microcontroller:
638 source [find interface/signalyzer.cfg]
640 # GDB can also flash my flash!
641 gdb_memory_map enable
642 gdb_flash_program enable
644 source [find target/sam7x256.cfg]
647 Here is the command line equivalent of that configuration:
650 openocd -f interface/signalyzer.cfg \
651 -c "gdb_memory_map enable" \
652 -c "gdb_flash_program enable" \
653 -f target/sam7x256.cfg
656 You could wrap such long command lines in shell scripts,
657 each supporting a different development task.
658 One might re-flash the board with a specific firmware version.
659 Another might set up a particular debugging or run-time environment.
661 Here we will focus on the simpler solution: one user config
662 file, including basic configuration plus any TCL procedures
663 to simplify your work.
665 @section User Config Files
666 @cindex config file, user
667 @cindex user config file
668 @cindex config file, overview
670 A user configuration file ties together all the parts of a project
672 One of the following will match your situation best:
675 @item Ideally almost everything comes from configuration files
676 provided by someone else.
677 For example, OpenOCD distributes a @file{scripts} directory
678 (probably in @file{/usr/share/openocd/scripts} on Linux).
679 Board and tool vendors can provide these too, as can individual
680 user sites; the @option{-s} command line option lets you say
681 where to find these files. (@xref{Running}.)
682 The AT91SAM7X256 example above works this way.
684 Three main types of non-user configuration file each have their
685 own subdirectory in the @file{scripts} directory:
688 @item @b{interface} -- one for each kind of JTAG adapter/dongle
689 @item @b{board} -- one for each different board
690 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
693 Best case: include just two files, and they handle everything else.
694 The first is an interface config file.
695 The second is board-specific, and it sets up the JTAG TAPs and
696 their GDB targets (by deferring to some @file{target.cfg} file),
697 declares all flash memory, and leaves you nothing to do except
701 source [find interface/olimex-jtag-tiny.cfg]
702 source [find board/csb337.cfg]
705 Boards with a single microcontroller often won't need more
706 than the target config file, as in the AT91SAM7X256 example.
707 That's because there is no external memory (flash, DDR RAM), and
708 the board differences are encapsulated by application code.
710 @item You can often reuse some standard config files but
711 need to write a few new ones, probably a @file{board.cfg} file.
712 You will be using commands described later in this User's Guide,
713 and working with the guidelines in the next chapter.
715 For example, there may be configuration files for your JTAG adapter
716 and target chip, but you need a new board-specific config file
717 giving access to your particular flash chips.
718 Or you might need to write another target chip configuration file
719 for a new chip built around the Cortex M3 core.
722 When you write new configuration files, please submit
723 them for inclusion in the next OpenOCD release.
724 For example, a @file{board/newboard.cfg} file will help the
725 next users of that board, and a @file{target/newcpu.cfg}
726 will help support users of any board using that chip.
730 You may may need to write some C code.
731 It may be as simple as a supporting a new ft2232 or parport
732 based dongle; a bit more involved, like a NAND or NOR flash
733 controller driver; or a big piece of work like supporting
734 a new chip architecture.
737 Reuse the existing config files when you can.
738 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
739 You may find a board configuration that's a good example to follow.
741 When you write config files, separate the reusable parts
742 (things every user of that interface, chip, or board needs)
743 from ones specific to your environment and debugging approach.
747 For example, a @code{gdb-attach} event handler that invokes
748 the @command{reset init} command will interfere with debugging
749 early boot code, which performs some of the same actions
750 that the @code{reset-init} event handler does.
753 Likewise, the @command{arm9tdmi vector_catch} command (or
755 its siblings @command{xscale vector_catch}
756 and @command{cortex_m3 vector_catch}) can be a timesaver
757 during some debug sessions, but don't make everyone use that either.
758 Keep those kinds of debugging aids in your user config file,
759 along with messaging and tracing setup.
760 (@xref{Software Debug Messages and Tracing}.)
763 You might need to override some defaults.
764 For example, you might need to move, shrink, or back up the target's
765 work area if your application needs much SRAM.
768 TCP/IP port configuration is another example of something which
769 is environment-specific, and should only appear in
770 a user config file. @xref{TCP/IP Ports}.
773 @section Project-Specific Utilities
775 A few project-specific utility
776 routines may well speed up your work.
777 Write them, and keep them in your project's user config file.
779 For example, if you are making a boot loader work on a
780 board, it's nice to be able to debug the ``after it's
781 loaded to RAM'' parts separately from the finicky early
782 code which sets up the DDR RAM controller and clocks.
783 A script like this one, or a more GDB-aware sibling,
787 proc ramboot @{ @} @{
788 # Reset, running the target's "reset-init" scripts
789 # to initialize clocks and the DDR RAM controller.
790 # Leave the CPU halted.
793 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
794 load_image u-boot.bin 0x20000000
801 Then once that code is working you will need to make it
802 boot from NOR flash; a different utility would help.
803 Alternatively, some developers write to flash using GDB.
804 (You might use a similar script if you're working with a flash
805 based microcontroller application instead of a boot loader.)
808 proc newboot @{ @} @{
809 # Reset, leaving the CPU halted. The "reset-init" event
810 # proc gives faster access to the CPU and to NOR flash;
811 # "reset halt" would be slower.
814 # Write standard version of U-Boot into the first two
815 # sectors of NOR flash ... the standard version should
816 # do the same lowlevel init as "reset-init".
817 flash protect 0 0 1 off
818 flash erase_sector 0 0 1
819 flash write_bank 0 u-boot.bin 0x0
820 flash protect 0 0 1 on
822 # Reboot from scratch using that new boot loader.
827 You may need more complicated utility procedures when booting
829 That often involves an extra bootloader stage,
830 running from on-chip SRAM to perform DDR RAM setup so it can load
831 the main bootloader code (which won't fit into that SRAM).
833 Other helper scripts might be used to write production system images,
834 involving considerably more than just a three stage bootloader.
837 @node Config File Guidelines
838 @chapter Config File Guidelines
840 This chapter is aimed at any user who needs to write a config file,
841 including developers and integrators of OpenOCD and any user who
842 needs to get a new board working smoothly.
843 It provides guidelines for creating those files.
845 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
848 @item @file{interface} ...
849 think JTAG Dongle. Files that configure JTAG adapters go here.
850 @item @file{board} ...
851 think Circuit Board, PWA, PCB, they go by many names. Board files
852 contain initialization items that are specific to a board. For
853 example, the SDRAM initialization sequence for the board, or the type
854 of external flash and what address it uses. Any initialization
855 sequence to enable that external flash or SDRAM should be found in the
856 board file. Boards may also contain multiple targets: two CPUs; or
857 a CPU and an FPGA or CPLD.
858 @item @file{target} ...
859 think chip. The ``target'' directory represents the JTAG TAPs
861 which OpenOCD should control, not a board. Two common types of targets
862 are ARM chips and FPGA or CPLD chips.
863 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
864 the target config file defines all of them.
867 The @file{openocd.cfg} user config
868 file may override features in any of the above files by
869 setting variables before sourcing the target file, or by adding
870 commands specific to their situation.
872 @section Interface Config Files
875 should be able to source one of these files with a command like this:
878 source [find interface/FOOBAR.cfg]
881 A preconfigured interface file should exist for every interface in use
882 today, that said, perhaps some interfaces have only been used by the
883 sole developer who created it.
885 A separate chapter gives information about how to set these up.
886 @xref{Interface - Dongle Configuration}.
887 Read the OpenOCD source code if you have a new kind of hardware interface
888 and need to provide a driver for it.
890 @section Board Config Files
891 @cindex config file, board
892 @cindex board config file
895 should be able to source one of these files with a command like this:
898 source [find board/FOOBAR.cfg]
901 The point of a board config file is to package everything
902 about a given board that user config files need to know.
903 In summary the board files should contain (if present)
906 @item One or more @command{source [target/...cfg]} statements
907 @item NOR flash configuration (@pxref{NOR Configuration})
908 @item NAND flash configuration (@pxref{NAND Configuration})
909 @item Target @code{reset} handlers for SDRAM and I/O configuration
910 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
911 @item All things that are not ``inside a chip''
914 Generic things inside target chips belong in target config files,
915 not board config files. So for example a @code{reset-init} event
916 handler should know board-specific oscillator and PLL parameters,
917 which it passes to target-specific utility code.
919 The most complex task of a board config file is creating such a
920 @code{reset-init} event handler.
921 Define those handlers last, after you verify the rest of the board
924 @subsection Communication Between Config files
926 In addition to target-specific utility code, another way that
927 board and target config files communicate is by following a
928 convention on how to use certain variables.
930 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
931 Thus the rule we follow in OpenOCD is this: Variables that begin with
932 a leading underscore are temporary in nature, and can be modified and
933 used at will within a target configuration file.
935 Complex board config files can do the things like this,
936 for a board with three chips:
939 # Chip #1: PXA270 for network side, big endian
942 source [find target/pxa270.cfg]
943 # on return: _TARGETNAME = network.cpu
944 # other commands can refer to the "network.cpu" target.
945 $_TARGETNAME configure .... events for this CPU..
947 # Chip #2: PXA270 for video side, little endian
950 source [find target/pxa270.cfg]
951 # on return: _TARGETNAME = video.cpu
952 # other commands can refer to the "video.cpu" target.
953 $_TARGETNAME configure .... events for this CPU..
955 # Chip #3: Xilinx FPGA for glue logic
958 source [find target/spartan3.cfg]
961 That example is oversimplified because it doesn't show any flash memory,
962 or the @code{reset-init} event handlers to initialize external DRAM
963 or (assuming it needs it) load a configuration into the FPGA.
964 Such features are usually needed for low-level work with many boards,
965 where ``low level'' implies that the board initialization software may
966 not be working. (That's a common reason to need JTAG tools. Another
967 is to enable working with microcontroller-based systems, which often
968 have no debugging support except a JTAG connector.)
970 Target config files may also export utility functions to board and user
971 config files. Such functions should use name prefixes, to help avoid
974 Board files could also accept input variables from user config files.
975 For example, there might be a @code{J4_JUMPER} setting used to identify
976 what kind of flash memory a development board is using, or how to set
977 up other clocks and peripherals.
979 @subsection Variable Naming Convention
980 @cindex variable names
982 Most boards have only one instance of a chip.
983 However, it should be easy to create a board with more than
984 one such chip (as shown above).
985 Accordingly, we encourage these conventions for naming
986 variables associated with different @file{target.cfg} files,
987 to promote consistency and
988 so that board files can override target defaults.
990 Inputs to target config files include:
993 @item @code{CHIPNAME} ...
994 This gives a name to the overall chip, and is used as part of
995 tap identifier dotted names.
996 While the default is normally provided by the chip manufacturer,
997 board files may need to distinguish between instances of a chip.
998 @item @code{ENDIAN} ...
999 By default @option{little} - although chips may hard-wire @option{big}.
1000 Chips that can't change endianness don't need to use this variable.
1001 @item @code{CPUTAPID} ...
1002 When OpenOCD examines the JTAG chain, it can be told verify the
1003 chips against the JTAG IDCODE register.
1004 The target file will hold one or more defaults, but sometimes the
1005 chip in a board will use a different ID (perhaps a newer revision).
1008 Outputs from target config files include:
1011 @item @code{_TARGETNAME} ...
1012 By convention, this variable is created by the target configuration
1013 script. The board configuration file may make use of this variable to
1014 configure things like a ``reset init'' script, or other things
1015 specific to that board and that target.
1016 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1017 @code{_TARGETNAME1}, ... etc.
1020 @subsection The reset-init Event Handler
1021 @cindex event, reset-init
1022 @cindex reset-init handler
1024 Board config files run in the OpenOCD configuration stage;
1025 they can't use TAPs or targets, since they haven't been
1027 This means you can't write memory or access chip registers;
1028 you can't even verify that a flash chip is present.
1029 That's done later in event handlers, of which the target @code{reset-init}
1030 handler is one of the most important.
1032 Except on microcontrollers, the basic job of @code{reset-init} event
1033 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1034 Microcontrollers rarely use boot loaders; they run right out of their
1035 on-chip flash and SRAM memory. But they may want to use one of these
1036 handlers too, if just for developer convenience.
1039 Because this is so very board-specific, and chip-specific, no examples
1041 Instead, look at the board config files distributed with OpenOCD.
1042 If you have a boot loader, its source code may also be useful.
1045 Some of this code could probably be shared between different boards.
1046 For example, setting up a DRAM controller often doesn't differ by
1047 much except the bus width (16 bits or 32?) and memory timings, so a
1048 reusable TCL procedure loaded by the @file{target.cfg} file might take
1049 those as parameters.
1050 Similarly with oscillator, PLL, and clock setup;
1051 and disabling the watchdog.
1052 Structure the code cleanly, and provide comments to help
1053 the next developer doing such work.
1054 (@emph{You might be that next person} trying to reuse init code!)
1056 The last thing normally done in a @code{reset-init} handler is probing
1057 whatever flash memory was configured. For most chips that needs to be
1058 done while the associated target is halted, either because JTAG memory
1059 access uses the CPU or to prevent conflicting CPU access.
1061 @subsection JTAG Clock Rate
1063 Before your @code{reset-init} handler has set up
1064 the PLLs and clocking, you may need to use
1065 a low JTAG clock rate; then you'd increase it later.
1066 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1067 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1068 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1069 Consult chip documentation to determine the peak JTAG clock rate,
1070 which might be less than that.
1073 On most ARMs, JTAG clock detection is coupled to the core clock, so
1074 software using a @option{wait for interrupt} operation blocks JTAG access.
1075 Adaptive clocking provides a partial workaround, but a more complete
1076 solution just avoids using that instruction with JTAG debuggers.
1079 If the board supports adaptive clocking, use the @command{jtag_rclk}
1080 command, in case your board is used with JTAG adapter which
1081 also supports it. Otherwise use @command{jtag_khz}.
1082 Set the slow rate at the beginning of the reset sequence,
1083 and the faster rate as soon as the clocks are at full speed.
1085 @section Target Config Files
1086 @cindex config file, target
1087 @cindex target config file
1089 Board config files communicate with target config files using
1090 naming conventions as described above, and may source one or
1091 more target config files like this:
1094 source [find target/FOOBAR.cfg]
1097 The point of a target config file is to package everything
1098 about a given chip that board config files need to know.
1099 In summary the target files should contain
1103 @item Add TAPs to the scan chain
1104 @item Add CPU targets (includes GDB support)
1105 @item CPU/Chip/CPU-Core specific features
1109 As a rule of thumb, a target file sets up only one chip.
1110 For a microcontroller, that will often include a single TAP,
1111 which is a CPU needing a GDB target, and its on-chip flash.
1113 More complex chips may include multiple TAPs, and the target
1114 config file may need to define them all before OpenOCD
1115 can talk to the chip.
1116 For example, some phone chips have JTAG scan chains that include
1117 an ARM core for operating system use, a DSP,
1118 another ARM core embedded in an image processing engine,
1119 and other processing engines.
1121 @subsection Default Value Boiler Plate Code
1123 All target configuration files should start with code like this,
1124 letting board config files express environment-specific
1125 differences in how things should be set up.
1128 # Boards may override chip names, perhaps based on role,
1129 # but the default should match what the vendor uses
1130 if @{ [info exists CHIPNAME] @} @{
1131 set _CHIPNAME $CHIPNAME
1133 set _CHIPNAME sam7x256
1136 # ONLY use ENDIAN with targets that can change it.
1137 if @{ [info exists ENDIAN] @} @{
1143 # TAP identifiers may change as chips mature, for example with
1144 # new revision fields (the "3" here). Pick a good default; you
1145 # can pass several such identifiers to the "jtag newtap" command.
1146 if @{ [info exists CPUTAPID ] @} @{
1147 set _CPUTAPID $CPUTAPID
1149 set _CPUTAPID 0x3f0f0f0f
1152 @c but 0x3f0f0f0f is for an str73x part ...
1154 @emph{Remember:} Board config files may include multiple target
1155 config files, or the same target file multiple times
1156 (changing at least @code{CHIPNAME}).
1158 Likewise, the target configuration file should define
1159 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1160 use it later on when defining debug targets:
1163 set _TARGETNAME $_CHIPNAME.cpu
1164 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1167 @subsection Adding TAPs to the Scan Chain
1168 After the ``defaults'' are set up,
1169 add the TAPs on each chip to the JTAG scan chain.
1170 @xref{TAP Declaration}, and the naming convention
1173 In the simplest case the chip has only one TAP,
1174 probably for a CPU or FPGA.
1175 The config file for the Atmel AT91SAM7X256
1176 looks (in part) like this:
1179 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1180 -expected-id $_CPUTAPID
1183 A board with two such at91sam7 chips would be able
1184 to source such a config file twice, with different
1185 values for @code{CHIPNAME}, so
1186 it adds a different TAP each time.
1188 If there are one or more nonzero @option{-expected-id} values,
1189 OpenOCD attempts to verify the actual tap id against those values.
1190 It will issue error messages if there is mismatch, which
1191 can help to pinpoint problems in OpenOCD configurations.
1194 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1195 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1196 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1197 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1198 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1201 There are more complex examples too, with chips that have
1202 multiple TAPs. Ones worth looking at include:
1205 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1206 plus a JRC to enable them
1207 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1208 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1209 is not currently used)
1212 @subsection Add CPU targets
1214 After adding a TAP for a CPU, you should set it up so that
1215 GDB and other commands can use it.
1216 @xref{CPU Configuration}.
1217 For the at91sam7 example above, the command can look like this;
1218 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1219 to little endian, and this chip doesn't support changing that.
1222 set _TARGETNAME $_CHIPNAME.cpu
1223 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1226 Work areas are small RAM areas associated with CPU targets.
1227 They are used by OpenOCD to speed up downloads,
1228 and to download small snippets of code to program flash chips.
1229 If the chip includes a form of ``on-chip-ram'' - and many do - define
1230 a work area if you can.
1231 Again using the at91sam7 as an example, this can look like:
1234 $_TARGETNAME configure -work-area-phys 0x00200000 \
1235 -work-area-size 0x4000 -work-area-backup 0
1238 @subsection Chip Reset Setup
1240 As a rule, you should put the @command{reset_config} command
1241 into the board file. Most things you think you know about a
1242 chip can be tweaked by the board.
1244 Some chips have specific ways the TRST and SRST signals are
1245 managed. In the unusual case that these are @emph{chip specific}
1246 and can never be changed by board wiring, they could go here.
1248 Some chips need special attention during reset handling if
1249 they're going to be used with JTAG.
1250 An example might be needing to send some commands right
1251 after the target's TAP has been reset, providing a
1252 @code{reset-deassert-post} event handler that writes a chip
1253 register to report that JTAG debugging is being done.
1255 @subsection ARM Core Specific Hacks
1257 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1258 special high speed download features - enable it.
1260 If present, the MMU, the MPU and the CACHE should be disabled.
1262 Some ARM cores are equipped with trace support, which permits
1263 examination of the instruction and data bus activity. Trace
1264 activity is controlled through an ``Embedded Trace Module'' (ETM)
1265 on one of the core's scan chains. The ETM emits voluminous data
1266 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1267 If you are using an external trace port,
1268 configure it in your board config file.
1269 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1270 configure it in your target config file.
1273 etm config $_TARGETNAME 16 normal full etb
1274 etb config $_TARGETNAME $_CHIPNAME.etb
1277 @subsection Internal Flash Configuration
1279 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1281 @b{Never ever} in the ``target configuration file'' define any type of
1282 flash that is external to the chip. (For example a BOOT flash on
1283 Chip Select 0.) Such flash information goes in a board file - not
1284 the TARGET (chip) file.
1288 @item at91sam7x256 - has 256K flash YES enable it.
1289 @item str912 - has flash internal YES enable it.
1290 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1291 @item pxa270 - again - CS0 flash - it goes in the board file.
1294 @node Daemon Configuration
1295 @chapter Daemon Configuration
1296 @cindex initialization
1297 The commands here are commonly found in the openocd.cfg file and are
1298 used to specify what TCP/IP ports are used, and how GDB should be
1301 @section Configuration Stage
1302 @cindex configuration stage
1303 @cindex config command
1305 When the OpenOCD server process starts up, it enters a
1306 @emph{configuration stage} which is the only time that
1307 certain commands, @emph{configuration commands}, may be issued.
1308 In this manual, the definition of a configuration command is
1309 presented as a @emph{Config Command}, not as a @emph{Command}
1310 which may be issued interactively.
1312 Those configuration commands include declaration of TAPs,
1314 the interface used for JTAG communication,
1315 and other basic setup.
1316 The server must leave the configuration stage before it
1317 may access or activate TAPs.
1318 After it leaves this stage, configuration commands may no
1321 @deffn {Config Command} init
1322 This command terminates the configuration stage and
1323 enters the normal command mode. This can be useful to add commands to
1324 the startup scripts and commands such as resetting the target,
1325 programming flash, etc. To reset the CPU upon startup, add "init" and
1326 "reset" at the end of the config script or at the end of the OpenOCD
1327 command line using the @option{-c} command line switch.
1329 If this command does not appear in any startup/configuration file
1330 OpenOCD executes the command for you after processing all
1331 configuration files and/or command line options.
1333 @b{NOTE:} This command normally occurs at or near the end of your
1334 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1335 targets ready. For example: If your openocd.cfg file needs to
1336 read/write memory on your target, @command{init} must occur before
1337 the memory read/write commands. This includes @command{nand probe}.
1340 @anchor{TCP/IP Ports}
1341 @section TCP/IP Ports
1346 The OpenOCD server accepts remote commands in several syntaxes.
1347 Each syntax uses a different TCP/IP port, which you may specify
1348 only during configuration (before those ports are opened).
1350 For reasons including security, you may wish to prevent remote
1351 access using one or more of these ports.
1352 In such cases, just specify the relevant port number as zero.
1353 If you disable all access through TCP/IP, you will need to
1354 use the command line @option{-pipe} option.
1356 @deffn {Command} gdb_port (number)
1358 Specify or query the first port used for incoming GDB connections.
1359 The GDB port for the
1360 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1361 When not specified during the configuration stage,
1362 the port @var{number} defaults to 3333.
1363 When specified as zero, this port is not activated.
1366 @deffn {Command} tcl_port (number)
1367 Specify or query the port used for a simplified RPC
1368 connection that can be used by clients to issue TCL commands and get the
1369 output from the Tcl engine.
1370 Intended as a machine interface.
1371 When not specified during the configuration stage,
1372 the port @var{number} defaults to 6666.
1373 When specified as zero, this port is not activated.
1376 @deffn {Command} telnet_port (number)
1377 Specify or query the
1378 port on which to listen for incoming telnet connections.
1379 This port is intended for interaction with one human through TCL commands.
1380 When not specified during the configuration stage,
1381 the port @var{number} defaults to 4444.
1382 When specified as zero, this port is not activated.
1385 @anchor{GDB Configuration}
1386 @section GDB Configuration
1388 @cindex GDB configuration
1389 You can reconfigure some GDB behaviors if needed.
1390 The ones listed here are static and global.
1391 @xref{Target Configuration}, about configuring individual targets.
1392 @xref{Target Events}, about configuring target-specific event handling.
1394 @anchor{gdb_breakpoint_override}
1395 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1396 Force breakpoint type for gdb @command{break} commands.
1397 This option supports GDB GUIs which don't
1398 distinguish hard versus soft breakpoints, if the default OpenOCD and
1399 GDB behaviour is not sufficient. GDB normally uses hardware
1400 breakpoints if the memory map has been set up for flash regions.
1403 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1404 Configures what OpenOCD will do when GDB detaches from the daemon.
1405 Default behaviour is @option{resume}.
1408 @anchor{gdb_flash_program}
1409 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1410 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1411 vFlash packet is received.
1412 The default behaviour is @option{enable}.
1415 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1416 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1417 requested. GDB will then know when to set hardware breakpoints, and program flash
1418 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1419 for flash programming to work.
1420 Default behaviour is @option{enable}.
1421 @xref{gdb_flash_program}.
1424 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1425 Specifies whether data aborts cause an error to be reported
1426 by GDB memory read packets.
1427 The default behaviour is @option{disable};
1428 use @option{enable} see these errors reported.
1431 @anchor{Event Polling}
1432 @section Event Polling
1434 Hardware debuggers are parts of asynchronous systems,
1435 where significant events can happen at any time.
1436 The OpenOCD server needs to detect some of these events,
1437 so it can report them to through TCL command line
1440 Examples of such events include:
1443 @item One of the targets can stop running ... maybe it triggers
1444 a code breakpoint or data watchpoint, or halts itself.
1445 @item Messages may be sent over ``debug message'' channels ... many
1446 targets support such messages sent over JTAG,
1447 for receipt by the person debugging or tools.
1448 @item Loss of power ... some adapters can detect these events.
1449 @item Resets not issued through JTAG ... such reset sources
1450 can include button presses or other system hardware, sometimes
1451 including the target itself (perhaps through a watchdog).
1452 @item Debug instrumentation sometimes supports event triggering
1453 such as ``trace buffer full'' (so it can quickly be emptied)
1454 or other signals (to correlate with code behavior).
1457 None of those events are signaled through standard JTAG signals.
1458 However, most conventions for JTAG connectors include voltage
1459 level and system reset (SRST) signal detection.
1460 Some connectors also include instrumentation signals, which
1461 can imply events when those signals are inputs.
1463 In general, OpenOCD needs to periodically check for those events,
1464 either by looking at the status of signals on the JTAG connector
1465 or by sending synchronous ``tell me your status'' JTAG requests
1466 to the various active targets.
1467 There is a command to manage and monitor that polling,
1468 which is normally done in the background.
1470 @deffn Command poll [@option{on}|@option{off}]
1471 Poll the current target for its current state.
1472 (Also, @pxref{target curstate}.)
1473 If that target is in debug mode, architecture
1474 specific information about the current state is printed.
1475 An optional parameter
1476 allows background polling to be enabled and disabled.
1478 You could use this from the TCL command shell, or
1479 from GDB using @command{monitor poll} command.
1482 background polling: on
1483 target state: halted
1484 target halted in ARM state due to debug-request, \
1485 current mode: Supervisor
1486 cpsr: 0x800000d3 pc: 0x11081bfc
1487 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1492 @node Interface - Dongle Configuration
1493 @chapter Interface - Dongle Configuration
1494 @cindex config file, interface
1495 @cindex interface config file
1497 JTAG Adapters/Interfaces/Dongles are normally configured
1498 through commands in an interface configuration
1499 file which is sourced by your @file{openocd.cfg} file, or
1500 through a command line @option{-f interface/....cfg} option.
1503 source [find interface/olimex-jtag-tiny.cfg]
1507 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1508 A few cases are so simple that you only need to say what driver to use:
1515 Most adapters need a bit more configuration than that.
1518 @section Interface Configuration
1520 The interface command tells OpenOCD what type of JTAG dongle you are
1521 using. Depending on the type of dongle, you may need to have one or
1522 more additional commands.
1524 @deffn {Config Command} {interface} name
1525 Use the interface driver @var{name} to connect to the
1529 @deffn Command {interface_list}
1530 List the interface drivers that have been built into
1531 the running copy of OpenOCD.
1534 @deffn Command {jtag interface}
1535 Returns the name of the interface driver being used.
1538 @section Interface Drivers
1540 Each of the interface drivers listed here must be explicitly
1541 enabled when OpenOCD is configured, in order to be made
1542 available at run time.
1544 @deffn {Interface Driver} {amt_jtagaccel}
1545 Amontec Chameleon in its JTAG Accelerator configuration,
1546 connected to a PC's EPP mode parallel port.
1547 This defines some driver-specific commands:
1549 @deffn {Config Command} {parport_port} number
1550 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1551 the number of the @file{/dev/parport} device.
1554 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1555 Displays status of RTCK option.
1556 Optionally sets that option first.
1560 @deffn {Interface Driver} {arm-jtag-ew}
1561 Olimex ARM-JTAG-EW USB adapter
1562 This has one driver-specific command:
1564 @deffn Command {armjtagew_info}
1569 @deffn {Interface Driver} {at91rm9200}
1570 Supports bitbanged JTAG from the local system,
1571 presuming that system is an Atmel AT91rm9200
1572 and a specific set of GPIOs is used.
1573 @c command: at91rm9200_device NAME
1574 @c chooses among list of bit configs ... only one option
1577 @deffn {Interface Driver} {dummy}
1578 A dummy software-only driver for debugging.
1581 @deffn {Interface Driver} {ep93xx}
1582 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1585 @deffn {Interface Driver} {ft2232}
1586 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1587 These interfaces have several commands, used to configure the driver
1588 before initializing the JTAG scan chain:
1590 @deffn {Config Command} {ft2232_device_desc} description
1591 Provides the USB device description (the @emph{iProduct string})
1592 of the FTDI FT2232 device. If not
1593 specified, the FTDI default value is used. This setting is only valid
1594 if compiled with FTD2XX support.
1597 @deffn {Config Command} {ft2232_serial} serial-number
1598 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1599 in case the vendor provides unique IDs and more than one FT2232 device
1600 is connected to the host.
1601 If not specified, serial numbers are not considered.
1602 (Note that USB serial numbers can be arbitrary Unicode strings,
1603 and are not restricted to containing only decimal digits.)
1606 @deffn {Config Command} {ft2232_layout} name
1607 Each vendor's FT2232 device can use different GPIO signals
1608 to control output-enables, reset signals, and LEDs.
1609 Currently valid layout @var{name} values include:
1611 @item @b{axm0432_jtag} Axiom AXM-0432
1612 @item @b{comstick} Hitex STR9 comstick
1613 @item @b{cortino} Hitex Cortino JTAG interface
1614 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1615 either for the local Cortex-M3 (SRST only)
1616 or in a passthrough mode (neither SRST nor TRST)
1617 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1618 @item @b{flyswatter} Tin Can Tools Flyswatter
1619 @item @b{icebear} ICEbear JTAG adapter from Section 5
1620 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1621 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1622 @item @b{m5960} American Microsystems M5960
1623 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1624 @item @b{oocdlink} OOCDLink
1625 @c oocdlink ~= jtagkey_prototype_v1
1626 @item @b{sheevaplug} Marvell Sheevaplug development kit
1627 @item @b{signalyzer} Xverve Signalyzer
1628 @item @b{stm32stick} Hitex STM32 Performance Stick
1629 @item @b{turtelizer2} egnite Software turtelizer2
1630 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1634 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1635 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1636 default values are used.
1637 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1639 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1643 @deffn {Config Command} {ft2232_latency} ms
1644 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1645 ft2232_read() fails to return the expected number of bytes. This can be caused by
1646 USB communication delays and has proved hard to reproduce and debug. Setting the
1647 FT2232 latency timer to a larger value increases delays for short USB packets but it
1648 also reduces the risk of timeouts before receiving the expected number of bytes.
1649 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1652 For example, the interface config file for a
1653 Turtelizer JTAG Adapter looks something like this:
1657 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1658 ft2232_layout turtelizer2
1659 ft2232_vid_pid 0x0403 0xbdc8
1663 @deffn {Interface Driver} {gw16012}
1664 Gateworks GW16012 JTAG programmer.
1665 This has one driver-specific command:
1667 @deffn {Config Command} {parport_port} number
1668 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1669 the number of the @file{/dev/parport} device.
1673 @deffn {Interface Driver} {jlink}
1674 Segger jlink USB adapter
1675 @c command: jlink_info
1677 @c command: jlink_hw_jtag (2|3)
1678 @c sets version 2 or 3
1681 @deffn {Interface Driver} {parport}
1682 Supports PC parallel port bit-banging cables:
1683 Wigglers, PLD download cable, and more.
1684 These interfaces have several commands, used to configure the driver
1685 before initializing the JTAG scan chain:
1687 @deffn {Config Command} {parport_cable} name
1688 The layout of the parallel port cable used to connect to the target.
1689 Currently valid cable @var{name} values include:
1692 @item @b{altium} Altium Universal JTAG cable.
1693 @item @b{arm-jtag} Same as original wiggler except SRST and
1694 TRST connections reversed and TRST is also inverted.
1695 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1696 in configuration mode. This is only used to
1697 program the Chameleon itself, not a connected target.
1698 @item @b{dlc5} The Xilinx Parallel cable III.
1699 @item @b{flashlink} The ST Parallel cable.
1700 @item @b{lattice} Lattice ispDOWNLOAD Cable
1701 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1703 Amontec's Chameleon Programmer. The new version available from
1704 the website uses the original Wiggler layout ('@var{wiggler}')
1705 @item @b{triton} The parallel port adapter found on the
1706 ``Karo Triton 1 Development Board''.
1707 This is also the layout used by the HollyGates design
1708 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1709 @item @b{wiggler} The original Wiggler layout, also supported by
1710 several clones, such as the Olimex ARM-JTAG
1711 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1712 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1716 @deffn {Config Command} {parport_port} number
1717 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1718 the @file{/dev/parport} device
1720 When using PPDEV to access the parallel port, use the number of the parallel port:
1721 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1722 you may encounter a problem.
1725 @deffn {Config Command} {parport_write_on_exit} (on|off)
1726 This will configure the parallel driver to write a known
1727 cable-specific value to the parallel interface on exiting OpenOCD
1730 For example, the interface configuration file for a
1731 classic ``Wiggler'' cable might look something like this:
1736 parport_cable wiggler
1740 @deffn {Interface Driver} {presto}
1741 ASIX PRESTO USB JTAG programmer.
1742 @c command: presto_serial str
1743 @c sets serial number
1746 @deffn {Interface Driver} {rlink}
1747 Raisonance RLink USB adapter
1750 @deffn {Interface Driver} {usbprog}
1751 usbprog is a freely programmable USB adapter.
1754 @deffn {Interface Driver} {vsllink}
1755 vsllink is part of Versaloon which is a versatile USB programmer.
1758 This defines quite a few driver-specific commands,
1759 which are not currently documented here.
1763 @deffn {Interface Driver} {ZY1000}
1764 This is the Zylin ZY1000 JTAG debugger.
1767 This defines some driver-specific commands,
1768 which are not currently documented here.
1771 @deffn Command power [@option{on}|@option{off}]
1772 Turn power switch to target on/off.
1773 No arguments: print status.
1780 JTAG clock setup is part of system setup.
1781 It @emph{does not belong with interface setup} since any interface
1782 only knows a few of the constraints for the JTAG clock speed.
1783 Sometimes the JTAG speed is
1784 changed during the target initialization process: (1) slow at
1785 reset, (2) program the CPU clocks, (3) run fast.
1786 Both the "slow" and "fast" clock rates are functions of the
1787 oscillators used, the chip, the board design, and sometimes
1788 power management software that may be active.
1790 The speed used during reset can be adjusted using pre_reset
1791 and post_reset event handlers.
1792 @xref{Target Events}.
1794 If your system supports adaptive clocking (RTCK), configuring
1795 JTAG to use that is probably the most robust approach.
1796 However, it introduces delays to synchronize clocks; so it
1797 may not be the fastest solution.
1799 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1800 instead of @command{jtag_khz}.
1802 @deffn {Command} jtag_khz max_speed_kHz
1803 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1804 JTAG interfaces usually support a limited number of
1805 speeds. The speed actually used won't be faster
1806 than the speed specified.
1808 Chip data sheets generally include a top JTAG clock rate.
1809 The actual rate is often a function of a CPU core clock,
1810 and is normally less than that peak rate.
1811 For example, most ARM cores accept at most one sixth of the CPU clock.
1813 Speed 0 (khz) selects RTCK method.
1815 If your system uses RTCK, you won't need to change the
1816 JTAG clocking after setup.
1817 Not all interfaces, boards, or targets support ``rtck''.
1818 If the interface device can not
1819 support it, an error is returned when you try to use RTCK.
1822 @defun jtag_rclk fallback_speed_kHz
1823 @cindex adaptive clocking
1825 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1826 If that fails (maybe the interface, board, or target doesn't
1827 support it), falls back to the specified frequency.
1829 # Fall back to 3mhz if RTCK is not supported
1834 @node Reset Configuration
1835 @chapter Reset Configuration
1836 @cindex Reset Configuration
1838 Every system configuration may require a different reset
1839 configuration. This can also be quite confusing.
1840 Resets also interact with @var{reset-init} event handlers,
1841 which do things like setting up clocks and DRAM, and
1842 JTAG clock rates. (@xref{JTAG Speed}.)
1843 They can also interact with JTAG routers.
1844 Please see the various board files for examples.
1847 To maintainers and integrators:
1848 Reset configuration touches several things at once.
1849 Normally the board configuration file
1850 should define it and assume that the JTAG adapter supports
1851 everything that's wired up to the board's JTAG connector.
1853 However, the target configuration file could also make note
1854 of something the silicon vendor has done inside the chip,
1855 which will be true for most (or all) boards using that chip.
1856 And when the JTAG adapter doesn't support everything, the
1857 user configuration file will need to override parts of
1858 the reset configuration provided by other files.
1861 @section Types of Reset
1863 There are many kinds of reset possible through JTAG, but
1864 they may not all work with a given board and adapter.
1865 That's part of why reset configuration can be error prone.
1869 @emph{System Reset} ... the @emph{SRST} hardware signal
1870 resets all chips connected to the JTAG adapter, such as processors,
1871 power management chips, and I/O controllers. Normally resets triggered
1872 with this signal behave exactly like pressing a RESET button.
1874 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1875 just the TAP controllers connected to the JTAG adapter.
1876 Such resets should not be visible to the rest of the system; resetting a
1877 device's the TAP controller just puts that controller into a known state.
1879 @emph{Emulation Reset} ... many devices can be reset through JTAG
1880 commands. These resets are often distinguishable from system
1881 resets, either explicitly (a "reset reason" register says so)
1882 or implicitly (not all parts of the chip get reset).
1884 @emph{Other Resets} ... system-on-chip devices often support
1885 several other types of reset.
1886 You may need to arrange that a watchdog timer stops
1887 while debugging, preventing a watchdog reset.
1888 There may be individual module resets.
1891 In the best case, OpenOCD can hold SRST, then reset
1892 the TAPs via TRST and send commands through JTAG to halt the
1893 CPU at the reset vector before the 1st instruction is executed.
1894 Then when it finally releases the SRST signal, the system is
1895 halted under debugger control before any code has executed.
1896 This is the behavior required to support the @command{reset halt}
1897 and @command{reset init} commands; after @command{reset init} a
1898 board-specific script might do things like setting up DRAM.
1899 (@xref{Reset Command}.)
1901 @anchor{SRST and TRST Issues}
1902 @section SRST and TRST Issues
1904 Because SRST and TRST are hardware signals, they can have a
1905 variety of system-specific constraints. Some of the most
1910 @item @emph{Signal not available} ... Some boards don't wire
1911 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1912 support such signals even if they are wired up.
1913 Use the @command{reset_config} @var{signals} options to say
1914 when either of those signals is not connected.
1915 When SRST is not available, your code might not be able to rely
1916 on controllers having been fully reset during code startup.
1917 Missing TRST is not a problem, since JTAG level resets can
1918 be triggered using with TMS signaling.
1920 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1921 adapter will connect SRST to TRST, instead of keeping them separate.
1922 Use the @command{reset_config} @var{combination} options to say
1923 when those signals aren't properly independent.
1925 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1926 delay circuit, reset supervisor, or on-chip features can extend
1927 the effect of a JTAG adapter's reset for some time after the adapter
1928 stops issuing the reset. For example, there may be chip or board
1929 requirements that all reset pulses last for at least a
1930 certain amount of time; and reset buttons commonly have
1931 hardware debouncing.
1932 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1933 commands to say when extra delays are needed.
1935 @item @emph{Drive type} ... Reset lines often have a pullup
1936 resistor, letting the JTAG interface treat them as open-drain
1937 signals. But that's not a requirement, so the adapter may need
1938 to use push/pull output drivers.
1939 Also, with weak pullups it may be advisable to drive
1940 signals to both levels (push/pull) to minimize rise times.
1941 Use the @command{reset_config} @var{trst_type} and
1942 @var{srst_type} parameters to say how to drive reset signals.
1944 @item @emph{Special initialization} ... Targets sometimes need
1945 special JTAG initialization sequences to handle chip-specific
1946 issues (not limited to errata).
1947 For example, certain JTAG commands might need to be issued while
1948 the system as a whole is in a reset state (SRST active)
1949 but the JTAG scan chain is usable (TRST inactive).
1950 (@xref{JTAG Commands}, where the @command{jtag_reset}
1951 command is presented.)
1954 There can also be other issues.
1955 Some devices don't fully conform to the JTAG specifications.
1956 Trivial system-specific differences are common, such as
1957 SRST and TRST using slightly different names.
1958 There are also vendors who distribute key JTAG documentation for
1959 their chips only to developers who have signed a Non-Disclosure
1962 Sometimes there are chip-specific extensions like a requirement to use
1963 the normally-optional TRST signal (precluding use of JTAG adapters which
1964 don't pass TRST through), or needing extra steps to complete a TAP reset.
1966 In short, SRST and especially TRST handling may be very finicky,
1967 needing to cope with both architecture and board specific constraints.
1969 @section Commands for Handling Resets
1971 @deffn {Command} jtag_nsrst_delay milliseconds
1972 How long (in milliseconds) OpenOCD should wait after deasserting
1973 nSRST (active-low system reset) before starting new JTAG operations.
1974 When a board has a reset button connected to SRST line it will
1975 probably have hardware debouncing, implying you should use this.
1978 @deffn {Command} jtag_ntrst_delay milliseconds
1979 How long (in milliseconds) OpenOCD should wait after deasserting
1980 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1983 @deffn {Command} reset_config mode_flag ...
1984 This command tells OpenOCD the reset configuration
1985 of your combination of JTAG board and target in target
1986 configuration scripts.
1988 Information earlier in this section describes the kind of problems
1989 the command is intended to address (@pxref{SRST and TRST Issues}).
1990 As a rule this command belongs only in board config files,
1991 describing issues like @emph{board doesn't connect TRST};
1992 or in user config files, addressing limitations derived
1993 from a particular combination of interface and board.
1994 (An unlikely example would be using a TRST-only adapter
1995 with a board that only wires up SRST.)
1997 The @var{mode_flag} options can be specified in any order, but only one
1998 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1999 and @var{srst_type} -- may be specified at a time.
2000 If you don't provide a new value for a given type, its previous
2001 value (perhaps the default) is unchanged.
2002 For example, this means that you don't need to say anything at all about
2003 TRST just to declare that if the JTAG adapter should want to drive SRST,
2004 it must explicitly be driven high (@option{srst_push_pull}).
2006 @var{signals} can specify which of the reset signals are connected.
2007 For example, If the JTAG interface provides SRST, but the board doesn't
2008 connect that signal properly, then OpenOCD can't use it.
2009 Possible values are @option{none} (the default), @option{trst_only},
2010 @option{srst_only} and @option{trst_and_srst}.
2013 If your board provides SRST or TRST through the JTAG connector,
2014 you must declare that or else those signals will not be used.
2017 The @var{combination} is an optional value specifying broken reset
2018 signal implementations.
2019 The default behaviour if no option given is @option{separate},
2020 indicating everything behaves normally.
2021 @option{srst_pulls_trst} states that the
2022 test logic is reset together with the reset of the system (e.g. Philips
2023 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2024 the system is reset together with the test logic (only hypothetical, I
2025 haven't seen hardware with such a bug, and can be worked around).
2026 @option{combined} implies both @option{srst_pulls_trst} and
2027 @option{trst_pulls_srst}.
2029 @option{srst_gates_jtag} indicates that asserting SRST gates the
2030 JTAG clock. This means that no communication can happen on JTAG
2031 while SRST is asserted.
2033 The optional @var{trst_type} and @var{srst_type} parameters allow the
2034 driver mode of each reset line to be specified. These values only affect
2035 JTAG interfaces with support for different driver modes, like the Amontec
2036 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2037 relevant signal (TRST or SRST) is not connected.
2039 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2040 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2041 Most boards connect this signal to a pulldown, so the JTAG TAPs
2042 never leave reset unless they are hooked up to a JTAG adapter.
2044 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2045 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2046 Most boards connect this signal to a pullup, and allow the
2047 signal to be pulled low by various events including system
2048 powerup and pressing a reset button.
2052 @node TAP Declaration
2053 @chapter TAP Declaration
2054 @cindex TAP declaration
2055 @cindex TAP configuration
2057 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2058 TAPs serve many roles, including:
2061 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2062 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2063 Others do it indirectly, making a CPU do it.
2064 @item @b{Program Download} Using the same CPU support GDB uses,
2065 you can initialize a DRAM controller, download code to DRAM, and then
2066 start running that code.
2067 @item @b{Boundary Scan} Most chips support boundary scan, which
2068 helps test for board assembly problems like solder bridges
2069 and missing connections
2072 OpenOCD must know about the active TAPs on your board(s).
2073 Setting up the TAPs is the core task of your configuration files.
2074 Once those TAPs are set up, you can pass their names to code
2075 which sets up CPUs and exports them as GDB targets,
2076 probes flash memory, performs low-level JTAG operations, and more.
2078 @section Scan Chains
2081 TAPs are part of a hardware @dfn{scan chain},
2082 which is daisy chain of TAPs.
2083 They also need to be added to
2084 OpenOCD's software mirror of that hardware list,
2085 giving each member a name and associating other data with it.
2086 Simple scan chains, with a single TAP, are common in
2087 systems with a single microcontroller or microprocessor.
2088 More complex chips may have several TAPs internally.
2089 Very complex scan chains might have a dozen or more TAPs:
2090 several in one chip, more in the next, and connecting
2091 to other boards with their own chips and TAPs.
2093 You can display the list with the @command{scan_chain} command.
2094 (Don't confuse this with the list displayed by the @command{targets}
2095 command, presented in the next chapter.
2096 That only displays TAPs for CPUs which are configured as
2098 Here's what the scan chain might look like for a chip more than one TAP:
2101 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2102 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2103 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2104 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2105 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2108 Unfortunately those TAPs can't always be autoconfigured,
2109 because not all devices provide good support for that.
2110 JTAG doesn't require supporting IDCODE instructions, and
2111 chips with JTAG routers may not link TAPs into the chain
2112 until they are told to do so.
2114 The configuration mechanism currently supported by OpenOCD
2115 requires explicit configuration of all TAP devices using
2116 @command{jtag newtap} commands, as detailed later in this chapter.
2117 A command like this would declare one tap and name it @code{chip1.cpu}:
2120 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2123 Each target configuration file lists the TAPs provided
2125 Board configuration files combine all the targets on a board,
2127 Note that @emph{the order in which TAPs are declared is very important.}
2128 It must match the order in the JTAG scan chain, both inside
2129 a single chip and between them.
2130 @xref{FAQ TAP Order}.
2132 For example, the ST Microsystems STR912 chip has
2133 three separate TAPs@footnote{See the ST
2134 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2135 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2136 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2137 To configure those taps, @file{target/str912.cfg}
2138 includes commands something like this:
2141 jtag newtap str912 flash ... params ...
2142 jtag newtap str912 cpu ... params ...
2143 jtag newtap str912 bs ... params ...
2146 Actual config files use a variable instead of literals like
2147 @option{str912}, to support more than one chip of each type.
2148 @xref{Config File Guidelines}.
2150 @deffn Command {jtag names}
2151 Returns the names of all current TAPs in the scan chain.
2152 Use @command{jtag cget} or @command{jtag tapisenabled}
2153 to examine attributes and state of each TAP.
2155 foreach t [jtag names] @{
2156 puts [format "TAP: %s\n" $t]
2161 @deffn Command {scan_chain}
2162 Displays the TAPs in the scan chain configuration,
2164 The set of TAPs listed by this command is fixed by
2165 exiting the OpenOCD configuration stage,
2166 but systems with a JTAG router can
2167 enable or disable TAPs dynamically.
2168 In addition to the enable/disable status, the contents of
2169 each TAP's instruction register can also change.
2172 @c FIXME! "jtag cget" should be able to return all TAP
2173 @c attributes, like "$target_name cget" does for targets.
2175 @c Probably want "jtag eventlist", and a "tap-reset" event
2176 @c (on entry to RESET state).
2181 When TAP objects are declared with @command{jtag newtap},
2182 a @dfn{dotted.name} is created for the TAP, combining the
2183 name of a module (usually a chip) and a label for the TAP.
2184 For example: @code{xilinx.tap}, @code{str912.flash},
2185 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2186 Many other commands use that dotted.name to manipulate or
2187 refer to the TAP. For example, CPU configuration uses the
2188 name, as does declaration of NAND or NOR flash banks.
2190 The components of a dotted name should follow ``C'' symbol
2191 name rules: start with an alphabetic character, then numbers
2192 and underscores are OK; while others (including dots!) are not.
2195 In older code, JTAG TAPs were numbered from 0..N.
2196 This feature is still present.
2197 However its use is highly discouraged, and
2198 should not be relied on; it will be removed by mid-2010.
2199 Update all of your scripts to use TAP names rather than numbers,
2200 by paying attention to the runtime warnings they trigger.
2201 Using TAP numbers in target configuration scripts prevents
2202 reusing those scripts on boards with multiple targets.
2205 @section TAP Declaration Commands
2207 @c shouldn't this be(come) a {Config Command}?
2208 @anchor{jtag newtap}
2209 @deffn Command {jtag newtap} chipname tapname configparams...
2210 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2211 and configured according to the various @var{configparams}.
2213 The @var{chipname} is a symbolic name for the chip.
2214 Conventionally target config files use @code{$_CHIPNAME},
2215 defaulting to the model name given by the chip vendor but
2218 @cindex TAP naming convention
2219 The @var{tapname} reflects the role of that TAP,
2220 and should follow this convention:
2223 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2224 @item @code{cpu} -- The main CPU of the chip, alternatively
2225 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2226 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2227 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2228 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2229 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2230 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2231 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2233 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2234 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2235 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2236 a JTAG TAP; that TAP should be named @code{sdma}.
2239 Every TAP requires at least the following @var{configparams}:
2242 @item @code{-ircapture} @var{NUMBER}
2243 @*The bit pattern loaded by the TAP into the JTAG shift register
2244 on entry to the @sc{ircapture} state, such as 0x01.
2245 JTAG requires the two LSBs of this value to be 01.
2246 The value is used to verify that instruction scans work correctly.
2247 @item @code{-irlen} @var{NUMBER}
2248 @*The length in bits of the
2249 instruction register, such as 4 or 5 bits.
2250 @item @code{-irmask} @var{NUMBER}
2251 @*A mask for the IR register.
2252 For some devices, there are bits in the IR that aren't used.
2253 This lets OpenOCD mask them off when doing IDCODE comparisons.
2254 In general, this should just be all ones for the size of the IR.
2257 A TAP may also provide optional @var{configparams}:
2260 @item @code{-disable} (or @code{-enable})
2261 @*Use the @code{-disable} parameter to flag a TAP which is not
2262 linked in to the scan chain after a reset using either TRST
2263 or the JTAG state machine's @sc{reset} state.
2264 You may use @code{-enable} to highlight the default state
2265 (the TAP is linked in).
2266 @xref{Enabling and Disabling TAPs}.
2267 @item @code{-expected-id} @var{number}
2268 @*A non-zero value represents the expected 32-bit IDCODE
2269 found when the JTAG chain is examined.
2270 These codes are not required by all JTAG devices.
2271 @emph{Repeat the option} as many times as required if more than one
2272 ID code could appear (for example, multiple versions).
2276 @c @deffn Command {jtag arp_init-reset}
2277 @c ... more or less "init" ?
2279 @anchor{Enabling and Disabling TAPs}
2280 @section Enabling and Disabling TAPs
2282 @cindex JTAG Route Controller
2285 In some systems, a @dfn{JTAG Route Controller} (JRC)
2286 is used to enable and/or disable specific JTAG TAPs.
2287 Many ARM based chips from Texas Instruments include
2288 an ``ICEpick'' module, which is a JRC.
2289 Such chips include DaVinci and OMAP3 processors.
2291 A given TAP may not be visible until the JRC has been
2292 told to link it into the scan chain; and if the JRC
2293 has been told to unlink that TAP, it will no longer
2295 Such routers address problems that JTAG ``bypass mode''
2299 @item The scan chain can only go as fast as its slowest TAP.
2300 @item Having many TAPs slows instruction scans, since all
2301 TAPs receive new instructions.
2302 @item TAPs in the scan chain must be powered up, which wastes
2303 power and prevents debugging some power management mechanisms.
2306 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2307 as implied by the existence of JTAG routers.
2308 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2309 does include a kind of JTAG router functionality.
2311 @c (a) currently the event handlers don't seem to be able to
2312 @c fail in a way that could lead to no-change-of-state.
2313 @c (b) eventually non-event configuration should be possible,
2314 @c in which case some this documentation must move.
2316 @deffn Command {jtag cget} dotted.name @option{-event} name
2317 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2318 At this writing this mechanism is used only for event handling.
2319 Three events are available. Two events relate to TAP enabling
2320 and disabling, one to post reset handling.
2322 The @code{configure} subcommand assigns an event handler,
2323 a TCL string which is evaluated when the event is triggered.
2324 The @code{cget} subcommand returns that handler.
2325 The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
2327 So for example, when defining a TAP for a CPU connected to
2328 a JTAG router, you should define TAP event handlers using
2329 code that looks something like this:
2332 jtag configure CHIP.cpu -event tap-enable @{
2333 echo "Enabling CPU TAP"
2334 ... jtag operations using CHIP.jrc
2336 jtag configure CHIP.cpu -event tap-disable @{
2337 echo "Disabling CPU TAP"
2338 ... jtag operations using CHIP.jrc
2342 If you need some post reset action, you can do:
2345 jtag configure CHIP.cpu -event post-reset @{
2347 ... jtag operations to be done after reset
2352 @deffn Command {jtag tapdisable} dotted.name
2353 @deffnx Command {jtag tapenable} dotted.name
2354 @deffnx Command {jtag tapisenabled} dotted.name
2355 These three commands all return the string "1" if the tap
2356 specified by @var{dotted.name} is enabled,
2357 and "0" if it is disbabled.
2358 The @command{tapenable} variant first enables the tap
2359 by sending it a @option{tap-enable} event.
2360 The @command{tapdisable} variant first disables the tap
2361 by sending it a @option{tap-disable} event.
2364 Humans will find the @command{scan_chain} command more helpful
2365 than the script-oriented @command{tapisenabled}
2366 for querying the state of the JTAG taps.
2370 @node CPU Configuration
2371 @chapter CPU Configuration
2374 This chapter discusses how to set up GDB debug targets for CPUs.
2375 You can also access these targets without GDB
2376 (@pxref{Architecture and Core Commands},
2377 and @ref{Target State handling}) and
2378 through various kinds of NAND and NOR flash commands.
2379 If you have multiple CPUs you can have multiple such targets.
2381 We'll start by looking at how to examine the targets you have,
2382 then look at how to add one more target and how to configure it.
2384 @section Target List
2385 @cindex target, current
2386 @cindex target, list
2388 All targets that have been set up are part of a list,
2389 where each member has a name.
2390 That name should normally be the same as the TAP name.
2391 You can display the list with the @command{targets}
2393 This display often has only one CPU; here's what it might
2394 look like with more than one:
2396 TargetName Type Endian TapName State
2397 -- ------------------ ---------- ------ ------------------ ------------
2398 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2399 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2402 One member of that list is the @dfn{current target}, which
2403 is implicitly referenced by many commands.
2404 It's the one marked with a @code{*} near the target name.
2405 In particular, memory addresses often refer to the address
2406 space seen by that current target.
2407 Commands like @command{mdw} (memory display words)
2408 and @command{flash erase_address} (erase NOR flash blocks)
2409 are examples; and there are many more.
2411 Several commands let you examine the list of targets:
2413 @deffn Command {target count}
2414 @emph{Note: target numbers are deprecated; don't use them.
2415 They will be removed shortly after August 2010, including this command.
2416 Iterate target using @command{target names}, not by counting.}
2418 Returns the number of targets, @math{N}.
2419 The highest numbered target is @math{N - 1}.
2421 set c [target count]
2422 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2423 # Assuming you have created this function
2424 print_target_details $x
2429 @deffn Command {target current}
2430 Returns the name of the current target.
2433 @deffn Command {target names}
2434 Lists the names of all current targets in the list.
2436 foreach t [target names] @{
2437 puts [format "Target: %s\n" $t]
2442 @deffn Command {target number} number
2443 @emph{Note: target numbers are deprecated; don't use them.
2444 They will be removed shortly after August 2010, including this command.}
2446 The list of targets is numbered starting at zero.
2447 This command returns the name of the target at index @var{number}.
2449 set thename [target number $x]
2450 puts [format "Target %d is: %s\n" $x $thename]
2454 @c yep, "target list" would have been better.
2455 @c plus maybe "target setdefault".
2457 @deffn Command targets [name]
2458 @emph{Note: the name of this command is plural. Other target
2459 command names are singular.}
2461 With no parameter, this command displays a table of all known
2462 targets in a user friendly form.
2464 With a parameter, this command sets the current target to
2465 the given target with the given @var{name}; this is
2466 only relevant on boards which have more than one target.
2469 @section Target CPU Types and Variants
2474 Each target has a @dfn{CPU type}, as shown in the output of
2475 the @command{targets} command. You need to specify that type
2476 when calling @command{target create}.
2477 The CPU type indicates more than just the instruction set.
2478 It also indicates how that instruction set is implemented,
2479 what kind of debug support it integrates,
2480 whether it has an MMU (and if so, what kind),
2481 what core-specific commands may be available
2482 (@pxref{Architecture and Core Commands}),
2485 For some CPU types, OpenOCD also defines @dfn{variants} which
2486 indicate differences that affect their handling.
2487 For example, a particular implementation bug might need to be
2488 worked around in some chip versions.
2490 It's easy to see what target types are supported,
2491 since there's a command to list them.
2492 However, there is currently no way to list what target variants
2493 are supported (other than by reading the OpenOCD source code).
2495 @anchor{target types}
2496 @deffn Command {target types}
2497 Lists all supported target types.
2498 At this writing, the supported CPU types and variants are:
2501 @item @code{arm11} -- this is a generation of ARMv6 cores
2502 @item @code{arm720t} -- this is an ARMv4 core
2503 @item @code{arm7tdmi} -- this is an ARMv4 core
2504 @item @code{arm920t} -- this is an ARMv5 core
2505 @item @code{arm926ejs} -- this is an ARMv5 core
2506 @item @code{arm966e} -- this is an ARMv5 core
2507 @item @code{arm9tdmi} -- this is an ARMv4 core
2508 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2509 (Support for this is preliminary and incomplete.)
2510 @item @code{cortex_a8} -- this is an ARMv7 core
2511 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2512 compact Thumb2 instruction set. It supports one variant:
2514 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2515 This will cause OpenOCD to use a software reset rather than asserting
2516 SRST, to avoid a issue with clearing the debug registers.
2517 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2518 be detected and the normal reset behaviour used.
2520 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2521 @item @code{feroceon} -- resembles arm926
2522 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2524 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2525 provide a functional SRST line on the EJTAG connector. This causes
2526 OpenOCD to instead use an EJTAG software reset command to reset the
2528 You still need to enable @option{srst} on the @command{reset_config}
2529 command to enable OpenOCD hardware reset functionality.
2531 @item @code{xscale} -- this is actually an architecture,
2532 not a CPU type. It is based on the ARMv5 architecture.
2533 There are several variants defined:
2535 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2536 @code{pxa27x} ... instruction register length is 7 bits
2537 @item @code{pxa250}, @code{pxa255},
2538 @code{pxa26x} ... instruction register length is 5 bits
2543 To avoid being confused by the variety of ARM based cores, remember
2544 this key point: @emph{ARM is a technology licencing company}.
2545 (See: @url{http://www.arm.com}.)
2546 The CPU name used by OpenOCD will reflect the CPU design that was
2547 licenced, not a vendor brand which incorporates that design.
2548 Name prefixes like arm7, arm9, arm11, and cortex
2549 reflect design generations;
2550 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2551 reflect an architecture version implemented by a CPU design.
2553 @anchor{Target Configuration}
2554 @section Target Configuration
2556 Before creating a ``target'', you must have added its TAP to the scan chain.
2557 When you've added that TAP, you will have a @code{dotted.name}
2558 which is used to set up the CPU support.
2559 The chip-specific configuration file will normally configure its CPU(s)
2560 right after it adds all of the chip's TAPs to the scan chain.
2562 Although you can set up a target in one step, it's often clearer if you
2563 use shorter commands and do it in two steps: create it, then configure
2565 All operations on the target after it's created will use a new
2566 command, created as part of target creation.
2568 The two main things to configure after target creation are
2569 a work area, which usually has target-specific defaults even
2570 if the board setup code overrides them later;
2571 and event handlers (@pxref{Target Events}), which tend
2572 to be much more board-specific.
2573 The key steps you use might look something like this
2576 target create MyTarget cortex_m3 -chain-position mychip.cpu
2577 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2578 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2579 $MyTarget configure -event reset-init @{ myboard_reinit @}
2582 You should specify a working area if you can; typically it uses some
2584 Such a working area can speed up many things, including bulk
2585 writes to target memory;
2586 flash operations like checking to see if memory needs to be erased;
2587 GDB memory checksumming;
2591 On more complex chips, the work area can become
2592 inaccessible when application code
2593 (such as an operating system)
2594 enables or disables the MMU.
2595 For example, the particular MMU context used to acess the virtual
2596 address will probably matter ... and that context might not have
2597 easy access to other addresses needed.
2598 At this writing, OpenOCD doesn't have much MMU intelligence.
2601 It's often very useful to define a @code{reset-init} event handler.
2602 For systems that are normally used with a boot loader,
2603 common tasks include updating clocks and initializing memory
2605 That may be needed to let you write the boot loader into flash,
2606 in order to ``de-brick'' your board; or to load programs into
2607 external DDR memory without having run the boot loader.
2609 @deffn Command {target create} target_name type configparams...
2610 This command creates a GDB debug target that refers to a specific JTAG tap.
2611 It enters that target into a list, and creates a new
2612 command (@command{@var{target_name}}) which is used for various
2613 purposes including additional configuration.
2616 @item @var{target_name} ... is the name of the debug target.
2617 By convention this should be the same as the @emph{dotted.name}
2618 of the TAP associated with this target, which must be specified here
2619 using the @code{-chain-position @var{dotted.name}} configparam.
2621 This name is also used to create the target object command,
2622 referred to here as @command{$target_name},
2623 and in other places the target needs to be identified.
2624 @item @var{type} ... specifies the target type. @xref{target types}.
2625 @item @var{configparams} ... all parameters accepted by
2626 @command{$target_name configure} are permitted.
2627 If the target is big-endian, set it here with @code{-endian big}.
2628 If the variant matters, set it here with @code{-variant}.
2630 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2634 @deffn Command {$target_name configure} configparams...
2635 The options accepted by this command may also be
2636 specified as parameters to @command{target create}.
2637 Their values can later be queried one at a time by
2638 using the @command{$target_name cget} command.
2640 @emph{Warning:} changing some of these after setup is dangerous.
2641 For example, moving a target from one TAP to another;
2642 and changing its endianness or variant.
2646 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2647 used to access this target.
2649 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2650 whether the CPU uses big or little endian conventions
2652 @item @code{-event} @var{event_name} @var{event_body} --
2653 @xref{Target Events}.
2654 Note that this updates a list of named event handlers.
2655 Calling this twice with two different event names assigns
2656 two different handlers, but calling it twice with the
2657 same event name assigns only one handler.
2659 @item @code{-variant} @var{name} -- specifies a variant of the target,
2660 which OpenOCD needs to know about.
2662 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2663 whether the work area gets backed up; by default,
2664 @emph{it is not backed up.}
2665 When possible, use a working_area that doesn't need to be backed up,
2666 since performing a backup slows down operations.
2667 For example, the beginning of an SRAM block is likely to
2668 be used by most build systems, but the end is often unused.
2670 @item @code{-work-area-size} @var{size} -- specify/set the work area
2672 @item @code{-work-area-phys} @var{address} -- set the work area
2673 base @var{address} to be used when no MMU is active.
2675 @item @code{-work-area-virt} @var{address} -- set the work area
2676 base @var{address} to be used when an MMU is active.
2681 @section Other $target_name Commands
2682 @cindex object command
2684 The Tcl/Tk language has the concept of object commands,
2685 and OpenOCD adopts that same model for targets.
2687 A good Tk example is a on screen button.
2688 Once a button is created a button
2689 has a name (a path in Tk terms) and that name is useable as a first
2690 class command. For example in Tk, one can create a button and later
2691 configure it like this:
2695 button .foobar -background red -command @{ foo @}
2697 .foobar configure -foreground blue
2699 set x [.foobar cget -background]
2701 puts [format "The button is %s" $x]
2704 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2705 button, and its object commands are invoked the same way.
2708 str912.cpu mww 0x1234 0x42
2709 omap3530.cpu mww 0x5555 123
2712 The commands supported by OpenOCD target objects are:
2714 @deffn Command {$target_name arp_examine}
2715 @deffnx Command {$target_name arp_halt}
2716 @deffnx Command {$target_name arp_poll}
2717 @deffnx Command {$target_name arp_reset}
2718 @deffnx Command {$target_name arp_waitstate}
2719 Internal OpenOCD scripts (most notably @file{startup.tcl})
2720 use these to deal with specific reset cases.
2721 They are not otherwise documented here.
2724 @deffn Command {$target_name array2mem} arrayname width address count
2725 @deffnx Command {$target_name mem2array} arrayname width address count
2726 These provide an efficient script-oriented interface to memory.
2727 The @code{array2mem} primitive writes bytes, halfwords, or words;
2728 while @code{mem2array} reads them.
2729 In both cases, the TCL side uses an array, and
2730 the target side uses raw memory.
2732 The efficiency comes from enabling the use of
2733 bulk JTAG data transfer operations.
2734 The script orientation comes from working with data
2735 values that are packaged for use by TCL scripts;
2736 @command{mdw} type primitives only print data they retrieve,
2737 and neither store nor return those values.
2740 @item @var{arrayname} ... is the name of an array variable
2741 @item @var{width} ... is 8/16/32 - indicating the memory access size
2742 @item @var{address} ... is the target memory address
2743 @item @var{count} ... is the number of elements to process
2747 @deffn Command {$target_name cget} queryparm
2748 Each configuration parameter accepted by
2749 @command{$target_name configure}
2750 can be individually queried, to return its current value.
2751 The @var{queryparm} is a parameter name
2752 accepted by that command, such as @code{-work-area-phys}.
2753 There are a few special cases:
2756 @item @code{-event} @var{event_name} -- returns the handler for the
2757 event named @var{event_name}.
2758 This is a special case because setting a handler requires
2760 @item @code{-type} -- returns the target type.
2761 This is a special case because this is set using
2762 @command{target create} and can't be changed
2763 using @command{$target_name configure}.
2766 For example, if you wanted to summarize information about
2767 all the targets you might use something like this:
2770 foreach name [target names] @{
2771 set y [$name cget -endian]
2772 set z [$name cget -type]
2773 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2779 @anchor{target curstate}
2780 @deffn Command {$target_name curstate}
2781 Displays the current target state:
2782 @code{debug-running},
2785 @code{running}, or @code{unknown}.
2786 (Also, @pxref{Event Polling}.)
2789 @deffn Command {$target_name eventlist}
2790 Displays a table listing all event handlers
2791 currently associated with this target.
2792 @xref{Target Events}.
2795 @deffn Command {$target_name invoke-event} event_name
2796 Invokes the handler for the event named @var{event_name}.
2797 (This is primarily intended for use by OpenOCD framework
2798 code, for example by the reset code in @file{startup.tcl}.)
2801 @deffn Command {$target_name mdw} addr [count]
2802 @deffnx Command {$target_name mdh} addr [count]
2803 @deffnx Command {$target_name mdb} addr [count]
2804 Display contents of address @var{addr}, as
2805 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2806 or 8-bit bytes (@command{mdb}).
2807 If @var{count} is specified, displays that many units.
2808 (If you want to manipulate the data instead of displaying it,
2809 see the @code{mem2array} primitives.)
2812 @deffn Command {$target_name mww} addr word
2813 @deffnx Command {$target_name mwh} addr halfword
2814 @deffnx Command {$target_name mwb} addr byte
2815 Writes the specified @var{word} (32 bits),
2816 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2817 at the specified address @var{addr}.
2820 @anchor{Target Events}
2821 @section Target Events
2823 At various times, certain things can happen, or you want them to happen.
2826 @item What should happen when GDB connects? Should your target reset?
2827 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2828 @item During reset, do you need to write to certain memory locations
2829 to set up system clocks or
2830 to reconfigure the SDRAM?
2833 All of the above items can be addressed by target event handlers.
2834 These are set up by @command{$target_name configure -event} or
2835 @command{target create ... -event}.
2837 The programmer's model matches the @code{-command} option used in Tcl/Tk
2838 buttons and events. The two examples below act the same, but one creates
2839 and invokes a small procedure while the other inlines it.
2842 proc my_attach_proc @{ @} @{
2846 mychip.cpu configure -event gdb-attach my_attach_proc
2847 mychip.cpu configure -event gdb-attach @{
2853 The following target events are defined:
2856 @item @b{debug-halted}
2857 @* The target has halted for debug reasons (i.e.: breakpoint)
2858 @item @b{debug-resumed}
2859 @* The target has resumed (i.e.: gdb said run)
2860 @item @b{early-halted}
2861 @* Occurs early in the halt process
2863 @item @b{examine-end}
2864 @* Currently not used (goal: when JTAG examine completes)
2865 @item @b{examine-start}
2866 @* Currently not used (goal: when JTAG examine starts)
2868 @item @b{gdb-attach}
2869 @* When GDB connects
2870 @item @b{gdb-detach}
2871 @* When GDB disconnects
2873 @* When the target has halted and GDB is not doing anything (see early halt)
2874 @item @b{gdb-flash-erase-start}
2875 @* Before the GDB flash process tries to erase the flash
2876 @item @b{gdb-flash-erase-end}
2877 @* After the GDB flash process has finished erasing the flash
2878 @item @b{gdb-flash-write-start}
2879 @* Before GDB writes to the flash
2880 @item @b{gdb-flash-write-end}
2881 @* After GDB writes to the flash
2883 @* Before the target steps, gdb is trying to start/resume the target
2885 @* The target has halted
2887 @item @b{old-gdb_program_config}
2888 @* DO NOT USE THIS: Used internally
2889 @item @b{old-pre_resume}
2890 @* DO NOT USE THIS: Used internally
2892 @item @b{reset-assert-pre}
2893 @* Issued as part of @command{reset} processing
2894 after SRST and/or TRST were activated and deactivated,
2895 but before reset is asserted on the tap.
2896 @item @b{reset-assert-post}
2897 @* Issued as part of @command{reset} processing
2898 when reset is asserted on the tap.
2899 @item @b{reset-deassert-pre}
2900 @* Issued as part of @command{reset} processing
2901 when reset is about to be released on the tap.
2903 For some chips, this may be a good place to make sure
2904 the JTAG clock is slow enough to work before the PLL
2905 has been set up to allow faster JTAG speeds.
2906 @item @b{reset-deassert-post}
2907 @* Issued as part of @command{reset} processing
2908 when reset has been released on the tap.
2910 @* Issued as the final step in @command{reset} processing.
2912 @item @b{reset-halt-post}
2913 @* Currently not used
2914 @item @b{reset-halt-pre}
2915 @* Currently not used
2917 @item @b{reset-init}
2918 @* Used by @b{reset init} command for board-specific initialization.
2919 This event fires after @emph{reset-deassert-post}.
2921 This is where you would configure PLLs and clocking, set up DRAM so
2922 you can download programs that don't fit in on-chip SRAM, set up pin
2923 multiplexing, and so on.
2924 @item @b{reset-start}
2925 @* Issued as part of @command{reset} processing
2926 before either SRST or TRST are activated.
2928 @item @b{reset-wait-pos}
2929 @* Currently not used
2930 @item @b{reset-wait-pre}
2931 @* Currently not used
2933 @item @b{resume-start}
2934 @* Before any target is resumed
2935 @item @b{resume-end}
2936 @* After all targets have resumed
2940 @* Target has resumed
2944 @node Flash Commands
2945 @chapter Flash Commands
2947 OpenOCD has different commands for NOR and NAND flash;
2948 the ``flash'' command works with NOR flash, while
2949 the ``nand'' command works with NAND flash.
2950 This partially reflects different hardware technologies:
2951 NOR flash usually supports direct CPU instruction and data bus access,
2952 while data from a NAND flash must be copied to memory before it can be
2953 used. (SPI flash must also be copied to memory before use.)
2954 However, the documentation also uses ``flash'' as a generic term;
2955 for example, ``Put flash configuration in board-specific files''.
2959 @item Configure via the command @command{flash bank}
2960 @* Do this in a board-specific configuration file,
2961 passing parameters as needed by the driver.
2962 @item Operate on the flash via @command{flash subcommand}
2963 @* Often commands to manipulate the flash are typed by a human, or run
2964 via a script in some automated way. Common tasks include writing a
2965 boot loader, operating system, or other data.
2967 @* Flashing via GDB requires the flash be configured via ``flash
2968 bank'', and the GDB flash features be enabled.
2969 @xref{GDB Configuration}.
2972 Many CPUs have the ablity to ``boot'' from the first flash bank.
2973 This means that misprogramming that bank can ``brick'' a system,
2974 so that it can't boot.
2975 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2976 board by (re)installing working boot firmware.
2978 @anchor{NOR Configuration}
2979 @section Flash Configuration Commands
2980 @cindex flash configuration
2982 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2983 Configures a flash bank which provides persistent storage
2984 for addresses from @math{base} to @math{base + size - 1}.
2985 These banks will often be visible to GDB through the target's memory map.
2986 In some cases, configuring a flash bank will activate extra commands;
2987 see the driver-specific documentation.
2990 @item @var{driver} ... identifies the controller driver
2991 associated with the flash bank being declared.
2992 This is usually @code{cfi} for external flash, or else
2993 the name of a microcontroller with embedded flash memory.
2994 @xref{Flash Driver List}.
2995 @item @var{base} ... Base address of the flash chip.
2996 @item @var{size} ... Size of the chip, in bytes.
2997 For some drivers, this value is detected from the hardware.
2998 @item @var{chip_width} ... Width of the flash chip, in bytes;
2999 ignored for most microcontroller drivers.
3000 @item @var{bus_width} ... Width of the data bus used to access the
3001 chip, in bytes; ignored for most microcontroller drivers.
3002 @item @var{target} ... Names the target used to issue
3003 commands to the flash controller.
3004 @comment Actually, it's currently a controller-specific parameter...
3005 @item @var{driver_options} ... drivers may support, or require,
3006 additional parameters. See the driver-specific documentation
3007 for more information.
3010 This command is not available after OpenOCD initialization has completed.
3011 Use it in board specific configuration files, not interactively.
3015 @comment the REAL name for this command is "ocd_flash_banks"
3016 @comment less confusing would be: "flash list" (like "nand list")
3017 @deffn Command {flash banks}
3018 Prints a one-line summary of each device declared
3019 using @command{flash bank}, numbered from zero.
3020 Note that this is the @emph{plural} form;
3021 the @emph{singular} form is a very different command.
3024 @deffn Command {flash probe} num
3025 Identify the flash, or validate the parameters of the configured flash. Operation
3026 depends on the flash type.
3027 The @var{num} parameter is a value shown by @command{flash banks}.
3028 Most flash commands will implicitly @emph{autoprobe} the bank;
3029 flash drivers can distinguish between probing and autoprobing,
3030 but most don't bother.
3033 @section Erasing, Reading, Writing to Flash
3034 @cindex flash erasing
3035 @cindex flash reading
3036 @cindex flash writing
3037 @cindex flash programming
3039 One feature distinguishing NOR flash from NAND or serial flash technologies
3040 is that for read access, it acts exactly like any other addressible memory.
3041 This means you can use normal memory read commands like @command{mdw} or
3042 @command{dump_image} with it, with no special @command{flash} subcommands.
3043 @xref{Memory access}, and @ref{Image access}.
3045 Write access works differently. Flash memory normally needs to be erased
3046 before it's written. Erasing a sector turns all of its bits to ones, and
3047 writing can turn ones into zeroes. This is why there are special commands
3048 for interactive erasing and writing, and why GDB needs to know which parts
3049 of the address space hold NOR flash memory.
3052 Most of these erase and write commands leverage the fact that NOR flash
3053 chips consume target address space. They implicitly refer to the current
3054 JTAG target, and map from an address in that target's address space
3055 back to a flash bank.
3056 @comment In May 2009, those mappings may fail if any bank associated
3057 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3058 A few commands use abstract addressing based on bank and sector numbers,
3059 and don't depend on searching the current target and its address space.
3060 Avoid confusing the two command models.
3063 Some flash chips implement software protection against accidental writes,
3064 since such buggy writes could in some cases ``brick'' a system.
3065 For such systems, erasing and writing may require sector protection to be
3067 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3068 and AT91SAM7 on-chip flash.
3069 @xref{flash protect}.
3071 @anchor{flash erase_sector}
3072 @deffn Command {flash erase_sector} num first last
3073 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3074 @var{last}. Sector numbering starts at 0.
3075 The @var{num} parameter is a value shown by @command{flash banks}.
3078 @deffn Command {flash erase_address} address length
3079 Erase sectors starting at @var{address} for @var{length} bytes.
3080 The flash bank to use is inferred from the @var{address}, and
3081 the specified length must stay within that bank.
3082 As a special case, when @var{length} is zero and @var{address} is
3083 the start of the bank, the whole flash is erased.
3086 @deffn Command {flash fillw} address word length
3087 @deffnx Command {flash fillh} address halfword length
3088 @deffnx Command {flash fillb} address byte length
3089 Fills flash memory with the specified @var{word} (32 bits),
3090 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3091 starting at @var{address} and continuing
3092 for @var{length} units (word/halfword/byte).
3093 No erasure is done before writing; when needed, that must be done
3094 before issuing this command.
3095 Writes are done in blocks of up to 1024 bytes, and each write is
3096 verified by reading back the data and comparing it to what was written.
3097 The flash bank to use is inferred from the @var{address} of
3098 each block, and the specified length must stay within that bank.
3100 @comment no current checks for errors if fill blocks touch multiple banks!
3102 @anchor{flash write_bank}
3103 @deffn Command {flash write_bank} num filename offset
3104 Write the binary @file{filename} to flash bank @var{num},
3105 starting at @var{offset} bytes from the beginning of the bank.
3106 The @var{num} parameter is a value shown by @command{flash banks}.
3109 @anchor{flash write_image}
3110 @deffn Command {flash write_image} [erase] filename [offset] [type]
3111 Write the image @file{filename} to the current target's flash bank(s).
3112 A relocation @var{offset} may be specified, in which case it is added
3113 to the base address for each section in the image.
3114 The file [@var{type}] can be specified
3115 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3116 @option{elf} (ELF file), @option{s19} (Motorola s19).
3117 @option{mem}, or @option{builder}.
3118 The relevant flash sectors will be erased prior to programming
3119 if the @option{erase} parameter is given.
3120 The flash bank to use is inferred from the @var{address} of
3124 @section Other Flash commands
3125 @cindex flash protection
3127 @deffn Command {flash erase_check} num
3128 Check erase state of sectors in flash bank @var{num},
3129 and display that status.
3130 The @var{num} parameter is a value shown by @command{flash banks}.
3131 This is the only operation that
3132 updates the erase state information displayed by @option{flash info}. That means you have
3133 to issue an @command{flash erase_check} command after erasing or programming the device
3134 to get updated information.
3135 (Code execution may have invalidated any state records kept by OpenOCD.)
3138 @deffn Command {flash info} num
3139 Print info about flash bank @var{num}
3140 The @var{num} parameter is a value shown by @command{flash banks}.
3141 The information includes per-sector protect status.
3144 @anchor{flash protect}
3145 @deffn Command {flash protect} num first last (on|off)
3146 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3147 @var{first} to @var{last} of flash bank @var{num}.
3148 The @var{num} parameter is a value shown by @command{flash banks}.
3151 @deffn Command {flash protect_check} num
3152 Check protection state of sectors in flash bank @var{num}.
3153 The @var{num} parameter is a value shown by @command{flash banks}.
3154 @comment @option{flash erase_sector} using the same syntax.
3157 @anchor{Flash Driver List}
3158 @section Flash Drivers, Options, and Commands
3159 As noted above, the @command{flash bank} command requires a driver name,
3160 and allows driver-specific options and behaviors.
3161 Some drivers also activate driver-specific commands.
3163 @subsection External Flash
3165 @deffn {Flash Driver} cfi
3166 @cindex Common Flash Interface
3168 The ``Common Flash Interface'' (CFI) is the main standard for
3169 external NOR flash chips, each of which connects to a
3170 specific external chip select on the CPU.
3171 Frequently the first such chip is used to boot the system.
3172 Your board's @code{reset-init} handler might need to
3173 configure additional chip selects using other commands (like: @command{mww} to
3174 configure a bus and its timings) , or
3175 perhaps configure a GPIO pin that controls the ``write protect'' pin
3177 The CFI driver can use a target-specific working area to significantly
3180 The CFI driver can accept the following optional parameters, in any order:
3183 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3184 like AM29LV010 and similar types.
3185 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3188 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3189 wide on a sixteen bit bus:
3192 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3193 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3195 @c "cfi part_id" disabled
3198 @subsection Internal Flash (Microcontrollers)
3200 @deffn {Flash Driver} aduc702x
3201 The ADUC702x analog microcontrollers from Analog Devices
3202 include internal flash and use ARM7TDMI cores.
3203 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3204 The setup command only requires the @var{target} argument
3205 since all devices in this family have the same memory layout.
3208 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3212 @deffn {Flash Driver} at91sam3
3214 All members of the AT91SAM3 microcontroller family from
3215 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3216 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3217 that the driver was orginaly developed and tested using the
3218 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3219 the family was cribbed from the data sheet. @emph{Note to future
3220 readers/updaters: Please remove this worrysome comment after other
3221 chips are confirmed.}
3223 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3224 have one flash bank. In all cases the flash banks are at
3225 the following fixed locations:
3228 # Flash bank 0 - all chips
3229 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3230 # Flash bank 1 - only 256K chips
3231 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3234 Internally, the AT91SAM3 flash memory is organized as follows.
3235 Unlike the AT91SAM7 chips, these are not used as parameters
3236 to the @command{flash bank} command:
3239 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3240 @item @emph{Bank Size:} 128K/64K Per flash bank
3241 @item @emph{Sectors:} 16 or 8 per bank
3242 @item @emph{SectorSize:} 8K Per Sector
3243 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3246 The AT91SAM3 driver adds some additional commands:
3248 @deffn Command {at91sam3 gpnvm}
3249 @deffnx Command {at91sam3 gpnvm clear} number
3250 @deffnx Command {at91sam3 gpnvm set} number
3251 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3252 With no parameters, @command{show} or @command{show all},
3253 shows the status of all GPNVM bits.
3254 With @command{show} @var{number}, displays that bit.
3256 With @command{set} @var{number} or @command{clear} @var{number},
3257 modifies that GPNVM bit.
3260 @deffn Command {at91sam3 info}
3261 This command attempts to display information about the AT91SAM3
3262 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3263 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3264 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3265 various clock configuration registers and attempts to display how it
3266 believes the chip is configured. By default, the SLOWCLK is assumed to
3267 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3270 @deffn Command {at91sam3 slowclk} [value]
3271 This command shows/sets the slow clock frequency used in the
3272 @command{at91sam3 info} command calculations above.
3276 @deffn {Flash Driver} at91sam7
3277 All members of the AT91SAM7 microcontroller family from Atmel include
3278 internal flash and use ARM7TDMI cores. The driver automatically
3279 recognizes a number of these chips using the chip identification
3280 register, and autoconfigures itself.
3283 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3286 For chips which are not recognized by the controller driver, you must
3287 provide additional parameters in the following order:
3290 @item @var{chip_model} ... label used with @command{flash info}
3292 @item @var{sectors_per_bank}
3293 @item @var{pages_per_sector}
3294 @item @var{pages_size}
3295 @item @var{num_nvm_bits}
3296 @item @var{freq_khz} ... required if an external clock is provided,
3297 optional (but recommended) when the oscillator frequency is known
3300 It is recommended that you provide zeroes for all of those values
3301 except the clock frequency, so that everything except that frequency
3302 will be autoconfigured.
3303 Knowing the frequency helps ensure correct timings for flash access.
3305 The flash controller handles erases automatically on a page (128/256 byte)
3306 basis, so explicit erase commands are not necessary for flash programming.
3307 However, there is an ``EraseAll`` command that can erase an entire flash
3308 plane (of up to 256KB), and it will be used automatically when you issue
3309 @command{flash erase_sector} or @command{flash erase_address} commands.
3311 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3312 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3313 bit for the processor. Each processor has a number of such bits,
3314 used for controlling features such as brownout detection (so they
3315 are not truly general purpose).
3317 This assumes that the first flash bank (number 0) is associated with
3318 the appropriate at91sam7 target.
3323 @deffn {Flash Driver} avr
3324 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3325 @emph{The current implementation is incomplete.}
3326 @comment - defines mass_erase ... pointless given flash_erase_address
3329 @deffn {Flash Driver} ecosflash
3330 @emph{No idea what this is...}
3331 The @var{ecosflash} driver defines one mandatory parameter,
3332 the name of a modules of target code which is downloaded
3336 @deffn {Flash Driver} lpc2000
3337 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3338 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3341 There are LPC2000 devices which are not supported by the @var{lpc2000}
3343 The LPC2888 is supported by the @var{lpc288x} driver.
3344 The LPC29xx family is supported by the @var{lpc2900} driver.
3347 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3348 which must appear in the following order:
3351 @item @var{variant} ... required, may be
3352 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3353 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3354 or @var{lpc1700} (LPC175x and LPC176x)
3355 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3356 at which the core is running
3357 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3358 telling the driver to calculate a valid checksum for the exception vector table.
3361 LPC flashes don't require the chip and bus width to be specified.
3364 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3365 lpc2000_v2 14765 calc_checksum
3368 @deffn {Command} {lpc2000 part_id} bank
3369 Displays the four byte part identifier associated with
3370 the specified flash @var{bank}.
3374 @deffn {Flash Driver} lpc288x
3375 The LPC2888 microcontroller from NXP needs slightly different flash
3376 support from its lpc2000 siblings.
3377 The @var{lpc288x} driver defines one mandatory parameter,
3378 the programming clock rate in Hz.
3379 LPC flashes don't require the chip and bus width to be specified.
3382 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3386 @deffn {Flash Driver} lpc2900
3387 This driver supports the LPC29xx ARM968E based microcontroller family
3390 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3391 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3392 sector layout are auto-configured by the driver.
3393 The driver has one additional mandatory parameter: The CPU clock rate
3394 (in kHz) at the time the flash operations will take place. Most of the time this
3395 will not be the crystal frequency, but a higher PLL frequency. The
3396 @code{reset-init} event handler in the board script is usually the place where
3399 The driver rejects flashless devices (currently the LPC2930).
3401 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3402 It must be handled much more like NAND flash memory, and will therefore be
3403 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3405 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3406 sector needs to be erased or programmed, it is automatically unprotected.
3407 What is shown as protection status in the @code{flash info} command, is
3408 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3409 sector from ever being erased or programmed again. As this is an irreversible
3410 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3411 and not by the standard @code{flash protect} command.
3413 Example for a 125 MHz clock frequency:
3415 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3418 Some @code{lpc2900}-specific commands are defined. In the following command list,
3419 the @var{bank} parameter is the bank number as obtained by the
3420 @code{flash banks} command.
3422 @deffn Command {lpc2900 signature} bank
3423 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3424 content. This is a hardware feature of the flash block, hence the calculation is
3425 very fast. You may use this to verify the content of a programmed device against
3430 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3434 @deffn Command {lpc2900 read_custom} bank filename
3435 Reads the 912 bytes of customer information from the flash index sector, and
3436 saves it to a file in binary format.
3439 lpc2900 read_custom 0 /path_to/customer_info.bin
3443 The index sector of the flash is a @emph{write-only} sector. It cannot be
3444 erased! In order to guard against unintentional write access, all following
3445 commands need to be preceeded by a successful call to the @code{password}
3448 @deffn Command {lpc2900 password} bank password
3449 You need to use this command right before each of the following commands:
3450 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3451 @code{lpc2900 secure_jtag}.
3453 The password string is fixed to "I_know_what_I_am_doing".
3456 lpc2900 password 0 I_know_what_I_am_doing
3457 Potentially dangerous operation allowed in next command!
3461 @deffn Command {lpc2900 write_custom} bank filename type
3462 Writes the content of the file into the customer info space of the flash index
3463 sector. The filetype can be specified with the @var{type} field. Possible values
3464 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3465 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3466 contain a single section, and the contained data length must be exactly
3468 @quotation Attention
3469 This cannot be reverted! Be careful!
3473 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3477 @deffn Command {lpc2900 secure_sector} bank first last
3478 Secures the sector range from @var{first} to @var{last} (including) against
3479 further program and erase operations. The sector security will be effective
3480 after the next power cycle.
3481 @quotation Attention
3482 This cannot be reverted! Be careful!
3484 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3487 lpc2900 secure_sector 0 1 1
3489 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3490 # 0: 0x00000000 (0x2000 8kB) not protected
3491 # 1: 0x00002000 (0x2000 8kB) protected
3492 # 2: 0x00004000 (0x2000 8kB) not protected
3496 @deffn Command {lpc2900 secure_jtag} bank
3497 Irreversibly disable the JTAG port. The new JTAG security setting will be
3498 effective after the next power cycle.
3499 @quotation Attention
3500 This cannot be reverted! Be careful!
3504 lpc2900 secure_jtag 0
3509 @deffn {Flash Driver} ocl
3510 @emph{No idea what this is, other than using some arm7/arm9 core.}
3513 flash bank ocl 0 0 0 0 $_TARGETNAME
3517 @deffn {Flash Driver} pic32mx
3518 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3519 and integrate flash memory.
3520 @emph{The current implementation is incomplete.}
3523 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3526 @comment numerous *disabled* commands are defined:
3527 @comment - chip_erase ... pointless given flash_erase_address
3528 @comment - lock, unlock ... pointless given protect on/off (yes?)
3529 @comment - pgm_word ... shouldn't bank be deduced from address??
3530 Some pic32mx-specific commands are defined:
3531 @deffn Command {pic32mx pgm_word} address value bank
3532 Programs the specified 32-bit @var{value} at the given @var{address}
3533 in the specified chip @var{bank}.
3537 @deffn {Flash Driver} stellaris
3538 All members of the Stellaris LM3Sxxx microcontroller family from
3540 include internal flash and use ARM Cortex M3 cores.
3541 The driver automatically recognizes a number of these chips using
3542 the chip identification register, and autoconfigures itself.
3543 @footnote{Currently there is a @command{stellaris mass_erase} command.
3544 That seems pointless since the same effect can be had using the
3545 standard @command{flash erase_address} command.}
3548 flash bank stellaris 0 0 0 0 $_TARGETNAME
3552 @deffn {Flash Driver} stm32x
3553 All members of the STM32 microcontroller family from ST Microelectronics
3554 include internal flash and use ARM Cortex M3 cores.
3555 The driver automatically recognizes a number of these chips using
3556 the chip identification register, and autoconfigures itself.
3559 flash bank stm32x 0 0 0 0 $_TARGETNAME
3562 Some stm32x-specific commands
3563 @footnote{Currently there is a @command{stm32x mass_erase} command.
3564 That seems pointless since the same effect can be had using the
3565 standard @command{flash erase_address} command.}
3568 @deffn Command {stm32x lock} num
3569 Locks the entire stm32 device.
3570 The @var{num} parameter is a value shown by @command{flash banks}.
3573 @deffn Command {stm32x unlock} num
3574 Unlocks the entire stm32 device.
3575 The @var{num} parameter is a value shown by @command{flash banks}.
3578 @deffn Command {stm32x options_read} num
3579 Read and display the stm32 option bytes written by
3580 the @command{stm32x options_write} command.
3581 The @var{num} parameter is a value shown by @command{flash banks}.
3584 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3585 Writes the stm32 option byte with the specified values.
3586 The @var{num} parameter is a value shown by @command{flash banks}.
3590 @deffn {Flash Driver} str7x
3591 All members of the STR7 microcontroller family from ST Microelectronics
3592 include internal flash and use ARM7TDMI cores.
3593 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3594 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3597 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3600 @deffn Command {str7x disable_jtag} bank
3601 Activate the Debug/Readout protection mechanism
3602 for the specified flash bank.
3606 @deffn {Flash Driver} str9x
3607 Most members of the STR9 microcontroller family from ST Microelectronics
3608 include internal flash and use ARM966E cores.
3609 The str9 needs the flash controller to be configured using
3610 the @command{str9x flash_config} command prior to Flash programming.
3613 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3614 str9x flash_config 0 4 2 0 0x80000
3617 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3618 Configures the str9 flash controller.
3619 The @var{num} parameter is a value shown by @command{flash banks}.
3622 @item @var{bbsr} - Boot Bank Size register
3623 @item @var{nbbsr} - Non Boot Bank Size register
3624 @item @var{bbadr} - Boot Bank Start Address register
3625 @item @var{nbbadr} - Boot Bank Start Address register
3631 @deffn {Flash Driver} tms470
3632 Most members of the TMS470 microcontroller family from Texas Instruments
3633 include internal flash and use ARM7TDMI cores.
3634 This driver doesn't require the chip and bus width to be specified.
3636 Some tms470-specific commands are defined:
3638 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3639 Saves programming keys in a register, to enable flash erase and write commands.
3642 @deffn Command {tms470 osc_mhz} clock_mhz
3643 Reports the clock speed, which is used to calculate timings.
3646 @deffn Command {tms470 plldis} (0|1)
3647 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3652 @subsection str9xpec driver
3655 Here is some background info to help
3656 you better understand how this driver works. OpenOCD has two flash drivers for
3660 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3661 flash programming as it is faster than the @option{str9xpec} driver.
3663 Direct programming @option{str9xpec} using the flash controller. This is an
3664 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3665 core does not need to be running to program using this flash driver. Typical use
3666 for this driver is locking/unlocking the target and programming the option bytes.
3669 Before we run any commands using the @option{str9xpec} driver we must first disable
3670 the str9 core. This example assumes the @option{str9xpec} driver has been
3671 configured for flash bank 0.
3673 # assert srst, we do not want core running
3674 # while accessing str9xpec flash driver
3676 # turn off target polling
3679 str9xpec enable_turbo 0
3681 str9xpec options_read 0
3682 # re-enable str9 core
3683 str9xpec disable_turbo 0
3687 The above example will read the str9 option bytes.
3688 When performing a unlock remember that you will not be able to halt the str9 - it
3689 has been locked. Halting the core is not required for the @option{str9xpec} driver
3690 as mentioned above, just issue the commands above manually or from a telnet prompt.
3692 @deffn {Flash Driver} str9xpec
3693 Only use this driver for locking/unlocking the device or configuring the option bytes.
3694 Use the standard str9 driver for programming.
3695 Before using the flash commands the turbo mode must be enabled using the
3696 @command{str9xpec enable_turbo} command.
3698 Several str9xpec-specific commands are defined:
3700 @deffn Command {str9xpec disable_turbo} num
3701 Restore the str9 into JTAG chain.
3704 @deffn Command {str9xpec enable_turbo} num
3705 Enable turbo mode, will simply remove the str9 from the chain and talk
3706 directly to the embedded flash controller.
3709 @deffn Command {str9xpec lock} num
3710 Lock str9 device. The str9 will only respond to an unlock command that will
3714 @deffn Command {str9xpec part_id} num
3715 Prints the part identifier for bank @var{num}.
3718 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3719 Configure str9 boot bank.
3722 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3723 Configure str9 lvd source.
3726 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3727 Configure str9 lvd threshold.
3730 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3731 Configure str9 lvd reset warning source.
3734 @deffn Command {str9xpec options_read} num
3735 Read str9 option bytes.
3738 @deffn Command {str9xpec options_write} num
3739 Write str9 option bytes.
3742 @deffn Command {str9xpec unlock} num
3751 @subsection mFlash Configuration
3752 @cindex mFlash Configuration
3754 @deffn {Config Command} {mflash bank} soc base RST_pin target
3755 Configures a mflash for @var{soc} host bank at
3757 The pin number format depends on the host GPIO naming convention.
3758 Currently, the mflash driver supports s3c2440 and pxa270.
3760 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3763 mflash bank s3c2440 0x10000000 1b 0
3766 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3769 mflash bank pxa270 0x08000000 43 0
3773 @subsection mFlash commands
3774 @cindex mFlash commands
3776 @deffn Command {mflash config pll} frequency
3777 Configure mflash PLL.
3778 The @var{frequency} is the mflash input frequency, in Hz.
3779 Issuing this command will erase mflash's whole internal nand and write new pll.
3780 After this command, mflash needs power-on-reset for normal operation.
3781 If pll was newly configured, storage and boot(optional) info also need to be update.
3784 @deffn Command {mflash config boot}
3785 Configure bootable option.
3786 If bootable option is set, mflash offer the first 8 sectors
3790 @deffn Command {mflash config storage}
3791 Configure storage information.
3792 For the normal storage operation, this information must be
3796 @deffn Command {mflash dump} num filename offset size
3797 Dump @var{size} bytes, starting at @var{offset} bytes from the
3798 beginning of the bank @var{num}, to the file named @var{filename}.
3801 @deffn Command {mflash probe}
3805 @deffn Command {mflash write} num filename offset
3806 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3807 @var{offset} bytes from the beginning of the bank.
3810 @node NAND Flash Commands
3811 @chapter NAND Flash Commands
3814 Compared to NOR or SPI flash, NAND devices are inexpensive
3815 and high density. Today's NAND chips, and multi-chip modules,
3816 commonly hold multiple GigaBytes of data.
3818 NAND chips consist of a number of ``erase blocks'' of a given
3819 size (such as 128 KBytes), each of which is divided into a
3820 number of pages (of perhaps 512 or 2048 bytes each). Each
3821 page of a NAND flash has an ``out of band'' (OOB) area to hold
3822 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3823 of OOB for every 512 bytes of page data.
3825 One key characteristic of NAND flash is that its error rate
3826 is higher than that of NOR flash. In normal operation, that
3827 ECC is used to correct and detect errors. However, NAND
3828 blocks can also wear out and become unusable; those blocks
3829 are then marked "bad". NAND chips are even shipped from the
3830 manufacturer with a few bad blocks. The highest density chips
3831 use a technology (MLC) that wears out more quickly, so ECC
3832 support is increasingly important as a way to detect blocks
3833 that have begun to fail, and help to preserve data integrity
3834 with techniques such as wear leveling.
3836 Software is used to manage the ECC. Some controllers don't
3837 support ECC directly; in those cases, software ECC is used.
3838 Other controllers speed up the ECC calculations with hardware.
3839 Single-bit error correction hardware is routine. Controllers
3840 geared for newer MLC chips may correct 4 or more errors for
3841 every 512 bytes of data.
3843 You will need to make sure that any data you write using
3844 OpenOCD includes the apppropriate kind of ECC. For example,
3845 that may mean passing the @code{oob_softecc} flag when
3846 writing NAND data, or ensuring that the correct hardware
3849 The basic steps for using NAND devices include:
3851 @item Declare via the command @command{nand device}
3852 @* Do this in a board-specific configuration file,
3853 passing parameters as needed by the controller.
3854 @item Configure each device using @command{nand probe}.
3855 @* Do this only after the associated target is set up,
3856 such as in its reset-init script or in procures defined
3857 to access that device.
3858 @item Operate on the flash via @command{nand subcommand}
3859 @* Often commands to manipulate the flash are typed by a human, or run
3860 via a script in some automated way. Common task include writing a
3861 boot loader, operating system, or other data needed to initialize or
3865 @b{NOTE:} At the time this text was written, the largest NAND
3866 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3867 This is because the variables used to hold offsets and lengths
3868 are only 32 bits wide.
3869 (Larger chips may work in some cases, unless an offset or length
3870 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3871 Some larger devices will work, since they are actually multi-chip
3872 modules with two smaller chips and individual chipselect lines.
3874 @anchor{NAND Configuration}
3875 @section NAND Configuration Commands
3876 @cindex NAND configuration
3878 NAND chips must be declared in configuration scripts,
3879 plus some additional configuration that's done after
3880 OpenOCD has initialized.
3882 @deffn {Config Command} {nand device} controller target [configparams...]
3883 Declares a NAND device, which can be read and written to
3884 after it has been configured through @command{nand probe}.
3885 In OpenOCD, devices are single chips; this is unlike some
3886 operating systems, which may manage multiple chips as if
3887 they were a single (larger) device.
3888 In some cases, configuring a device will activate extra
3889 commands; see the controller-specific documentation.
3891 @b{NOTE:} This command is not available after OpenOCD
3892 initialization has completed. Use it in board specific
3893 configuration files, not interactively.
3896 @item @var{controller} ... identifies the controller driver
3897 associated with the NAND device being declared.
3898 @xref{NAND Driver List}.
3899 @item @var{target} ... names the target used when issuing
3900 commands to the NAND controller.
3901 @comment Actually, it's currently a controller-specific parameter...
3902 @item @var{configparams} ... controllers may support, or require,
3903 additional parameters. See the controller-specific documentation
3904 for more information.
3908 @deffn Command {nand list}
3909 Prints a summary of each device declared
3910 using @command{nand device}, numbered from zero.
3911 Note that un-probed devices show no details.
3914 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3915 blocksize: 131072, blocks: 8192
3916 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3917 blocksize: 131072, blocks: 8192
3922 @deffn Command {nand probe} num
3923 Probes the specified device to determine key characteristics
3924 like its page and block sizes, and how many blocks it has.
3925 The @var{num} parameter is the value shown by @command{nand list}.
3926 You must (successfully) probe a device before you can use
3927 it with most other NAND commands.
3930 @section Erasing, Reading, Writing to NAND Flash
3932 @deffn Command {nand dump} num filename offset length [oob_option]
3933 @cindex NAND reading
3934 Reads binary data from the NAND device and writes it to the file,
3935 starting at the specified offset.
3936 The @var{num} parameter is the value shown by @command{nand list}.
3938 Use a complete path name for @var{filename}, so you don't depend
3939 on the directory used to start the OpenOCD server.
3941 The @var{offset} and @var{length} must be exact multiples of the
3942 device's page size. They describe a data region; the OOB data
3943 associated with each such page may also be accessed.
3945 @b{NOTE:} At the time this text was written, no error correction
3946 was done on the data that's read, unless raw access was disabled
3947 and the underlying NAND controller driver had a @code{read_page}
3948 method which handled that error correction.
3950 By default, only page data is saved to the specified file.
3951 Use an @var{oob_option} parameter to save OOB data:
3953 @item no oob_* parameter
3954 @*Output file holds only page data; OOB is discarded.
3955 @item @code{oob_raw}
3956 @*Output file interleaves page data and OOB data;
3957 the file will be longer than "length" by the size of the
3958 spare areas associated with each data page.
3959 Note that this kind of "raw" access is different from
3960 what's implied by @command{nand raw_access}, which just
3961 controls whether a hardware-aware access method is used.
3962 @item @code{oob_only}
3963 @*Output file has only raw OOB data, and will
3964 be smaller than "length" since it will contain only the
3965 spare areas associated with each data page.
3969 @deffn Command {nand erase} num [offset length]
3970 @cindex NAND erasing
3971 @cindex NAND programming
3972 Erases blocks on the specified NAND device, starting at the
3973 specified @var{offset} and continuing for @var{length} bytes.
3974 Both of those values must be exact multiples of the device's
3975 block size, and the region they specify must fit entirely in the chip.
3976 If those parameters are not specified,
3977 the whole NAND chip will be erased.
3978 The @var{num} parameter is the value shown by @command{nand list}.
3980 @b{NOTE:} This command will try to erase bad blocks, when told
3981 to do so, which will probably invalidate the manufacturer's bad
3983 For the remainder of the current server session, @command{nand info}
3984 will still report that the block ``is'' bad.
3987 @deffn Command {nand write} num filename offset [option...]
3988 @cindex NAND writing
3989 @cindex NAND programming
3990 Writes binary data from the file into the specified NAND device,
3991 starting at the specified offset. Those pages should already
3992 have been erased; you can't change zero bits to one bits.
3993 The @var{num} parameter is the value shown by @command{nand list}.
3995 Use a complete path name for @var{filename}, so you don't depend
3996 on the directory used to start the OpenOCD server.
3998 The @var{offset} must be an exact multiple of the device's page size.
3999 All data in the file will be written, assuming it doesn't run
4000 past the end of the device.
4001 Only full pages are written, and any extra space in the last
4002 page will be filled with 0xff bytes. (That includes OOB data,
4003 if that's being written.)
4005 @b{NOTE:} At the time this text was written, bad blocks are
4006 ignored. That is, this routine will not skip bad blocks,
4007 but will instead try to write them. This can cause problems.
4009 Provide at most one @var{option} parameter. With some
4010 NAND drivers, the meanings of these parameters may change
4011 if @command{nand raw_access} was used to disable hardware ECC.
4013 @item no oob_* parameter
4014 @*File has only page data, which is written.
4015 If raw acccess is in use, the OOB area will not be written.
4016 Otherwise, if the underlying NAND controller driver has
4017 a @code{write_page} routine, that routine may write the OOB
4018 with hardware-computed ECC data.
4019 @item @code{oob_only}
4020 @*File has only raw OOB data, which is written to the OOB area.
4021 Each page's data area stays untouched. @i{This can be a dangerous
4022 option}, since it can invalidate the ECC data.
4023 You may need to force raw access to use this mode.
4024 @item @code{oob_raw}
4025 @*File interleaves data and OOB data, both of which are written
4026 If raw access is enabled, the data is written first, then the
4028 Otherwise, if the underlying NAND controller driver has
4029 a @code{write_page} routine, that routine may modify the OOB
4030 before it's written, to include hardware-computed ECC data.
4031 @item @code{oob_softecc}
4032 @*File has only page data, which is written.
4033 The OOB area is filled with 0xff, except for a standard 1-bit
4034 software ECC code stored in conventional locations.
4035 You might need to force raw access to use this mode, to prevent
4036 the underlying driver from applying hardware ECC.
4037 @item @code{oob_softecc_kw}
4038 @*File has only page data, which is written.
4039 The OOB area is filled with 0xff, except for a 4-bit software ECC
4040 specific to the boot ROM in Marvell Kirkwood SoCs.
4041 You might need to force raw access to use this mode, to prevent
4042 the underlying driver from applying hardware ECC.
4046 @section Other NAND commands
4047 @cindex NAND other commands
4049 @deffn Command {nand check_bad_blocks} [offset length]
4050 Checks for manufacturer bad block markers on the specified NAND
4051 device. If no parameters are provided, checks the whole
4052 device; otherwise, starts at the specified @var{offset} and
4053 continues for @var{length} bytes.
4054 Both of those values must be exact multiples of the device's
4055 block size, and the region they specify must fit entirely in the chip.
4056 The @var{num} parameter is the value shown by @command{nand list}.
4058 @b{NOTE:} Before using this command you should force raw access
4059 with @command{nand raw_access enable} to ensure that the underlying
4060 driver will not try to apply hardware ECC.
4063 @deffn Command {nand info} num
4064 The @var{num} parameter is the value shown by @command{nand list}.
4065 This prints the one-line summary from "nand list", plus for
4066 devices which have been probed this also prints any known
4067 status for each block.
4070 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4071 Sets or clears an flag affecting how page I/O is done.
4072 The @var{num} parameter is the value shown by @command{nand list}.
4074 This flag is cleared (disabled) by default, but changing that
4075 value won't affect all NAND devices. The key factor is whether
4076 the underlying driver provides @code{read_page} or @code{write_page}
4077 methods. If it doesn't provide those methods, the setting of
4078 this flag is irrelevant; all access is effectively ``raw''.
4080 When those methods exist, they are normally used when reading
4081 data (@command{nand dump} or reading bad block markers) or
4082 writing it (@command{nand write}). However, enabling
4083 raw access (setting the flag) prevents use of those methods,
4084 bypassing hardware ECC logic.
4085 @i{This can be a dangerous option}, since writing blocks
4086 with the wrong ECC data can cause them to be marked as bad.
4089 @anchor{NAND Driver List}
4090 @section NAND Drivers, Options, and Commands
4091 As noted above, the @command{nand device} command allows
4092 driver-specific options and behaviors.
4093 Some controllers also activate controller-specific commands.
4095 @deffn {NAND Driver} davinci
4096 This driver handles the NAND controllers found on DaVinci family
4097 chips from Texas Instruments.
4098 It takes three extra parameters:
4099 address of the NAND chip;
4100 hardware ECC mode to use (@option{hwecc1},
4101 @option{hwecc4}, @option{hwecc4_infix});
4102 address of the AEMIF controller on this processor.
4104 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4106 All DaVinci processors support the single-bit ECC hardware,
4107 and newer ones also support the four-bit ECC hardware.
4108 The @code{write_page} and @code{read_page} methods are used
4109 to implement those ECC modes, unless they are disabled using
4110 the @command{nand raw_access} command.
4113 @deffn {NAND Driver} lpc3180
4114 These controllers require an extra @command{nand device}
4115 parameter: the clock rate used by the controller.
4116 @deffn Command {lpc3180 select} num [mlc|slc]
4117 Configures use of the MLC or SLC controller mode.
4118 MLC implies use of hardware ECC.
4119 The @var{num} parameter is the value shown by @command{nand list}.
4122 At this writing, this driver includes @code{write_page}
4123 and @code{read_page} methods. Using @command{nand raw_access}
4124 to disable those methods will prevent use of hardware ECC
4125 in the MLC controller mode, but won't change SLC behavior.
4127 @comment current lpc3180 code won't issue 5-byte address cycles
4129 @deffn {NAND Driver} orion
4130 These controllers require an extra @command{nand device}
4131 parameter: the address of the controller.
4133 nand device orion 0xd8000000
4135 These controllers don't define any specialized commands.
4136 At this writing, their drivers don't include @code{write_page}
4137 or @code{read_page} methods, so @command{nand raw_access} won't
4138 change any behavior.
4141 @deffn {NAND Driver} s3c2410
4142 @deffnx {NAND Driver} s3c2412
4143 @deffnx {NAND Driver} s3c2440
4144 @deffnx {NAND Driver} s3c2443
4145 These S3C24xx family controllers don't have any special
4146 @command{nand device} options, and don't define any
4147 specialized commands.
4148 At this writing, their drivers don't include @code{write_page}
4149 or @code{read_page} methods, so @command{nand raw_access} won't
4150 change any behavior.
4153 @node PLD/FPGA Commands
4154 @chapter PLD/FPGA Commands
4158 Programmable Logic Devices (PLDs) and the more flexible
4159 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4160 OpenOCD can support programming them.
4161 Although PLDs are generally restrictive (cells are less functional, and
4162 there are no special purpose cells for memory or computational tasks),
4163 they share the same OpenOCD infrastructure.
4164 Accordingly, both are called PLDs here.
4166 @section PLD/FPGA Configuration and Commands
4168 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4169 OpenOCD maintains a list of PLDs available for use in various commands.
4170 Also, each such PLD requires a driver.
4172 They are referenced by the number shown by the @command{pld devices} command,
4173 and new PLDs are defined by @command{pld device driver_name}.
4175 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4176 Defines a new PLD device, supported by driver @var{driver_name},
4177 using the TAP named @var{tap_name}.
4178 The driver may make use of any @var{driver_options} to configure its
4182 @deffn {Command} {pld devices}
4183 Lists the PLDs and their numbers.
4186 @deffn {Command} {pld load} num filename
4187 Loads the file @file{filename} into the PLD identified by @var{num}.
4188 The file format must be inferred by the driver.
4191 @section PLD/FPGA Drivers, Options, and Commands
4193 Drivers may support PLD-specific options to the @command{pld device}
4194 definition command, and may also define commands usable only with
4195 that particular type of PLD.
4197 @deffn {FPGA Driver} virtex2
4198 Virtex-II is a family of FPGAs sold by Xilinx.
4199 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4200 No driver-specific PLD definition options are used,
4201 and one driver-specific command is defined.
4203 @deffn {Command} {virtex2 read_stat} num
4204 Reads and displays the Virtex-II status register (STAT)
4209 @node General Commands
4210 @chapter General Commands
4213 The commands documented in this chapter here are common commands that
4214 you, as a human, may want to type and see the output of. Configuration type
4215 commands are documented elsewhere.
4219 @item @b{Source Of Commands}
4220 @* OpenOCD commands can occur in a configuration script (discussed
4221 elsewhere) or typed manually by a human or supplied programatically,
4222 or via one of several TCP/IP Ports.
4224 @item @b{From the human}
4225 @* A human should interact with the telnet interface (default port: 4444)
4226 or via GDB (default port 3333).
4228 To issue commands from within a GDB session, use the @option{monitor}
4229 command, e.g. use @option{monitor poll} to issue the @option{poll}
4230 command. All output is relayed through the GDB session.
4232 @item @b{Machine Interface}
4233 The Tcl interface's intent is to be a machine interface. The default Tcl
4238 @section Daemon Commands
4240 @deffn {Command} exit
4241 Exits the current telnet session.
4244 @c note EXTREMELY ANNOYING word wrap at column 75
4245 @c even when lines are e.g. 100+ columns ...
4246 @c coded in startup.tcl
4247 @deffn {Command} help [string]
4248 With no parameters, prints help text for all commands.
4249 Otherwise, prints each helptext containing @var{string}.
4250 Not every command provides helptext.
4253 @deffn Command sleep msec [@option{busy}]
4254 Wait for at least @var{msec} milliseconds before resuming.
4255 If @option{busy} is passed, busy-wait instead of sleeping.
4256 (This option is strongly discouraged.)
4257 Useful in connection with script files
4258 (@command{script} command and @command{target_name} configuration).
4261 @deffn Command shutdown
4262 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4265 @anchor{debug_level}
4266 @deffn Command debug_level [n]
4267 @cindex message level
4268 Display debug level.
4269 If @var{n} (from 0..3) is provided, then set it to that level.
4270 This affects the kind of messages sent to the server log.
4271 Level 0 is error messages only;
4272 level 1 adds warnings;
4273 level 2 adds informational messages;
4274 and level 3 adds debugging messages.
4275 The default is level 2, but that can be overridden on
4276 the command line along with the location of that log
4277 file (which is normally the server's standard output).
4281 @deffn Command fast (@option{enable}|@option{disable})
4283 Set default behaviour of OpenOCD to be "fast and dangerous".
4285 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4286 fast memory access, and DCC downloads. Those parameters may still be
4287 individually overridden.
4289 The target specific "dangerous" optimisation tweaking options may come and go
4290 as more robust and user friendly ways are found to ensure maximum throughput
4291 and robustness with a minimum of configuration.
4293 Typically the "fast enable" is specified first on the command line:
4296 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4300 @deffn Command echo message
4301 Logs a message at "user" priority.
4302 Output @var{message} to stdout.
4304 echo "Downloading kernel -- please wait"
4308 @deffn Command log_output [filename]
4309 Redirect logging to @var{filename};
4310 the initial log output channel is stderr.
4313 @anchor{Target State handling}
4314 @section Target State handling
4317 @cindex target initialization
4319 In this section ``target'' refers to a CPU configured as
4320 shown earlier (@pxref{CPU Configuration}).
4321 These commands, like many, implicitly refer to
4322 a current target which is used to perform the
4323 various operations. The current target may be changed
4324 by using @command{targets} command with the name of the
4325 target which should become current.
4327 @deffn Command reg [(number|name) [value]]
4328 Access a single register by @var{number} or by its @var{name}.
4330 @emph{With no arguments}:
4331 list all available registers for the current target,
4332 showing number, name, size, value, and cache status.
4334 @emph{With number/name}: display that register's value.
4336 @emph{With both number/name and value}: set register's value.
4338 Cores may have surprisingly many registers in their
4339 Debug and trace infrastructure:
4343 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4344 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4345 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4347 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4348 0x00000000 (dirty: 0, valid: 0)
4353 @deffn Command halt [ms]
4354 @deffnx Command wait_halt [ms]
4355 The @command{halt} command first sends a halt request to the target,
4356 which @command{wait_halt} doesn't.
4357 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4358 or 5 seconds if there is no parameter, for the target to halt
4359 (and enter debug mode).
4360 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4363 On ARM cores, software using the @emph{wait for interrupt} operation
4364 often blocks the JTAG access needed by a @command{halt} command.
4365 This is because that operation also puts the core into a low
4366 power mode by gating the core clock;
4367 but the core clock is needed to detect JTAG clock transitions.
4369 One partial workaround uses adaptive clocking: when the core is
4370 interrupted the operation completes, then JTAG clocks are accepted
4371 at least until the interrupt handler completes.
4372 However, this workaround is often unusable since the processor, board,
4373 and JTAG adapter must all support adaptive JTAG clocking.
4374 Also, it can't work until an interrupt is issued.
4376 A more complete workaround is to not use that operation while you
4377 work with a JTAG debugger.
4378 Tasking environments generaly have idle loops where the body is the
4379 @emph{wait for interrupt} operation.
4380 (On older cores, it is a coprocessor action;
4381 newer cores have a @option{wfi} instruction.)
4382 Such loops can just remove that operation, at the cost of higher
4383 power consumption (because the CPU is needlessly clocked).
4388 @deffn Command resume [address]
4389 Resume the target at its current code position,
4390 or the optional @var{address} if it is provided.
4391 OpenOCD will wait 5 seconds for the target to resume.
4394 @deffn Command step [address]
4395 Single-step the target at its current code position,
4396 or the optional @var{address} if it is provided.
4399 @anchor{Reset Command}
4400 @deffn Command reset
4401 @deffnx Command {reset run}
4402 @deffnx Command {reset halt}
4403 @deffnx Command {reset init}
4404 Perform as hard a reset as possible, using SRST if possible.
4405 @emph{All defined targets will be reset, and target
4406 events will fire during the reset sequence.}
4408 The optional parameter specifies what should
4409 happen after the reset.
4410 If there is no parameter, a @command{reset run} is executed.
4411 The other options will not work on all systems.
4412 @xref{Reset Configuration}.
4415 @item @b{run} Let the target run
4416 @item @b{halt} Immediately halt the target
4417 @item @b{init} Immediately halt the target, and execute the reset-init script
4421 @deffn Command soft_reset_halt
4422 Requesting target halt and executing a soft reset. This is often used
4423 when a target cannot be reset and halted. The target, after reset is
4424 released begins to execute code. OpenOCD attempts to stop the CPU and
4425 then sets the program counter back to the reset vector. Unfortunately
4426 the code that was executed may have left the hardware in an unknown
4430 @section I/O Utilities
4432 These commands are available when
4433 OpenOCD is built with @option{--enable-ioutil}.
4434 They are mainly useful on embedded targets,
4436 Hosts with operating systems have complementary tools.
4438 @emph{Note:} there are several more such commands.
4440 @deffn Command append_file filename [string]*
4441 Appends the @var{string} parameters to
4442 the text file @file{filename}.
4443 Each string except the last one is followed by one space.
4444 The last string is followed by a newline.
4447 @deffn Command cat filename
4448 Reads and displays the text file @file{filename}.
4451 @deffn Command cp src_filename dest_filename
4452 Copies contents from the file @file{src_filename}
4453 into @file{dest_filename}.
4457 @emph{No description provided.}
4461 @emph{No description provided.}
4465 @emph{No description provided.}
4468 @deffn Command meminfo
4469 Display available RAM memory on OpenOCD host.
4470 Used in OpenOCD regression testing scripts.
4474 @emph{No description provided.}
4478 @emph{No description provided.}
4481 @deffn Command rm filename
4482 @c "rm" has both normal and Jim-level versions??
4483 Unlinks the file @file{filename}.
4486 @deffn Command trunc filename
4487 Removes all data in the file @file{filename}.
4490 @anchor{Memory access}
4491 @section Memory access commands
4492 @cindex memory access
4494 These commands allow accesses of a specific size to the memory
4495 system. Often these are used to configure the current target in some
4496 special way. For example - one may need to write certain values to the
4497 SDRAM controller to enable SDRAM.
4500 @item Use the @command{targets} (plural) command
4501 to change the current target.
4502 @item In system level scripts these commands are deprecated.
4503 Please use their TARGET object siblings to avoid making assumptions
4504 about what TAP is the current target, or about MMU configuration.
4507 @deffn Command mdw addr [count]
4508 @deffnx Command mdh addr [count]
4509 @deffnx Command mdb addr [count]
4510 Display contents of address @var{addr}, as
4511 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4512 or 8-bit bytes (@command{mdb}).
4513 If @var{count} is specified, displays that many units.
4514 (If you want to manipulate the data instead of displaying it,
4515 see the @code{mem2array} primitives.)
4518 @deffn Command mww addr word
4519 @deffnx Command mwh addr halfword
4520 @deffnx Command mwb addr byte
4521 Writes the specified @var{word} (32 bits),
4522 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4523 at the specified address @var{addr}.
4527 @anchor{Image access}
4528 @section Image loading commands
4529 @cindex image loading
4530 @cindex image dumping
4533 @deffn Command {dump_image} filename address size
4534 Dump @var{size} bytes of target memory starting at @var{address} to the
4535 binary file named @var{filename}.
4538 @deffn Command {fast_load}
4539 Loads an image stored in memory by @command{fast_load_image} to the
4540 current target. Must be preceeded by fast_load_image.
4543 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4544 Normally you should be using @command{load_image} or GDB load. However, for
4545 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4546 host), storing the image in memory and uploading the image to the target
4547 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4548 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4549 memory, i.e. does not affect target. This approach is also useful when profiling
4550 target programming performance as I/O and target programming can easily be profiled
4555 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4556 Load image from file @var{filename} to target memory at @var{address}.
4557 The file format may optionally be specified
4558 (@option{bin}, @option{ihex}, or @option{elf})
4561 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4562 Displays image section sizes and addresses
4563 as if @var{filename} were loaded into target memory
4564 starting at @var{address} (defaults to zero).
4565 The file format may optionally be specified
4566 (@option{bin}, @option{ihex}, or @option{elf})
4569 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4570 Verify @var{filename} against target memory starting at @var{address}.
4571 The file format may optionally be specified
4572 (@option{bin}, @option{ihex}, or @option{elf})
4573 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4577 @section Breakpoint and Watchpoint commands
4581 CPUs often make debug modules accessible through JTAG, with
4582 hardware support for a handful of code breakpoints and data
4584 In addition, CPUs almost always support software breakpoints.
4586 @deffn Command {bp} [address len [@option{hw}]]
4587 With no parameters, lists all active breakpoints.
4588 Else sets a breakpoint on code execution starting
4589 at @var{address} for @var{length} bytes.
4590 This is a software breakpoint, unless @option{hw} is specified
4591 in which case it will be a hardware breakpoint.
4593 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4594 for similar mechanisms that do not consume hardware breakpoints.)
4597 @deffn Command {rbp} address
4598 Remove the breakpoint at @var{address}.
4601 @deffn Command {rwp} address
4602 Remove data watchpoint on @var{address}
4605 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4606 With no parameters, lists all active watchpoints.
4607 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4608 The watch point is an "access" watchpoint unless
4609 the @option{r} or @option{w} parameter is provided,
4610 defining it as respectively a read or write watchpoint.
4611 If a @var{value} is provided, that value is used when determining if
4612 the watchpoint should trigger. The value may be first be masked
4613 using @var{mask} to mark ``don't care'' fields.
4616 @section Misc Commands
4619 @deffn Command {profile} seconds filename
4620 Profiling samples the CPU's program counter as quickly as possible,
4621 which is useful for non-intrusive stochastic profiling.
4622 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4625 @deffn Command {version}
4626 Displays a string identifying the version of this OpenOCD server.
4629 @deffn Command {virt2phys} virtual_address
4630 Requests the current target to map the specified @var{virtual_address}
4631 to its corresponding physical address, and displays the result.
4634 @node Architecture and Core Commands
4635 @chapter Architecture and Core Commands
4636 @cindex Architecture Specific Commands
4637 @cindex Core Specific Commands
4639 Most CPUs have specialized JTAG operations to support debugging.
4640 OpenOCD packages most such operations in its standard command framework.
4641 Some of those operations don't fit well in that framework, so they are
4642 exposed here as architecture or implementation (core) specific commands.
4644 @anchor{ARM Hardware Tracing}
4645 @section ARM Hardware Tracing
4650 CPUs based on ARM cores may include standard tracing interfaces,
4651 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4652 address and data bus trace records to a ``Trace Port''.
4656 Development-oriented boards will sometimes provide a high speed
4657 trace connector for collecting that data, when the particular CPU
4658 supports such an interface.
4659 (The standard connector is a 38-pin Mictor, with both JTAG
4660 and trace port support.)
4661 Those trace connectors are supported by higher end JTAG adapters
4662 and some logic analyzer modules; frequently those modules can
4663 buffer several megabytes of trace data.
4664 Configuring an ETM coupled to such an external trace port belongs
4665 in the board-specific configuration file.
4667 If the CPU doesn't provide an external interface, it probably
4668 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4669 dedicated SRAM. 4KBytes is one common ETB size.
4670 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4671 (target) configuration file, since it works the same on all boards.
4674 ETM support in OpenOCD doesn't seem to be widely used yet.
4677 ETM support may be buggy, and at least some @command{etm config}
4678 parameters should be detected by asking the ETM for them.
4679 It seems like a GDB hookup should be possible,
4680 as well as triggering trace on specific events
4681 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4682 There should be GUI tools to manipulate saved trace data and help
4683 analyse it in conjunction with the source code.
4684 It's unclear how much of a common interface is shared
4685 with the current XScale trace support, or should be
4686 shared with eventual Nexus-style trace module support.
4689 @subsection ETM Configuration
4690 ETM setup is coupled with the trace port driver configuration.
4692 @deffn {Config Command} {etm config} target width mode clocking driver
4693 Declares the ETM associated with @var{target}, and associates it
4694 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4696 Several of the parameters must reflect the trace port configuration.
4697 The @var{width} must be either 4, 8, or 16.
4698 The @var{mode} must be @option{normal}, @option{multiplexted},
4699 or @option{demultiplexted}.
4700 The @var{clocking} must be @option{half} or @option{full}.
4703 You can see the ETM registers using the @command{reg} command, although
4704 not all of those possible registers are present in every ETM.
4708 @deffn Command {etm info}
4709 Displays information about the current target's ETM.
4712 @deffn Command {etm status}
4713 Displays status of the current target's ETM:
4714 is the ETM idle, or is it collecting data?
4715 Did trace data overflow?
4719 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4720 Displays what data that ETM will collect.
4721 If arguments are provided, first configures that data.
4722 When the configuration changes, tracing is stopped
4723 and any buffered trace data is invalidated.
4726 @item @var{type} ... one of
4727 @option{none} (save nothing),
4728 @option{data} (save data),
4729 @option{address} (save addresses),
4730 @option{all} (save data and addresses)
4731 @item @var{context_id_bits} ... 0, 8, 16, or 32
4732 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4733 @item @var{branch_output} ... @option{enable} or @option{disable}
4737 @deffn Command {etm trigger_percent} percent
4738 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4741 @subsection ETM Trace Operation
4743 After setting up the ETM, you can use it to collect data.
4744 That data can be exported to files for later analysis.
4745 It can also be parsed with OpenOCD, for basic sanity checking.
4747 @deffn Command {etm analyze}
4748 Reads trace data into memory, if it wasn't already present.
4749 Decodes and prints the data that was collected.
4752 @deffn Command {etm dump} filename
4753 Stores the captured trace data in @file{filename}.
4756 @deffn Command {etm image} filename [base_address] [type]
4757 Opens an image file.
4760 @deffn Command {etm load} filename
4761 Loads captured trace data from @file{filename}.
4764 @deffn Command {etm start}
4765 Starts trace data collection.
4768 @deffn Command {etm stop}
4769 Stops trace data collection.
4772 @anchor{Trace Port Drivers}
4773 @subsection Trace Port Drivers
4775 To use an ETM trace port it must be associated with a driver.
4777 @deffn {Trace Port Driver} dummy
4778 Use the @option{dummy} driver if you are configuring an ETM that's
4779 not connected to anything (on-chip ETB or off-chip trace connector).
4780 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4781 any trace data collection.}
4782 @deffn {Config Command} {etm_dummy config} target
4783 Associates the ETM for @var{target} with a dummy driver.
4787 @deffn {Trace Port Driver} etb
4788 Use the @option{etb} driver if you are configuring an ETM
4789 to use on-chip ETB memory.
4790 @deffn {Config Command} {etb config} target etb_tap
4791 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4792 You can see the ETB registers using the @command{reg} command.
4796 @deffn {Trace Port Driver} oocd_trace
4797 This driver isn't available unless OpenOCD was explicitly configured
4798 with the @option{--enable-oocd_trace} option. You probably don't want
4799 to configure it unless you've built the appropriate prototype hardware;
4800 it's @emph{proof-of-concept} software.
4802 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4803 connected to an off-chip trace connector.
4805 @deffn {Config Command} {oocd_trace config} target tty
4806 Associates the ETM for @var{target} with a trace driver which
4807 collects data through the serial port @var{tty}.
4810 @deffn Command {oocd_trace resync}
4811 Re-synchronizes with the capture clock.
4814 @deffn Command {oocd_trace status}
4815 Reports whether the capture clock is locked or not.
4820 @section ARMv4 and ARMv5 Architecture
4824 These commands are specific to ARM architecture v4 and v5,
4825 including all ARM7 or ARM9 systems and Intel XScale.
4826 They are available in addition to other core-specific
4827 commands that may be available.
4829 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4830 Displays the core_state, optionally changing it to process
4831 either @option{arm} or @option{thumb} instructions.
4832 The target may later be resumed in the currently set core_state.
4833 (Processors may also support the Jazelle state, but
4834 that is not currently supported in OpenOCD.)
4837 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
4839 Disassembles @var{count} instructions starting at @var{address}.
4840 If @var{count} is not specified, a single instruction is disassembled.
4841 If @option{thumb} is specified, or the low bit of the address is set,
4842 Thumb (16-bit) instructions are used;
4843 else ARM (32-bit) instructions are used.
4844 (Processors may also support the Jazelle state, but
4845 those instructions are not currently understood by OpenOCD.)
4848 @deffn Command {armv4_5 reg}
4849 Display a table of all banked core registers, fetching the current value from every
4850 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4854 @subsection ARM7 and ARM9 specific commands
4858 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4859 ARM9TDMI, ARM920T or ARM926EJ-S.
4860 They are available in addition to the ARMv4/5 commands,
4861 and any other core-specific commands that may be available.
4863 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4864 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4865 instead of breakpoints. This should be
4866 safe for all but ARM7TDMI--S cores (like Philips LPC).
4867 This feature is enabled by default on most ARM9 cores,
4868 including ARM9TDMI, ARM920T, and ARM926EJ-S.
4871 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4873 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4874 amounts of memory. DCC downloads offer a huge speed increase, but might be
4875 unsafe, especially with targets running at very low speeds. This command was introduced
4876 with OpenOCD rev. 60, and requires a few bytes of working area.
4879 @anchor{arm7_9 fast_memory_access}
4880 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4881 Enable or disable memory writes and reads that don't check completion of
4882 the operation. This provides a huge speed increase, especially with USB JTAG
4883 cables (FT2232), but might be unsafe if used with targets running at very low
4884 speeds, like the 32kHz startup clock of an AT91RM9200.
4887 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4888 @emph{This is intended for use while debugging OpenOCD; you probably
4891 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4892 as used in the specified @var{mode}
4893 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4894 the M4..M0 bits of the PSR).
4895 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4896 Register 16 is the mode-specific SPSR,
4897 unless the specified mode is 0xffffffff (32-bit all-ones)
4898 in which case register 16 is the CPSR.
4899 The write goes directly to the CPU, bypassing the register cache.
4902 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4903 @emph{This is intended for use while debugging OpenOCD; you probably
4906 If the second parameter is zero, writes @var{word} to the
4907 Current Program Status register (CPSR).
4908 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4909 In both cases, this bypasses the register cache.
4912 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4913 @emph{This is intended for use while debugging OpenOCD; you probably
4916 Writes eight bits to the CPSR or SPSR,
4917 first rotating them by @math{2*rotate} bits,
4918 and bypassing the register cache.
4919 This has lower JTAG overhead than writing the entire CPSR or SPSR
4920 with @command{arm7_9 write_xpsr}.
4923 @subsection ARM720T specific commands
4926 These commands are available to ARM720T based CPUs,
4927 which are implementations of the ARMv4T architecture
4928 based on the ARM7TDMI-S integer core.
4929 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4931 @deffn Command {arm720t cp15} regnum [value]
4932 Display cp15 register @var{regnum};
4933 else if a @var{value} is provided, that value is written to that register.
4936 @deffn Command {arm720t mdw_phys} addr [count]
4937 @deffnx Command {arm720t mdh_phys} addr [count]
4938 @deffnx Command {arm720t mdb_phys} addr [count]
4939 Display contents of physical address @var{addr}, as
4940 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4941 or 8-bit bytes (@command{mdb_phys}).
4942 If @var{count} is specified, displays that many units.
4945 @deffn Command {arm720t mww_phys} addr word
4946 @deffnx Command {arm720t mwh_phys} addr halfword
4947 @deffnx Command {arm720t mwb_phys} addr byte
4948 Writes the specified @var{word} (32 bits),
4949 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4950 at the specified physical address @var{addr}.
4953 @deffn Command {arm720t virt2phys} va
4954 Translate a virtual address @var{va} to a physical address
4955 and display the result.
4958 @subsection ARM9 specific commands
4961 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
4963 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4965 For historical reasons, one command shared by these cores starts
4966 with the @command{arm9tdmi} prefix.
4967 This is true even for ARM9E based processors, which implement the
4968 ARMv5TE architecture instead of ARMv4T.
4970 @c 9-june-2009: tried this on arm920t, it didn't work.
4971 @c no-params always lists nothing caught, and that's how it acts.
4973 @anchor{arm9tdmi vector_catch}
4974 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
4975 @cindex vector_catch
4976 Vector Catch hardware provides a sort of dedicated breakpoint
4977 for hardware events such as reset, interrupt, and abort.
4978 You can use this to conserve normal breakpoint resources,
4979 so long as you're not concerned with code that branches directly
4980 to those hardware vectors.
4982 This always finishes by listing the current configuration.
4983 If parameters are provided, it first reconfigures the
4984 vector catch hardware to intercept
4985 @option{all} of the hardware vectors,
4986 @option{none} of them,
4987 or a list with one or more of the following:
4988 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4989 @option{irq} @option{fiq}.
4992 @subsection ARM920T specific commands
4995 These commands are available to ARM920T based CPUs,
4996 which are implementations of the ARMv4T architecture
4997 built using the ARM9TDMI integer core.
4998 They are available in addition to the ARMv4/5, ARM7/ARM9,
4999 and ARM9TDMI commands.
5001 @deffn Command {arm920t cache_info}
5002 Print information about the caches found. This allows to see whether your target
5003 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5006 @deffn Command {arm920t cp15} regnum [value]
5007 Display cp15 register @var{regnum};
5008 else if a @var{value} is provided, that value is written to that register.
5011 @deffn Command {arm920t cp15i} opcode [value [address]]
5012 Interpreted access using cp15 @var{opcode}.
5013 If no @var{value} is provided, the result is displayed.
5014 Else if that value is written using the specified @var{address},
5015 or using zero if no other address is not provided.
5018 @deffn Command {arm920t mdw_phys} addr [count]
5019 @deffnx Command {arm920t mdh_phys} addr [count]
5020 @deffnx Command {arm920t mdb_phys} addr [count]
5021 Display contents of physical address @var{addr}, as
5022 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5023 or 8-bit bytes (@command{mdb_phys}).
5024 If @var{count} is specified, displays that many units.
5027 @deffn Command {arm920t mww_phys} addr word
5028 @deffnx Command {arm920t mwh_phys} addr halfword
5029 @deffnx Command {arm920t mwb_phys} addr byte
5030 Writes the specified @var{word} (32 bits),
5031 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5032 at the specified physical address @var{addr}.
5035 @deffn Command {arm920t read_cache} filename
5036 Dump the content of ICache and DCache to a file named @file{filename}.
5039 @deffn Command {arm920t read_mmu} filename
5040 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5043 @deffn Command {arm920t virt2phys} va
5044 Translate a virtual address @var{va} to a physical address
5045 and display the result.
5048 @subsection ARM926ej-s specific commands
5051 These commands are available to ARM926ej-s based CPUs,
5052 which are implementations of the ARMv5TEJ architecture
5053 based on the ARM9EJ-S integer core.
5054 They are available in addition to the ARMv4/5, ARM7/ARM9,
5055 and ARM9TDMI commands.
5057 The Feroceon cores also support these commands, although
5058 they are not built from ARM926ej-s designs.
5060 @deffn Command {arm926ejs cache_info}
5061 Print information about the caches found.
5064 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5065 Accesses cp15 register @var{regnum} using
5066 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5067 If a @var{value} is provided, that value is written to that register.
5068 Else that register is read and displayed.
5071 @deffn Command {arm926ejs mdw_phys} addr [count]
5072 @deffnx Command {arm926ejs mdh_phys} addr [count]
5073 @deffnx Command {arm926ejs mdb_phys} addr [count]
5074 Display contents of physical address @var{addr}, as
5075 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5076 or 8-bit bytes (@command{mdb_phys}).
5077 If @var{count} is specified, displays that many units.
5080 @deffn Command {arm926ejs mww_phys} addr word
5081 @deffnx Command {arm926ejs mwh_phys} addr halfword
5082 @deffnx Command {arm926ejs mwb_phys} addr byte
5083 Writes the specified @var{word} (32 bits),
5084 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5085 at the specified physical address @var{addr}.
5088 @deffn Command {arm926ejs virt2phys} va
5089 Translate a virtual address @var{va} to a physical address
5090 and display the result.
5093 @subsection ARM966E specific commands
5096 These commands are available to ARM966 based CPUs,
5097 which are implementations of the ARMv5TE architecture.
5098 They are available in addition to the ARMv4/5, ARM7/ARM9,
5099 and ARM9TDMI commands.
5101 @deffn Command {arm966e cp15} regnum [value]
5102 Display cp15 register @var{regnum};
5103 else if a @var{value} is provided, that value is written to that register.
5106 @subsection XScale specific commands
5109 Some notes about the debug implementation on the XScale CPUs:
5111 The XScale CPU provides a special debug-only mini-instruction cache
5112 (mini-IC) in which exception vectors and target-resident debug handler
5113 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5114 must point vector 0 (the reset vector) to the entry of the debug
5115 handler. However, this means that the complete first cacheline in the
5116 mini-IC is marked valid, which makes the CPU fetch all exception
5117 handlers from the mini-IC, ignoring the code in RAM.
5119 OpenOCD currently does not sync the mini-IC entries with the RAM
5120 contents (which would fail anyway while the target is running), so
5121 the user must provide appropriate values using the @code{xscale
5122 vector_table} command.
5124 It is recommended to place a pc-relative indirect branch in the vector
5125 table, and put the branch destination somewhere in memory. Doing so
5126 makes sure the code in the vector table stays constant regardless of
5127 code layout in memory:
5130 ldr pc,[pc,#0x100-8]
5131 ldr pc,[pc,#0x100-8]
5132 ldr pc,[pc,#0x100-8]
5133 ldr pc,[pc,#0x100-8]
5134 ldr pc,[pc,#0x100-8]
5135 ldr pc,[pc,#0x100-8]
5136 ldr pc,[pc,#0x100-8]
5137 ldr pc,[pc,#0x100-8]
5139 .long real_reset_vector
5140 .long real_ui_handler
5141 .long real_swi_handler
5143 .long real_data_abort
5144 .long 0 /* unused */
5145 .long real_irq_handler
5146 .long real_fiq_handler
5149 The debug handler must be placed somewhere in the address space using
5150 the @code{xscale debug_handler} command. The allowed locations for the
5151 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5152 0xfffff800). The default value is 0xfe000800.
5155 These commands are available to XScale based CPUs,
5156 which are implementations of the ARMv5TE architecture.
5158 @deffn Command {xscale analyze_trace}
5159 Displays the contents of the trace buffer.
5162 @deffn Command {xscale cache_clean_address} address
5163 Changes the address used when cleaning the data cache.
5166 @deffn Command {xscale cache_info}
5167 Displays information about the CPU caches.
5170 @deffn Command {xscale cp15} regnum [value]
5171 Display cp15 register @var{regnum};
5172 else if a @var{value} is provided, that value is written to that register.
5175 @deffn Command {xscale debug_handler} target address
5176 Changes the address used for the specified target's debug handler.
5179 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5180 Enables or disable the CPU's data cache.
5183 @deffn Command {xscale dump_trace} filename
5184 Dumps the raw contents of the trace buffer to @file{filename}.
5187 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5188 Enables or disable the CPU's instruction cache.
5191 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5192 Enables or disable the CPU's memory management unit.
5195 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5196 Enables or disables the trace buffer,
5197 and controls how it is emptied.
5200 @deffn Command {xscale trace_image} filename [offset [type]]
5201 Opens a trace image from @file{filename}, optionally rebasing
5202 its segment addresses by @var{offset}.
5203 The image @var{type} may be one of
5204 @option{bin} (binary), @option{ihex} (Intel hex),
5205 @option{elf} (ELF file), @option{s19} (Motorola s19),
5206 @option{mem}, or @option{builder}.
5209 @anchor{xscale vector_catch}
5210 @deffn Command {xscale vector_catch} [mask]
5211 @cindex vector_catch
5212 Display a bitmask showing the hardware vectors to catch.
5213 If the optional parameter is provided, first set the bitmask to that value.
5215 The mask bits correspond with bit 16..23 in the DCSR:
5218 0x02 Trap Undefined Instructions
5219 0x04 Trap Software Interrupt
5220 0x08 Trap Prefetch Abort
5221 0x10 Trap Data Abort
5228 @anchor{xscale vector_table}
5229 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5230 @cindex vector_table
5232 Set an entry in the mini-IC vector table. There are two tables: one for
5233 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5234 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5235 points to the debug handler entry and can not be overwritten.
5236 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5238 Without arguments, the current settings are displayed.
5242 @section ARMv6 Architecture
5245 @subsection ARM11 specific commands
5248 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5249 Write @var{value} to a coprocessor @var{pX} register
5250 passing parameters @var{CRn},
5251 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5252 and the MCR instruction.
5253 (The difference beween this and the MCR2 instruction is
5254 one bit in the encoding, effecively a fifth parameter.)
5257 @deffn Command {arm11 memwrite burst} [value]
5258 Displays the value of the memwrite burst-enable flag,
5259 which is enabled by default.
5260 If @var{value} is defined, first assigns that.
5263 @deffn Command {arm11 memwrite error_fatal} [value]
5264 Displays the value of the memwrite error_fatal flag,
5265 which is enabled by default.
5266 If @var{value} is defined, first assigns that.
5269 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5270 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5271 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5272 and the MRC instruction.
5273 (The difference beween this and the MRC2 instruction is
5274 one bit in the encoding, effecively a fifth parameter.)
5275 Displays the result.
5278 @deffn Command {arm11 no_increment} [value]
5279 Displays the value of the flag controlling whether
5280 some read or write operations increment the pointer
5281 (the default behavior) or not (acting like a FIFO).
5282 If @var{value} is defined, first assigns that.
5285 @deffn Command {arm11 step_irq_enable} [value]
5286 Displays the value of the flag controlling whether
5287 IRQs are enabled during single stepping;
5288 they is disabled by default.
5289 If @var{value} is defined, first assigns that.
5292 @section ARMv7 Architecture
5295 @subsection ARMv7 Debug Access Port (DAP) specific commands
5296 @cindex Debug Access Port
5298 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5299 included on cortex-m3 and cortex-a8 systems.
5300 They are available in addition to other core-specific commands that may be available.
5302 @deffn Command {dap info} [num]
5303 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5306 @deffn Command {dap apsel} [num]
5307 Select AP @var{num}, defaulting to 0.
5310 @deffn Command {dap apid} [num]
5311 Displays id register from AP @var{num},
5312 defaulting to the currently selected AP.
5315 @deffn Command {dap baseaddr} [num]
5316 Displays debug base address from AP @var{num},
5317 defaulting to the currently selected AP.
5320 @deffn Command {dap memaccess} [value]
5321 Displays the number of extra tck for mem-ap memory bus access [0-255].
5322 If @var{value} is defined, first assigns that.
5325 @subsection ARMv7-A specific commands
5328 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5330 Disassembles @var{count} instructions starting at @var{address}.
5331 If @var{count} is not specified, a single instruction is disassembled.
5332 If @option{thumb} is specified, or the low bit of the address is set,
5333 Thumb2 (mixed 16/32-bit) instructions are used;
5334 else ARM (32-bit) instructions are used.
5335 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5336 ThumbEE disassembly currently has no explicit support.
5337 (Processors may also support the Jazelle state, but
5338 those instructions are not currently understood by OpenOCD.)
5342 @subsection Cortex-M3 specific commands
5345 @deffn Command {cortex_m3 disassemble} address [count]
5347 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5348 If @var{count} is not specified, a single instruction is disassembled.
5351 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5352 Control masking (disabling) interrupts during target step/resume.
5355 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5356 @cindex vector_catch
5357 Vector Catch hardware provides dedicated breakpoints
5358 for certain hardware events.
5360 Parameters request interception of
5361 @option{all} of these hardware event vectors,
5362 @option{none} of them,
5363 or one or more of the following:
5364 @option{hard_err} for a HardFault exception;
5365 @option{mm_err} for a MemManage exception;
5366 @option{bus_err} for a BusFault exception;
5369 @option{chk_err}, or
5370 @option{nocp_err} for various UsageFault exceptions; or
5372 If NVIC setup code does not enable them,
5373 MemManage, BusFault, and UsageFault exceptions
5374 are mapped to HardFault.
5375 UsageFault checks for
5376 divide-by-zero and unaligned access
5377 must also be explicitly enabled.
5379 This finishes by listing the current vector catch configuration.
5382 @anchor{Software Debug Messages and Tracing}
5383 @section Software Debug Messages and Tracing
5384 @cindex Linux-ARM DCC support
5388 OpenOCD can process certain requests from target software. Currently
5389 @command{target_request debugmsgs}
5390 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5391 These messages are received as part of target polling, so
5392 you need to have @command{poll on} active to receive them.
5393 They are intrusive in that they will affect program execution
5394 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5396 See @file{libdcc} in the contrib dir for more details.
5397 In addition to sending strings, characters, and
5398 arrays of various size integers from the target,
5399 @file{libdcc} also exports a software trace point mechanism.
5400 The target being debugged may
5401 issue trace messages which include a 24-bit @dfn{trace point} number.
5402 Trace point support includes two distinct mechanisms,
5403 each supported by a command:
5406 @item @emph{History} ... A circular buffer of trace points
5407 can be set up, and then displayed at any time.
5408 This tracks where code has been, which can be invaluable in
5409 finding out how some fault was triggered.
5411 The buffer may overflow, since it collects records continuously.
5412 It may be useful to use some of the 24 bits to represent a
5413 particular event, and other bits to hold data.
5415 @item @emph{Counting} ... An array of counters can be set up,
5416 and then displayed at any time.
5417 This can help establish code coverage and identify hot spots.
5419 The array of counters is directly indexed by the trace point
5420 number, so trace points with higher numbers are not counted.
5423 Linux-ARM kernels have a ``Kernel low-level debugging
5424 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5425 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5426 deliver messages before a serial console can be activated.
5427 This is not the same format used by @file{libdcc}.
5428 Other software, such as the U-Boot boot loader, sometimes
5429 does the same thing.
5431 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5432 Displays current handling of target DCC message requests.
5433 These messages may be sent to the debugger while the target is running.
5434 The optional @option{enable} and @option{charmsg} parameters
5435 both enable the messages, while @option{disable} disables them.
5437 With @option{charmsg} the DCC words each contain one character,
5438 as used by Linux with CONFIG_DEBUG_ICEDCC;
5439 otherwise the libdcc format is used.
5442 @deffn Command {trace history} (@option{clear}|count)
5443 With no parameter, displays all the trace points that have triggered
5444 in the order they triggered.
5445 With the parameter @option{clear}, erases all current trace history records.
5446 With a @var{count} parameter, allocates space for that many
5450 @deffn Command {trace point} (@option{clear}|identifier)
5451 With no parameter, displays all trace point identifiers and how many times
5452 they have been triggered.
5453 With the parameter @option{clear}, erases all current trace point counters.
5454 With a numeric @var{identifier} parameter, creates a new a trace point counter
5455 and associates it with that identifier.
5457 @emph{Important:} The identifier and the trace point number
5458 are not related except by this command.
5459 These trace point numbers always start at zero (from server startup,
5460 or after @command{trace point clear}) and count up from there.
5465 @chapter JTAG Commands
5466 @cindex JTAG Commands
5467 Most general purpose JTAG commands have been presented earlier.
5468 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5469 Lower level JTAG commands, as presented here,
5470 may be needed to work with targets which require special
5471 attention during operations such as reset or initialization.
5473 To use these commands you will need to understand some
5474 of the basics of JTAG, including:
5477 @item A JTAG scan chain consists of a sequence of individual TAP
5478 devices such as a CPUs.
5479 @item Control operations involve moving each TAP through the same
5480 standard state machine (in parallel)
5481 using their shared TMS and clock signals.
5482 @item Data transfer involves shifting data through the chain of
5483 instruction or data registers of each TAP, writing new register values
5484 while the reading previous ones.
5485 @item Data register sizes are a function of the instruction active in
5486 a given TAP, while instruction register sizes are fixed for each TAP.
5487 All TAPs support a BYPASS instruction with a single bit data register.
5488 @item The way OpenOCD differentiates between TAP devices is by
5489 shifting different instructions into (and out of) their instruction
5493 @section Low Level JTAG Commands
5495 These commands are used by developers who need to access
5496 JTAG instruction or data registers, possibly controlling
5497 the order of TAP state transitions.
5498 If you're not debugging OpenOCD internals, or bringing up a
5499 new JTAG adapter or a new type of TAP device (like a CPU or
5500 JTAG router), you probably won't need to use these commands.
5502 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5503 Loads the data register of @var{tap} with a series of bit fields
5504 that specify the entire register.
5505 Each field is @var{numbits} bits long with
5506 a numeric @var{value} (hexadecimal encouraged).
5507 The return value holds the original value of each
5510 For example, a 38 bit number might be specified as one
5511 field of 32 bits then one of 6 bits.
5512 @emph{For portability, never pass fields which are more
5513 than 32 bits long. Many OpenOCD implementations do not
5514 support 64-bit (or larger) integer values.}
5516 All TAPs other than @var{tap} must be in BYPASS mode.
5517 The single bit in their data registers does not matter.
5519 When @var{tap_state} is specified, the JTAG state machine is left
5521 For example @sc{drpause} might be specified, so that more
5522 instructions can be issued before re-entering the @sc{run/idle} state.
5523 If the end state is not specified, the @sc{run/idle} state is entered.
5526 OpenOCD does not record information about data register lengths,
5527 so @emph{it is important that you get the bit field lengths right}.
5528 Remember that different JTAG instructions refer to different
5529 data registers, which may have different lengths.
5530 Moreover, those lengths may not be fixed;
5531 the SCAN_N instruction can change the length of
5532 the register accessed by the INTEST instruction
5533 (by connecting a different scan chain).
5537 @deffn Command {flush_count}
5538 Returns the number of times the JTAG queue has been flushed.
5539 This may be used for performance tuning.
5541 For example, flushing a queue over USB involves a
5542 minimum latency, often several milliseconds, which does
5543 not change with the amount of data which is written.
5544 You may be able to identify performance problems by finding
5545 tasks which waste bandwidth by flushing small transfers too often,
5546 instead of batching them into larger operations.
5549 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5550 For each @var{tap} listed, loads the instruction register
5551 with its associated numeric @var{instruction}.
5552 (The number of bits in that instruction may be displayed
5553 using the @command{scan_chain} command.)
5554 For other TAPs, a BYPASS instruction is loaded.
5556 When @var{tap_state} is specified, the JTAG state machine is left
5558 For example @sc{irpause} might be specified, so the data register
5559 can be loaded before re-entering the @sc{run/idle} state.
5560 If the end state is not specified, the @sc{run/idle} state is entered.
5563 OpenOCD currently supports only a single field for instruction
5564 register values, unlike data register values.
5565 For TAPs where the instruction register length is more than 32 bits,
5566 portable scripts currently must issue only BYPASS instructions.
5570 @deffn Command {jtag_reset} trst srst
5571 Set values of reset signals.
5572 The @var{trst} and @var{srst} parameter values may be
5573 @option{0}, indicating that reset is inactive (pulled or driven high),
5574 or @option{1}, indicating it is active (pulled or driven low).
5575 The @command{reset_config} command should already have been used
5576 to configure how the board and JTAG adapter treat these two
5577 signals, and to say if either signal is even present.
5578 @xref{Reset Configuration}.
5581 @deffn Command {runtest} @var{num_cycles}
5582 Move to the @sc{run/idle} state, and execute at least
5583 @var{num_cycles} of the JTAG clock (TCK).
5584 Instructions often need some time
5585 to execute before they take effect.
5588 @c tms_sequence (short|long)
5589 @c ... temporary, debug-only, probably gone before 0.2 ships
5591 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5592 Verify values captured during @sc{ircapture} and returned
5593 during IR scans. Default is enabled, but this can be
5594 overridden by @command{verify_jtag}.
5597 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5598 Enables verification of DR and IR scans, to help detect
5599 programming errors. For IR scans, @command{verify_ircapture}
5600 must also be enabled.
5604 @section TAP state names
5605 @cindex TAP state names
5607 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5608 and @command{irscan} commands are:
5611 @item @b{RESET} ... should act as if TRST were active
5612 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5615 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5617 @item @b{DRPAUSE} ... data register ready for update or more shifting
5622 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5624 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5629 Note that only six of those states are fully ``stable'' in the
5630 face of TMS fixed (low except for @sc{reset})
5631 and a free-running JTAG clock. For all the
5632 others, the next TCK transition changes to a new state.
5635 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5636 produce side effects by changing register contents. The values
5637 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5638 may not be as expected.
5639 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5640 choices after @command{drscan} or @command{irscan} commands,
5641 since they are free of JTAG side effects.
5642 However, @sc{run/idle} may have side effects that appear at other
5643 levels, such as advancing the ARM9E-S instruction pipeline.
5644 Consult the documentation for the TAP(s) you are working with.
5647 @node Boundary Scan Commands
5648 @chapter Boundary Scan Commands
5650 One of the original purposes of JTAG was to support
5651 boundary scan based hardware testing.
5652 Although its primary focus is to support On-Chip Debugging,
5653 OpenOCD also includes some boundary scan commands.
5655 @section SVF: Serial Vector Format
5656 @cindex Serial Vector Format
5659 The Serial Vector Format, better known as @dfn{SVF}, is a
5660 way to represent JTAG test patterns in text files.
5661 OpenOCD supports running such test files.
5663 @deffn Command {svf} filename [@option{quiet}]
5664 This issues a JTAG reset (Test-Logic-Reset) and then
5665 runs the SVF script from @file{filename}.
5666 Unless the @option{quiet} option is specified,
5667 each command is logged before it is executed.
5670 @section XSVF: Xilinx Serial Vector Format
5671 @cindex Xilinx Serial Vector Format
5674 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5675 binary representation of SVF which is optimized for use with
5677 OpenOCD supports running such test files.
5679 @quotation Important
5680 Not all XSVF commands are supported.
5683 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5684 This issues a JTAG reset (Test-Logic-Reset) and then
5685 runs the XSVF script from @file{filename}.
5686 When a @var{tapname} is specified, the commands are directed at
5688 When @option{virt2} is specified, the @sc{xruntest} command counts
5689 are interpreted as TCK cycles instead of microseconds.
5690 Unless the @option{quiet} option is specified,
5691 messages are logged for comments and some retries.
5697 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5698 be used to access files on PCs (either the developer's PC or some other PC).
5700 The way this works on the ZY1000 is to prefix a filename by
5701 "/tftp/ip/" and append the TFTP path on the TFTP
5702 server (tftpd). For example,
5705 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5708 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5709 if the file was hosted on the embedded host.
5711 In order to achieve decent performance, you must choose a TFTP server
5712 that supports a packet size bigger than the default packet size (512 bytes). There
5713 are numerous TFTP servers out there (free and commercial) and you will have to do
5714 a bit of googling to find something that fits your requirements.
5716 @node GDB and OpenOCD
5717 @chapter GDB and OpenOCD
5719 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5720 to debug remote targets.
5722 @anchor{Connecting to GDB}
5723 @section Connecting to GDB
5724 @cindex Connecting to GDB
5725 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5726 instance GDB 6.3 has a known bug that produces bogus memory access
5727 errors, which has since been fixed: look up 1836 in
5728 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5730 OpenOCD can communicate with GDB in two ways:
5734 A socket (TCP/IP) connection is typically started as follows:
5736 target remote localhost:3333
5738 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5740 A pipe connection is typically started as follows:
5742 target remote | openocd --pipe
5744 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5745 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5749 To list the available OpenOCD commands type @command{monitor help} on the
5752 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5753 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5754 packet size and the device's memory map.
5756 Previous versions of OpenOCD required the following GDB options to increase
5757 the packet size and speed up GDB communication:
5759 set remote memory-write-packet-size 1024
5760 set remote memory-write-packet-size fixed
5761 set remote memory-read-packet-size 1024
5762 set remote memory-read-packet-size fixed
5764 This is now handled in the @option{qSupported} PacketSize and should not be required.
5766 @section Programming using GDB
5767 @cindex Programming using GDB
5769 By default the target memory map is sent to GDB. This can be disabled by
5770 the following OpenOCD configuration option:
5772 gdb_memory_map disable
5774 For this to function correctly a valid flash configuration must also be set
5775 in OpenOCD. For faster performance you should also configure a valid
5778 Informing GDB of the memory map of the target will enable GDB to protect any
5779 flash areas of the target and use hardware breakpoints by default. This means
5780 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5781 using a memory map. @xref{gdb_breakpoint_override}.
5783 To view the configured memory map in GDB, use the GDB command @option{info mem}
5784 All other unassigned addresses within GDB are treated as RAM.
5786 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5787 This can be changed to the old behaviour by using the following GDB command
5789 set mem inaccessible-by-default off
5792 If @command{gdb_flash_program enable} is also used, GDB will be able to
5793 program any flash memory using the vFlash interface.
5795 GDB will look at the target memory map when a load command is given, if any
5796 areas to be programmed lie within the target flash area the vFlash packets
5799 If the target needs configuring before GDB programming, an event
5800 script can be executed:
5802 $_TARGETNAME configure -event EVENTNAME BODY
5805 To verify any flash programming the GDB command @option{compare-sections}
5808 @node Tcl Scripting API
5809 @chapter Tcl Scripting API
5810 @cindex Tcl Scripting API
5814 The commands are stateless. E.g. the telnet command line has a concept
5815 of currently active target, the Tcl API proc's take this sort of state
5816 information as an argument to each proc.
5818 There are three main types of return values: single value, name value
5819 pair list and lists.
5821 Name value pair. The proc 'foo' below returns a name/value pair
5827 > set foo(you) Oyvind
5828 > set foo(mouse) Micky
5829 > set foo(duck) Donald
5837 me Duane you Oyvind mouse Micky duck Donald
5839 Thus, to get the names of the associative array is easy:
5841 foreach { name value } [set foo] {
5842 puts "Name: $name, Value: $value"
5846 Lists returned must be relatively small. Otherwise a range
5847 should be passed in to the proc in question.
5849 @section Internal low-level Commands
5851 By low-level, the intent is a human would not directly use these commands.
5853 Low-level commands are (should be) prefixed with "ocd_", e.g.
5854 @command{ocd_flash_banks}
5855 is the low level API upon which @command{flash banks} is implemented.
5858 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5860 Read memory and return as a Tcl array for script processing
5861 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5863 Convert a Tcl array to memory locations and write the values
5864 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
5866 Return information about the flash banks
5869 OpenOCD commands can consist of two words, e.g. "flash banks". The
5870 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
5871 called "flash_banks".
5873 @section OpenOCD specific Global Variables
5877 Real Tcl has ::tcl_platform(), and platform::identify, and many other
5878 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
5879 holds one of the following values:
5882 @item @b{winxx} Built using Microsoft Visual Studio
5883 @item @b{linux} Linux is the underlying operating sytem
5884 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
5885 @item @b{cygwin} Running under Cygwin
5886 @item @b{mingw32} Running under MingW32
5887 @item @b{other} Unknown, none of the above.
5890 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5893 We should add support for a variable like Tcl variable
5894 @code{tcl_platform(platform)}, it should be called
5895 @code{jim_platform} (because it
5896 is jim, not real tcl).
5900 @chapter Deprecated/Removed Commands
5901 @cindex Deprecated/Removed Commands
5902 Certain OpenOCD commands have been deprecated or
5903 removed during the various revisions.
5905 Upgrade your scripts as soon as possible.
5906 These descriptions for old commands may be removed
5907 a year after the command itself was removed.
5908 This means that in January 2010 this chapter may
5909 become much shorter.
5912 @item @b{arm7_9 fast_writes}
5913 @cindex arm7_9 fast_writes
5914 @*Use @command{arm7_9 fast_memory_access} instead.
5915 @xref{arm7_9 fast_memory_access}.
5918 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5919 @item @b{arm7_9 force_hw_bkpts}
5920 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5921 for flash if the GDB memory map has been set up(default when flash is declared in
5922 target configuration). @xref{gdb_breakpoint_override}.
5923 @item @b{arm7_9 sw_bkpts}
5924 @*On by default. @xref{gdb_breakpoint_override}.
5925 @item @b{daemon_startup}
5926 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5927 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5928 and @option{target cortex_m3 little reset_halt 0}.
5929 @item @b{dump_binary}
5930 @*use @option{dump_image} command with same args. @xref{dump_image}.
5931 @item @b{flash erase}
5932 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5933 @item @b{flash write}
5934 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5935 @item @b{flash write_binary}
5936 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5937 @item @b{flash auto_erase}
5938 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5940 @item @b{jtag_device}
5941 @*use the @command{jtag newtap} command, converting from positional syntax
5942 to named prefixes, and naming the TAP.
5944 Note that if you try to use the old command, a message will tell you the
5945 right new command to use; and that the fourth parameter in the old syntax
5946 was never actually used.
5948 OLD: jtag_device 8 0x01 0xe3 0xfe
5949 NEW: jtag newtap CHIPNAME TAPNAME \
5950 -irlen 8 -ircapture 0x01 -irmask 0xe3
5953 @item @b{jtag_speed} value
5954 @*@xref{JTAG Speed}.
5955 Usually, a value of zero means maximum
5956 speed. The actual effect of this option depends on the JTAG interface used.
5958 @item wiggler: maximum speed / @var{number}
5959 @item ft2232: 6MHz / (@var{number}+1)
5960 @item amt jtagaccel: 8 / 2**@var{number}
5961 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5962 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5963 @comment end speed list.
5966 @item @b{load_binary}
5967 @*use @option{load_image} command with same args. @xref{load_image}.
5968 @item @b{run_and_halt_time}
5969 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5976 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5977 @*use the create subcommand of @option{target}.
5978 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5979 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5980 @item @b{working_area}
5981 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5989 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5991 @cindex adaptive clocking
5994 In digital circuit design it is often refered to as ``clock
5995 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5996 operating at some speed, your target is operating at another. The two
5997 clocks are not synchronised, they are ``asynchronous''
5999 In order for the two to work together they must be synchronised. Otherwise
6000 the two systems will get out of sync with each other and nothing will
6001 work. There are 2 basic options:
6004 Use a special circuit.
6006 One clock must be some multiple slower than the other.
6009 @b{Does this really matter?} For some chips and some situations, this
6010 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6011 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6012 program/enable the oscillators and eventually the main clock. It is in
6013 those critical times you must slow the JTAG clock to sometimes 1 to
6016 Imagine debugging a 500MHz ARM926 hand held battery powered device
6017 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6020 @b{Solution #1 - A special circuit}
6022 In order to make use of this, your JTAG dongle must support the RTCK
6023 feature. Not all dongles support this - keep reading!
6025 The RTCK signal often found in some ARM chips is used to help with
6026 this problem. ARM has a good description of the problem described at
6027 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6028 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6029 work? / how does adaptive clocking work?''.
6031 The nice thing about adaptive clocking is that ``battery powered hand
6032 held device example'' - the adaptiveness works perfectly all the
6033 time. One can set a break point or halt the system in the deep power
6034 down code, slow step out until the system speeds up.
6036 Note that adaptive clocking may also need to work at the board level,
6037 when a board-level scan chain has multiple chips.
6038 Parallel clock voting schemes are good way to implement this,
6039 both within and between chips, and can easily be implemented
6041 It's not difficult to have logic fan a module's input TCK signal out
6042 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6043 back with the right polarity before changing the output RTCK signal.
6044 Texas Instruments makes some clock voting logic available
6045 for free (with no support) in VHDL form; see
6046 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6048 @b{Solution #2 - Always works - but may be slower}
6050 Often this is a perfectly acceptable solution.
6052 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6053 the target clock speed. But what that ``magic division'' is varies
6054 depending on the chips on your board.
6055 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6056 ARM11 cores use an 8:1 division.
6057 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6059 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6061 You can still debug the 'low power' situations - you just need to
6062 manually adjust the clock speed at every step. While painful and
6063 tedious, it is not always practical.
6065 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6066 have a special debug mode in your application that does a ``high power
6067 sleep''. If you are careful - 98% of your problems can be debugged
6070 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6071 operation in your idle loops even if you don't otherwise change the CPU
6073 That operation gates the CPU clock, and thus the JTAG clock; which
6074 prevents JTAG access. One consequence is not being able to @command{halt}
6075 cores which are executing that @emph{wait for interrupt} operation.
6077 To set the JTAG frequency use the command:
6085 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6087 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6088 around Windows filenames.
6101 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6103 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6104 claims to come with all the necessary DLLs. When using Cygwin, try launching
6105 OpenOCD from the Cygwin shell.
6107 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6108 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6109 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6111 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6112 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6113 software breakpoints consume one of the two available hardware breakpoints.
6115 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6117 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6118 clock at the time you're programming the flash. If you've specified the crystal's
6119 frequency, make sure the PLL is disabled. If you've specified the full core speed
6120 (e.g. 60MHz), make sure the PLL is enabled.
6122 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6123 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6124 out while waiting for end of scan, rtck was disabled".
6126 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6127 settings in your PC BIOS (ECP, EPP, and different versions of those).
6129 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6130 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6131 memory read caused data abort".
6133 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6134 beyond the last valid frame. It might be possible to prevent this by setting up
6135 a proper "initial" stack frame, if you happen to know what exactly has to
6136 be done, feel free to add this here.
6138 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6139 stack before calling main(). What GDB is doing is ``climbing'' the run
6140 time stack by reading various values on the stack using the standard
6141 call frame for the target. GDB keeps going - until one of 2 things
6142 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6143 stackframes have been processed. By pushing zeros on the stack, GDB
6146 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6147 your C code, do the same - artifically push some zeros onto the stack,
6148 remember to pop them off when the ISR is done.
6150 @b{Also note:} If you have a multi-threaded operating system, they
6151 often do not @b{in the intrest of saving memory} waste these few
6155 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6156 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6158 This warning doesn't indicate any serious problem, as long as you don't want to
6159 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6160 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6161 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6162 independently. With this setup, it's not possible to halt the core right out of
6163 reset, everything else should work fine.
6165 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6166 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6167 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6168 quit with an error message. Is there a stability issue with OpenOCD?
6170 No, this is not a stability issue concerning OpenOCD. Most users have solved
6171 this issue by simply using a self-powered USB hub, which they connect their
6172 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6173 supply stable enough for the Amontec JTAGkey to be operated.
6175 @b{Laptops running on battery have this problem too...}
6177 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6178 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6179 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6180 What does that mean and what might be the reason for this?
6182 First of all, the reason might be the USB power supply. Try using a self-powered
6183 hub instead of a direct connection to your computer. Secondly, the error code 4
6184 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6185 chip ran into some sort of error - this points us to a USB problem.
6187 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6188 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6189 What does that mean and what might be the reason for this?
6191 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6192 has closed the connection to OpenOCD. This might be a GDB issue.
6194 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6195 are described, there is a parameter for specifying the clock frequency
6196 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6197 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6198 specified in kilohertz. However, I do have a quartz crystal of a
6199 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6200 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6203 No. The clock frequency specified here must be given as an integral number.
6204 However, this clock frequency is used by the In-Application-Programming (IAP)
6205 routines of the LPC2000 family only, which seems to be very tolerant concerning
6206 the given clock frequency, so a slight difference between the specified clock
6207 frequency and the actual clock frequency will not cause any trouble.
6209 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6211 Well, yes and no. Commands can be given in arbitrary order, yet the
6212 devices listed for the JTAG scan chain must be given in the right
6213 order (jtag newdevice), with the device closest to the TDO-Pin being
6214 listed first. In general, whenever objects of the same type exist
6215 which require an index number, then these objects must be given in the
6216 right order (jtag newtap, targets and flash banks - a target
6217 references a jtag newtap and a flash bank references a target).
6219 You can use the ``scan_chain'' command to verify and display the tap order.
6221 Also, some commands can't execute until after @command{init} has been
6222 processed. Such commands include @command{nand probe} and everything
6223 else that needs to write to controller registers, perhaps for setting
6224 up DRAM and loading it with code.
6226 @anchor{FAQ TAP Order}
6227 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6230 Yes; whenever you have more than one, you must declare them in
6231 the same order used by the hardware.
6233 Many newer devices have multiple JTAG TAPs. For example: ST
6234 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6235 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6236 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6237 connected to the boundary scan TAP, which then connects to the
6238 Cortex-M3 TAP, which then connects to the TDO pin.
6240 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6241 (2) The boundary scan TAP. If your board includes an additional JTAG
6242 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6243 place it before or after the STM32 chip in the chain. For example:
6246 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6247 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6248 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6249 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6250 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6253 The ``jtag device'' commands would thus be in the order shown below. Note:
6256 @item jtag newtap Xilinx tap -irlen ...
6257 @item jtag newtap stm32 cpu -irlen ...
6258 @item jtag newtap stm32 bs -irlen ...
6259 @item # Create the debug target and say where it is
6260 @item target create stm32.cpu -chain-position stm32.cpu ...
6264 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6265 log file, I can see these error messages: Error: arm7_9_common.c:561
6266 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6272 @node Tcl Crash Course
6273 @chapter Tcl Crash Course
6276 Not everyone knows Tcl - this is not intended to be a replacement for
6277 learning Tcl, the intent of this chapter is to give you some idea of
6278 how the Tcl scripts work.
6280 This chapter is written with two audiences in mind. (1) OpenOCD users
6281 who need to understand a bit more of how JIM-Tcl works so they can do
6282 something useful, and (2) those that want to add a new command to
6285 @section Tcl Rule #1
6286 There is a famous joke, it goes like this:
6288 @item Rule #1: The wife is always correct
6289 @item Rule #2: If you think otherwise, See Rule #1
6292 The Tcl equal is this:
6295 @item Rule #1: Everything is a string
6296 @item Rule #2: If you think otherwise, See Rule #1
6299 As in the famous joke, the consequences of Rule #1 are profound. Once
6300 you understand Rule #1, you will understand Tcl.
6302 @section Tcl Rule #1b
6303 There is a second pair of rules.
6305 @item Rule #1: Control flow does not exist. Only commands
6306 @* For example: the classic FOR loop or IF statement is not a control
6307 flow item, they are commands, there is no such thing as control flow
6309 @item Rule #2: If you think otherwise, See Rule #1
6310 @* Actually what happens is this: There are commands that by
6311 convention, act like control flow key words in other languages. One of
6312 those commands is the word ``for'', another command is ``if''.
6315 @section Per Rule #1 - All Results are strings
6316 Every Tcl command results in a string. The word ``result'' is used
6317 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6318 Everything is a string}
6320 @section Tcl Quoting Operators
6321 In life of a Tcl script, there are two important periods of time, the
6322 difference is subtle.
6325 @item Evaluation Time
6328 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6329 three primary quoting constructs, the [square-brackets] the
6330 @{curly-braces@} and ``double-quotes''
6332 By now you should know $VARIABLES always start with a $DOLLAR
6333 sign. BTW: To set a variable, you actually use the command ``set'', as
6334 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6335 = 1'' statement, but without the equal sign.
6338 @item @b{[square-brackets]}
6339 @* @b{[square-brackets]} are command substitutions. It operates much
6340 like Unix Shell `back-ticks`. The result of a [square-bracket]
6341 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6342 string}. These two statements are roughly identical:
6346 echo "The Date is: $X"
6349 puts "The Date is: $X"
6351 @item @b{``double-quoted-things''}
6352 @* @b{``double-quoted-things''} are just simply quoted
6353 text. $VARIABLES and [square-brackets] are expanded in place - the
6354 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6358 puts "It is now \"[date]\", $x is in 1 hour"
6360 @item @b{@{Curly-Braces@}}
6361 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6362 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6363 'single-quote' operators in BASH shell scripts, with the added
6364 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6365 nested 3 times@}@}@} NOTE: [date] is a bad example;
6366 at this writing, Jim/OpenOCD does not have a date command.
6369 @section Consequences of Rule 1/2/3/4
6371 The consequences of Rule 1 are profound.
6373 @subsection Tokenisation & Execution.
6375 Of course, whitespace, blank lines and #comment lines are handled in
6378 As a script is parsed, each (multi) line in the script file is
6379 tokenised and according to the quoting rules. After tokenisation, that
6380 line is immedatly executed.
6382 Multi line statements end with one or more ``still-open''
6383 @{curly-braces@} which - eventually - closes a few lines later.
6385 @subsection Command Execution
6387 Remember earlier: There are no ``control flow''
6388 statements in Tcl. Instead there are COMMANDS that simply act like
6389 control flow operators.
6391 Commands are executed like this:
6394 @item Parse the next line into (argc) and (argv[]).
6395 @item Look up (argv[0]) in a table and call its function.
6396 @item Repeat until End Of File.
6399 It sort of works like this:
6402 ReadAndParse( &argc, &argv );
6404 cmdPtr = LookupCommand( argv[0] );
6406 (*cmdPtr->Execute)( argc, argv );
6410 When the command ``proc'' is parsed (which creates a procedure
6411 function) it gets 3 parameters on the command line. @b{1} the name of
6412 the proc (function), @b{2} the list of parameters, and @b{3} the body
6413 of the function. Not the choice of words: LIST and BODY. The PROC
6414 command stores these items in a table somewhere so it can be found by
6417 @subsection The FOR command
6419 The most interesting command to look at is the FOR command. In Tcl,
6420 the FOR command is normally implemented in C. Remember, FOR is a
6421 command just like any other command.
6423 When the ascii text containing the FOR command is parsed, the parser
6424 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6428 @item The ascii text 'for'
6429 @item The start text
6430 @item The test expression
6435 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6436 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6437 Often many of those parameters are in @{curly-braces@} - thus the
6438 variables inside are not expanded or replaced until later.
6440 Remember that every Tcl command looks like the classic ``main( argc,
6441 argv )'' function in C. In JimTCL - they actually look like this:
6445 MyCommand( Jim_Interp *interp,
6447 Jim_Obj * const *argvs );
6450 Real Tcl is nearly identical. Although the newer versions have
6451 introduced a byte-code parser and intepreter, but at the core, it
6452 still operates in the same basic way.
6454 @subsection FOR command implementation
6456 To understand Tcl it is perhaps most helpful to see the FOR
6457 command. Remember, it is a COMMAND not a control flow structure.
6459 In Tcl there are two underlying C helper functions.
6461 Remember Rule #1 - You are a string.
6463 The @b{first} helper parses and executes commands found in an ascii
6464 string. Commands can be seperated by semicolons, or newlines. While
6465 parsing, variables are expanded via the quoting rules.
6467 The @b{second} helper evaluates an ascii string as a numerical
6468 expression and returns a value.
6470 Here is an example of how the @b{FOR} command could be
6471 implemented. The pseudo code below does not show error handling.
6473 void Execute_AsciiString( void *interp, const char *string );
6475 int Evaluate_AsciiExpression( void *interp, const char *string );
6478 MyForCommand( void *interp,
6483 SetResult( interp, "WRONG number of parameters");
6487 // argv[0] = the ascii string just like C
6489 // Execute the start statement.
6490 Execute_AsciiString( interp, argv[1] );
6494 i = Evaluate_AsciiExpression(interp, argv[2]);
6499 Execute_AsciiString( interp, argv[3] );
6501 // Execute the LOOP part
6502 Execute_AsciiString( interp, argv[4] );
6506 SetResult( interp, "" );
6511 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6512 in the same basic way.
6514 @section OpenOCD Tcl Usage
6516 @subsection source and find commands
6517 @b{Where:} In many configuration files
6518 @* Example: @b{ source [find FILENAME] }
6519 @*Remember the parsing rules
6521 @item The FIND command is in square brackets.
6522 @* The FIND command is executed with the parameter FILENAME. It should
6523 find the full path to the named file. The RESULT is a string, which is
6524 substituted on the orginal command line.
6525 @item The command source is executed with the resulting filename.
6526 @* SOURCE reads a file and executes as a script.
6528 @subsection format command
6529 @b{Where:} Generally occurs in numerous places.
6530 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6536 puts [format "The answer: %d" [expr $x * $y]]
6539 @item The SET command creates 2 variables, X and Y.
6540 @item The double [nested] EXPR command performs math
6541 @* The EXPR command produces numerical result as a string.
6543 @item The format command is executed, producing a single string
6544 @* Refer to Rule #1.
6545 @item The PUTS command outputs the text.
6547 @subsection Body or Inlined Text
6548 @b{Where:} Various TARGET scripts.
6551 proc someproc @{@} @{
6552 ... multiple lines of stuff ...
6554 $_TARGETNAME configure -event FOO someproc
6555 #2 Good - no variables
6556 $_TARGETNAME confgure -event foo "this ; that;"
6557 #3 Good Curly Braces
6558 $_TARGETNAME configure -event FOO @{
6561 #4 DANGER DANGER DANGER
6562 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6565 @item The $_TARGETNAME is an OpenOCD variable convention.
6566 @*@b{$_TARGETNAME} represents the last target created, the value changes
6567 each time a new target is created. Remember the parsing rules. When
6568 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6569 the name of the target which happens to be a TARGET (object)
6571 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6572 @*There are 4 examples:
6574 @item The TCLBODY is a simple string that happens to be a proc name
6575 @item The TCLBODY is several simple commands seperated by semicolons
6576 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6577 @item The TCLBODY is a string with variables that get expanded.
6580 In the end, when the target event FOO occurs the TCLBODY is
6581 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6582 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6584 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6585 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6586 and the text is evaluated. In case #4, they are replaced before the
6587 ``Target Object Command'' is executed. This occurs at the same time
6588 $_TARGETNAME is replaced. In case #4 the date will never
6589 change. @{BTW: [date] is a bad example; at this writing,
6590 Jim/OpenOCD does not have a date command@}
6592 @subsection Global Variables
6593 @b{Where:} You might discover this when writing your own procs @* In
6594 simple terms: Inside a PROC, if you need to access a global variable
6595 you must say so. See also ``upvar''. Example:
6597 proc myproc @{ @} @{
6598 set y 0 #Local variable Y
6599 global x #Global variable X
6600 puts [format "X=%d, Y=%d" $x $y]
6603 @section Other Tcl Hacks
6604 @b{Dynamic variable creation}
6606 # Dynamically create a bunch of variables.
6607 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6609 set vn [format "BIT%d" $x]
6613 set $vn [expr (1 << $x)]
6616 @b{Dynamic proc/command creation}
6618 # One "X" function - 5 uart functions.
6619 foreach who @{A B C D E@}
6620 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6624 @node Target Library
6625 @chapter Target Library
6626 @cindex Target Library
6628 OpenOCD comes with a target configuration script library. These scripts can be
6629 used as-is or serve as a starting point.
6631 The target library is published together with the OpenOCD executable and
6632 the path to the target library is in the OpenOCD script search path.
6633 Similarly there are example scripts for configuring the JTAG interface.
6635 The command line below uses the example parport configuration script
6636 that ship with OpenOCD, then configures the str710.cfg target and
6637 finally issues the init and reset commands. The communication speed
6638 is set to 10kHz for reset and 8MHz for post reset.
6641 openocd -f interface/parport.cfg -f target/str710.cfg \
6642 -c "init" -c "reset"
6645 To list the target scripts available:
6648 $ ls /usr/local/lib/openocd/target
6650 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6651 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6652 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6653 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6658 @node OpenOCD Concept Index
6659 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6660 @comment case issue with ``Index.html'' and ``index.html''
6661 @comment Occurs when creating ``--html --no-split'' output
6662 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6663 @unnumbered OpenOCD Concept Index
6667 @node Command and Driver Index
6668 @unnumbered Command and Driver Index