1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
29 Permission is granted to copy, distribute and/or modify this document
30 under the terms of the GNU Free Documentation License, Version 1.2 or
31 any later version published by the Free Software Foundation; with no
32 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
33 Texts. A copy of the license is included in the section entitled ``GNU
34 Free Documentation License''.
39 @titlefont{@emph{Open On-Chip Debugger:}}
41 @title OpenOCD User's Guide
42 @subtitle for release @value{VERSION}
43 @subtitle @value{UPDATED}
46 @vskip 0pt plus 1filll
55 @top OpenOCD User's Guide
61 * About:: About OpenOCD
62 * Developers:: OpenOCD Developers
63 * Building OpenOCD:: Building OpenOCD From SVN
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * Running:: Running OpenOCD
66 * OpenOCD Project Setup:: OpenOCD Project Setup
67 * Config File Guidelines:: Config File Guidelines
68 * About JIM-Tcl:: About JIM-Tcl
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * General Commands:: General Commands
77 * Architecture and Core Commands:: Architecture and Core Commands
78 * JTAG Commands:: JTAG Commands
80 * GDB and OpenOCD:: Using GDB and OpenOCD
81 * Tcl Scripting API:: Tcl Scripting API
82 * Upgrading:: Deprecated/Removed Commands
83 * Target Library:: Target Library
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
115 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
116 A @dfn{TAP} is a ``Test Access Port'', a module which processes
117 special instructions and data. TAPs are daisy-chained within and
118 between chips and boards.
120 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
121 based, parallel port based, and other standalone boxes that run
122 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
125 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
126 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
127 debugged via the GDB protocol.
129 @b{Flash Programing:} Flash writing is supported for external CFI
130 compatible NOR flashes (Intel and AMD/Spansion command set) and several
131 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
132 STM32x). Preliminary support for various NAND flash controllers
133 (LPC3180, Orion, S3C24xx, more) controller is included.
135 @section OpenOCD Web Site
137 The OpenOCD web site provides the latest public news from the community:
139 @uref{http://openocd.berlios.de/web/}
141 @section Latest User's Guide:
143 The user's guide you are now reading may not be the latest one
144 available. A version for more recent code may be available.
145 Its HTML form is published irregularly at:
147 @uref{http://openocd.berlios.de/doc/html/index.html}
149 PDF form is likewise published at:
151 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
153 @section OpenOCD User's Forum
155 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
161 @chapter OpenOCD Developer Resources
164 If you are interested in improving the state of OpenOCD's debugging and
165 testing support, new contributions will be welcome. Motivated developers
166 can produce new target, flash or interface drivers, improve the
167 documentation, as well as more conventional bug fixes and enhancements.
169 The resources in this chapter are available for developers wishing to explore
170 or expand the OpenOCD source code.
172 @section OpenOCD Subversion Repository
174 The ``Building From Source'' section provides instructions to retrieve
175 and and build the latest version of the OpenOCD source code.
176 @xref{Building OpenOCD}.
178 Developers that want to contribute patches to the OpenOCD system are
179 @b{strongly} encouraged to base their work off of the most recent trunk
180 revision. Patches created against older versions may require additional
181 work from their submitter in order to be updated for newer releases.
183 @section Doxygen Developer Manual
185 During the development of the 0.2.0 release, the OpenOCD project began
186 providing a Doxygen reference manual. This document contains more
187 technical information about the software internals, development
188 processes, and similar documentation:
190 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
192 This document is a work-in-progress, but contributions would be welcome
193 to fill in the gaps. All of the source files are provided in-tree,
194 listed in the Doxyfile configuration in the top of the repository trunk.
196 @section OpenOCD Developer Mailing List
198 The OpenOCD Developer Mailing List provides the primary means of
199 communication between developers:
201 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
203 All drivers developers are enouraged to also subscribe to the list of
204 SVN commits to keep pace with the ongoing changes:
206 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
209 @node Building OpenOCD
210 @chapter Building OpenOCD
213 @section Pre-Built Tools
214 If you are interested in getting actual work done rather than building
215 OpenOCD, then check if your interface supplier provides binaries for
216 you. Chances are that that binary is from some SVN version that is more
217 stable than SVN trunk where bleeding edge development takes place.
219 @section Packagers Please Read!
221 You are a @b{PACKAGER} of OpenOCD if you
224 @item @b{Sell dongles} and include pre-built binaries
225 @item @b{Supply tools} i.e.: A complete development solution
226 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
227 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
230 As a @b{PACKAGER}, you will experience first reports of most issues.
231 When you fix those problems for your users, your solution may help
232 prevent hundreds (if not thousands) of other questions from other users.
234 If something does not work for you, please work to inform the OpenOCD
235 developers know how to improve the system or documentation to avoid
236 future problems, and follow-up to help us ensure the issue will be fully
237 resolved in our future releases.
239 That said, the OpenOCD developers would also like you to follow a few
243 @item Send patches, including config files, upstream.
244 @item Always build with printer ports enabled.
245 @item Use libftdi + libusb for FT2232 support.
248 @section Building From Source
250 You can download the current SVN version with an SVN client of your choice from the
251 following repositories:
253 @uref{svn://svn.berlios.de/openocd/trunk}
257 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
259 Using the SVN command line client, you can use the following command to fetch the
260 latest version (make sure there is no (non-svn) directory called "openocd" in the
264 svn checkout svn://svn.berlios.de/openocd/trunk openocd
267 If you prefer GIT based tools, the @command{git-svn} package works too:
270 git svn clone -s svn://svn.berlios.de/openocd
273 Building OpenOCD from a repository requires a recent version of the
274 GNU autotools (autoconf >= 2.59 and automake >= 1.9).
275 For building on Windows,
276 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
277 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
278 paths, resulting in obscure dependency errors (This is an observation I've gathered
279 from the logs of one user - correct me if I'm wrong).
281 You further need the appropriate driver files, if you want to build support for
282 a FTDI FT2232 based interface:
285 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
286 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}),
287 or the Amontec version (from @uref{http://www.amontec.com}),
288 for easier support of JTAGkey's vendor and product IDs.
291 libftdi is supported under Windows. Do not use versions earlier than 0.14.
292 To use the newer FT2232H chips, supporting RTCK and USB high speed (480 Mbps),
293 you need libftdi version 0.16 or newer.
295 Some people say that FTDI's libftd2xx code provides better performance.
296 However, it is binary-only, while OpenOCD is licenced according
297 to GNU GPLv2 without any exceptions.
298 That means that @emph{distributing} copies of OpenOCD built with
299 the FTDI code would violate the OpenOCD licensing terms.
300 You may, however, build such copies for personal use.
302 To build OpenOCD (on both Linux and Cygwin), use the following commands:
308 Bootstrap generates the configure script, and prepares building on your system.
311 ./configure [options, see below]
314 Configure generates the Makefiles used to build OpenOCD.
321 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
323 The configure script takes several options, specifying which JTAG interfaces
324 should be included (among other things):
328 @option{--enable-parport} - Enable building the PC parallel port driver.
330 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
332 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
334 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
336 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
338 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
340 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
342 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
344 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
346 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
348 @option{--enable-ft2232_ftd2xx} - Support FT2232-family chips using
349 the closed-source library from FTDICHIP.COM
350 (result not for re-distribution).
352 @option{--enable-ft2232_libftdi} - Support FT2232-family chips using
353 a GPL'd ft2232 support library (result OK for re-distribution).
355 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
356 give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
358 @option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
359 on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
361 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static.
362 Specifies how the FTDICHIP.COM libftd2xx driver should be linked.
363 Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}.
364 The 'shared' value is supported, however you must manually install the required
365 header files and shared libraries in an appropriate place.
367 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
369 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
371 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
373 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
375 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
377 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
379 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
381 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
383 @option{--enable-dummy} - Enable building the dummy port driver.
386 @section Parallel Port Dongles
388 If you want to access the parallel port using the PPDEV interface you have to specify
389 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
390 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
391 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
393 The same is true for the @option{--enable-parport_giveio} option, you have to
394 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
396 @section FT2232C Based USB Dongles
398 There are 2 methods of using the FTD2232, either (1) using the
399 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
400 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster,
401 which is the motivation for supporting it even though its licensing
402 restricts it to non-redistributable OpenOCD binaries, and it is
403 not available for all operating systems used with OpenOCD.
405 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
406 TAR.GZ file. You must unpack them ``some where'' convient. As of this
407 writing FTDICHIP does not supply means to install these
408 files ``in an appropriate place''.
409 As a result, there are two
410 ``./configure'' options that help.
412 Below is an example build process:
415 @item Check out the latest version of ``openocd'' from SVN.
417 @item If you are using the FTDICHIP.COM driver, download
418 and unpack the Windows or Linux FTD2xx drivers
419 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
420 If you are using the libftdi driver, install that package
421 (e.g. @command{apt-get install libftdi} on systems with APT).
424 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents
425 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
428 @item Configure with options resembling the following.
431 @item Cygwin FTDICHIP solution:
433 ./configure --prefix=/home/duane/mytools \
434 --enable-ft2232_ftd2xx \
435 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
438 @item Linux FTDICHIP solution:
440 ./configure --prefix=/home/duane/mytools \
441 --enable-ft2232_ftd2xx \
442 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
445 @item Cygwin/Linux LIBFTDI solution ... assuming that
447 @item For Windows -- that the Windows port of LIBUSB is in place.
448 @item For Linux -- that libusb has been built/installed and is in place.
449 @item That libftdi has been built and installed (relies on libusb).
452 Then configure the libftdi solution like this:
455 ./configure --prefix=/home/duane/mytools \
456 --enable-ft2232_libftdi
460 @item Then just type ``make'', and perhaps ``make install''.
464 @section Miscellaneous Configure Options
468 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
470 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
473 @option{--enable-release} - Enable building of an OpenOCD release, generally
474 this is for developers. It simply omits the svn version string when the
475 openocd @option{-v} is executed.
478 @node JTAG Hardware Dongles
479 @chapter JTAG Hardware Dongles
488 Defined: @b{dongle}: A small device that plugins into a computer and serves as
489 an adapter .... [snip]
491 In the OpenOCD case, this generally refers to @b{a small adapater} one
492 attaches to your computer via USB or the Parallel Printer Port. The
493 execption being the Zylin ZY1000 which is a small box you attach via
494 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
495 require any drivers to be installed on the developer PC. It also has
496 a built in web interface. It supports RTCK/RCLK or adaptive clocking
497 and has a built in relay to power cycle targets remotely.
500 @section Choosing a Dongle
502 There are three things you should keep in mind when choosing a dongle.
505 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
506 @item @b{Connection} Printer Ports - Does your computer have one?
507 @item @b{Connection} Is that long printer bit-bang cable practical?
508 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
511 @section Stand alone Systems
513 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
514 dongle, but a standalone box. The ZY1000 has the advantage that it does
515 not require any drivers installed on the developer PC. It also has
516 a built in web interface. It supports RTCK/RCLK or adaptive clocking
517 and has a built in relay to power cycle targets remotely.
519 @section USB FT2232 Based
521 There are many USB JTAG dongles on the market, many of them are based
522 on a chip from ``Future Technology Devices International'' (FTDI)
523 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
524 See: @url{http://www.ftdichip.com} for more information.
525 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
526 chips are starting to become available in JTAG adapters.
530 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
532 @* See: @url{http://www.amontec.com/jtagkey.shtml}
534 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
536 @* See: @url{http://www.signalyzer.com}
537 @item @b{evb_lm3s811}
538 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
539 @item @b{olimex-jtag}
540 @* See: @url{http://www.olimex.com}
542 @* See: @url{http://www.tincantools.com}
543 @item @b{turtelizer2}
545 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
546 @url{http://www.ethernut.de}
548 @* Link: @url{http://www.hitex.com/index.php?id=383}
550 @* Link @url{http://www.hitex.com/stm32-stick}
551 @item @b{axm0432_jtag}
552 @* Axiom AXM-0432 Link @url{http://www.axman.com}
554 @* Link @url{http://www.hitex.com/index.php?id=cortino}
557 @section USB JLINK based
558 There are several OEM versions of the Segger @b{JLINK} adapter. It is
559 an example of a micro controller based JTAG adapter, it uses an
560 AT91SAM764 internally.
563 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
564 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
565 @item @b{SEGGER JLINK}
566 @* Link: @url{http://www.segger.com/jlink.html}
568 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
571 @section USB RLINK based
572 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
575 @item @b{Raisonance RLink}
576 @* Link: @url{http://www.raisonance.com/products/RLink.php}
577 @item @b{STM32 Primer}
578 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
579 @item @b{STM32 Primer2}
580 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
586 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
588 @item @b{USB - Presto}
589 @* Link: @url{http://tools.asix.net/prg_presto.htm}
591 @item @b{Versaloon-Link}
592 @* Link: @url{http://www.simonqian.com/en/Versaloon}
594 @item @b{ARM-JTAG-EW}
595 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
598 @section IBM PC Parallel Printer Port Based
600 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
601 and the MacGraigor Wiggler. There are many clones and variations of
606 @item @b{Wiggler} - There are many clones of this.
607 @* Link: @url{http://www.macraigor.com/wiggler.htm}
609 @item @b{DLC5} - From XILINX - There are many clones of this
610 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
611 produced, PDF schematics are easily found and it is easy to make.
613 @item @b{Amontec - JTAG Accelerator}
614 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
617 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
620 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
621 Improved parallel-port wiggler-style JTAG adapter}
623 @item @b{Wiggler_ntrst_inverted}
624 @* Yet another variation - See the source code, src/jtag/parport.c
626 @item @b{old_amt_wiggler}
627 @* Unknown - probably not on the market today
630 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
633 @* Link: @url{http://www.amontec.com/chameleon.shtml}
639 @* ispDownload from Lattice Semiconductor
640 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
643 @* From ST Microsystems;
644 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
645 FlashLINK JTAG programing cable for PSD and uPSD}
653 @* An EP93xx based Linux machine using the GPIO pins directly.
656 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
662 @cindex command line options
664 @cindex directory search
666 The @option{--help} option shows:
670 --help | -h display this help
671 --version | -v display OpenOCD version
672 --file | -f use configuration file <name>
673 --search | -s dir to search for config files and scripts
674 --debug | -d set debug level <0-3>
675 --log_output | -l redirect log output to file <name>
676 --command | -c run <command>
677 --pipe | -p use pipes when talking to gdb
680 By default OpenOCD reads the file configuration file ``openocd.cfg''
681 in the current directory. To specify a different (or multiple)
682 configuration file, you can use the ``-f'' option. For example:
685 openocd -f config1.cfg -f config2.cfg -f config3.cfg
688 Once started, OpenOCD runs as a daemon, waiting for connections from
689 clients (Telnet, GDB, Other).
691 If you are having problems, you can enable internal debug messages via
694 Also it is possible to interleave commands w/config scripts using the
695 @option{-c} command line switch.
697 To enable debug output (when reporting problems or working on OpenOCD
698 itself), use the @option{-d} command line switch. This sets the
699 @option{debug_level} to "3", outputting the most information,
700 including debug messages. The default setting is "2", outputting only
701 informational messages, warnings and errors. You can also change this
702 setting from within a telnet or gdb session using @command{debug_level
703 <n>} (@pxref{debug_level}).
705 You can redirect all output from the daemon to a file using the
706 @option{-l <logfile>} switch.
708 Search paths for config/script files can be added to OpenOCD by using
709 the @option{-s <search>} switch. The current directory and the OpenOCD
710 target library is in the search path by default.
712 For details on the @option{-p} option. @xref{Connecting to GDB}.
714 Note! OpenOCD will launch the GDB & telnet server even if it can not
715 establish a connection with the target. In general, it is possible for
716 the JTAG controller to be unresponsive until the target is set up
717 correctly via e.g. GDB monitor commands in a GDB init script.
719 @node OpenOCD Project Setup
720 @chapter OpenOCD Project Setup
722 To use OpenOCD with your development projects, you need to do more than
723 just connecting the JTAG adapter hardware (dongle) to your development board
724 and then starting the OpenOCD server.
725 You also need to configure that server so that it knows
726 about that adapter and board, and helps your work.
728 @section Hooking up the JTAG Adapter
730 Today's most common case is a dongle with a JTAG cable on one side
731 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
732 and a USB cable on the other.
733 Instead of USB, some cables use Ethernet;
734 older ones may use a PC parallel port, or even a serial port.
737 @item @emph{Start with power to your target board turned off},
738 and nothing connected to your JTAG adapter.
739 If you're particularly paranoid, unplug power to the board.
740 It's important to have the ground signal properly set up,
741 unless you are using a JTAG adapter which provides
742 galvanic isolation between the target board and the
745 @item @emph{Be sure it's the right kind of JTAG connector.}
746 If your dongle has a 20-pin ARM connector, you need some kind
747 of adapter (or octopus, see below) to hook it up to
748 boards using 14-pin or 10-pin connectors ... or to 20-pin
749 connectors which don't use ARM's pinout.
751 In the same vein, make sure the voltage levels are compatible.
752 Not all JTAG adapters have the level shifters needed to work
753 with 1.2 Volt boards.
755 @item @emph{Be certain the cable is properly oriented} or you might
756 damage your board. In most cases there are only two possible
757 ways to connect the cable.
758 Connect the JTAG cable from your adapter to the board.
759 Be sure it's firmly connected.
761 In the best case, the connector is keyed to physically
762 prevent you from inserting it wrong.
763 This is most often done using a slot on the board's male connector
764 housing, which must match a key on the JTAG cable's female connector.
765 If there's no housing, then you must look carefully and
766 make sure pin 1 on the cable hooks up to pin 1 on the board.
767 Ribbon cables are frequently all grey except for a wire on one
768 edge, which is red. The red wire is pin 1.
770 Sometimes dongles provide cables where one end is an ``octopus'' of
771 color coded single-wire connectors, instead of a connector block.
772 These are great when converting from one JTAG pinout to another,
773 but are tedious to set up.
774 Use these with connector pinout diagrams to help you match up the
775 adapter signals to the right board pins.
777 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
778 A USB, parallel, or serial port connector will go to the host which
779 you are using to run OpenOCD.
780 For Ethernet, consult the documentation and your network administrator.
782 For USB based JTAG adapters you have an easy sanity check at this point:
783 does the host operating system see the JTAG adapter?
785 @item @emph{Connect the adapter's power supply, if needed.}
786 This step is primarily for non-USB adapters,
787 but sometimes USB adapters need extra power.
789 @item @emph{Power up the target board.}
790 Unless you just let the magic smoke escape,
791 you're now ready to set up the OpenOCD server
792 so you can use JTAG to work with that board.
796 Talk with the OpenOCD server using
797 telnet (@code{telnet localhost 4444} on many systems) or GDB.
798 @xref{GDB and OpenOCD}.
800 @section Project Directory
802 There are many ways you can configure OpenOCD and start it up.
804 A simple way to organize them all involves keeping a
805 single directory for your work with a given board.
806 When you start OpenOCD from that directory,
807 it searches there first for configuration files
808 and for code you upload to the target board.
809 It is also be the natural place to write files,
810 such as log files and data you download from the board.
812 @section Configuration Basics
814 There are two basic ways of configuring OpenOCD, and
815 a variety of ways you can mix them.
816 Think of the difference as just being how you start the server:
819 @item Many @option{-f file} or @option{-c command} options on the command line
820 @item No options, but a @dfn{user config file}
821 in the current directory named @file{openocd.cfg}
824 Here is an example @file{openocd.cfg} file for a setup
825 using a Signalyzer FT2232-based JTAG adapter to talk to
826 a board with an Atmel AT91SAM7X256 microcontroller:
829 source [find interface/signalyzer.cfg]
831 # GDB can also flash my flash!
832 gdb_memory_map enable
833 gdb_flash_program enable
835 source [find target/sam7x256.cfg]
838 Here is the command line equivalent of that configuration:
841 openocd -f interface/signalyzer.cfg \
842 -c "gdb_memory_map enable" \
843 -c "gdb_flash_program enable" \
844 -f target/sam7x256.cfg
847 You could wrap such long command lines in shell scripts,
848 each supporting a different development task.
849 One might re-flash the board with specific firmware version.
850 Another might set up a particular debugging or run-time environment.
852 Here we will focus on the simpler solution: one user config
853 file, including basic configuration plus any TCL procedures
854 to simplify your work.
856 @section User Config Files
857 @cindex config file, user
858 @cindex user config file
859 @cindex config file, overview
861 A user configuration file ties together all the parts of a project
863 One of the following will match your situation best:
866 @item Ideally almost everything comes from configuration files
867 provided by someone else.
868 For example, OpenOCD distributes a @file{scripts} directory
869 (probably in @file{/usr/share/openocd/scripts} on Linux).
870 Board and tool vendors can provide these too, as can individual
871 user sites; the @option{-s} command line option lets you say
872 where to find these files. (@xref{Running}.)
873 The AT91SAM7X256 example above works this way.
875 Three main types of non-user configuration file each have their
876 own subdirectory in the @file{scripts} directory:
879 @item @b{interface} -- one for each kind of JTAG adapter/dongle
880 @item @b{board} -- one for each different board
881 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
884 Best case: include just two files, and they handle everything else.
885 The first is an interface config file.
886 The second is board-specific, and it sets up the JTAG TAPs and
887 their GDB targets (by deferring to some @file{target.cfg} file),
888 declares all flash memory, and leaves you nothing to do except
892 source [find interface/olimex-jtag-tiny.cfg]
893 source [find board/csb337.cfg]
896 Boards with a single microcontroller often won't need more
897 than the target config file, as in the AT91SAM7X256 example.
898 That's because there is no external memory (flash, DDR RAM), and
899 the board differences are encapsulated by application code.
901 @item You can often reuse some standard config files but
902 need to write a few new ones, probably a @file{board.cfg} file.
903 You will be using commands described later in this User's Guide,
904 and working with the guidelines in the next chapter.
906 For example, there may be configuration files for your JTAG adapter
907 and target chip, but you need a new board-specific config file
908 giving access to your particular flash chips.
909 Or you might need to write another target chip configuration file
910 for a new chip built around the Cortex M3 core.
913 When you write new configuration files, please submit
914 them for inclusion in the next OpenOCD release.
915 For example, a @file{board/newboard.cfg} file will help the
916 next users of that board, and a @file{target/newcpu.cfg}
917 will help support users of any board using that chip.
921 You may may need to write some C code.
922 It may be as simple as a supporting a new new ft2232 or parport
923 based dongle; a bit more involved, like a NAND or NOR flash
924 controller driver; or a big piece of work like supporting
925 a new chip architecture.
928 Reuse the existing config files when you can.
929 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
930 You may find a board configuration that's a good example to follow.
932 When you write config files, separate the reusable parts
933 (things every user of that interface, chip, or board needs)
934 from ones specific to your environment and debugging approach.
936 For example, a @code{gdb-attach} event handler that invokes
937 the @command{reset init} command will interfere with debugging
938 early boot code, which performs some of the same actions
939 that the @code{reset-init} event handler does.
940 Likewise, the @command{arm9tdmi vector_catch} command (or
941 its @command{xscale vector_catch} sibling) can be a timesaver
942 during some debug sessions, but don't make everyone use that either.
943 Keep those kinds of debugging aids in your user config file.
945 @section Project-Specific Utilities
947 A few project-specific utility
948 routines may well speed up your work.
949 Write them, and keep them in your project's user config file.
951 For example, if you are making a boot loader work on a
952 board, it's nice to be able to debug the ``after it's
953 loaded to RAM'' parts separately from the finicky early
954 code which sets up the DDR RAM controller and clocks.
955 A script like this one, or a more GDB-aware sibling,
959 proc ramboot @{ @} @{
960 # Reset, running the target's "reset-init" scripts
961 # to initialize clocks and the DDR RAM controller.
962 # Leave the CPU halted.
965 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
966 load_image u-boot.bin 0x20000000
973 Then once that code is working you will need to make it
974 boot from NOR flash; a different utility would help.
975 Alternatively, some developers write to flash using GDB.
976 (You might use a similar script if you're working with a flash
977 based microcontroller application instead of a boot loader.)
980 proc newboot @{ @} @{
981 # Reset, leaving the CPU halted. The "reset-init" event
982 # proc gives faster access to the CPU and to NOR flash;
983 # "reset halt" would be slower.
986 # Write standard version of U-Boot into the first two
987 # sectors of NOR flash ... the standard version should
988 # do the same lowlevel init as "reset-init".
989 flash protect 0 0 1 off
990 flash erase_sector 0 0 1
991 flash write_bank 0 u-boot.bin 0x0
992 flash protect 0 0 1 on
994 # Reboot from scratch using that new boot loader.
999 You may need more complicated utility procedures when booting
1001 That often involves an extra bootloader stage,
1002 running from on-chip SRAM to perform DDR RAM setup so it can load
1003 the main bootloader code (which won't fit into that SRAM).
1005 Other helper scripts might be used to write production system images,
1006 involving considerably more than just a three stage bootloader.
1009 @node Config File Guidelines
1010 @chapter Config File Guidelines
1012 This chapter is aimed at any user who needs to write a config file,
1013 including developers and integrators of OpenOCD and any user who
1014 needs to get a new board working smoothly.
1015 It provides guidelines for creating those files.
1017 You should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
1021 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
1023 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
1024 contain initialization items that are specific to a board - for
1025 example: The SDRAM initialization sequence for the board, or the type
1026 of external flash and what address it is found at. Any initialization
1027 sequence to enable that external flash or SDRAM should be found in the
1028 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
1029 a CPU and an FPGA or CPLD.
1031 @* Think chip. The ``target'' directory represents the JTAG TAPs
1033 which OpenOCD should control, not a board. Two common types of targets
1034 are ARM chips and FPGA or CPLD chips.
1035 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1036 the target config file defines all of them.
1039 The @file{openocd.cfg} user config
1040 file may override features in any of the above files by
1041 setting variables before sourcing the target file, or by adding
1042 commands specific to their situation.
1044 @section Interface Config Files
1046 The user config file
1047 should be able to source one of these files via a command like this:
1050 source [find interface/FOOBAR.cfg]
1053 A preconfigured interface file should exist for every interface in use
1054 today, that said, perhaps some interfaces have only been used by the
1055 sole developer who created it.
1057 A separate chapter gives information about how to set these up.
1058 @xref{Interface - Dongle Configuration}.
1059 Read the OpenOCD source code if you have a new kind of hardware interface
1060 and need to provide a driver for it.
1062 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
1064 @section Board Config Files
1065 @cindex config file, board
1066 @cindex board config file
1068 The user config file
1069 should be able to source one of these files via a command like this:
1072 source [find board/FOOBAR.cfg]
1075 The board config file should contain one or more @command{source [find
1076 target/FOO.cfg]} statements along with any board specific things.
1078 In summary the board files should contain (if present)
1081 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
1082 @item SDRAM configuration (size, speed, etc.
1083 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
1084 @item Multiple TARGET source statements
1085 @item Reset configuration
1086 @item All things that are not ``inside a chip''
1087 @item Things inside a chip go in a 'target' file
1090 @section Target Config Files
1091 @cindex config file, target
1092 @cindex target config file
1094 Board config files should be able to source one or more
1095 target config files via a command like this:
1098 source [find target/FOOBAR.cfg]
1101 In summary the target files should contain
1105 @item Add TAPs to the scan chain
1106 @item Add CPU targets (includes GDB support)
1107 @item CPU/Chip/CPU-Core specific features
1111 As a rule of thumb, a target file sets up only one chip.
1112 For a microcontroller, that will often include a single TAP,
1113 which is a CPU needing a GDB target; and its on-chip flash.
1115 More complex chips may include multiple TAPs, and the target
1116 config file may need to define them all before OpenOCD
1117 can talk to the chip.
1118 For example, some phone chips have JTAG scan chains that include
1119 an ARM core for operating system use, a DSP,
1120 another ARM core embedded in an image processing engine,
1121 and other processing engines.
1123 @subsection Important variable names
1125 Most boards will have only one instance of a chip.
1126 However, it should be easy to create a board with more than
1128 Accordingly, we encourage some conventions for naming
1129 variables associated with different TAPs, to promote
1131 so that board files can override target defaults, and
1135 @* This gives a name to the overall chip, and is used as part of the
1136 tap identifier dotted name.
1137 It's normally provided by the chip manufacturer.
1139 @* By default little - unless the chip or board is not normally used that way.
1140 Chips that can't change endianness don't need to use this variable.
1142 @* When OpenOCD examines the JTAG chain, it will attempt to identify
1143 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
1144 to verify the tap id number verses configuration file and may issue an
1145 error or warning like this. The hope is that this will help to pinpoint
1146 problems in OpenOCD configurations.
1149 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1150 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1151 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
1153 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1154 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1157 @item @b{_TARGETNAME}
1158 @* By convention, this variable is created by the target configuration
1159 script. The board configuration file may make use of this variable to
1160 configure things like a ``reset init'' script, or other things
1161 specific to that board and that target.
1163 If the chip has 2 targets, use the names @b{_TARGETNAME0},
1164 @b{_TARGETNAME1}, ... etc.
1166 @emph{Remember:} The ``board file'' may include multiple targets.
1167 The user (or board) config file should reasonably be able to:
1170 source [find target/FOO.cfg]
1171 $_TARGETNAME configure ... FOO specific parameters
1173 source [find target/BAR.cfg]
1174 $_TARGETNAME configure ... BAR specific parameters
1179 @subsection Tcl Variables Guide Line
1180 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
1182 Thus the rule we follow in OpenOCD is this: Variables that begin with
1183 a leading underscore are temporary in nature, and can be modified and
1184 used at will within a ?TARGET? configuration file.
1186 @b{EXAMPLE:} The user config file should be able to do this:
1189 # Board has 3 chips,
1190 # PXA270 #1 network side, big endian
1191 # PXA270 #2 video side, little endian
1193 set CHIPNAME network
1195 source [find target/pxa270.cfg]
1196 # variable: _TARGETNAME = network.cpu
1197 # other commands can refer to the "network.cpu" tap.
1198 $_TARGETNAME configure .... params for this CPU..
1202 source [find target/pxa270.cfg]
1203 # variable: _TARGETNAME = video.cpu
1204 # other commands can refer to the "video.cpu" tap.
1205 $_TARGETNAME configure .... params for this CPU..
1209 source [find target/spartan3.cfg]
1211 # Since $_TARGETNAME is temporal..
1212 # these names still work!
1213 network.cpu configure ... params
1214 video.cpu configure ... params
1217 @subsection Default Value Boiler Plate Code
1219 All target configuration files should start with this (or a modified form)
1223 if @{ [info exists CHIPNAME] @} @{
1224 set _CHIPNAME $CHIPNAME
1226 set _CHIPNAME sam7x256
1229 if @{ [info exists ENDIAN] @} @{
1235 if @{ [info exists CPUTAPID ] @} @{
1236 set _CPUTAPID $CPUTAPID
1238 set _CPUTAPID 0x3f0f0f0f
1242 @subsection Adding TAPs to the Scan Chain
1243 After the ``defaults'' are set up,
1244 add the TAPs on each chip to the JTAG scan chain.
1245 @xref{TAP Declaration}, and the naming convention
1248 In the simplest case the chip has only one TAP,
1249 probably for a CPU or FPGA.
1250 The config file for the Atmel AT91SAM7X256
1251 looks (in part) like this:
1254 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1255 -expected-id $_CPUTAPID
1258 A board with two such at91sam7 chips would be able
1259 to source such a config file twice, with different
1260 values for @code{CHIPNAME}, so
1261 it adds a different TAP each time.
1263 There are more complex examples too, with chips that have
1264 multiple TAPs. Ones worth looking at include:
1267 @item @file{target/omap3530.cfg} -- with a disabled ARM, and a JRC
1268 (there's a DSP too, which is not listed)
1269 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1270 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1271 is not currently used)
1274 @subsection Add CPU targets
1276 After adding a TAP for a CPU, you should set it up so that
1277 GDB and other commands can use it.
1278 @xref{CPU Configuration}.
1279 For the at91sam7 example above, the command can look like this:
1282 set _TARGETNAME $_CHIPNAME.cpu
1283 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1286 Work areas are small RAM areas associated with CPU targets.
1287 They are used by OpenOCD to speed up downloads,
1288 and to download small snippets of code to program flash chips.
1289 If the chip includes a form of ``on-chip-ram'' - and many do - define
1290 a work area if you can.
1291 Again using the at91sam7 as an example, this can look like:
1294 $_TARGETNAME configure -work-area-phys 0x00200000 \
1295 -work-area-size 0x4000 -work-area-backup 0
1298 @subsection Chip Reset Setup
1300 As a rule, you should put the @command{reset_config} command
1301 into the board file. Most things you think you know about a
1302 chip can be tweaked by the board.
1304 Some chips have specific ways the TRST and SRST signals are
1305 managed. In the unusual case that these are @emph{chip specific}
1306 and can never be changed by board wiring, they could go here.
1308 Some chips need special attention during reset handling if
1309 they're going to be used with JTAG.
1310 An example might be needing to send some commands right
1311 after the target's TAP has been reset, providing a
1312 @code{reset-deassert-post} event handler that writes a chip
1313 register to report that JTAG debugging is being done.
1315 @subsection ARM Core Specific Hacks
1317 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1318 special high speed download features - enable it.
1320 If present, the MMU, the MPU and the CACHE should be disabled.
1322 Some ARM cores are equipped with trace support, which permits
1323 examination of the instruction and data bus activity. Trace
1324 activity is controlled through an ``Embedded Trace Module'' (ETM)
1325 on one of the core's scan chains. The ETM emits voluminous data
1326 through a ``trace port''. (@xref{ARM Tracing}.)
1327 If you are using an external trace port,
1328 configure it in your board config file.
1329 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1330 configure it in your target config file.
1333 etm config $_TARGETNAME 16 normal full etb
1334 etb config $_TARGETNAME $_CHIPNAME.etb
1337 @subsection Internal Flash Configuration
1339 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1341 @b{Never ever} in the ``target configuration file'' define any type of
1342 flash that is external to the chip. (For example a BOOT flash on
1343 Chip Select 0.) Such flash information goes in a board file - not
1344 the TARGET (chip) file.
1348 @item at91sam7x256 - has 256K flash YES enable it.
1349 @item str912 - has flash internal YES enable it.
1350 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1351 @item pxa270 - again - CS0 flash - it goes in the board file.
1355 @chapter About JIM-Tcl
1359 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1360 learn more about JIM here: @url{http://jim.berlios.de}
1363 @item @b{JIM vs. Tcl}
1364 @* JIM-TCL is a stripped down version of the well known Tcl language,
1365 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1366 fewer features. JIM-Tcl is a single .C file and a single .H file and
1367 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1368 4.2 MB .zip file containing 1540 files.
1370 @item @b{Missing Features}
1371 @* Our practice has been: Add/clone the real Tcl feature if/when
1372 needed. We welcome JIM Tcl improvements, not bloat.
1375 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1376 command interpreter today is a mixture of (newer)
1377 JIM-Tcl commands, and (older) the orginal command interpreter.
1380 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1381 can type a Tcl for() loop, set variables, etc.
1383 @item @b{Historical Note}
1384 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1386 @item @b{Need a crash course in Tcl?}
1387 @*@xref{Tcl Crash Course}.
1390 @node Daemon Configuration
1391 @chapter Daemon Configuration
1392 @cindex initialization
1393 The commands here are commonly found in the openocd.cfg file and are
1394 used to specify what TCP/IP ports are used, and how GDB should be
1397 @section Configuration Stage
1398 @cindex configuration stage
1399 @cindex configuration command
1401 When the OpenOCD server process starts up, it enters a
1402 @emph{configuration stage} which is the only time that
1403 certain commands, @emph{configuration commands}, may be issued.
1404 Those configuration commands include declaration of TAPs
1405 and other basic setup.
1406 The server must leave the configuration stage before it
1407 may access or activate TAPs.
1408 After it leaves this stage, configuration commands may no
1411 @deffn {Config Command} init
1412 This command terminates the configuration stage and
1413 enters the normal command mode. This can be useful to add commands to
1414 the startup scripts and commands such as resetting the target,
1415 programming flash, etc. To reset the CPU upon startup, add "init" and
1416 "reset" at the end of the config script or at the end of the OpenOCD
1417 command line using the @option{-c} command line switch.
1419 If this command does not appear in any startup/configuration file
1420 OpenOCD executes the command for you after processing all
1421 configuration files and/or command line options.
1423 @b{NOTE:} This command normally occurs at or near the end of your
1424 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1425 targets ready. For example: If your openocd.cfg file needs to
1426 read/write memory on your target, @command{init} must occur before
1427 the memory read/write commands. This includes @command{nand probe}.
1430 @section TCP/IP Ports
1435 The OpenOCD server accepts remote commands in several syntaxes.
1436 Each syntax uses a different TCP/IP port, which you may specify
1437 only during configuration (before those ports are opened).
1439 For reasons including security, you may wish to prevent remote
1440 access using one or more of these ports.
1441 In such cases, just specify the relevant port number as zero.
1442 If you disable all access through TCP/IP, you will need to
1443 use the command line @option{-pipe} option.
1445 @deffn {Command} gdb_port (number)
1447 Specify or query the first port used for incoming GDB connections.
1448 The GDB port for the
1449 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1450 When not specified during the configuration stage,
1451 the port @var{number} defaults to 3333.
1452 When specified as zero, this port is not activated.
1455 @deffn {Command} tcl_port (number)
1456 Specify or query the port used for a simplified RPC
1457 connection that can be used by clients to issue TCL commands and get the
1458 output from the Tcl engine.
1459 Intended as a machine interface.
1460 When not specified during the configuration stage,
1461 the port @var{number} defaults to 6666.
1462 When specified as zero, this port is not activated.
1465 @deffn {Command} telnet_port (number)
1466 Specify or query the
1467 port on which to listen for incoming telnet connections.
1468 This port is intended for interaction with one human through TCL commands.
1469 When not specified during the configuration stage,
1470 the port @var{number} defaults to 4444.
1471 When specified as zero, this port is not activated.
1474 @anchor{GDB Configuration}
1475 @section GDB Configuration
1477 @cindex GDB configuration
1478 You can reconfigure some GDB behaviors if needed.
1479 The ones listed here are static and global.
1480 @xref{Target Configuration}, about configuring individual targets.
1481 @xref{Target Events}, about configuring target-specific event handling.
1483 @anchor{gdb_breakpoint_override}
1484 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1485 Force breakpoint type for gdb @command{break} commands.
1486 This option supports GDB GUIs which don't
1487 distinguish hard versus soft breakpoints, if the default OpenOCD and
1488 GDB behaviour is not sufficient. GDB normally uses hardware
1489 breakpoints if the memory map has been set up for flash regions.
1492 @deffn {Config command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1493 Configures what OpenOCD will do when GDB detaches from the daemon.
1494 Default behaviour is @option{resume}.
1497 @anchor{gdb_flash_program}
1498 @deffn {Config command} gdb_flash_program (@option{enable}|@option{disable})
1499 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1500 vFlash packet is received.
1501 The default behaviour is @option{enable}.
1504 @deffn {Config command} gdb_memory_map (@option{enable}|@option{disable})
1505 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1506 requested. GDB will then know when to set hardware breakpoints, and program flash
1507 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1508 for flash programming to work.
1509 Default behaviour is @option{enable}.
1510 @xref{gdb_flash_program}.
1513 @deffn {Config command} gdb_report_data_abort (@option{enable}|@option{disable})
1514 Specifies whether data aborts cause an error to be reported
1515 by GDB memory read packets.
1516 The default behaviour is @option{disable};
1517 use @option{enable} see these errors reported.
1520 @anchor{Event Polling}
1521 @section Event Polling
1523 Hardware debuggers are parts of asynchronous systems,
1524 where significant events can happen at any time.
1525 The OpenOCD server needs to detect some of these events,
1526 so it can report them to through TCL command line
1529 Examples of such events include:
1532 @item One of the targets can stop running ... maybe it triggers
1533 a code breakpoint or data watchpoint, or halts itself.
1534 @item Messages may be sent over ``debug message'' channels ... many
1535 targets support such messages sent over JTAG,
1536 for receipt by the person debugging or tools.
1537 @item Loss of power ... some adapters can detect these events.
1538 @item Resets not issued through JTAG ... such reset sources
1539 can include button presses or other system hardware, sometimes
1540 including the target itself (perhaps through a watchdog).
1541 @item Debug instrumentation sometimes supports event triggering
1542 such as ``trace buffer full'' (so it can quickly be emptied)
1543 or other signals (to correlate with code behavior).
1546 None of those events are signaled through standard JTAG signals.
1547 However, most conventions for JTAG connectors include voltage
1548 level and system reset (SRST) signal detection.
1549 Some connectors also include instrumentation signals, which
1550 can imply events when those signals are inputs.
1552 In general, OpenOCD needs to periodically check for those events,
1553 either by looking at the status of signals on the JTAG connector
1554 or by sending synchronous ``tell me your status'' JTAG requests
1555 to the various active targets.
1556 There is a command to manage and monitor that polling,
1557 which is normally done in the background.
1559 @deffn Command poll [@option{on}|@option{off}]
1560 Poll the current target for its current state.
1561 (Also, @pxref{target curstate}.)
1562 If that target is in debug mode, architecture
1563 specific information about the current state is printed.
1564 An optional parameter
1565 allows background polling to be enabled and disabled.
1567 You could use this from the TCL command shell, or
1568 from GDB using @command{monitor poll} command.
1571 background polling: on
1572 target state: halted
1573 target halted in ARM state due to debug-request, \
1574 current mode: Supervisor
1575 cpsr: 0x800000d3 pc: 0x11081bfc
1576 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1581 @node Interface - Dongle Configuration
1582 @chapter Interface - Dongle Configuration
1583 @cindex config file, interface
1584 @cindex interface config file
1586 JTAG Adapters/Interfaces/Dongles are normally configured
1587 through commands in an interface configuration
1588 file which is sourced by your @file{openocd.cfg} file, or
1589 through a command line @option{-f interface/....cfg} option.
1592 source [find interface/olimex-jtag-tiny.cfg]
1596 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1597 A few cases are so simple that you only need to say what driver to use:
1604 Most adapters need a bit more configuration than that.
1607 @section Interface Configuration
1609 The interface command tells OpenOCD what type of JTAG dongle you are
1610 using. Depending on the type of dongle, you may need to have one or
1611 more additional commands.
1613 @deffn {Config Command} {interface} name
1614 Use the interface driver @var{name} to connect to the
1618 @deffn Command {interface_list}
1619 List the interface drivers that have been built into
1620 the running copy of OpenOCD.
1623 @deffn Command {jtag interface}
1624 Returns the name of the interface driver being used.
1627 @section Interface Drivers
1629 Each of the interface drivers listed here must be explicitly
1630 enabled when OpenOCD is configured, in order to be made
1631 available at run time.
1633 @deffn {Interface Driver} {amt_jtagaccel}
1634 Amontec Chameleon in its JTAG Accelerator configuration,
1635 connected to a PC's EPP mode parallel port.
1636 This defines some driver-specific commands:
1638 @deffn {Config Command} {parport_port} number
1639 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1640 the number of the @file{/dev/parport} device.
1643 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1644 Displays status of RTCK option.
1645 Optionally sets that option first.
1649 @deffn {Interface Driver} {arm-jtag-ew}
1650 Olimex ARM-JTAG-EW USB adapter
1651 This has one driver-specific command:
1653 @deffn Command {armjtagew_info}
1658 @deffn {Interface Driver} {at91rm9200}
1659 Supports bitbanged JTAG from the local system,
1660 presuming that system is an Atmel AT91rm9200
1661 and a specific set of GPIOs is used.
1662 @c command: at91rm9200_device NAME
1663 @c chooses among list of bit configs ... only one option
1666 @deffn {Interface Driver} {dummy}
1667 A dummy software-only driver for debugging.
1670 @deffn {Interface Driver} {ep93xx}
1671 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1674 @deffn {Interface Driver} {ft2232}
1675 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1676 These interfaces have several commands, used to configure the driver
1677 before initializing the JTAG scan chain:
1679 @deffn {Config Command} {ft2232_device_desc} description
1680 Provides the USB device description (the @emph{iProduct string})
1681 of the FTDI FT2232 device. If not
1682 specified, the FTDI default value is used. This setting is only valid
1683 if compiled with FTD2XX support.
1686 @deffn {Config Command} {ft2232_serial} serial-number
1687 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1688 in case the vendor provides unique IDs and more than one FT2232 device
1689 is connected to the host.
1690 If not specified, serial numbers are not considered.
1693 @deffn {Config Command} {ft2232_layout} name
1694 Each vendor's FT2232 device can use different GPIO signals
1695 to control output-enables, reset signals, and LEDs.
1696 Currently valid layout @var{name} values include:
1698 @item @b{axm0432_jtag} Axiom AXM-0432
1699 @item @b{comstick} Hitex STR9 comstick
1700 @item @b{cortino} Hitex Cortino JTAG interface
1701 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1702 either for the local Cortex-M3 (SRST only)
1703 or in a passthrough mode (neither SRST nor TRST)
1704 @item @b{flyswatter} Tin Can Tools Flyswatter
1705 @item @b{icebear} ICEbear JTAG adapter from Section 5
1706 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1707 @item @b{m5960} American Microsystems M5960
1708 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1709 @item @b{oocdlink} OOCDLink
1710 @c oocdlink ~= jtagkey_prototype_v1
1711 @item @b{sheevaplug} Marvell Sheevaplug development kit
1712 @item @b{signalyzer} Xverve Signalyzer
1713 @item @b{stm32stick} Hitex STM32 Performance Stick
1714 @item @b{turtelizer2} egnite Software turtelizer2
1715 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1719 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1720 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1721 default values are used.
1722 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1724 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1728 @deffn {Config Command} {ft2232_latency} ms
1729 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1730 ft2232_read() fails to return the expected number of bytes. This can be caused by
1731 USB communication delays and has proved hard to reproduce and debug. Setting the
1732 FT2232 latency timer to a larger value increases delays for short USB packets but it
1733 also reduces the risk of timeouts before receiving the expected number of bytes.
1734 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1737 For example, the interface config file for a
1738 Turtelizer JTAG Adapter looks something like this:
1742 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1743 ft2232_layout turtelizer2
1744 ft2232_vid_pid 0x0403 0xbdc8
1748 @deffn {Interface Driver} {gw16012}
1749 Gateworks GW16012 JTAG programmer.
1750 This has one driver-specific command:
1752 @deffn {Config Command} {parport_port} number
1753 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1754 the number of the @file{/dev/parport} device.
1758 @deffn {Interface Driver} {jlink}
1759 Segger jlink USB adapter
1760 @c command: jlink_info
1762 @c command: jlink_hw_jtag (2|3)
1763 @c sets version 2 or 3
1766 @deffn {Interface Driver} {parport}
1767 Supports PC parallel port bit-banging cables:
1768 Wigglers, PLD download cable, and more.
1769 These interfaces have several commands, used to configure the driver
1770 before initializing the JTAG scan chain:
1772 @deffn {Config Command} {parport_cable} name
1773 The layout of the parallel port cable used to connect to the target.
1774 Currently valid cable @var{name} values include:
1777 @item @b{altium} Altium Universal JTAG cable.
1778 @item @b{arm-jtag} Same as original wiggler except SRST and
1779 TRST connections reversed and TRST is also inverted.
1780 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1781 in configuration mode. This is only used to
1782 program the Chameleon itself, not a connected target.
1783 @item @b{dlc5} The Xilinx Parallel cable III.
1784 @item @b{flashlink} The ST Parallel cable.
1785 @item @b{lattice} Lattice ispDOWNLOAD Cable
1786 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1788 Amontec's Chameleon Programmer. The new version available from
1789 the website uses the original Wiggler layout ('@var{wiggler}')
1790 @item @b{triton} The parallel port adapter found on the
1791 ``Karo Triton 1 Development Board''.
1792 This is also the layout used by the HollyGates design
1793 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1794 @item @b{wiggler} The original Wiggler layout, also supported by
1795 several clones, such as the Olimex ARM-JTAG
1796 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1797 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1801 @deffn {Config Command} {parport_port} number
1802 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1803 the @file{/dev/parport} device
1805 When using PPDEV to access the parallel port, use the number of the parallel port:
1806 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1807 you may encounter a problem.
1810 @deffn {Config Command} {parport_write_on_exit} (on|off)
1811 This will configure the parallel driver to write a known
1812 cable-specific value to the parallel interface on exiting OpenOCD
1815 For example, the interface configuration file for a
1816 classic ``Wiggler'' cable might look something like this:
1821 parport_cable wiggler
1825 @deffn {Interface Driver} {presto}
1826 ASIX PRESTO USB JTAG programmer.
1827 @c command: presto_serial str
1828 @c sets serial number
1831 @deffn {Interface Driver} {rlink}
1832 Raisonance RLink USB adapter
1835 @deffn {Interface Driver} {usbprog}
1836 usbprog is a freely programmable USB adapter.
1839 @deffn {Interface Driver} {vsllink}
1840 vsllink is part of Versaloon which is a versatile USB programmer.
1843 This defines quite a few driver-specific commands,
1844 which are not currently documented here.
1848 @deffn {Interface Driver} {ZY1000}
1849 This is the Zylin ZY1000 JTAG debugger.
1852 This defines some driver-specific commands,
1853 which are not currently documented here.
1856 @deffn Command power [@option{on}|@option{off}]
1857 Turn power switch to target on/off.
1858 No arguments: print status.
1865 JTAG clock setup is part of system setup.
1866 It @emph{does not belong with interface setup} since any interface
1867 only knows a few of the constraints for the JTAG clock speed.
1868 Sometimes the JTAG speed is
1869 changed during the target initialization process: (1) slow at
1870 reset, (2) program the CPU clocks, (3) run fast.
1871 Both the "slow" and "fast" clock rates are functions of the
1872 oscillators used, the chip, the board design, and sometimes
1873 power management software that may be active.
1875 The speed used during reset can be adjusted using pre_reset
1876 and post_reset event handlers.
1877 @xref{Target Events}.
1879 If your system supports adaptive clocking (RTCK), configuring
1880 JTAG to use that is probably the most robust approach.
1881 However, it introduces delays to synchronize clocks; so it
1882 may not be the fastest solution.
1884 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1885 instead of @command{jtag_khz}.
1887 @deffn {Command} jtag_khz max_speed_kHz
1888 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1889 JTAG interfaces usually support a limited number of
1890 speeds. The speed actually used won't be faster
1891 than the speed specified.
1893 As a rule of thumb, if you specify a clock rate make
1894 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1895 This is especially true for synthesized cores (ARMxxx-S).
1897 Speed 0 (khz) selects RTCK method.
1899 If your system uses RTCK, you won't need to change the
1900 JTAG clocking after setup.
1901 Not all interfaces, boards, or targets support ``rtck''.
1902 If the interface device can not
1903 support it, an error is returned when you try to use RTCK.
1906 @defun jtag_rclk fallback_speed_kHz
1908 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1909 If that fails (maybe the interface, board, or target doesn't
1910 support it), falls back to the specified frequency.
1912 # Fall back to 3mhz if RTCK is not supported
1917 @node Reset Configuration
1918 @chapter Reset Configuration
1919 @cindex Reset Configuration
1921 Every system configuration may require a different reset
1922 configuration. This can also be quite confusing.
1923 Resets also interact with @var{reset-init} event handlers,
1924 which do things like setting up clocks and DRAM, and
1925 JTAG clock rates. (@xref{JTAG Speed}.)
1926 They can also interact with JTAG routers.
1927 Please see the various board files for examples.
1930 To maintainers and integrators:
1931 Reset configuration touches several things at once.
1932 Normally the board configuration file
1933 should define it and assume that the JTAG adapter supports
1934 everything that's wired up to the board's JTAG connector.
1936 However, the target configuration file could also make note
1937 of something the silicon vendor has done inside the chip,
1938 which will be true for most (or all) boards using that chip.
1939 And when the JTAG adapter doesn't support everything, the
1940 user configuration file will need to override parts of
1941 the reset configuration provided by other files.
1944 @section Types of Reset
1946 There are many kinds of reset possible through JTAG, but
1947 they may not all work with a given board and adapter.
1948 That's part of why reset configuration can be error prone.
1952 @emph{System Reset} ... the @emph{SRST} hardware signal
1953 resets all chips connected to the JTAG adapter, such as processors,
1954 power management chips, and I/O controllers. Normally resets triggered
1955 with this signal behave exactly like pressing a RESET button.
1957 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1958 just the TAP controllers connected to the JTAG adapter.
1959 Such resets should not be visible to the rest of the system; resetting a
1960 device's the TAP controller just puts that controller into a known state.
1962 @emph{Emulation Reset} ... many devices can be reset through JTAG
1963 commands. These resets are often distinguishable from system
1964 resets, either explicitly (a "reset reason" register says so)
1965 or implicitly (not all parts of the chip get reset).
1967 @emph{Other Resets} ... system-on-chip devices often support
1968 several other types of reset.
1969 You may need to arrange that a watchdog timer stops
1970 while debugging, preventing a watchdog reset.
1971 There may be individual module resets.
1974 In the best case, OpenOCD can hold SRST, then reset
1975 the TAPs via TRST and send commands through JTAG to halt the
1976 CPU at the reset vector before the 1st instruction is executed.
1977 Then when it finally releases the SRST signal, the system is
1978 halted under debugger control before any code has executed.
1979 This is the behavior required to support the @command{reset halt}
1980 and @command{reset init} commands; after @command{reset init} a
1981 board-specific script might do things like setting up DRAM.
1982 (@xref{Reset Command}.)
1984 @anchor{SRST and TRST Issues}
1985 @section SRST and TRST Issues
1987 Because SRST and TRST are hardware signals, they can have a
1988 variety of system-specific constraints. Some of the most
1993 @item @emph{Signal not available} ... Some boards don't wire
1994 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1995 support such signals even if they are wired up.
1996 Use the @command{reset_config} @var{signals} options to say
1997 when either of those signals is not connected.
1998 When SRST is not available, your code might not be able to rely
1999 on controllers having been fully reset during code startup.
2000 Missing TRST is not a problem, since JTAG level resets can
2001 be triggered using with TMS signaling.
2003 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2004 adapter will connect SRST to TRST, instead of keeping them separate.
2005 Use the @command{reset_config} @var{combination} options to say
2006 when those signals aren't properly independent.
2008 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2009 delay circuit, reset supervisor, or on-chip features can extend
2010 the effect of a JTAG adapter's reset for some time after the adapter
2011 stops issuing the reset. For example, there may be chip or board
2012 requirements that all reset pulses last for at least a
2013 certain amount of time; and reset buttons commonly have
2014 hardware debouncing.
2015 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2016 commands to say when extra delays are needed.
2018 @item @emph{Drive type} ... Reset lines often have a pullup
2019 resistor, letting the JTAG interface treat them as open-drain
2020 signals. But that's not a requirement, so the adapter may need
2021 to use push/pull output drivers.
2022 Also, with weak pullups it may be advisable to drive
2023 signals to both levels (push/pull) to minimize rise times.
2024 Use the @command{reset_config} @var{trst_type} and
2025 @var{srst_type} parameters to say how to drive reset signals.
2027 @item @emph{Special initialization} ... Targets sometimes need
2028 special JTAG initialization sequences to handle chip-specific
2029 issues (not limited to errata).
2030 For example, certain JTAG commands might need to be issued while
2031 the system as a whole is in a reset state (SRST active)
2032 but the JTAG scan chain is usable (TRST inactive).
2033 (@xref{JTAG Commands}, where the @command{jtag_reset}
2034 command is presented.)
2037 There can also be other issues.
2038 Some devices don't fully conform to the JTAG specifications.
2039 Trivial system-specific differences are common, such as
2040 SRST and TRST using slightly different names.
2041 There are also vendors who distribute key JTAG documentation for
2042 their chips only to developers who have signed a Non-Disclosure
2045 Sometimes there are chip-specific extensions like a requirement to use
2046 the normally-optional TRST signal (precluding use of JTAG adapters which
2047 don't pass TRST through), or needing extra steps to complete a TAP reset.
2049 In short, SRST and especially TRST handling may be very finicky,
2050 needing to cope with both architecture and board specific constraints.
2052 @section Commands for Handling Resets
2054 @deffn {Command} jtag_nsrst_delay milliseconds
2055 How long (in milliseconds) OpenOCD should wait after deasserting
2056 nSRST (active-low system reset) before starting new JTAG operations.
2057 When a board has a reset button connected to SRST line it will
2058 probably have hardware debouncing, implying you should use this.
2061 @deffn {Command} jtag_ntrst_delay milliseconds
2062 How long (in milliseconds) OpenOCD should wait after deasserting
2063 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2066 @deffn {Command} reset_config mode_flag ...
2067 This command tells OpenOCD the reset configuration
2068 of your combination of JTAG board and target in target
2069 configuration scripts.
2071 Information earlier in this section describes the kind of problems
2072 the command is intended to address (@pxref{SRST and TRST Issues}).
2073 As a rule this command belongs only in board config files,
2074 describing issues like @emph{board doesn't connect TRST};
2075 or in user config files, addressing limitations derived
2076 from a particular combination of interface and board.
2077 (An unlikely example would be using a TRST-only adapter
2078 with a board that only wires up SRST.)
2080 The @var{mode_flag} options can be specified in any order, but only one
2081 of each type -- @var{signals}, @var{combination}, @var{trst_type},
2082 and @var{srst_type} -- may be specified at a time.
2083 If you don't provide a new value for a given type, its previous
2084 value (perhaps the default) is unchanged.
2085 For example, this means that you don't need to say anything at all about
2086 TRST just to declare that if the JTAG adapter should want to drive SRST,
2087 it must explicitly be driven high (@option{srst_push_pull}).
2089 @var{signals} can specify which of the reset signals are connected.
2090 For example, If the JTAG interface provides SRST, but the board doesn't
2091 connect that signal properly, then OpenOCD can't use it.
2092 Possible values are @option{none} (the default), @option{trst_only},
2093 @option{srst_only} and @option{trst_and_srst}.
2096 If your board provides SRST or TRST through the JTAG connector,
2097 you must declare that or else those signals will not be used.
2100 The @var{combination} is an optional value specifying broken reset
2101 signal implementations.
2102 The default behaviour if no option given is @option{separate},
2103 indicating everything behaves normally.
2104 @option{srst_pulls_trst} states that the
2105 test logic is reset together with the reset of the system (e.g. Philips
2106 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2107 the system is reset together with the test logic (only hypothetical, I
2108 haven't seen hardware with such a bug, and can be worked around).
2109 @option{combined} implies both @option{srst_pulls_trst} and
2110 @option{trst_pulls_srst}.
2112 The optional @var{trst_type} and @var{srst_type} parameters allow the
2113 driver mode of each reset line to be specified. These values only affect
2114 JTAG interfaces with support for different driver modes, like the Amontec
2115 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2116 relevant signal (TRST or SRST) is not connected.
2118 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2119 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2120 Most boards connect this signal to a pulldown, so the JTAG TAPs
2121 never leave reset unless they are hooked up to a JTAG adapter.
2123 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2124 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2125 Most boards connect this signal to a pullup, and allow the
2126 signal to be pulled low by various events including system
2127 powerup and pressing a reset button.
2131 @node TAP Declaration
2132 @chapter TAP Declaration
2133 @cindex TAP declaration
2134 @cindex TAP configuration
2136 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2137 TAPs serve many roles, including:
2140 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2141 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2142 Others do it indirectly, making a CPU do it.
2143 @item @b{Program Download} Using the same CPU support GDB uses,
2144 you can initialize a DRAM controller, download code to DRAM, and then
2145 start running that code.
2146 @item @b{Boundary Scan} Most chips support boundary scan, which
2147 helps test for board assembly problems like solder bridges
2148 and missing connections
2151 OpenOCD must know about the active TAPs on your board(s).
2152 Setting up the TAPs is the core task of your configuration files.
2153 Once those TAPs are set up, you can pass their names to code
2154 which sets up CPUs and exports them as GDB targets,
2155 probes flash memory, performs low-level JTAG operations, and more.
2157 @section Scan Chains
2160 TAPs are part of a hardware @dfn{scan chain},
2161 which is daisy chain of TAPs.
2162 They also need to be added to
2163 OpenOCD's software mirror of that hardware list,
2164 giving each member a name and associating other data with it.
2165 Simple scan chains, with a single TAP, are common in
2166 systems with a single microcontroller or microprocessor.
2167 More complex chips may have several TAPs internally.
2168 Very complex scan chains might have a dozen or more TAPs:
2169 several in one chip, more in the next, and connecting
2170 to other boards with their own chips and TAPs.
2172 You can display the list with the @command{scan_chain} command.
2173 (Don't confuse this with the list displayed by the @command{targets}
2174 command, presented in the next chapter.
2175 That only displays TAPs for CPUs which are configured as
2177 Here's what the scan chain might look like for a chip more than one TAP:
2180 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2181 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2182 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2183 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2184 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2187 Unfortunately those TAPs can't always be autoconfigured,
2188 because not all devices provide good support for that.
2189 JTAG doesn't require supporting IDCODE instructions, and
2190 chips with JTAG routers may not link TAPs into the chain
2191 until they are told to do so.
2193 The configuration mechanism currently supported by OpenOCD
2194 requires explicit configuration of all TAP devices using
2195 @command{jtag newtap} commands, as detailed later in this chapter.
2196 A command like this would declare one tap and name it @code{chip1.cpu}:
2199 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2202 Each target configuration file lists the TAPs provided
2204 Board configuration files combine all the targets on a board,
2206 Note that @emph{the order in which TAPs are declared is very important.}
2207 It must match the order in the JTAG scan chain, both inside
2208 a single chip and between them.
2209 @xref{FAQ TAP Order}.
2211 For example, the ST Microsystems STR912 chip has
2212 three separate TAPs@footnote{See the ST
2213 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2214 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2215 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2216 To configure those taps, @file{target/str912.cfg}
2217 includes commands something like this:
2220 jtag newtap str912 flash ... params ...
2221 jtag newtap str912 cpu ... params ...
2222 jtag newtap str912 bs ... params ...
2225 Actual config files use a variable instead of literals like
2226 @option{str912}, to support more than one chip of each type.
2227 @xref{Config File Guidelines}.
2229 At this writing there is only a single command to work with
2230 scan chains, and there is no support for enumerating
2231 TAPs or examining their attributes.
2233 @deffn Command {scan_chain}
2234 Displays the TAPs in the scan chain configuration,
2236 The set of TAPs listed by this command is fixed by
2237 exiting the OpenOCD configuration stage,
2238 but systems with a JTAG router can
2239 enable or disable TAPs dynamically.
2240 In addition to the enable/disable status, the contents of
2241 each TAP's instruction register can also change.
2244 @c FIXME! there should be commands to enumerate TAPs
2245 @c and get their attributes, like there are for targets.
2246 @c "jtag cget ..." will handle attributes.
2247 @c "jtag names" for enumerating TAPs, maybe.
2249 @c Probably want "jtag eventlist", and a "tap-reset" event
2250 @c (on entry to RESET state).
2255 When TAP objects are declared with @command{jtag newtap},
2256 a @dfn{dotted.name} is created for the TAP, combining the
2257 name of a module (usually a chip) and a label for the TAP.
2258 For example: @code{xilinx.tap}, @code{str912.flash},
2259 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2260 Many other commands use that dotted.name to manipulate or
2261 refer to the TAP. For example, CPU configuration uses the
2262 name, as does declaration of NAND or NOR flash banks.
2264 The components of a dotted name should follow ``C'' symbol
2265 name rules: start with an alphabetic character, then numbers
2266 and underscores are OK; while others (including dots!) are not.
2269 In older code, JTAG TAPs were numbered from 0..N.
2270 This feature is still present.
2271 However its use is highly discouraged, and
2272 should not be counted upon.
2273 Update all of your scripts to use TAP names rather than numbers.
2274 Using TAP numbers in target configuration scripts prevents
2275 reusing those scripts on boards with multiple targets.
2278 @section TAP Declaration Commands
2280 @c shouldn't this be(come) a {Config Command}?
2281 @anchor{jtag newtap}
2282 @deffn Command {jtag newtap} chipname tapname configparams...
2283 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2284 and configured according to the various @var{configparams}.
2286 The @var{chipname} is a symbolic name for the chip.
2287 Conventionally target config files use @code{$_CHIPNAME},
2288 defaulting to the model name given by the chip vendor but
2291 @cindex TAP naming convention
2292 The @var{tapname} reflects the role of that TAP,
2293 and should follow this convention:
2296 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2297 @item @code{cpu} -- The main CPU of the chip, alternatively
2298 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2299 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2300 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2301 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2302 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2303 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2304 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2306 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2307 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2308 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2309 a JTAG TAP; that TAP should be named @code{sdma}.
2312 Every TAP requires at least the following @var{configparams}:
2315 @item @code{-ircapture} @var{NUMBER}
2316 @*The IDCODE capture command, such as 0x01.
2317 @item @code{-irlen} @var{NUMBER}
2318 @*The length in bits of the
2319 instruction register, such as 4 or 5 bits.
2320 @item @code{-irmask} @var{NUMBER}
2321 @*A mask for the IR register.
2322 For some devices, there are bits in the IR that aren't used.
2323 This lets OpenOCD mask them off when doing IDCODE comparisons.
2324 In general, this should just be all ones for the size of the IR.
2327 A TAP may also provide optional @var{configparams}:
2330 @item @code{-disable} (or @code{-enable})
2331 @*Use the @code{-disable} parameter to flag a TAP which is not
2332 linked in to the scan chain after a reset using either TRST
2333 or the JTAG state machine's @sc{reset} state.
2334 You may use @code{-enable} to highlight the default state
2335 (the TAP is linked in).
2336 @xref{Enabling and Disabling TAPs}.
2337 @item @code{-expected-id} @var{number}
2338 @*A non-zero value represents the expected 32-bit IDCODE
2339 found when the JTAG chain is examined.
2340 These codes are not required by all JTAG devices.
2341 @emph{Repeat the option} as many times as required if more than one
2342 ID code could appear (for example, multiple versions).
2346 @c @deffn Command {jtag arp_init-reset}
2347 @c ... more or less "init" ?
2349 @anchor{Enabling and Disabling TAPs}
2350 @section Enabling and Disabling TAPs
2352 @cindex JTAG Route Controller
2355 In some systems, a @dfn{JTAG Route Controller} (JRC)
2356 is used to enable and/or disable specific JTAG TAPs.
2357 Many ARM based chips from Texas Instruments include
2358 an ``ICEpick'' module, which is a JRC.
2359 Such chips include DaVinci and OMAP3 processors.
2361 A given TAP may not be visible until the JRC has been
2362 told to link it into the scan chain; and if the JRC
2363 has been told to unlink that TAP, it will no longer
2365 Such routers address problems that JTAG ``bypass mode''
2369 @item The scan chain can only go as fast as its slowest TAP.
2370 @item Having many TAPs slows instruction scans, since all
2371 TAPs receive new instructions.
2372 @item TAPs in the scan chain must be powered up, which wastes
2373 power and prevents debugging some power management mechanisms.
2376 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2377 as implied by the existence of JTAG routers.
2378 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2379 does include a kind of JTAG router functionality.
2381 @c (a) currently the event handlers don't seem to be able to
2382 @c fail in a way that could lead to no-change-of-state.
2383 @c (b) eventually non-event configuration should be possible,
2384 @c in which case some this documentation must move.
2386 @deffn Command {jtag cget} dotted.name @option{-event} name
2387 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2388 At this writing this mechanism is used only for event handling,
2389 and the only two events relate to TAP enabling and disabling.
2391 The @code{configure} subcommand assigns an event handler,
2392 a TCL string which is evaluated when the event is triggered.
2393 The @code{cget} subcommand returns that handler.
2394 The two possible values for an event @var{name}
2395 are @option{tap-disable} and @option{tap-enable}.
2397 So for example, when defining a TAP for a CPU connected to
2398 a JTAG router, you should define TAP event handlers using
2399 code that looks something like this:
2402 jtag configure CHIP.cpu -event tap-enable @{
2403 echo "Enabling CPU TAP"
2404 ... jtag operations using CHIP.jrc
2406 jtag configure CHIP.cpu -event tap-disable @{
2407 echo "Disabling CPU TAP"
2408 ... jtag operations using CHIP.jrc
2413 @deffn Command {jtag tapdisable} dotted.name
2414 @deffnx Command {jtag tapenable} dotted.name
2415 @deffnx Command {jtag tapisenabled} dotted.name
2416 These three commands all return the string "1" if the tap
2417 specified by @var{dotted.name} is enabled,
2418 and "0" if it is disbabled.
2419 The @command{tapenable} variant first enables the tap
2420 by sending it a @option{tap-enable} event.
2421 The @command{tapdisable} variant first disables the tap
2422 by sending it a @option{tap-disable} event.
2425 Humans will find the @command{scan_chain} command more helpful
2426 than the script-oriented @command{tapisenabled}
2427 for querying the state of the JTAG taps.
2431 @node CPU Configuration
2432 @chapter CPU Configuration
2435 This chapter discusses how to set up GDB debug targets for CPUs.
2436 You can also access these targets without GDB
2437 (@pxref{Architecture and Core Commands},
2438 and @ref{Target State handling}) and
2439 through various kinds of NAND and NOR flash commands.
2440 If you have multiple CPUs you can have multiple such targets.
2442 We'll start by looking at how to examine the targets you have,
2443 then look at how to add one more target and how to configure it.
2445 @section Target List
2446 @cindex target, current
2447 @cindex target, list
2449 All targets that have been set up are part of a list,
2450 where each member has a name.
2451 That name should normally be the same as the TAP name.
2452 You can display the list with the @command{targets}
2454 This display often has only one CPU; here's what it might
2455 look like with more than one:
2457 TargetName Type Endian TapName State
2458 -- ------------------ ---------- ------ ------------------ ------------
2459 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2460 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2463 One member of that list is the @dfn{current target}, which
2464 is implicitly referenced by many commands.
2465 It's the one marked with a @code{*} near the target name.
2466 In particular, memory addresses often refer to the address
2467 space seen by that current target.
2468 Commands like @command{mdw} (memory display words)
2469 and @command{flash erase_address} (erase NOR flash blocks)
2470 are examples; and there are many more.
2472 Several commands let you examine the list of targets:
2474 @deffn Command {target count}
2475 Returns the number of targets, @math{N}.
2476 The highest numbered target is @math{N - 1}.
2478 set c [target count]
2479 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2480 # Assuming you have created this function
2481 print_target_details $x
2486 @deffn Command {target current}
2487 Returns the name of the current target.
2490 @deffn Command {target names}
2491 Lists the names of all current targets in the list.
2493 foreach t [target names] @{
2494 puts [format "Target: %s\n" $t]
2499 @deffn Command {target number} number
2500 The list of targets is numbered starting at zero.
2501 This command returns the name of the target at index @var{number}.
2503 set thename [target number $x]
2504 puts [format "Target %d is: %s\n" $x $thename]
2508 @c yep, "target list" would have been better.
2509 @c plus maybe "target setdefault".
2511 @deffn Command targets [name]
2512 @emph{Note: the name of this command is plural. Other target
2513 command names are singular.}
2515 With no parameter, this command displays a table of all known
2516 targets in a user friendly form.
2518 With a parameter, this command sets the current target to
2519 the given target with the given @var{name}; this is
2520 only relevant on boards which have more than one target.
2523 @section Target CPU Types and Variants
2528 Each target has a @dfn{CPU type}, as shown in the output of
2529 the @command{targets} command. You need to specify that type
2530 when calling @command{target create}.
2531 The CPU type indicates more than just the instruction set.
2532 It also indicates how that instruction set is implemented,
2533 what kind of debug support it integrates,
2534 whether it has an MMU (and if so, what kind),
2535 what core-specific commands may be available
2536 (@pxref{Architecture and Core Commands}),
2539 For some CPU types, OpenOCD also defines @dfn{variants} which
2540 indicate differences that affect their handling.
2541 For example, a particular implementation bug might need to be
2542 worked around in some chip versions.
2544 It's easy to see what target types are supported,
2545 since there's a command to list them.
2546 However, there is currently no way to list what target variants
2547 are supported (other than by reading the OpenOCD source code).
2549 @anchor{target types}
2550 @deffn Command {target types}
2551 Lists all supported target types.
2552 At this writing, the supported CPU types and variants are:
2555 @item @code{arm11} -- this is a generation of ARMv6 cores
2556 @item @code{arm720t} -- this is an ARMv4 core
2557 @item @code{arm7tdmi} -- this is an ARMv4 core
2558 @item @code{arm920t} -- this is an ARMv5 core
2559 @item @code{arm926ejs} -- this is an ARMv5 core
2560 @item @code{arm966e} -- this is an ARMv5 core
2561 @item @code{arm9tdmi} -- this is an ARMv4 core
2562 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2563 (Support for this is preliminary and incomplete.)
2564 @item @code{cortex_a8} -- this is an ARMv7 core
2565 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2566 compact Thumb2 instruction set. It supports one variant:
2568 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2569 This will cause OpenOCD to use a software reset rather than asserting
2570 SRST, to avoid a issue with clearing the debug registers.
2571 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2572 be detected and the normal reset behaviour used.
2574 @item @code{feroceon} -- resembles arm926
2575 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2577 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2578 provide a functional SRST line on the EJTAG connector. This causes
2579 OpenOCD to instead use an EJTAG software reset command to reset the
2581 You still need to enable @option{srst} on the @command{reset_config}
2582 command to enable OpenOCD hardware reset functionality.
2584 @item @code{xscale} -- this is actually an architecture,
2585 not a CPU type. It is based on the ARMv5 architecture.
2586 There are several variants defined:
2588 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2589 @code{pxa27x} ... instruction register length is 7 bits
2590 @item @code{pxa250}, @code{pxa255},
2591 @code{pxa26x} ... instruction register length is 5 bits
2596 To avoid being confused by the variety of ARM based cores, remember
2597 this key point: @emph{ARM is a technology licencing company}.
2598 (See: @url{http://www.arm.com}.)
2599 The CPU name used by OpenOCD will reflect the CPU design that was
2600 licenced, not a vendor brand which incorporates that design.
2601 Name prefixes like arm7, arm9, arm11, and cortex
2602 reflect design generations;
2603 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2604 reflect an architecture version implemented by a CPU design.
2606 @anchor{Target Configuration}
2607 @section Target Configuration
2609 Before creating a ``target'', you must have added its TAP to the scan chain.
2610 When you've added that TAP, you will have a @code{dotted.name}
2611 which is used to set up the CPU support.
2612 The chip-specific configuration file will normally configure its CPU(s)
2613 right after it adds all of the chip's TAPs to the scan chain.
2615 Although you can set up a target in one step, it's often clearer if you
2616 use shorter commands and do it in two steps: create it, then configure
2618 All operations on the target after it's created will use a new
2619 command, created as part of target creation.
2621 The two main things to configure after target creation are
2622 a work area, which usually has target-specific defaults even
2623 if the board setup code overrides them later;
2624 and event handlers (@pxref{Target Events}), which tend
2625 to be much more board-specific.
2626 The key steps you use might look something like this
2629 target create MyTarget cortex_m3 -chain-position mychip.cpu
2630 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2631 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2632 $MyTarget configure -event reset-init @{ myboard_reinit @}
2635 You should specify a working area if you can; typically it uses some
2637 Such a working area can speed up many things, including bulk
2638 writes to target memory;
2639 flash operations like checking to see if memory needs to be erased;
2640 GDB memory checksumming;
2644 On more complex chips, the work area can become
2645 inaccessible when application code
2646 (such as an operating system)
2647 enables or disables the MMU.
2648 For example, the particular MMU context used to acess the virtual
2649 address will probably matter ... and that context might not have
2650 easy access to other addresses needed.
2651 At this writing, OpenOCD doesn't have much MMU intelligence.
2654 It's often very useful to define a @code{reset-init} event handler.
2655 For systems that are normally used with a boot loader,
2656 common tasks include updating clocks and initializing memory
2658 That may be needed to let you write the boot loader into flash,
2659 in order to ``de-brick'' your board; or to load programs into
2660 external DDR memory without having run the boot loader.
2662 @deffn Command {target create} target_name type configparams...
2663 This command creates a GDB debug target that refers to a specific JTAG tap.
2664 It enters that target into a list, and creates a new
2665 command (@command{@var{target_name}}) which is used for various
2666 purposes including additional configuration.
2669 @item @var{target_name} ... is the name of the debug target.
2670 By convention this should be the same as the @emph{dotted.name}
2671 of the TAP associated with this target, which must be specified here
2672 using the @code{-chain-position @var{dotted.name}} configparam.
2674 This name is also used to create the target object command,
2675 referred to here as @command{$target_name},
2676 and in other places the target needs to be identified.
2677 @item @var{type} ... specifies the target type. @xref{target types}.
2678 @item @var{configparams} ... all parameters accepted by
2679 @command{$target_name configure} are permitted.
2680 If the target is big-endian, set it here with @code{-endian big}.
2681 If the variant matters, set it here with @code{-variant}.
2683 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2687 @deffn Command {$target_name configure} configparams...
2688 The options accepted by this command may also be
2689 specified as parameters to @command{target create}.
2690 Their values can later be queried one at a time by
2691 using the @command{$target_name cget} command.
2693 @emph{Warning:} changing some of these after setup is dangerous.
2694 For example, moving a target from one TAP to another;
2695 and changing its endianness or variant.
2699 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2700 used to access this target.
2702 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2703 whether the CPU uses big or little endian conventions
2705 @item @code{-event} @var{event_name} @var{event_body} --
2706 @xref{Target Events}.
2707 Note that this updates a list of named event handlers.
2708 Calling this twice with two different event names assigns
2709 two different handlers, but calling it twice with the
2710 same event name assigns only one handler.
2712 @item @code{-variant} @var{name} -- specifies a variant of the target,
2713 which OpenOCD needs to know about.
2715 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2716 whether the work area gets backed up; by default, it doesn't.
2717 When possible, use a working_area that doesn't need to be backed up,
2718 since performing a backup slows down operations.
2720 @item @code{-work-area-size} @var{size} -- specify/set the work area
2722 @item @code{-work-area-phys} @var{address} -- set the work area
2723 base @var{address} to be used when no MMU is active.
2725 @item @code{-work-area-virt} @var{address} -- set the work area
2726 base @var{address} to be used when an MMU is active.
2731 @section Other $target_name Commands
2732 @cindex object command
2734 The Tcl/Tk language has the concept of object commands,
2735 and OpenOCD adopts that same model for targets.
2737 A good Tk example is a on screen button.
2738 Once a button is created a button
2739 has a name (a path in Tk terms) and that name is useable as a first
2740 class command. For example in Tk, one can create a button and later
2741 configure it like this:
2745 button .foobar -background red -command @{ foo @}
2747 .foobar configure -foreground blue
2749 set x [.foobar cget -background]
2751 puts [format "The button is %s" $x]
2754 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2755 button, and its object commands are invoked the same way.
2758 str912.cpu mww 0x1234 0x42
2759 omap3530.cpu mww 0x5555 123
2762 The commands supported by OpenOCD target objects are:
2764 @deffn Command {$target_name arp_examine}
2765 @deffnx Command {$target_name arp_halt}
2766 @deffnx Command {$target_name arp_poll}
2767 @deffnx Command {$target_name arp_reset}
2768 @deffnx Command {$target_name arp_waitstate}
2769 Internal OpenOCD scripts (most notably @file{startup.tcl})
2770 use these to deal with specific reset cases.
2771 They are not otherwise documented here.
2774 @deffn Command {$target_name array2mem} arrayname width address count
2775 @deffnx Command {$target_name mem2array} arrayname width address count
2776 These provide an efficient script-oriented interface to memory.
2777 The @code{array2mem} primitive writes bytes, halfwords, or words;
2778 while @code{mem2array} reads them.
2779 In both cases, the TCL side uses an array, and
2780 the target side uses raw memory.
2782 The efficiency comes from enabling the use of
2783 bulk JTAG data transfer operations.
2784 The script orientation comes from working with data
2785 values that are packaged for use by TCL scripts;
2786 @command{mdw} type primitives only print data they retrieve,
2787 and neither store nor return those values.
2790 @item @var{arrayname} ... is the name of an array variable
2791 @item @var{width} ... is 8/16/32 - indicating the memory access size
2792 @item @var{address} ... is the target memory address
2793 @item @var{count} ... is the number of elements to process
2797 @deffn Command {$target_name cget} queryparm
2798 Each configuration parameter accepted by
2799 @command{$target_name configure}
2800 can be individually queried, to return its current value.
2801 The @var{queryparm} is a parameter name
2802 accepted by that command, such as @code{-work-area-phys}.
2803 There are a few special cases:
2806 @item @code{-event} @var{event_name} -- returns the handler for the
2807 event named @var{event_name}.
2808 This is a special case because setting a handler requires
2810 @item @code{-type} -- returns the target type.
2811 This is a special case because this is set using
2812 @command{target create} and can't be changed
2813 using @command{$target_name configure}.
2816 For example, if you wanted to summarize information about
2817 all the targets you might use something like this:
2820 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2821 set name [target number $x]
2822 set y [$name cget -endian]
2823 set z [$name cget -type]
2824 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2830 @anchor{target curstate}
2831 @deffn Command {$target_name curstate}
2832 Displays the current target state:
2833 @code{debug-running},
2836 @code{running}, or @code{unknown}.
2837 (Also, @pxref{Event Polling}.)
2840 @deffn Command {$target_name eventlist}
2841 Displays a table listing all event handlers
2842 currently associated with this target.
2843 @xref{Target Events}.
2846 @deffn Command {$target_name invoke-event} event_name
2847 Invokes the handler for the event named @var{event_name}.
2848 (This is primarily intended for use by OpenOCD framework
2849 code, for example by the reset code in @file{startup.tcl}.)
2852 @deffn Command {$target_name mdw} addr [count]
2853 @deffnx Command {$target_name mdh} addr [count]
2854 @deffnx Command {$target_name mdb} addr [count]
2855 Display contents of address @var{addr}, as
2856 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2857 or 8-bit bytes (@command{mdb}).
2858 If @var{count} is specified, displays that many units.
2859 (If you want to manipulate the data instead of displaying it,
2860 see the @code{mem2array} primitives.)
2863 @deffn Command {$target_name mww} addr word
2864 @deffnx Command {$target_name mwh} addr halfword
2865 @deffnx Command {$target_name mwb} addr byte
2866 Writes the specified @var{word} (32 bits),
2867 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2868 at the specified address @var{addr}.
2871 @anchor{Target Events}
2872 @section Target Events
2874 At various times, certain things can happen, or you want them to happen.
2877 @item What should happen when GDB connects? Should your target reset?
2878 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2879 @item During reset, do you need to write to certain memory locations
2880 to set up system clocks or
2881 to reconfigure the SDRAM?
2884 All of the above items can be addressed by target event handlers.
2885 These are set up by @command{$target_name configure -event} or
2886 @command{target create ... -event}.
2888 The programmer's model matches the @code{-command} option used in Tcl/Tk
2889 buttons and events. The two examples below act the same, but one creates
2890 and invokes a small procedure while the other inlines it.
2893 proc my_attach_proc @{ @} @{
2897 mychip.cpu configure -event gdb-attach my_attach_proc
2898 mychip.cpu configure -event gdb-attach @{
2904 The following target events are defined:
2907 @item @b{debug-halted}
2908 @* The target has halted for debug reasons (i.e.: breakpoint)
2909 @item @b{debug-resumed}
2910 @* The target has resumed (i.e.: gdb said run)
2911 @item @b{early-halted}
2912 @* Occurs early in the halt process
2914 @item @b{examine-end}
2915 @* Currently not used (goal: when JTAG examine completes)
2916 @item @b{examine-start}
2917 @* Currently not used (goal: when JTAG examine starts)
2919 @item @b{gdb-attach}
2920 @* When GDB connects
2921 @item @b{gdb-detach}
2922 @* When GDB disconnects
2924 @* When the target has halted and GDB is not doing anything (see early halt)
2925 @item @b{gdb-flash-erase-start}
2926 @* Before the GDB flash process tries to erase the flash
2927 @item @b{gdb-flash-erase-end}
2928 @* After the GDB flash process has finished erasing the flash
2929 @item @b{gdb-flash-write-start}
2930 @* Before GDB writes to the flash
2931 @item @b{gdb-flash-write-end}
2932 @* After GDB writes to the flash
2934 @* Before the target steps, gdb is trying to start/resume the target
2936 @* The target has halted
2938 @item @b{old-gdb_program_config}
2939 @* DO NOT USE THIS: Used internally
2940 @item @b{old-pre_resume}
2941 @* DO NOT USE THIS: Used internally
2943 @item @b{reset-assert-pre}
2944 @* Issued as part of @command{reset} processing
2945 after SRST and/or TRST were activated and deactivated,
2946 but before reset is asserted on the tap.
2947 @item @b{reset-assert-post}
2948 @* Issued as part of @command{reset} processing
2949 when reset is asserted on the tap.
2950 @item @b{reset-deassert-pre}
2951 @* Issued as part of @command{reset} processing
2952 when reset is about to be released on the tap.
2954 For some chips, this may be a good place to make sure
2955 the JTAG clock is slow enough to work before the PLL
2956 has been set up to allow faster JTAG speeds.
2957 @item @b{reset-deassert-post}
2958 @* Issued as part of @command{reset} processing
2959 when reset has been released on the tap.
2961 @* Issued as the final step in @command{reset} processing.
2963 @item @b{reset-halt-post}
2964 @* Currently not used
2965 @item @b{reset-halt-pre}
2966 @* Currently not used
2968 @item @b{reset-init}
2969 @* Used by @b{reset init} command for board-specific initialization.
2970 This event fires after @emph{reset-deassert-post}.
2972 This is where you would configure PLLs and clocking, set up DRAM so
2973 you can download programs that don't fit in on-chip SRAM, set up pin
2974 multiplexing, and so on.
2975 @item @b{reset-start}
2976 @* Issued as part of @command{reset} processing
2977 before either SRST or TRST are activated.
2979 @item @b{reset-wait-pos}
2980 @* Currently not used
2981 @item @b{reset-wait-pre}
2982 @* Currently not used
2984 @item @b{resume-start}
2985 @* Before any target is resumed
2986 @item @b{resume-end}
2987 @* After all targets have resumed
2991 @* Target has resumed
2995 @node Flash Commands
2996 @chapter Flash Commands
2998 OpenOCD has different commands for NOR and NAND flash;
2999 the ``flash'' command works with NOR flash, while
3000 the ``nand'' command works with NAND flash.
3001 This partially reflects different hardware technologies:
3002 NOR flash usually supports direct CPU instruction and data bus access,
3003 while data from a NAND flash must be copied to memory before it can be
3004 used. (SPI flash must also be copied to memory before use.)
3005 However, the documentation also uses ``flash'' as a generic term;
3006 for example, ``Put flash configuration in board-specific files''.
3010 @item Configure via the command @command{flash bank}
3011 @* Do this in a board-specific configuration file,
3012 passing parameters as needed by the driver.
3013 @item Operate on the flash via @command{flash subcommand}
3014 @* Often commands to manipulate the flash are typed by a human, or run
3015 via a script in some automated way. Common tasks include writing a
3016 boot loader, operating system, or other data.
3018 @* Flashing via GDB requires the flash be configured via ``flash
3019 bank'', and the GDB flash features be enabled.
3020 @xref{GDB Configuration}.
3023 Many CPUs have the ablity to ``boot'' from the first flash bank.
3024 This means that misprograming that bank can ``brick'' a system,
3025 so that it can't boot.
3026 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3027 board by (re)installing working boot firmware.
3029 @section Flash Configuration Commands
3030 @cindex flash configuration
3032 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3033 Configures a flash bank which provides persistent storage
3034 for addresses from @math{base} to @math{base + size - 1}.
3035 These banks will often be visible to GDB through the target's memory map.
3036 In some cases, configuring a flash bank will activate extra commands;
3037 see the driver-specific documentation.
3040 @item @var{driver} ... identifies the controller driver
3041 associated with the flash bank being declared.
3042 This is usually @code{cfi} for external flash, or else
3043 the name of a microcontroller with embedded flash memory.
3044 @xref{Flash Driver List}.
3045 @item @var{base} ... Base address of the flash chip.
3046 @item @var{size} ... Size of the chip, in bytes.
3047 For some drivers, this value is detected from the hardware.
3048 @item @var{chip_width} ... Width of the flash chip, in bytes;
3049 ignored for most microcontroller drivers.
3050 @item @var{bus_width} ... Width of the data bus used to access the
3051 chip, in bytes; ignored for most microcontroller drivers.
3052 @item @var{target} ... Names the target used to issue
3053 commands to the flash controller.
3054 @comment Actually, it's currently a controller-specific parameter...
3055 @item @var{driver_options} ... drivers may support, or require,
3056 additional parameters. See the driver-specific documentation
3057 for more information.
3060 This command is not available after OpenOCD initialization has completed.
3061 Use it in board specific configuration files, not interactively.
3065 @comment the REAL name for this command is "ocd_flash_banks"
3066 @comment less confusing would be: "flash list" (like "nand list")
3067 @deffn Command {flash banks}
3068 Prints a one-line summary of each device declared
3069 using @command{flash bank}, numbered from zero.
3070 Note that this is the @emph{plural} form;
3071 the @emph{singular} form is a very different command.
3074 @deffn Command {flash probe} num
3075 Identify the flash, or validate the parameters of the configured flash. Operation
3076 depends on the flash type.
3077 The @var{num} parameter is a value shown by @command{flash banks}.
3078 Most flash commands will implicitly @emph{autoprobe} the bank;
3079 flash drivers can distinguish between probing and autoprobing,
3080 but most don't bother.
3083 @section Erasing, Reading, Writing to Flash
3084 @cindex flash erasing
3085 @cindex flash reading
3086 @cindex flash writing
3087 @cindex flash programming
3089 One feature distinguishing NOR flash from NAND or serial flash technologies
3090 is that for read access, it acts exactly like any other addressible memory.
3091 This means you can use normal memory read commands like @command{mdw} or
3092 @command{dump_image} with it, with no special @command{flash} subcommands.
3093 @xref{Memory access}, and @ref{Image access}.
3095 Write access works differently. Flash memory normally needs to be erased
3096 before it's written. Erasing a sector turns all of its bits to ones, and
3097 writing can turn ones into zeroes. This is why there are special commands
3098 for interactive erasing and writing, and why GDB needs to know which parts
3099 of the address space hold NOR flash memory.
3102 Most of these erase and write commands leverage the fact that NOR flash
3103 chips consume target address space. They implicitly refer to the current
3104 JTAG target, and map from an address in that target's address space
3105 back to a flash bank.
3106 @comment In May 2009, those mappings may fail if any bank associated
3107 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3108 A few commands use abstract addressing based on bank and sector numbers,
3109 and don't depend on searching the current target and its address space.
3110 Avoid confusing the two command models.
3113 Some flash chips implement software protection against accidental writes,
3114 since such buggy writes could in some cases ``brick'' a system.
3115 For such systems, erasing and writing may require sector protection to be
3117 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3118 and AT91SAM7 on-chip flash.
3119 @xref{flash protect}.
3121 @anchor{flash erase_sector}
3122 @deffn Command {flash erase_sector} num first last
3123 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3124 @var{last}. Sector numbering starts at 0.
3125 The @var{num} parameter is a value shown by @command{flash banks}.
3128 @deffn Command {flash erase_address} address length
3129 Erase sectors starting at @var{address} for @var{length} bytes.
3130 The flash bank to use is inferred from the @var{address}, and
3131 the specified length must stay within that bank.
3132 As a special case, when @var{length} is zero and @var{address} is
3133 the start of the bank, the whole flash is erased.
3136 @deffn Command {flash fillw} address word length
3137 @deffnx Command {flash fillh} address halfword length
3138 @deffnx Command {flash fillb} address byte length
3139 Fills flash memory with the specified @var{word} (32 bits),
3140 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3141 starting at @var{address} and continuing
3142 for @var{length} units (word/halfword/byte).
3143 No erasure is done before writing; when needed, that must be done
3144 before issuing this command.
3145 Writes are done in blocks of up to 1024 bytes, and each write is
3146 verified by reading back the data and comparing it to what was written.
3147 The flash bank to use is inferred from the @var{address} of
3148 each block, and the specified length must stay within that bank.
3150 @comment no current checks for errors if fill blocks touch multiple banks!
3152 @anchor{flash write_bank}
3153 @deffn Command {flash write_bank} num filename offset
3154 Write the binary @file{filename} to flash bank @var{num},
3155 starting at @var{offset} bytes from the beginning of the bank.
3156 The @var{num} parameter is a value shown by @command{flash banks}.
3159 @anchor{flash write_image}
3160 @deffn Command {flash write_image} [erase] filename [offset] [type]
3161 Write the image @file{filename} to the current target's flash bank(s).
3162 A relocation @var{offset} may be specified, in which case it is added
3163 to the base address for each section in the image.
3164 The file [@var{type}] can be specified
3165 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3166 @option{elf} (ELF file), @option{s19} (Motorola s19).
3167 @option{mem}, or @option{builder}.
3168 The relevant flash sectors will be erased prior to programming
3169 if the @option{erase} parameter is given.
3170 The flash bank to use is inferred from the @var{address} of
3174 @section Other Flash commands
3175 @cindex flash protection
3177 @deffn Command {flash erase_check} num
3178 Check erase state of sectors in flash bank @var{num},
3179 and display that status.
3180 The @var{num} parameter is a value shown by @command{flash banks}.
3181 This is the only operation that
3182 updates the erase state information displayed by @option{flash info}. That means you have
3183 to issue an @command{flash erase_check} command after erasing or programming the device
3184 to get updated information.
3185 (Code execution may have invalidated any state records kept by OpenOCD.)
3188 @deffn Command {flash info} num
3189 Print info about flash bank @var{num}
3190 The @var{num} parameter is a value shown by @command{flash banks}.
3191 The information includes per-sector protect status.
3194 @anchor{flash protect}
3195 @deffn Command {flash protect} num first last (on|off)
3196 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3197 @var{first} to @var{last} of flash bank @var{num}.
3198 The @var{num} parameter is a value shown by @command{flash banks}.
3201 @deffn Command {flash protect_check} num
3202 Check protection state of sectors in flash bank @var{num}.
3203 The @var{num} parameter is a value shown by @command{flash banks}.
3204 @comment @option{flash erase_sector} using the same syntax.
3207 @anchor{Flash Driver List}
3208 @section Flash Drivers, Options, and Commands
3209 As noted above, the @command{flash bank} command requires a driver name,
3210 and allows driver-specific options and behaviors.
3211 Some drivers also activate driver-specific commands.
3213 @subsection External Flash
3215 @deffn {Flash Driver} cfi
3216 @cindex Common Flash Interface
3218 The ``Common Flash Interface'' (CFI) is the main standard for
3219 external NOR flash chips, each of which connects to a
3220 specific external chip select on the CPU.
3221 Frequently the first such chip is used to boot the system.
3222 Your board's @code{reset-init} handler might need to
3223 configure additional chip selects using other commands (like: @command{mww} to
3224 configure a bus and its timings) , or
3225 perhaps configure a GPIO pin that controls the ``write protect'' pin
3227 The CFI driver can use a target-specific working area to significantly
3230 The CFI driver can accept the following optional parameters, in any order:
3233 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3234 like AM29LV010 and similar types.
3235 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3238 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3239 wide on a sixteen bit bus:
3242 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3243 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3247 @subsection Internal Flash (Microcontrollers)
3249 @deffn {Flash Driver} aduc702x
3250 The ADUC702x analog microcontrollers from ST Micro
3251 include internal flash and use ARM7TDMI cores.
3252 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3253 The setup command only requires the @var{target} argument
3254 since all devices in this family have the same memory layout.
3257 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3261 @deffn {Flash Driver} at91sam7
3262 All members of the AT91SAM7 microcontroller family from Atmel
3263 include internal flash and use ARM7TDMI cores.
3264 The driver automatically recognizes a number of these chips using
3265 the chip identification register, and autoconfigures itself.
3268 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3271 For chips which are not recognized by the controller driver, you must
3272 provide additional parameters in the following order:
3275 @item @var{chip_model} ... label used with @command{flash info}
3277 @item @var{sectors_per_bank}
3278 @item @var{pages_per_sector}
3279 @item @var{pages_size}
3280 @item @var{num_nvm_bits}
3281 @item @var{freq_khz} ... required if an external clock is provided,
3282 optional (but recommended) when the oscillator frequency is known
3285 It is recommended that you provide zeroes for all of those values
3286 except the clock frequency, so that everything except that frequency
3287 will be autoconfigured.
3288 Knowing the frequency helps ensure correct timings for flash access.
3290 The flash controller handles erases automatically on a page (128/256 byte)
3291 basis, so explicit erase commands are not necessary for flash programming.
3292 However, there is an ``EraseAll`` command that can erase an entire flash
3293 plane (of up to 256KB), and it will be used automatically when you issue
3294 @command{flash erase_sector} or @command{flash erase_address} commands.
3296 @deffn Command {at91sam7 gpnvm} bitnum (set|clear)
3297 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3298 bit for the processor. Each processor has a number of such bits,
3299 used for controlling features such as brownout detection (so they
3300 are not truly general purpose).
3302 This assumes that the first flash bank (number 0) is associated with
3303 the appropriate at91sam7 target.
3308 @deffn {Flash Driver} avr
3309 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3310 @emph{The current implementation is incomplete.}
3311 @comment - defines mass_erase ... pointless given flash_erase_address
3314 @deffn {Flash Driver} ecosflash
3315 @emph{No idea what this is...}
3316 The @var{ecosflash} driver defines one mandatory parameter,
3317 the name of a modules of target code which is downloaded
3321 @deffn {Flash Driver} lpc2000
3322 Most members of the LPC2000 microcontroller family from NXP
3323 include internal flash and use ARM7TDMI cores.
3324 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3325 which must appear in the following order:
3328 @item @var{variant} ... required, may be
3329 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3330 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3331 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3332 at which the core is running
3333 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3334 telling the driver to calculate a valid checksum for the exception vector table.
3337 LPC flashes don't require the chip and bus width to be specified.
3340 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3341 lpc2000_v2 14765 calc_checksum
3345 @deffn {Flash Driver} lpc288x
3346 The LPC2888 microcontroller from NXP needs slightly different flash
3347 support from its lpc2000 siblings.
3348 The @var{lpc288x} driver defines one mandatory parameter,
3349 the programming clock rate in Hz.
3350 LPC flashes don't require the chip and bus width to be specified.
3353 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3357 @deffn {Flash Driver} ocl
3358 @emph{No idea what this is, other than using some arm7/arm9 core.}
3361 flash bank ocl 0 0 0 0 $_TARGETNAME
3365 @deffn {Flash Driver} pic32mx
3366 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3367 and integrate flash memory.
3368 @emph{The current implementation is incomplete.}
3371 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3374 @comment numerous *disabled* commands are defined:
3375 @comment - chip_erase ... pointless given flash_erase_address
3376 @comment - lock, unlock ... pointless given protect on/off (yes?)
3377 @comment - pgm_word ... shouldn't bank be deduced from address??
3378 Some pic32mx-specific commands are defined:
3379 @deffn Command {pic32mx pgm_word} address value bank
3380 Programs the specified 32-bit @var{value} at the given @var{address}
3381 in the specified chip @var{bank}.
3385 @deffn {Flash Driver} stellaris
3386 All members of the Stellaris LM3Sxxx microcontroller family from
3388 include internal flash and use ARM Cortex M3 cores.
3389 The driver automatically recognizes a number of these chips using
3390 the chip identification register, and autoconfigures itself.
3391 @footnote{Currently there is a @command{stellaris mass_erase} command.
3392 That seems pointless since the same effect can be had using the
3393 standard @command{flash erase_address} command.}
3396 flash bank stellaris 0 0 0 0 $_TARGETNAME
3400 @deffn {Flash Driver} stm32x
3401 All members of the STM32 microcontroller family from ST Microelectronics
3402 include internal flash and use ARM Cortex M3 cores.
3403 The driver automatically recognizes a number of these chips using
3404 the chip identification register, and autoconfigures itself.
3407 flash bank stm32x 0 0 0 0 $_TARGETNAME
3410 Some stm32x-specific commands
3411 @footnote{Currently there is a @command{stm32x mass_erase} command.
3412 That seems pointless since the same effect can be had using the
3413 standard @command{flash erase_address} command.}
3416 @deffn Command {stm32x lock} num
3417 Locks the entire stm32 device.
3418 The @var{num} parameter is a value shown by @command{flash banks}.
3421 @deffn Command {stm32x unlock} num
3422 Unlocks the entire stm32 device.
3423 The @var{num} parameter is a value shown by @command{flash banks}.
3426 @deffn Command {stm32x options_read} num
3427 Read and display the stm32 option bytes written by
3428 the @command{stm32x options_write} command.
3429 The @var{num} parameter is a value shown by @command{flash banks}.
3432 @deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
3433 Writes the stm32 option byte with the specified values.
3434 The @var{num} parameter is a value shown by @command{flash banks}.
3438 @deffn {Flash Driver} str7x
3439 All members of the STR7 microcontroller family from ST Microelectronics
3440 include internal flash and use ARM7TDMI cores.
3441 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3442 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3445 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3449 @deffn {Flash Driver} str9x
3450 Most members of the STR9 microcontroller family from ST Microelectronics
3451 include internal flash and use ARM966E cores.
3452 The str9 needs the flash controller to be configured using
3453 the @command{str9x flash_config} command prior to Flash programming.
3456 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3457 str9x flash_config 0 4 2 0 0x80000
3460 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3461 Configures the str9 flash controller.
3462 The @var{num} parameter is a value shown by @command{flash banks}.
3465 @item @var{bbsr} - Boot Bank Size register
3466 @item @var{nbbsr} - Non Boot Bank Size register
3467 @item @var{bbadr} - Boot Bank Start Address register
3468 @item @var{nbbadr} - Boot Bank Start Address register
3474 @deffn {Flash Driver} tms470
3475 Most members of the TMS470 microcontroller family from Texas Instruments
3476 include internal flash and use ARM7TDMI cores.
3477 This driver doesn't require the chip and bus width to be specified.
3479 Some tms470-specific commands are defined:
3481 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3482 Saves programming keys in a register, to enable flash erase and write commands.
3485 @deffn Command {tms470 osc_mhz} clock_mhz
3486 Reports the clock speed, which is used to calculate timings.
3489 @deffn Command {tms470 plldis} (0|1)
3490 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3495 @subsection str9xpec driver
3498 Here is some background info to help
3499 you better understand how this driver works. OpenOCD has two flash drivers for
3503 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3504 flash programming as it is faster than the @option{str9xpec} driver.
3506 Direct programming @option{str9xpec} using the flash controller. This is an
3507 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3508 core does not need to be running to program using this flash driver. Typical use
3509 for this driver is locking/unlocking the target and programming the option bytes.
3512 Before we run any commands using the @option{str9xpec} driver we must first disable
3513 the str9 core. This example assumes the @option{str9xpec} driver has been
3514 configured for flash bank 0.
3516 # assert srst, we do not want core running
3517 # while accessing str9xpec flash driver
3519 # turn off target polling
3522 str9xpec enable_turbo 0
3524 str9xpec options_read 0
3525 # re-enable str9 core
3526 str9xpec disable_turbo 0
3530 The above example will read the str9 option bytes.
3531 When performing a unlock remember that you will not be able to halt the str9 - it
3532 has been locked. Halting the core is not required for the @option{str9xpec} driver
3533 as mentioned above, just issue the commands above manually or from a telnet prompt.
3535 @deffn {Flash Driver} str9xpec
3536 Only use this driver for locking/unlocking the device or configuring the option bytes.
3537 Use the standard str9 driver for programming.
3538 Before using the flash commands the turbo mode must be enabled using the
3539 @command{str9xpec enable_turbo} command.
3541 Several str9xpec-specific commands are defined:
3543 @deffn Command {str9xpec disable_turbo} num
3544 Restore the str9 into JTAG chain.
3547 @deffn Command {str9xpec enable_turbo} num
3548 Enable turbo mode, will simply remove the str9 from the chain and talk
3549 directly to the embedded flash controller.
3552 @deffn Command {str9xpec lock} num
3553 Lock str9 device. The str9 will only respond to an unlock command that will
3557 @deffn Command {str9xpec part_id} num
3558 Prints the part identifier for bank @var{num}.
3561 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3562 Configure str9 boot bank.
3565 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3566 Configure str9 lvd source.
3569 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3570 Configure str9 lvd threshold.
3573 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3574 Configure str9 lvd reset warning source.
3577 @deffn Command {str9xpec options_read} num
3578 Read str9 option bytes.
3581 @deffn Command {str9xpec options_write} num
3582 Write str9 option bytes.
3585 @deffn Command {str9xpec unlock} num
3594 @subsection mFlash Configuration
3595 @cindex mFlash Configuration
3597 @deffn {Config Command} {mflash bank} soc base RST_pin target
3598 Configures a mflash for @var{soc} host bank at
3600 The pin number format depends on the host GPIO naming convention.
3601 Currently, the mflash driver supports s3c2440 and pxa270.
3603 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3606 mflash bank s3c2440 0x10000000 1b 0
3609 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3612 mflash bank pxa270 0x08000000 43 0
3616 @subsection mFlash commands
3617 @cindex mFlash commands
3619 @deffn Command {mflash config pll} frequency
3620 Configure mflash PLL.
3621 The @var{frequency} is the mflash input frequency, in Hz.
3622 Issuing this command will erase mflash's whole internal nand and write new pll.
3623 After this command, mflash needs power-on-reset for normal operation.
3624 If pll was newly configured, storage and boot(optional) info also need to be update.
3627 @deffn Command {mflash config boot}
3628 Configure bootable option.
3629 If bootable option is set, mflash offer the first 8 sectors
3633 @deffn Command {mflash config storage}
3634 Configure storage information.
3635 For the normal storage operation, this information must be
3639 @deffn Command {mflash dump} num filename offset size
3640 Dump @var{size} bytes, starting at @var{offset} bytes from the
3641 beginning of the bank @var{num}, to the file named @var{filename}.
3644 @deffn Command {mflash probe}
3648 @deffn Command {mflash write} num filename offset
3649 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3650 @var{offset} bytes from the beginning of the bank.
3653 @node NAND Flash Commands
3654 @chapter NAND Flash Commands
3657 Compared to NOR or SPI flash, NAND devices are inexpensive
3658 and high density. Today's NAND chips, and multi-chip modules,
3659 commonly hold multiple GigaBytes of data.
3661 NAND chips consist of a number of ``erase blocks'' of a given
3662 size (such as 128 KBytes), each of which is divided into a
3663 number of pages (of perhaps 512 or 2048 bytes each). Each
3664 page of a NAND flash has an ``out of band'' (OOB) area to hold
3665 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3666 of OOB for every 512 bytes of page data.
3668 One key characteristic of NAND flash is that its error rate
3669 is higher than that of NOR flash. In normal operation, that
3670 ECC is used to correct and detect errors. However, NAND
3671 blocks can also wear out and become unusable; those blocks
3672 are then marked "bad". NAND chips are even shipped from the
3673 manufacturer with a few bad blocks. The highest density chips
3674 use a technology (MLC) that wears out more quickly, so ECC
3675 support is increasingly important as a way to detect blocks
3676 that have begun to fail, and help to preserve data integrity
3677 with techniques such as wear leveling.
3679 Software is used to manage the ECC. Some controllers don't
3680 support ECC directly; in those cases, software ECC is used.
3681 Other controllers speed up the ECC calculations with hardware.
3682 Single-bit error correction hardware is routine. Controllers
3683 geared for newer MLC chips may correct 4 or more errors for
3684 every 512 bytes of data.
3686 You will need to make sure that any data you write using
3687 OpenOCD includes the apppropriate kind of ECC. For example,
3688 that may mean passing the @code{oob_softecc} flag when
3689 writing NAND data, or ensuring that the correct hardware
3692 The basic steps for using NAND devices include:
3694 @item Declare via the command @command{nand device}
3695 @* Do this in a board-specific configuration file,
3696 passing parameters as needed by the controller.
3697 @item Configure each device using @command{nand probe}.
3698 @* Do this only after the associated target is set up,
3699 such as in its reset-init script or in procures defined
3700 to access that device.
3701 @item Operate on the flash via @command{nand subcommand}
3702 @* Often commands to manipulate the flash are typed by a human, or run
3703 via a script in some automated way. Common task include writing a
3704 boot loader, operating system, or other data needed to initialize or
3708 @b{NOTE:} At the time this text was written, the largest NAND
3709 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3710 This is because the variables used to hold offsets and lengths
3711 are only 32 bits wide.
3712 (Larger chips may work in some cases, unless an offset or length
3713 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3714 Some larger devices will work, since they are actually multi-chip
3715 modules with two smaller chips and individual chipselect lines.
3717 @section NAND Configuration Commands
3718 @cindex NAND configuration
3720 NAND chips must be declared in configuration scripts,
3721 plus some additional configuration that's done after
3722 OpenOCD has initialized.
3724 @deffn {Config Command} {nand device} controller target [configparams...]
3725 Declares a NAND device, which can be read and written to
3726 after it has been configured through @command{nand probe}.
3727 In OpenOCD, devices are single chips; this is unlike some
3728 operating systems, which may manage multiple chips as if
3729 they were a single (larger) device.
3730 In some cases, configuring a device will activate extra
3731 commands; see the controller-specific documentation.
3733 @b{NOTE:} This command is not available after OpenOCD
3734 initialization has completed. Use it in board specific
3735 configuration files, not interactively.
3738 @item @var{controller} ... identifies the controller driver
3739 associated with the NAND device being declared.
3740 @xref{NAND Driver List}.
3741 @item @var{target} ... names the target used when issuing
3742 commands to the NAND controller.
3743 @comment Actually, it's currently a controller-specific parameter...
3744 @item @var{configparams} ... controllers may support, or require,
3745 additional parameters. See the controller-specific documentation
3746 for more information.
3750 @deffn Command {nand list}
3751 Prints a one-line summary of each device declared
3752 using @command{nand device}, numbered from zero.
3753 Note that un-probed devices show no details.
3756 @deffn Command {nand probe} num
3757 Probes the specified device to determine key characteristics
3758 like its page and block sizes, and how many blocks it has.
3759 The @var{num} parameter is the value shown by @command{nand list}.
3760 You must (successfully) probe a device before you can use
3761 it with most other NAND commands.
3764 @section Erasing, Reading, Writing to NAND Flash
3766 @deffn Command {nand dump} num filename offset length [oob_option]
3767 @cindex NAND reading
3768 Reads binary data from the NAND device and writes it to the file,
3769 starting at the specified offset.
3770 The @var{num} parameter is the value shown by @command{nand list}.
3772 Use a complete path name for @var{filename}, so you don't depend
3773 on the directory used to start the OpenOCD server.
3775 The @var{offset} and @var{length} must be exact multiples of the
3776 device's page size. They describe a data region; the OOB data
3777 associated with each such page may also be accessed.
3779 @b{NOTE:} At the time this text was written, no error correction
3780 was done on the data that's read, unless raw access was disabled
3781 and the underlying NAND controller driver had a @code{read_page}
3782 method which handled that error correction.
3784 By default, only page data is saved to the specified file.
3785 Use an @var{oob_option} parameter to save OOB data:
3787 @item no oob_* parameter
3788 @*Output file holds only page data; OOB is discarded.
3789 @item @code{oob_raw}
3790 @*Output file interleaves page data and OOB data;
3791 the file will be longer than "length" by the size of the
3792 spare areas associated with each data page.
3793 Note that this kind of "raw" access is different from
3794 what's implied by @command{nand raw_access}, which just
3795 controls whether a hardware-aware access method is used.
3796 @item @code{oob_only}
3797 @*Output file has only raw OOB data, and will
3798 be smaller than "length" since it will contain only the
3799 spare areas associated with each data page.
3803 @deffn Command {nand erase} num offset length
3804 @cindex NAND erasing
3805 @cindex NAND programming
3806 Erases blocks on the specified NAND device, starting at the
3807 specified @var{offset} and continuing for @var{length} bytes.
3808 Both of those values must be exact multiples of the device's
3809 block size, and the region they specify must fit entirely in the chip.
3810 The @var{num} parameter is the value shown by @command{nand list}.
3812 @b{NOTE:} This command will try to erase bad blocks, when told
3813 to do so, which will probably invalidate the manufacturer's bad
3815 For the remainder of the current server session, @command{nand info}
3816 will still report that the block ``is'' bad.
3819 @deffn Command {nand write} num filename offset [option...]
3820 @cindex NAND writing
3821 @cindex NAND programming
3822 Writes binary data from the file into the specified NAND device,
3823 starting at the specified offset. Those pages should already
3824 have been erased; you can't change zero bits to one bits.
3825 The @var{num} parameter is the value shown by @command{nand list}.
3827 Use a complete path name for @var{filename}, so you don't depend
3828 on the directory used to start the OpenOCD server.
3830 The @var{offset} must be an exact multiple of the device's page size.
3831 All data in the file will be written, assuming it doesn't run
3832 past the end of the device.
3833 Only full pages are written, and any extra space in the last
3834 page will be filled with 0xff bytes. (That includes OOB data,
3835 if that's being written.)
3837 @b{NOTE:} At the time this text was written, bad blocks are
3838 ignored. That is, this routine will not skip bad blocks,
3839 but will instead try to write them. This can cause problems.
3841 Provide at most one @var{option} parameter. With some
3842 NAND drivers, the meanings of these parameters may change
3843 if @command{nand raw_access} was used to disable hardware ECC.
3845 @item no oob_* parameter
3846 @*File has only page data, which is written.
3847 If raw acccess is in use, the OOB area will not be written.
3848 Otherwise, if the underlying NAND controller driver has
3849 a @code{write_page} routine, that routine may write the OOB
3850 with hardware-computed ECC data.
3851 @item @code{oob_only}
3852 @*File has only raw OOB data, which is written to the OOB area.
3853 Each page's data area stays untouched. @i{This can be a dangerous
3854 option}, since it can invalidate the ECC data.
3855 You may need to force raw access to use this mode.
3856 @item @code{oob_raw}
3857 @*File interleaves data and OOB data, both of which are written
3858 If raw access is enabled, the data is written first, then the
3860 Otherwise, if the underlying NAND controller driver has
3861 a @code{write_page} routine, that routine may modify the OOB
3862 before it's written, to include hardware-computed ECC data.
3863 @item @code{oob_softecc}
3864 @*File has only page data, which is written.
3865 The OOB area is filled with 0xff, except for a standard 1-bit
3866 software ECC code stored in conventional locations.
3867 You might need to force raw access to use this mode, to prevent
3868 the underlying driver from applying hardware ECC.
3869 @item @code{oob_softecc_kw}
3870 @*File has only page data, which is written.
3871 The OOB area is filled with 0xff, except for a 4-bit software ECC
3872 specific to the boot ROM in Marvell Kirkwood SoCs.
3873 You might need to force raw access to use this mode, to prevent
3874 the underlying driver from applying hardware ECC.
3878 @section Other NAND commands
3879 @cindex NAND other commands
3881 @deffn Command {nand check_bad_blocks} [offset length]
3882 Checks for manufacturer bad block markers on the specified NAND
3883 device. If no parameters are provided, checks the whole
3884 device; otherwise, starts at the specified @var{offset} and
3885 continues for @var{length} bytes.
3886 Both of those values must be exact multiples of the device's
3887 block size, and the region they specify must fit entirely in the chip.
3888 The @var{num} parameter is the value shown by @command{nand list}.
3890 @b{NOTE:} Before using this command you should force raw access
3891 with @command{nand raw_access enable} to ensure that the underlying
3892 driver will not try to apply hardware ECC.
3895 @deffn Command {nand info} num
3896 The @var{num} parameter is the value shown by @command{nand list}.
3897 This prints the one-line summary from "nand list", plus for
3898 devices which have been probed this also prints any known
3899 status for each block.
3902 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
3903 Sets or clears an flag affecting how page I/O is done.
3904 The @var{num} parameter is the value shown by @command{nand list}.
3906 This flag is cleared (disabled) by default, but changing that
3907 value won't affect all NAND devices. The key factor is whether
3908 the underlying driver provides @code{read_page} or @code{write_page}
3909 methods. If it doesn't provide those methods, the setting of
3910 this flag is irrelevant; all access is effectively ``raw''.
3912 When those methods exist, they are normally used when reading
3913 data (@command{nand dump} or reading bad block markers) or
3914 writing it (@command{nand write}). However, enabling
3915 raw access (setting the flag) prevents use of those methods,
3916 bypassing hardware ECC logic.
3917 @i{This can be a dangerous option}, since writing blocks
3918 with the wrong ECC data can cause them to be marked as bad.
3921 @anchor{NAND Driver List}
3922 @section NAND Drivers, Options, and Commands
3923 As noted above, the @command{nand device} command allows
3924 driver-specific options and behaviors.
3925 Some controllers also activate controller-specific commands.
3927 @deffn {NAND Driver} davinci
3928 This driver handles the NAND controllers found on DaVinci family
3929 chips from Texas Instruments.
3930 It takes three extra parameters:
3931 address of the NAND chip;
3932 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3933 address of the AEMIF controller on this processor.
3935 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3937 All DaVinci processors support the single-bit ECC hardware,
3938 and newer ones also support the four-bit ECC hardware.
3939 The @code{write_page} and @code{read_page} methods are used
3940 to implement those ECC modes, unless they are disabled using
3941 the @command{nand raw_access} command.
3944 @deffn {NAND Driver} lpc3180
3945 These controllers require an extra @command{nand device}
3946 parameter: the clock rate used by the controller.
3947 @deffn Command {lpc3180 select} num [mlc|slc]
3948 Configures use of the MLC or SLC controller mode.
3949 MLC implies use of hardware ECC.
3950 The @var{num} parameter is the value shown by @command{nand list}.
3953 At this writing, this driver includes @code{write_page}
3954 and @code{read_page} methods. Using @command{nand raw_access}
3955 to disable those methods will prevent use of hardware ECC
3956 in the MLC controller mode, but won't change SLC behavior.
3958 @comment current lpc3180 code won't issue 5-byte address cycles
3960 @deffn {NAND Driver} orion
3961 These controllers require an extra @command{nand device}
3962 parameter: the address of the controller.
3964 nand device orion 0xd8000000
3966 These controllers don't define any specialized commands.
3967 At this writing, their drivers don't include @code{write_page}
3968 or @code{read_page} methods, so @command{nand raw_access} won't
3969 change any behavior.
3972 @deffn {NAND Driver} s3c2410
3973 @deffnx {NAND Driver} s3c2412
3974 @deffnx {NAND Driver} s3c2440
3975 @deffnx {NAND Driver} s3c2443
3976 These S3C24xx family controllers don't have any special
3977 @command{nand device} options, and don't define any
3978 specialized commands.
3979 At this writing, their drivers don't include @code{write_page}
3980 or @code{read_page} methods, so @command{nand raw_access} won't
3981 change any behavior.
3984 @node General Commands
3985 @chapter General Commands
3988 The commands documented in this chapter here are common commands that
3989 you, as a human, may want to type and see the output of. Configuration type
3990 commands are documented elsewhere.
3994 @item @b{Source Of Commands}
3995 @* OpenOCD commands can occur in a configuration script (discussed
3996 elsewhere) or typed manually by a human or supplied programatically,
3997 or via one of several TCP/IP Ports.
3999 @item @b{From the human}
4000 @* A human should interact with the telnet interface (default port: 4444)
4001 or via GDB (default port 3333).
4003 To issue commands from within a GDB session, use the @option{monitor}
4004 command, e.g. use @option{monitor poll} to issue the @option{poll}
4005 command. All output is relayed through the GDB session.
4007 @item @b{Machine Interface}
4008 The Tcl interface's intent is to be a machine interface. The default Tcl
4013 @section Daemon Commands
4015 @deffn Command sleep msec [@option{busy}]
4016 Wait for at least @var{msec} milliseconds before resuming.
4017 If @option{busy} is passed, busy-wait instead of sleeping.
4018 (This option is strongly discouraged.)
4019 Useful in connection with script files
4020 (@command{script} command and @command{target_name} configuration).
4023 @deffn Command shutdown
4024 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4027 @anchor{debug_level}
4028 @deffn Command debug_level [n]
4029 @cindex message level
4030 Display debug level.
4031 If @var{n} (from 0..3) is provided, then set it to that level.
4032 This affects the kind of messages sent to the server log.
4033 Level 0 is error messages only;
4034 level 1 adds warnings;
4035 level 2 adds informational messages;
4036 and level 3 adds debugging messages.
4037 The default is level 2, but that can be overridden on
4038 the command line along with the location of that log
4039 file (which is normally the server's standard output).
4043 @deffn Command fast (@option{enable}|@option{disable})
4045 Set default behaviour of OpenOCD to be "fast and dangerous".
4047 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4048 fast memory access, and DCC downloads. Those parameters may still be
4049 individually overridden.
4051 The target specific "dangerous" optimisation tweaking options may come and go
4052 as more robust and user friendly ways are found to ensure maximum throughput
4053 and robustness with a minimum of configuration.
4055 Typically the "fast enable" is specified first on the command line:
4058 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4062 @deffn Command echo message
4063 Logs a message at "user" priority.
4064 Output @var{message} to stdout.
4066 echo "Downloading kernel -- please wait"
4070 @deffn Command log_output [filename]
4071 Redirect logging to @var{filename};
4072 the initial log output channel is stderr.
4075 @anchor{Target State handling}
4076 @section Target State handling
4079 @cindex target initialization
4081 In this section ``target'' refers to a CPU configured as
4082 shown earlier (@pxref{CPU Configuration}).
4083 These commands, like many, implicitly refer to
4084 a current target which is used to perform the
4085 various operations. The current target may be changed
4086 by using @command{targets} command with the name of the
4087 target which should become current.
4089 @deffn Command reg [(number|name) [value]]
4090 Access a single register by @var{number} or by its @var{name}.
4092 @emph{With no arguments}:
4093 list all available registers for the current target,
4094 showing number, name, size, value, and cache status.
4096 @emph{With number/name}: display that register's value.
4098 @emph{With both number/name and value}: set register's value.
4100 Cores may have surprisingly many registers in their
4101 Debug and trace infrastructure:
4105 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4106 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4107 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4109 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4110 0x00000000 (dirty: 0, valid: 0)
4115 @deffn Command halt [ms]
4116 @deffnx Command wait_halt [ms]
4117 The @command{halt} command first sends a halt request to the target,
4118 which @command{wait_halt} doesn't.
4119 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4120 or 5 seconds if there is no parameter, for the target to halt
4121 (and enter debug mode).
4122 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4125 @deffn Command resume [address]
4126 Resume the target at its current code position,
4127 or the optional @var{address} if it is provided.
4128 OpenOCD will wait 5 seconds for the target to resume.
4131 @deffn Command step [address]
4132 Single-step the target at its current code position,
4133 or the optional @var{address} if it is provided.
4136 @anchor{Reset Command}
4137 @deffn Command reset
4138 @deffnx Command {reset run}
4139 @deffnx Command {reset halt}
4140 @deffnx Command {reset init}
4141 Perform as hard a reset as possible, using SRST if possible.
4142 @emph{All defined targets will be reset, and target
4143 events will fire during the reset sequence.}
4145 The optional parameter specifies what should
4146 happen after the reset.
4147 If there is no parameter, a @command{reset run} is executed.
4148 The other options will not work on all systems.
4149 @xref{Reset Configuration}.
4152 @item @b{run} Let the target run
4153 @item @b{halt} Immediately halt the target
4154 @item @b{init} Immediately halt the target, and execute the reset-init script
4158 @deffn Command soft_reset_halt
4159 Requesting target halt and executing a soft reset. This is often used
4160 when a target cannot be reset and halted. The target, after reset is
4161 released begins to execute code. OpenOCD attempts to stop the CPU and
4162 then sets the program counter back to the reset vector. Unfortunately
4163 the code that was executed may have left the hardware in an unknown
4167 @section I/O Utilities
4169 These commands are available when
4170 OpenOCD is built with @option{--enable-ioutil}.
4171 They are mainly useful on embedded targets;
4172 PC type hosts have complementary tools.
4174 @emph{Note:} there are several more such commands.
4176 @deffn Command meminfo
4177 Display available RAM memory on OpenOCD host.
4178 Used in OpenOCD regression testing scripts.
4181 @anchor{Memory access}
4182 @section Memory access commands
4183 @cindex memory access
4185 These commands allow accesses of a specific size to the memory
4186 system. Often these are used to configure the current target in some
4187 special way. For example - one may need to write certain values to the
4188 SDRAM controller to enable SDRAM.
4191 @item Use the @command{targets} (plural) command
4192 to change the current target.
4193 @item In system level scripts these commands are deprecated.
4194 Please use their TARGET object siblings to avoid making assumptions
4195 about what TAP is the current target, or about MMU configuration.
4198 @deffn Command mdw addr [count]
4199 @deffnx Command mdh addr [count]
4200 @deffnx Command mdb addr [count]
4201 Display contents of address @var{addr}, as
4202 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4203 or 8-bit bytes (@command{mdb}).
4204 If @var{count} is specified, displays that many units.
4205 (If you want to manipulate the data instead of displaying it,
4206 see the @code{mem2array} primitives.)
4209 @deffn Command mww addr word
4210 @deffnx Command mwh addr halfword
4211 @deffnx Command mwb addr byte
4212 Writes the specified @var{word} (32 bits),
4213 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4214 at the specified address @var{addr}.
4218 @anchor{Image access}
4219 @section Image loading commands
4220 @cindex image loading
4221 @cindex image dumping
4224 @deffn Command {dump_image} filename address size
4225 Dump @var{size} bytes of target memory starting at @var{address} to the
4226 binary file named @var{filename}.
4229 @deffn Command {fast_load}
4230 Loads an image stored in memory by @command{fast_load_image} to the
4231 current target. Must be preceeded by fast_load_image.
4234 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4235 Normally you should be using @command{load_image} or GDB load. However, for
4236 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4237 host), storing the image in memory and uploading the image to the target
4238 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4239 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4240 memory, i.e. does not affect target. This approach is also useful when profiling
4241 target programming performance as I/O and target programming can easily be profiled
4246 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4247 Load image from file @var{filename} to target memory at @var{address}.
4248 The file format may optionally be specified
4249 (@option{bin}, @option{ihex}, or @option{elf})
4252 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4253 Verify @var{filename} against target memory starting at @var{address}.
4254 The file format may optionally be specified
4255 (@option{bin}, @option{ihex}, or @option{elf})
4256 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4260 @section Breakpoint and Watchpoint commands
4264 CPUs often make debug modules accessible through JTAG, with
4265 hardware support for a handful of code breakpoints and data
4267 In addition, CPUs almost always support software breakpoints.
4269 @deffn Command {bp} [address len [@option{hw}]]
4270 With no parameters, lists all active breakpoints.
4271 Else sets a breakpoint on code execution starting
4272 at @var{address} for @var{length} bytes.
4273 This is a software breakpoint, unless @option{hw} is specified
4274 in which case it will be a hardware breakpoint.
4276 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4277 for similar mechanisms that do not consume hardware breakpoints.)
4280 @deffn Command {rbp} address
4281 Remove the breakpoint at @var{address}.
4284 @deffn Command {rwp} address
4285 Remove data watchpoint on @var{address}
4288 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4289 With no parameters, lists all active watchpoints.
4290 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4291 The watch point is an "access" watchpoint unless
4292 the @option{r} or @option{w} parameter is provided,
4293 defining it as respectively a read or write watchpoint.
4294 If a @var{value} is provided, that value is used when determining if
4295 the watchpoint should trigger. The value may be first be masked
4296 using @var{mask} to mark ``don't care'' fields.
4299 @section Misc Commands
4302 @deffn Command {profile} seconds filename
4303 Profiling samples the CPU's program counter as quickly as possible,
4304 which is useful for non-intrusive stochastic profiling.
4305 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4308 @node Architecture and Core Commands
4309 @chapter Architecture and Core Commands
4310 @cindex Architecture Specific Commands
4311 @cindex Core Specific Commands
4313 Most CPUs have specialized JTAG operations to support debugging.
4314 OpenOCD packages most such operations in its standard command framework.
4315 Some of those operations don't fit well in that framework, so they are
4316 exposed here as architecture or implementation (core) specific commands.
4318 @anchor{ARM Tracing}
4319 @section ARM Tracing
4323 CPUs based on ARM cores may include standard tracing interfaces,
4324 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4325 address and data bus trace records to a ``Trace Port''.
4329 Development-oriented boards will sometimes provide a high speed
4330 trace connector for collecting that data, when the particular CPU
4331 supports such an interface.
4332 (The standard connector is a 38-pin Mictor, with both JTAG
4333 and trace port support.)
4334 Those trace connectors are supported by higher end JTAG adapters
4335 and some logic analyzer modules; frequently those modules can
4336 buffer several megabytes of trace data.
4337 Configuring an ETM coupled to such an external trace port belongs
4338 in the board-specific configuration file.
4340 If the CPU doesn't provide an external interface, it probably
4341 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4342 dedicated SRAM. 4KBytes is one common ETB size.
4343 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4344 (target) configuration file, since it works the same on all boards.
4347 ETM support in OpenOCD doesn't seem to be widely used yet.
4350 ETM support may be buggy, and at least some @command{etm config}
4351 parameters should be detected by asking the ETM for them.
4352 It seems like a GDB hookup should be possible,
4353 as well as triggering trace on specific events
4354 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4355 There should be GUI tools to manipulate saved trace data and help
4356 analyse it in conjunction with the source code.
4357 It's unclear how much of a common interface is shared
4358 with the current XScale trace support, or should be
4359 shared with eventual Nexus-style trace module support.
4362 @subsection ETM Configuration
4363 ETM setup is coupled with the trace port driver configuration.
4365 @deffn {Config Command} {etm config} target width mode clocking driver
4366 Declares the ETM associated with @var{target}, and associates it
4367 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4369 Several of the parameters must reflect the trace port configuration.
4370 The @var{width} must be either 4, 8, or 16.
4371 The @var{mode} must be @option{normal}, @option{multiplexted},
4372 or @option{demultiplexted}.
4373 The @var{clocking} must be @option{half} or @option{full}.
4376 You can see the ETM registers using the @command{reg} command, although
4377 not all of those possible registers are present in every ETM.
4381 @deffn Command {etm info}
4382 Displays information about the current target's ETM.
4385 @deffn Command {etm status}
4386 Displays status of the current target's ETM:
4387 is the ETM idle, or is it collecting data?
4388 Did trace data overflow?
4392 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4393 Displays what data that ETM will collect.
4394 If arguments are provided, first configures that data.
4395 When the configuration changes, tracing is stopped
4396 and any buffered trace data is invalidated.
4399 @item @var{type} ... one of
4400 @option{none} (save nothing),
4401 @option{data} (save data),
4402 @option{address} (save addresses),
4403 @option{all} (save data and addresses)
4404 @item @var{context_id_bits} ... 0, 8, 16, or 32
4405 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4406 @item @var{branch_output} ... @option{enable} or @option{disable}
4410 @deffn Command {etm trigger_percent} percent
4411 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4414 @subsection ETM Trace Operation
4416 After setting up the ETM, you can use it to collect data.
4417 That data can be exported to files for later analysis.
4418 It can also be parsed with OpenOCD, for basic sanity checking.
4420 @deffn Command {etm analyze}
4421 Reads trace data into memory, if it wasn't already present.
4422 Decodes and prints the data that was collected.
4425 @deffn Command {etm dump} filename
4426 Stores the captured trace data in @file{filename}.
4429 @deffn Command {etm image} filename [base_address] [type]
4430 Opens an image file.
4433 @deffn Command {etm load} filename
4434 Loads captured trace data from @file{filename}.
4437 @deffn Command {etm start}
4438 Starts trace data collection.
4441 @deffn Command {etm stop}
4442 Stops trace data collection.
4445 @anchor{Trace Port Drivers}
4446 @subsection Trace Port Drivers
4448 To use an ETM trace port it must be associated with a driver.
4450 @deffn {Trace Port Driver} dummy
4451 Use the @option{dummy} driver if you are configuring an ETM that's
4452 not connected to anything (on-chip ETB or off-chip trace connector).
4453 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4454 any trace data collection.}
4455 @deffn {Config Command} {etm_dummy config} target
4456 Associates the ETM for @var{target} with a dummy driver.
4460 @deffn {Trace Port Driver} etb
4461 Use the @option{etb} driver if you are configuring an ETM
4462 to use on-chip ETB memory.
4463 @deffn {Config Command} {etb config} target etb_tap
4464 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4465 You can see the ETB registers using the @command{reg} command.
4469 @deffn {Trace Port Driver} oocd_trace
4470 This driver isn't available unless OpenOCD was explicitly configured
4471 with the @option{--enable-oocd_trace} option. You probably don't want
4472 to configure it unless you've built the appropriate prototype hardware;
4473 it's @emph{proof-of-concept} software.
4475 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4476 connected to an off-chip trace connector.
4478 @deffn {Config Command} {oocd_trace config} target tty
4479 Associates the ETM for @var{target} with a trace driver which
4480 collects data through the serial port @var{tty}.
4483 @deffn Command {oocd_trace resync}
4484 Re-synchronizes with the capture clock.
4487 @deffn Command {oocd_trace status}
4488 Reports whether the capture clock is locked or not.
4493 @section ARMv4 and ARMv5 Architecture
4497 These commands are specific to ARM architecture v4 and v5,
4498 including all ARM7 or ARM9 systems and Intel XScale.
4499 They are available in addition to other core-specific
4500 commands that may be available.
4502 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4503 Displays the core_state, optionally changing it to process
4504 either @option{arm} or @option{thumb} instructions.
4505 The target may later be resumed in the currently set core_state.
4506 (Processors may also support the Jazelle state, but
4507 that is not currently supported in OpenOCD.)
4510 @deffn Command {armv4_5 disassemble} address count [thumb]
4512 Disassembles @var{count} instructions starting at @var{address}.
4513 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
4514 else ARM (32-bit) instructions are used.
4515 (Processors may also support the Jazelle state, but
4516 those instructions are not currently understood by OpenOCD.)
4519 @deffn Command {armv4_5 reg}
4520 Display a table of all banked core registers, fetching the current value from every
4521 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4525 @subsection ARM7 and ARM9 specific commands
4529 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4530 ARM9TDMI, ARM920T or ARM926EJ-S.
4531 They are available in addition to the ARMv4/5 commands,
4532 and any other core-specific commands that may be available.
4534 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4535 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4536 instead of breakpoints. This should be
4537 safe for all but ARM7TDMI--S cores (like Philips LPC).
4540 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4542 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4543 amounts of memory. DCC downloads offer a huge speed increase, but might be
4544 unsafe, especially with targets running at very low speeds. This command was introduced
4545 with OpenOCD rev. 60, and requires a few bytes of working area.
4548 @anchor{arm7_9 fast_memory_access}
4549 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4550 Enable or disable memory writes and reads that don't check completion of
4551 the operation. This provides a huge speed increase, especially with USB JTAG
4552 cables (FT2232), but might be unsafe if used with targets running at very low
4553 speeds, like the 32kHz startup clock of an AT91RM9200.
4556 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4557 @emph{This is intended for use while debugging OpenOCD; you probably
4560 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4561 as used in the specified @var{mode}
4562 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4563 the M4..M0 bits of the PSR).
4564 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4565 Register 16 is the mode-specific SPSR,
4566 unless the specified mode is 0xffffffff (32-bit all-ones)
4567 in which case register 16 is the CPSR.
4568 The write goes directly to the CPU, bypassing the register cache.
4571 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4572 @emph{This is intended for use while debugging OpenOCD; you probably
4575 If the second parameter is zero, writes @var{word} to the
4576 Current Program Status register (CPSR).
4577 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4578 In both cases, this bypasses the register cache.
4581 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4582 @emph{This is intended for use while debugging OpenOCD; you probably
4585 Writes eight bits to the CPSR or SPSR,
4586 first rotating them by @math{2*rotate} bits,
4587 and bypassing the register cache.
4588 This has lower JTAG overhead than writing the entire CPSR or SPSR
4589 with @command{arm7_9 write_xpsr}.
4592 @subsection ARM720T specific commands
4595 These commands are available to ARM720T based CPUs,
4596 which are implementations of the ARMv4T architecture
4597 based on the ARM7TDMI-S integer core.
4598 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4600 @deffn Command {arm720t cp15} regnum [value]
4601 Display cp15 register @var{regnum};
4602 else if a @var{value} is provided, that value is written to that register.
4605 @deffn Command {arm720t mdw_phys} addr [count]
4606 @deffnx Command {arm720t mdh_phys} addr [count]
4607 @deffnx Command {arm720t mdb_phys} addr [count]
4608 Display contents of physical address @var{addr}, as
4609 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4610 or 8-bit bytes (@command{mdb_phys}).
4611 If @var{count} is specified, displays that many units.
4614 @deffn Command {arm720t mww_phys} addr word
4615 @deffnx Command {arm720t mwh_phys} addr halfword
4616 @deffnx Command {arm720t mwb_phys} addr byte
4617 Writes the specified @var{word} (32 bits),
4618 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4619 at the specified physical address @var{addr}.
4622 @deffn Command {arm720t virt2phys} va
4623 Translate a virtual address @var{va} to a physical address
4624 and display the result.
4627 @subsection ARM9TDMI specific commands
4630 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
4631 or processors resembling ARM9TDMI, and can use these commands.
4632 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4634 @c 9-june-2009: tried this on arm920t, it didn't work.
4635 @c no-params always lists nothing caught, and that's how it acts.
4637 @anchor{arm9tdmi vector_catch}
4638 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
4639 Vector Catch hardware provides a sort of dedicated breakpoint
4640 for hardware events such as reset, interrupt, and abort.
4641 You can use this to conserve normal breakpoint resources,
4642 so long as you're not concerned with code that branches directly
4643 to those hardware vectors.
4645 This always finishes by listing the current configuration.
4646 If parameters are provided, it first reconfigures the
4647 vector catch hardware to intercept
4648 @option{all} of the hardware vectors,
4649 @option{none} of them,
4650 or a list with one or more of the following:
4651 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4652 @option{irq} @option{fiq}.
4655 @subsection ARM920T specific commands
4658 These commands are available to ARM920T based CPUs,
4659 which are implementations of the ARMv4T architecture
4660 built using the ARM9TDMI integer core.
4661 They are available in addition to the ARMv4/5, ARM7/ARM9,
4662 and ARM9TDMI commands.
4664 @deffn Command {arm920t cache_info}
4665 Print information about the caches found. This allows to see whether your target
4666 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
4669 @deffn Command {arm920t cp15} regnum [value]
4670 Display cp15 register @var{regnum};
4671 else if a @var{value} is provided, that value is written to that register.
4674 @deffn Command {arm920t cp15i} opcode [value [address]]
4675 Interpreted access using cp15 @var{opcode}.
4676 If no @var{value} is provided, the result is displayed.
4677 Else if that value is written using the specified @var{address},
4678 or using zero if no other address is not provided.
4681 @deffn Command {arm920t mdw_phys} addr [count]
4682 @deffnx Command {arm920t mdh_phys} addr [count]
4683 @deffnx Command {arm920t mdb_phys} addr [count]
4684 Display contents of physical address @var{addr}, as
4685 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4686 or 8-bit bytes (@command{mdb_phys}).
4687 If @var{count} is specified, displays that many units.
4690 @deffn Command {arm920t mww_phys} addr word
4691 @deffnx Command {arm920t mwh_phys} addr halfword
4692 @deffnx Command {arm920t mwb_phys} addr byte
4693 Writes the specified @var{word} (32 bits),
4694 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4695 at the specified physical address @var{addr}.
4698 @deffn Command {arm920t read_cache} filename
4699 Dump the content of ICache and DCache to a file named @file{filename}.
4702 @deffn Command {arm920t read_mmu} filename
4703 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4706 @deffn Command {arm920t virt2phys} va
4707 Translate a virtual address @var{va} to a physical address
4708 and display the result.
4711 @subsection ARM926ej-s specific commands
4714 These commands are available to ARM926ej-s based CPUs,
4715 which are implementations of the ARMv5TEJ architecture
4716 based on the ARM9EJ-S integer core.
4717 They are available in addition to the ARMv4/5, ARM7/ARM9,
4718 and ARM9TDMI commands.
4720 The Feroceon cores also support these commands, although
4721 they are not built from ARM926ej-s designs.
4723 @deffn Command {arm926ejs cache_info}
4724 Print information about the caches found.
4727 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4728 Accesses cp15 register @var{regnum} using
4729 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4730 If a @var{value} is provided, that value is written to that register.
4731 Else that register is read and displayed.
4734 @deffn Command {arm926ejs mdw_phys} addr [count]
4735 @deffnx Command {arm926ejs mdh_phys} addr [count]
4736 @deffnx Command {arm926ejs mdb_phys} addr [count]
4737 Display contents of physical address @var{addr}, as
4738 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4739 or 8-bit bytes (@command{mdb_phys}).
4740 If @var{count} is specified, displays that many units.
4743 @deffn Command {arm926ejs mww_phys} addr word
4744 @deffnx Command {arm926ejs mwh_phys} addr halfword
4745 @deffnx Command {arm926ejs mwb_phys} addr byte
4746 Writes the specified @var{word} (32 bits),
4747 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4748 at the specified physical address @var{addr}.
4751 @deffn Command {arm926ejs virt2phys} va
4752 Translate a virtual address @var{va} to a physical address
4753 and display the result.
4756 @subsection ARM966E specific commands
4759 These commands are available to ARM966 based CPUs,
4760 which are implementations of the ARMv5TE architecture.
4761 They are available in addition to the ARMv4/5, ARM7/ARM9,
4762 and ARM9TDMI commands.
4764 @deffn Command {arm966e cp15} regnum [value]
4765 Display cp15 register @var{regnum};
4766 else if a @var{value} is provided, that value is written to that register.
4769 @subsection XScale specific commands
4772 These commands are available to XScale based CPUs,
4773 which are implementations of the ARMv5TE architecture.
4775 @deffn Command {xscale analyze_trace}
4776 Displays the contents of the trace buffer.
4779 @deffn Command {xscale cache_clean_address} address
4780 Changes the address used when cleaning the data cache.
4783 @deffn Command {xscale cache_info}
4784 Displays information about the CPU caches.
4787 @deffn Command {xscale cp15} regnum [value]
4788 Display cp15 register @var{regnum};
4789 else if a @var{value} is provided, that value is written to that register.
4792 @deffn Command {xscale debug_handler} target address
4793 Changes the address used for the specified target's debug handler.
4796 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
4797 Enables or disable the CPU's data cache.
4800 @deffn Command {xscale dump_trace} filename
4801 Dumps the raw contents of the trace buffer to @file{filename}.
4804 @deffn Command {xscale icache} (@option{enable}|@option{disable})
4805 Enables or disable the CPU's instruction cache.
4808 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
4809 Enables or disable the CPU's memory management unit.
4812 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
4813 Enables or disables the trace buffer,
4814 and controls how it is emptied.
4817 @deffn Command {xscale trace_image} filename [offset [type]]
4818 Opens a trace image from @file{filename}, optionally rebasing
4819 its segment addresses by @var{offset}.
4820 The image @var{type} may be one of
4821 @option{bin} (binary), @option{ihex} (Intel hex),
4822 @option{elf} (ELF file), @option{s19} (Motorola s19),
4823 @option{mem}, or @option{builder}.
4826 @anchor{xscale vector_catch}
4827 @deffn Command {xscale vector_catch} [mask]
4828 Display a bitmask showing the hardware vectors to catch.
4829 If the optional parameter is provided, first set the bitmask to that value.
4832 @section ARMv6 Architecture
4835 @subsection ARM11 specific commands
4838 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
4839 Read coprocessor register
4842 @deffn Command {arm11 memwrite burst} [value]
4843 Displays the value of the memwrite burst-enable flag,
4844 which is enabled by default.
4845 If @var{value} is defined, first assigns that.
4848 @deffn Command {arm11 memwrite error_fatal} [value]
4849 Displays the value of the memwrite error_fatal flag,
4850 which is enabled by default.
4851 If @var{value} is defined, first assigns that.
4854 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
4855 Write coprocessor register
4858 @deffn Command {arm11 no_increment} [value]
4859 Displays the value of the flag controlling whether
4860 some read or write operations increment the pointer
4861 (the default behavior) or not (acting like a FIFO).
4862 If @var{value} is defined, first assigns that.
4865 @deffn Command {arm11 step_irq_enable} [value]
4866 Displays the value of the flag controlling whether
4867 IRQs are enabled during single stepping;
4868 they is disabled by default.
4869 If @var{value} is defined, first assigns that.
4872 @section ARMv7 Architecture
4875 @subsection ARMv7 Debug Access Port (DAP) specific commands
4876 @cindex Debug Access Port
4878 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
4879 included on cortex-m3 and cortex-a8 systems.
4880 They are available in addition to other core-specific commands that may be available.
4882 @deffn Command {dap info} [num]
4883 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
4886 @deffn Command {dap apsel} [num]
4887 Select AP @var{num}, defaulting to 0.
4890 @deffn Command {dap apid} [num]
4891 Displays id register from AP @var{num},
4892 defaulting to the currently selected AP.
4895 @deffn Command {dap baseaddr} [num]
4896 Displays debug base address from AP @var{num},
4897 defaulting to the currently selected AP.
4900 @deffn Command {dap memaccess} [value]
4901 Displays the number of extra tck for mem-ap memory bus access [0-255].
4902 If @var{value} is defined, first assigns that.
4905 @subsection Cortex-M3 specific commands
4908 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
4909 Control masking (disabling) interrupts during target step/resume.
4912 @section Target DCC Requests
4913 @cindex Linux-ARM DCC support
4916 OpenOCD can handle certain target requests; currently debugmsgs
4917 @command{target_request debugmsgs}
4918 are only supported for arm7_9 and cortex_m3.
4920 See libdcc in the contrib dir for more details.
4921 Linux-ARM kernels have a ``Kernel low-level debugging
4922 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
4923 depends on CONFIG_DEBUG_LL) which uses this mechanism to
4924 deliver messages before a serial console can be activated.
4926 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
4927 Displays current handling of target DCC message requests.
4928 These messages may be sent to the debugger while the target is running.
4929 The optional @option{enable} and @option{charmsg} parameters
4930 both enable the messages, while @option{disable} disables them.
4931 With @option{charmsg} the DCC words each contain one character,
4932 as used by Linux with CONFIG_DEBUG_ICEDCC;
4933 otherwise the libdcc format is used.
4937 @chapter JTAG Commands
4938 @cindex JTAG Commands
4939 Most general purpose JTAG commands have been presented earlier.
4940 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
4941 Lower level JTAG commands, as presented here,
4942 may be needed to work with targets which require special
4943 attention during operations such as reset or initialization.
4945 To use these commands you will need to understand some
4946 of the basics of JTAG, including:
4949 @item A JTAG scan chain consists of a sequence of individual TAP
4950 devices such as a CPUs.
4951 @item Control operations involve moving each TAP through the same
4952 standard state machine (in parallel)
4953 using their shared TMS and clock signals.
4954 @item Data transfer involves shifting data through the chain of
4955 instruction or data registers of each TAP, writing new register values
4956 while the reading previous ones.
4957 @item Data register sizes are a function of the instruction active in
4958 a given TAP, while instruction register sizes are fixed for each TAP.
4959 All TAPs support a BYPASS instruction with a single bit data register.
4960 @item The way OpenOCD differentiates between TAP devices is by
4961 shifting different instructions into (and out of) their instruction
4965 @section Low Level JTAG Commands
4967 These commands are used by developers who need to access
4968 JTAG instruction or data registers, possibly controlling
4969 the order of TAP state transitions.
4970 If you're not debugging OpenOCD internals, or bringing up a
4971 new JTAG adapter or a new type of TAP device (like a CPU or
4972 JTAG router), you probably won't need to use these commands.
4974 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
4975 Loads the data register of @var{tap} with a series of bit fields
4976 that specify the entire register.
4977 Each field is @var{numbits} bits long with
4978 a numeric @var{value} (hexadecimal encouraged).
4979 The return value holds the original value of each
4982 For example, a 38 bit number might be specified as one
4983 field of 32 bits then one of 6 bits.
4984 @emph{For portability, never pass fields which are more
4985 than 32 bits long. Many OpenOCD implementations do not
4986 support 64-bit (or larger) integer values.}
4988 All TAPs other than @var{tap} must be in BYPASS mode.
4989 The single bit in their data registers does not matter.
4991 When @var{tap_state} is specified, the JTAG state machine is left
4993 For example @sc{drpause} might be specified, so that more
4994 instructions can be issued before re-entering the @sc{run/idle} state.
4995 If the end state is not specified, the @sc{run/idle} state is entered.
4998 OpenOCD does not record information about data register lengths,
4999 so @emph{it is important that you get the bit field lengths right}.
5000 Remember that different JTAG instructions refer to different
5001 data registers, which may have different lengths.
5002 Moreover, those lengths may not be fixed;
5003 the SCAN_N instruction can change the length of
5004 the register accessed by the INTEST instruction
5005 (by connecting a different scan chain).
5009 @deffn Command {flush_count}
5010 Returns the number of times the JTAG queue has been flushed.
5011 This may be used for performance tuning.
5013 For example, flushing a queue over USB involves a
5014 minimum latency, often several milliseconds, which does
5015 not change with the amount of data which is written.
5016 You may be able to identify performance problems by finding
5017 tasks which waste bandwidth by flushing small transfers too often,
5018 instead of batching them into larger operations.
5021 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5022 For each @var{tap} listed, loads the instruction register
5023 with its associated numeric @var{instruction}.
5024 (The number of bits in that instruction may be displayed
5025 using the @command{scan_chain} command.)
5026 For other TAPs, a BYPASS instruction is loaded.
5028 When @var{tap_state} is specified, the JTAG state machine is left
5030 For example @sc{irpause} might be specified, so the data register
5031 can be loaded before re-entering the @sc{run/idle} state.
5032 If the end state is not specified, the @sc{run/idle} state is entered.
5035 OpenOCD currently supports only a single field for instruction
5036 register values, unlike data register values.
5037 For TAPs where the instruction register length is more than 32 bits,
5038 portable scripts currently must issue only BYPASS instructions.
5042 @deffn Command {jtag_reset} trst srst
5043 Set values of reset signals.
5044 The @var{trst} and @var{srst} parameter values may be
5045 @option{0}, indicating that reset is inactive (pulled or driven high),
5046 or @option{1}, indicating it is active (pulled or driven low).
5047 The @command{reset_config} command should already have been used
5048 to configure how the board and JTAG adapter treat these two
5049 signals, and to say if either signal is even present.
5050 @xref{Reset Configuration}.
5053 @deffn Command {runtest} @var{num_cycles}
5054 Move to the @sc{run/idle} state, and execute at least
5055 @var{num_cycles} of the JTAG clock (TCK).
5056 Instructions often need some time
5057 to execute before they take effect.
5060 @c tms_sequence (short|long)
5061 @c ... temporary, debug-only, probably gone before 0.2 ships
5063 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5064 Verify values captured during @sc{ircapture} and returned
5065 during IR scans. Default is enabled, but this can be
5066 overridden by @command{verify_jtag}.
5069 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5070 Enables verification of DR and IR scans, to help detect
5071 programming errors. For IR scans, @command{verify_ircapture}
5072 must also be enabled.
5076 @section TAP state names
5077 @cindex TAP state names
5079 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5080 and @command{irscan} commands are:
5083 @item @b{RESET} ... should act as if TRST were active
5084 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5087 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5089 @item @b{DRPAUSE} ... data register ready for update or more shifting
5094 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5096 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5101 Note that only six of those states are fully ``stable'' in the
5102 face of TMS fixed (low except for @sc{reset})
5103 and a free-running JTAG clock. For all the
5104 others, the next TCK transition changes to a new state.
5107 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5108 produce side effects by changing register contents. The values
5109 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5110 may not be as expected.
5111 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5112 choices after @command{drscan} or @command{irscan} commands,
5113 since they are free of JTAG side effects.
5114 However, @sc{run/idle} may have side effects that appear at other
5115 levels, such as advancing the ARM9E-S instruction pipeline.
5116 Consult the documentation for the TAP(s) you are working with.
5122 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5123 be used to access files on PCs (either the developer's PC or some other PC).
5125 The way this works on the ZY1000 is to prefix a filename by
5126 "/tftp/ip/" and append the TFTP path on the TFTP
5127 server (tftpd). For example,
5130 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5133 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5134 if the file was hosted on the embedded host.
5136 In order to achieve decent performance, you must choose a TFTP server
5137 that supports a packet size bigger than the default packet size (512 bytes). There
5138 are numerous TFTP servers out there (free and commercial) and you will have to do
5139 a bit of googling to find something that fits your requirements.
5141 @node GDB and OpenOCD
5142 @chapter GDB and OpenOCD
5144 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5145 to debug remote targets.
5147 @anchor{Connecting to GDB}
5148 @section Connecting to GDB
5149 @cindex Connecting to GDB
5150 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5151 instance GDB 6.3 has a known bug that produces bogus memory access
5152 errors, which has since been fixed: look up 1836 in
5153 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5155 OpenOCD can communicate with GDB in two ways:
5159 A socket (TCP/IP) connection is typically started as follows:
5161 target remote localhost:3333
5163 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5165 A pipe connection is typically started as follows:
5167 target remote | openocd --pipe
5169 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5170 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5174 To list the available OpenOCD commands type @command{monitor help} on the
5177 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5178 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5179 packet size and the device's memory map.
5181 Previous versions of OpenOCD required the following GDB options to increase
5182 the packet size and speed up GDB communication:
5184 set remote memory-write-packet-size 1024
5185 set remote memory-write-packet-size fixed
5186 set remote memory-read-packet-size 1024
5187 set remote memory-read-packet-size fixed
5189 This is now handled in the @option{qSupported} PacketSize and should not be required.
5191 @section Programming using GDB
5192 @cindex Programming using GDB
5194 By default the target memory map is sent to GDB. This can be disabled by
5195 the following OpenOCD configuration option:
5197 gdb_memory_map disable
5199 For this to function correctly a valid flash configuration must also be set
5200 in OpenOCD. For faster performance you should also configure a valid
5203 Informing GDB of the memory map of the target will enable GDB to protect any
5204 flash areas of the target and use hardware breakpoints by default. This means
5205 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5206 using a memory map. @xref{gdb_breakpoint_override}.
5208 To view the configured memory map in GDB, use the GDB command @option{info mem}
5209 All other unassigned addresses within GDB are treated as RAM.
5211 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5212 This can be changed to the old behaviour by using the following GDB command
5214 set mem inaccessible-by-default off
5217 If @command{gdb_flash_program enable} is also used, GDB will be able to
5218 program any flash memory using the vFlash interface.
5220 GDB will look at the target memory map when a load command is given, if any
5221 areas to be programmed lie within the target flash area the vFlash packets
5224 If the target needs configuring before GDB programming, an event
5225 script can be executed:
5227 $_TARGETNAME configure -event EVENTNAME BODY
5230 To verify any flash programming the GDB command @option{compare-sections}
5233 @node Tcl Scripting API
5234 @chapter Tcl Scripting API
5235 @cindex Tcl Scripting API
5239 The commands are stateless. E.g. the telnet command line has a concept
5240 of currently active target, the Tcl API proc's take this sort of state
5241 information as an argument to each proc.
5243 There are three main types of return values: single value, name value
5244 pair list and lists.
5246 Name value pair. The proc 'foo' below returns a name/value pair
5252 > set foo(you) Oyvind
5253 > set foo(mouse) Micky
5254 > set foo(duck) Donald
5262 me Duane you Oyvind mouse Micky duck Donald
5264 Thus, to get the names of the associative array is easy:
5266 foreach { name value } [set foo] {
5267 puts "Name: $name, Value: $value"
5271 Lists returned must be relatively small. Otherwise a range
5272 should be passed in to the proc in question.
5274 @section Internal low-level Commands
5276 By low-level, the intent is a human would not directly use these commands.
5278 Low-level commands are (should be) prefixed with "ocd_", e.g.
5279 @command{ocd_flash_banks}
5280 is the low level API upon which @command{flash banks} is implemented.
5283 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5285 Read memory and return as a Tcl array for script processing
5286 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5288 Convert a Tcl array to memory locations and write the values
5289 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
5291 Return information about the flash banks
5294 OpenOCD commands can consist of two words, e.g. "flash banks". The
5295 startup.tcl "unknown" proc will translate this into a Tcl proc
5296 called "flash_banks".
5298 @section OpenOCD specific Global Variables
5302 Real Tcl has ::tcl_platform(), and platform::identify, and many other
5303 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
5304 holds one of the following values:
5307 @item @b{winxx} Built using Microsoft Visual Studio
5308 @item @b{linux} Linux is the underlying operating sytem
5309 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
5310 @item @b{cygwin} Running under Cygwin
5311 @item @b{mingw32} Running under MingW32
5312 @item @b{other} Unknown, none of the above.
5315 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5318 We should add support for a variable like Tcl variable
5319 @code{tcl_platform(platform)}, it should be called
5320 @code{jim_platform} (because it
5321 is jim, not real tcl).
5325 @chapter Deprecated/Removed Commands
5326 @cindex Deprecated/Removed Commands
5327 Certain OpenOCD commands have been deprecated or
5328 removed during the various revisions.
5330 Upgrade your scripts as soon as possible.
5331 These descriptions for old commands may be removed
5332 a year after the command itself was removed.
5333 This means that in January 2010 this chapter may
5334 become much shorter.
5337 @item @b{arm7_9 fast_writes}
5338 @cindex arm7_9 fast_writes
5339 @*Use @command{arm7_9 fast_memory_access} instead.
5342 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5343 @xref{arm7_9 fast_memory_access}.
5344 @item @b{arm7_9 force_hw_bkpts}
5345 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5346 for flash if the GDB memory map has been set up(default when flash is declared in
5347 target configuration). @xref{gdb_breakpoint_override}.
5348 @item @b{arm7_9 sw_bkpts}
5349 @*On by default. @xref{gdb_breakpoint_override}.
5350 @item @b{daemon_startup}
5351 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5352 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5353 and @option{target cortex_m3 little reset_halt 0}.
5354 @item @b{dump_binary}
5355 @*use @option{dump_image} command with same args. @xref{dump_image}.
5356 @item @b{flash erase}
5357 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5358 @item @b{flash write}
5359 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5360 @item @b{flash write_binary}
5361 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5362 @item @b{flash auto_erase}
5363 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5365 @item @b{jtag_device}
5366 @*use the @command{jtag newtap} command, converting from positional syntax
5367 to named prefixes, and naming the TAP.
5369 Note that if you try to use the old command, a message will tell you the
5370 right new command to use; and that the fourth parameter in the old syntax
5371 was never actually used.
5373 OLD: jtag_device 8 0x01 0xe3 0xfe
5374 NEW: jtag newtap CHIPNAME TAPNAME \
5375 -irlen 8 -ircapture 0x01 -irmask 0xe3
5378 @item @b{jtag_speed} value
5379 @*@xref{JTAG Speed}.
5380 Usually, a value of zero means maximum
5381 speed. The actual effect of this option depends on the JTAG interface used.
5383 @item wiggler: maximum speed / @var{number}
5384 @item ft2232: 6MHz / (@var{number}+1)
5385 @item amt jtagaccel: 8 / 2**@var{number}
5386 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5387 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5388 @comment end speed list.
5391 @item @b{load_binary}
5392 @*use @option{load_image} command with same args. @xref{load_image}.
5393 @item @b{run_and_halt_time}
5394 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5401 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5402 @*use the create subcommand of @option{target}.
5403 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5404 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5405 @item @b{working_area}
5406 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5414 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5416 @cindex adaptive clocking
5419 In digital circuit design it is often refered to as ``clock
5420 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5421 operating at some speed, your target is operating at another. The two
5422 clocks are not synchronised, they are ``asynchronous''
5424 In order for the two to work together they must be synchronised. Otherwise
5425 the two systems will get out of sync with each other and nothing will
5426 work. There are 2 basic options:
5429 Use a special circuit.
5431 One clock must be some multiple slower than the other.
5434 @b{Does this really matter?} For some chips and some situations, this
5435 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
5436 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
5437 program/enable the oscillators and eventually the main clock. It is in
5438 those critical times you must slow the JTAG clock to sometimes 1 to
5441 Imagine debugging a 500MHz ARM926 hand held battery powered device
5442 that ``deep sleeps'' at 32kHz between every keystroke. It can be
5445 @b{Solution #1 - A special circuit}
5447 In order to make use of this, your JTAG dongle must support the RTCK
5448 feature. Not all dongles support this - keep reading!
5450 The RTCK signal often found in some ARM chips is used to help with
5451 this problem. ARM has a good description of the problem described at
5452 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
5453 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
5454 work? / how does adaptive clocking work?''.
5456 The nice thing about adaptive clocking is that ``battery powered hand
5457 held device example'' - the adaptiveness works perfectly all the
5458 time. One can set a break point or halt the system in the deep power
5459 down code, slow step out until the system speeds up.
5461 @b{Solution #2 - Always works - but may be slower}
5463 Often this is a perfectly acceptable solution.
5465 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
5466 the target clock speed. But what that ``magic division'' is varies
5467 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
5468 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
5469 1/12 the clock speed.
5471 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
5473 You can still debug the 'low power' situations - you just need to
5474 manually adjust the clock speed at every step. While painful and
5475 tedious, it is not always practical.
5477 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
5478 have a special debug mode in your application that does a ``high power
5479 sleep''. If you are careful - 98% of your problems can be debugged
5482 To set the JTAG frequency use the command:
5490 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
5492 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
5493 around Windows filenames.
5506 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
5508 Make sure you have Cygwin installed, or at least a version of OpenOCD that
5509 claims to come with all the necessary DLLs. When using Cygwin, try launching
5510 OpenOCD from the Cygwin shell.
5512 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
5513 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
5514 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
5516 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
5517 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
5518 software breakpoints consume one of the two available hardware breakpoints.
5520 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
5522 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
5523 clock at the time you're programming the flash. If you've specified the crystal's
5524 frequency, make sure the PLL is disabled. If you've specified the full core speed
5525 (e.g. 60MHz), make sure the PLL is enabled.
5527 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
5528 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
5529 out while waiting for end of scan, rtck was disabled".
5531 Make sure your PC's parallel port operates in EPP mode. You might have to try several
5532 settings in your PC BIOS (ECP, EPP, and different versions of those).
5534 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
5535 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
5536 memory read caused data abort".
5538 The errors are non-fatal, and are the result of GDB trying to trace stack frames
5539 beyond the last valid frame. It might be possible to prevent this by setting up
5540 a proper "initial" stack frame, if you happen to know what exactly has to
5541 be done, feel free to add this here.
5543 @b{Simple:} In your startup code - push 8 registers of zeros onto the
5544 stack before calling main(). What GDB is doing is ``climbing'' the run
5545 time stack by reading various values on the stack using the standard
5546 call frame for the target. GDB keeps going - until one of 2 things
5547 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
5548 stackframes have been processed. By pushing zeros on the stack, GDB
5551 @b{Debugging Interrupt Service Routines} - In your ISR before you call
5552 your C code, do the same - artifically push some zeros onto the stack,
5553 remember to pop them off when the ISR is done.
5555 @b{Also note:} If you have a multi-threaded operating system, they
5556 often do not @b{in the intrest of saving memory} waste these few
5560 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
5561 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
5563 This warning doesn't indicate any serious problem, as long as you don't want to
5564 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
5565 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
5566 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
5567 independently. With this setup, it's not possible to halt the core right out of
5568 reset, everything else should work fine.
5570 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
5571 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
5572 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
5573 quit with an error message. Is there a stability issue with OpenOCD?
5575 No, this is not a stability issue concerning OpenOCD. Most users have solved
5576 this issue by simply using a self-powered USB hub, which they connect their
5577 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
5578 supply stable enough for the Amontec JTAGkey to be operated.
5580 @b{Laptops running on battery have this problem too...}
5582 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
5583 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
5584 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
5585 What does that mean and what might be the reason for this?
5587 First of all, the reason might be the USB power supply. Try using a self-powered
5588 hub instead of a direct connection to your computer. Secondly, the error code 4
5589 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
5590 chip ran into some sort of error - this points us to a USB problem.
5592 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
5593 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
5594 What does that mean and what might be the reason for this?
5596 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
5597 has closed the connection to OpenOCD. This might be a GDB issue.
5599 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
5600 are described, there is a parameter for specifying the clock frequency
5601 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
5602 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
5603 specified in kilohertz. However, I do have a quartz crystal of a
5604 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
5605 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
5608 No. The clock frequency specified here must be given as an integral number.
5609 However, this clock frequency is used by the In-Application-Programming (IAP)
5610 routines of the LPC2000 family only, which seems to be very tolerant concerning
5611 the given clock frequency, so a slight difference between the specified clock
5612 frequency and the actual clock frequency will not cause any trouble.
5614 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
5616 Well, yes and no. Commands can be given in arbitrary order, yet the
5617 devices listed for the JTAG scan chain must be given in the right
5618 order (jtag newdevice), with the device closest to the TDO-Pin being
5619 listed first. In general, whenever objects of the same type exist
5620 which require an index number, then these objects must be given in the
5621 right order (jtag newtap, targets and flash banks - a target
5622 references a jtag newtap and a flash bank references a target).
5624 You can use the ``scan_chain'' command to verify and display the tap order.
5626 Also, some commands can't execute until after @command{init} has been
5627 processed. Such commands include @command{nand probe} and everything
5628 else that needs to write to controller registers, perhaps for setting
5629 up DRAM and loading it with code.
5631 @anchor{FAQ TAP Order}
5632 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
5635 Yes; whenever you have more than one, you must declare them in
5636 the same order used by the hardware.
5638 Many newer devices have multiple JTAG TAPs. For example: ST
5639 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
5640 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
5641 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
5642 connected to the boundary scan TAP, which then connects to the
5643 Cortex-M3 TAP, which then connects to the TDO pin.
5645 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
5646 (2) The boundary scan TAP. If your board includes an additional JTAG
5647 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
5648 place it before or after the STM32 chip in the chain. For example:
5651 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
5652 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
5653 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
5654 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
5655 @item Xilinx TDO Pin -> OpenOCD TDO (input)
5658 The ``jtag device'' commands would thus be in the order shown below. Note:
5661 @item jtag newtap Xilinx tap -irlen ...
5662 @item jtag newtap stm32 cpu -irlen ...
5663 @item jtag newtap stm32 bs -irlen ...
5664 @item # Create the debug target and say where it is
5665 @item target create stm32.cpu -chain-position stm32.cpu ...
5669 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
5670 log file, I can see these error messages: Error: arm7_9_common.c:561
5671 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
5677 @node Tcl Crash Course
5678 @chapter Tcl Crash Course
5681 Not everyone knows Tcl - this is not intended to be a replacement for
5682 learning Tcl, the intent of this chapter is to give you some idea of
5683 how the Tcl scripts work.
5685 This chapter is written with two audiences in mind. (1) OpenOCD users
5686 who need to understand a bit more of how JIM-Tcl works so they can do
5687 something useful, and (2) those that want to add a new command to
5690 @section Tcl Rule #1
5691 There is a famous joke, it goes like this:
5693 @item Rule #1: The wife is always correct
5694 @item Rule #2: If you think otherwise, See Rule #1
5697 The Tcl equal is this:
5700 @item Rule #1: Everything is a string
5701 @item Rule #2: If you think otherwise, See Rule #1
5704 As in the famous joke, the consequences of Rule #1 are profound. Once
5705 you understand Rule #1, you will understand Tcl.
5707 @section Tcl Rule #1b
5708 There is a second pair of rules.
5710 @item Rule #1: Control flow does not exist. Only commands
5711 @* For example: the classic FOR loop or IF statement is not a control
5712 flow item, they are commands, there is no such thing as control flow
5714 @item Rule #2: If you think otherwise, See Rule #1
5715 @* Actually what happens is this: There are commands that by
5716 convention, act like control flow key words in other languages. One of
5717 those commands is the word ``for'', another command is ``if''.
5720 @section Per Rule #1 - All Results are strings
5721 Every Tcl command results in a string. The word ``result'' is used
5722 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
5723 Everything is a string}
5725 @section Tcl Quoting Operators
5726 In life of a Tcl script, there are two important periods of time, the
5727 difference is subtle.
5730 @item Evaluation Time
5733 The two key items here are how ``quoted things'' work in Tcl. Tcl has
5734 three primary quoting constructs, the [square-brackets] the
5735 @{curly-braces@} and ``double-quotes''
5737 By now you should know $VARIABLES always start with a $DOLLAR
5738 sign. BTW: To set a variable, you actually use the command ``set'', as
5739 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
5740 = 1'' statement, but without the equal sign.
5743 @item @b{[square-brackets]}
5744 @* @b{[square-brackets]} are command substitutions. It operates much
5745 like Unix Shell `back-ticks`. The result of a [square-bracket]
5746 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
5747 string}. These two statements are roughly identical:
5751 echo "The Date is: $X"
5754 puts "The Date is: $X"
5756 @item @b{``double-quoted-things''}
5757 @* @b{``double-quoted-things''} are just simply quoted
5758 text. $VARIABLES and [square-brackets] are expanded in place - the
5759 result however is exactly 1 string. @i{Remember Rule #1 - Everything
5763 puts "It is now \"[date]\", $x is in 1 hour"
5765 @item @b{@{Curly-Braces@}}
5766 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
5767 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
5768 'single-quote' operators in BASH shell scripts, with the added
5769 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
5770 nested 3 times@}@}@} NOTE: [date] is a bad example;
5771 at this writing, Jim/OpenOCD does not have a date command.
5774 @section Consequences of Rule 1/2/3/4
5776 The consequences of Rule 1 are profound.
5778 @subsection Tokenisation & Execution.
5780 Of course, whitespace, blank lines and #comment lines are handled in
5783 As a script is parsed, each (multi) line in the script file is
5784 tokenised and according to the quoting rules. After tokenisation, that
5785 line is immedatly executed.
5787 Multi line statements end with one or more ``still-open''
5788 @{curly-braces@} which - eventually - closes a few lines later.
5790 @subsection Command Execution
5792 Remember earlier: There are no ``control flow''
5793 statements in Tcl. Instead there are COMMANDS that simply act like
5794 control flow operators.
5796 Commands are executed like this:
5799 @item Parse the next line into (argc) and (argv[]).
5800 @item Look up (argv[0]) in a table and call its function.
5801 @item Repeat until End Of File.
5804 It sort of works like this:
5807 ReadAndParse( &argc, &argv );
5809 cmdPtr = LookupCommand( argv[0] );
5811 (*cmdPtr->Execute)( argc, argv );
5815 When the command ``proc'' is parsed (which creates a procedure
5816 function) it gets 3 parameters on the command line. @b{1} the name of
5817 the proc (function), @b{2} the list of parameters, and @b{3} the body
5818 of the function. Not the choice of words: LIST and BODY. The PROC
5819 command stores these items in a table somewhere so it can be found by
5822 @subsection The FOR command
5824 The most interesting command to look at is the FOR command. In Tcl,
5825 the FOR command is normally implemented in C. Remember, FOR is a
5826 command just like any other command.
5828 When the ascii text containing the FOR command is parsed, the parser
5829 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
5833 @item The ascii text 'for'
5834 @item The start text
5835 @item The test expression
5840 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
5841 Remember @i{Rule #1 - Everything is a string.} The key point is this:
5842 Often many of those parameters are in @{curly-braces@} - thus the
5843 variables inside are not expanded or replaced until later.
5845 Remember that every Tcl command looks like the classic ``main( argc,
5846 argv )'' function in C. In JimTCL - they actually look like this:
5850 MyCommand( Jim_Interp *interp,
5852 Jim_Obj * const *argvs );
5855 Real Tcl is nearly identical. Although the newer versions have
5856 introduced a byte-code parser and intepreter, but at the core, it
5857 still operates in the same basic way.
5859 @subsection FOR command implementation
5861 To understand Tcl it is perhaps most helpful to see the FOR
5862 command. Remember, it is a COMMAND not a control flow structure.
5864 In Tcl there are two underlying C helper functions.
5866 Remember Rule #1 - You are a string.
5868 The @b{first} helper parses and executes commands found in an ascii
5869 string. Commands can be seperated by semicolons, or newlines. While
5870 parsing, variables are expanded via the quoting rules.
5872 The @b{second} helper evaluates an ascii string as a numerical
5873 expression and returns a value.
5875 Here is an example of how the @b{FOR} command could be
5876 implemented. The pseudo code below does not show error handling.
5878 void Execute_AsciiString( void *interp, const char *string );
5880 int Evaluate_AsciiExpression( void *interp, const char *string );
5883 MyForCommand( void *interp,
5888 SetResult( interp, "WRONG number of parameters");
5892 // argv[0] = the ascii string just like C
5894 // Execute the start statement.
5895 Execute_AsciiString( interp, argv[1] );
5899 i = Evaluate_AsciiExpression(interp, argv[2]);
5904 Execute_AsciiString( interp, argv[3] );
5906 // Execute the LOOP part
5907 Execute_AsciiString( interp, argv[4] );
5911 SetResult( interp, "" );
5916 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
5917 in the same basic way.
5919 @section OpenOCD Tcl Usage
5921 @subsection source and find commands
5922 @b{Where:} In many configuration files
5923 @* Example: @b{ source [find FILENAME] }
5924 @*Remember the parsing rules
5926 @item The FIND command is in square brackets.
5927 @* The FIND command is executed with the parameter FILENAME. It should
5928 find the full path to the named file. The RESULT is a string, which is
5929 substituted on the orginal command line.
5930 @item The command source is executed with the resulting filename.
5931 @* SOURCE reads a file and executes as a script.
5933 @subsection format command
5934 @b{Where:} Generally occurs in numerous places.
5935 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
5941 puts [format "The answer: %d" [expr $x * $y]]
5944 @item The SET command creates 2 variables, X and Y.
5945 @item The double [nested] EXPR command performs math
5946 @* The EXPR command produces numerical result as a string.
5948 @item The format command is executed, producing a single string
5949 @* Refer to Rule #1.
5950 @item The PUTS command outputs the text.
5952 @subsection Body or Inlined Text
5953 @b{Where:} Various TARGET scripts.
5956 proc someproc @{@} @{
5957 ... multiple lines of stuff ...
5959 $_TARGETNAME configure -event FOO someproc
5960 #2 Good - no variables
5961 $_TARGETNAME confgure -event foo "this ; that;"
5962 #3 Good Curly Braces
5963 $_TARGETNAME configure -event FOO @{
5966 #4 DANGER DANGER DANGER
5967 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
5970 @item The $_TARGETNAME is an OpenOCD variable convention.
5971 @*@b{$_TARGETNAME} represents the last target created, the value changes
5972 each time a new target is created. Remember the parsing rules. When
5973 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
5974 the name of the target which happens to be a TARGET (object)
5976 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
5977 @*There are 4 examples:
5979 @item The TCLBODY is a simple string that happens to be a proc name
5980 @item The TCLBODY is several simple commands seperated by semicolons
5981 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
5982 @item The TCLBODY is a string with variables that get expanded.
5985 In the end, when the target event FOO occurs the TCLBODY is
5986 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
5987 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
5989 Remember the parsing rules. In case #3, @{curly-braces@} mean the
5990 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
5991 and the text is evaluated. In case #4, they are replaced before the
5992 ``Target Object Command'' is executed. This occurs at the same time
5993 $_TARGETNAME is replaced. In case #4 the date will never
5994 change. @{BTW: [date] is a bad example; at this writing,
5995 Jim/OpenOCD does not have a date command@}
5997 @subsection Global Variables
5998 @b{Where:} You might discover this when writing your own procs @* In
5999 simple terms: Inside a PROC, if you need to access a global variable
6000 you must say so. See also ``upvar''. Example:
6002 proc myproc @{ @} @{
6003 set y 0 #Local variable Y
6004 global x #Global variable X
6005 puts [format "X=%d, Y=%d" $x $y]
6008 @section Other Tcl Hacks
6009 @b{Dynamic variable creation}
6011 # Dynamically create a bunch of variables.
6012 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6014 set vn [format "BIT%d" $x]
6018 set $vn [expr (1 << $x)]
6021 @b{Dynamic proc/command creation}
6023 # One "X" function - 5 uart functions.
6024 foreach who @{A B C D E@}
6025 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6029 @node Target Library
6030 @chapter Target Library
6031 @cindex Target Library
6033 OpenOCD comes with a target configuration script library. These scripts can be
6034 used as-is or serve as a starting point.
6036 The target library is published together with the OpenOCD executable and
6037 the path to the target library is in the OpenOCD script search path.
6038 Similarly there are example scripts for configuring the JTAG interface.
6040 The command line below uses the example parport configuration script
6041 that ship with OpenOCD, then configures the str710.cfg target and
6042 finally issues the init and reset commands. The communication speed
6043 is set to 10kHz for reset and 8MHz for post reset.
6046 openocd -f interface/parport.cfg -f target/str710.cfg \
6047 -c "init" -c "reset"
6050 To list the target scripts available:
6053 $ ls /usr/local/lib/openocd/target
6055 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6056 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6057 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6058 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6063 @node OpenOCD Concept Index
6064 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6065 @comment case issue with ``Index.html'' and ``index.html''
6066 @comment Occurs when creating ``--html --no-split'' output
6067 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6068 @unnumbered OpenOCD Concept Index
6072 @node Command and Driver Index
6073 @unnumbered Command and Driver Index