1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building:: Building OpenOCD
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
92 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
93 in-system programming and boundary-scan testing for embedded target
96 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
97 with the JTAG (IEEE 1149.1) compliant taps on your target board.
99 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
100 based, parallel port based, and other standalone boxes that run
101 OpenOCD internally. See the section titled: @xref{JTAG Hardware Dongles}.
103 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
104 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
105 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
106 debugged via the GDB protocol.
108 @b{Flash Programing:} Flash writing is supported for external CFI
109 compatible NOR flashes (Intel and AMD/Spansion command set) and several
110 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
111 STM32x). Preliminary support for various NAND flash controllers
112 (LPC3180, Orion, S3C24xx, more) controller is included.
118 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
119 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
120 Others interested in improving the state of free and open debug and testing technology
121 are welcome to participate.
123 Other developers have contributed support for additional targets and flashes as well
124 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
126 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}.
128 @section Coding Style
131 The following rules try to describe formatting and naming conventions that should be
132 followed to make the whole OpenOCD code look more consistent. The ultimate goal of
133 coding style should be readability, and these rules may be ignored for a particular
134 (small) piece of code if that makes it more readable.
136 @subsection Formatting rules:
138 @item remove any trailing white space
139 @item use TAB characters for indentation, not spaces
140 @item displayed TAB width is 4 characters
141 @item make sure NOT to use DOS '\r\n' line feeds
142 @item do not add more than 2 empty lines to source files
143 @item do not add trailing empty lines to source files
144 @item do not use C++ style comments (//)
145 @item lines may be reasonably wide - there's no anachronistic 80 characters limit
148 @subsection Naming rules:
150 @item identifiers use lower-case letters only
151 @item identifiers consisting of multiple words use underline characters between consecutive words
152 @item macros use upper-case letters only
153 @item structure names shall be appended with '_s'
154 @item typedefs shall be appended with '_t'
157 @subsection Function calls:
159 @item function calls have no space between the functions name and the parameter
160 list: my_func(param1, param2, ...)
165 @cindex building OpenOCD
167 @section Pre-Built Tools
168 If you are interested in getting actual work done rather than building
169 OpenOCD, then check if your interface supplier provides binaries for
170 you. Chances are that that binary is from some SVN version that is more
171 stable than SVN trunk where bleeding edge development takes place.
173 @section Packagers Please Read!
175 You are a @b{PACKAGER} of OpenOCD if you
178 @item @b{Sell dongles} and include pre-built binaries
179 @item @b{Supply tools} i.e.: A complete development solution
180 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
181 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
184 As a @b{PACKAGER} - you are at the top of the food chain. You solve
185 problems for downstream users. What you fix or solve - solves hundreds
186 if not thousands of user questions. If something does not work for you
187 please let us know. That said, would also like you to follow a few
191 @item @b{Always build with printer ports enabled.}
192 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
196 @item @b{Why YES to LIBFTDI + LIBUSB?}
198 @item @b{LESS} work - libusb perhaps already there
199 @item @b{LESS} work - identical code, multiple platforms
200 @item @b{MORE} dongles are supported
201 @item @b{MORE} platforms are supported
202 @item @b{MORE} complete solution
204 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
206 @item @b{LESS} speed - some say it is slower
207 @item @b{LESS} complex to distribute (external dependencies)
211 @section Building From Source
213 You can download the current SVN version with an SVN client of your choice from the
214 following repositories:
216 @uref{svn://svn.berlios.de/openocd/trunk}
220 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
222 Using the SVN command line client, you can use the following command to fetch the
223 latest version (make sure there is no (non-svn) directory called "openocd" in the
227 svn checkout svn://svn.berlios.de/openocd/trunk openocd
230 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
231 For building on Windows,
232 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
233 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
234 paths, resulting in obscure dependency errors (This is an observation I've gathered
235 from the logs of one user - correct me if I'm wrong).
237 You further need the appropriate driver files, if you want to build support for
238 a FTDI FT2232 based interface:
241 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
242 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
243 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
244 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
247 libftdi is supported under Windows. Do not use versions earlier than 0.14.
249 In general, the D2XX driver provides superior performance (several times as fast),
250 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
251 a kernel module, only a user space library.
253 To build OpenOCD (on both Linux and Cygwin), use the following commands:
259 Bootstrap generates the configure script, and prepares building on your system.
262 ./configure [options, see below]
265 Configure generates the Makefiles used to build OpenOCD.
272 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
274 The configure script takes several options, specifying which JTAG interfaces
275 should be included (among other things):
279 @option{--enable-parport} - Enable building the PC parallel port driver.
281 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
283 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
285 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
287 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
289 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
291 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
293 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
295 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
297 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
299 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
301 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
303 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
305 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
307 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
309 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
311 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
313 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
315 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
317 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
319 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
321 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
323 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
325 @option{--enable-dummy} - Enable building the dummy port driver.
328 @section Parallel Port Dongles
330 If you want to access the parallel port using the PPDEV interface you have to specify
331 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
332 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
333 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
335 The same is true for the @option{--enable-parport_giveio} option, you have to
336 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
338 @section FT2232C Based USB Dongles
340 There are 2 methods of using the FTD2232, either (1) using the
341 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
342 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
344 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
345 TAR.GZ file. You must unpack them ``some where'' convient. As of this
346 writing (12/26/2008) FTDICHIP does not supply means to install these
347 files ``in an appropriate place'' As a result, there are two
348 ``./configure'' options that help.
350 Below is an example build process:
352 1) Check out the latest version of ``openocd'' from SVN.
354 2) Download & unpack either the Windows or Linux FTD2xx drivers
355 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
358 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
359 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
362 3) Configure with these options:
365 Cygwin FTDICHIP solution:
366 ./configure --prefix=/home/duane/mytools \
367 --enable-ft2232_ftd2xx \
368 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
370 Linux FTDICHIP solution:
371 ./configure --prefix=/home/duane/mytools \
372 --enable-ft2232_ftd2xx \
373 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
375 Cygwin/Linux LIBFTDI solution:
377 1a) For Windows: The Windows port of LIBUSB is in place.
378 1b) For Linux: libusb has been built/installed and is in place.
380 2) And libftdi has been built and installed
381 Note: libftdi - relies upon libusb.
383 ./configure --prefix=/home/duane/mytools \
384 --enable-ft2232_libftdi
388 4) Then just type ``make'', and perhaps ``make install''.
391 @section Miscellaneous Configure Options
395 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
397 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
400 @option{--enable-release} - Enable building of an OpenOCD release, generally
401 this is for developers. It simply omits the svn version string when the
402 openocd @option{-v} is executed.
405 @node JTAG Hardware Dongles
406 @chapter JTAG Hardware Dongles
415 Defined: @b{dongle}: A small device that plugins into a computer and serves as
416 an adapter .... [snip]
418 In the OpenOCD case, this generally refers to @b{a small adapater} one
419 attaches to your computer via USB or the Parallel Printer Port. The
420 execption being the Zylin ZY1000 which is a small box you attach via
421 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
422 require any drivers to be installed on the developer PC. It also has
423 a built in web interface. It supports RTCK/RCLK or adaptive clocking
424 and has a built in relay to power cycle targets remotely.
427 @section Choosing a Dongle
429 There are three things you should keep in mind when choosing a dongle.
432 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
433 @item @b{Connection} Printer Ports - Does your computer have one?
434 @item @b{Connection} Is that long printer bit-bang cable practical?
435 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
438 @section Stand alone Systems
440 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
441 dongle, but a standalone box. The ZY1000 has the advantage that it does
442 not require any drivers installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
446 @section USB FT2232 Based
448 There are many USB JTAG dongles on the market, many of them are based
449 on a chip from ``Future Technology Devices International'' (FTDI)
450 known as the FTDI FT2232.
452 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
454 As of 28/Nov/2008, the following are supported:
458 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
460 @* See: @url{http://www.amontec.com/jtagkey.shtml}
462 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
464 @* See: @url{http://www.signalyzer.com}
465 @item @b{evb_lm3s811}
466 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
467 @item @b{olimex-jtag}
468 @* See: @url{http://www.olimex.com}
470 @* See: @url{http://www.tincantools.com}
471 @item @b{turtelizer2}
472 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
474 @* Link: @url{http://www.hitex.com/index.php?id=383}
476 @* Link @url{http://www.hitex.com/stm32-stick}
477 @item @b{axm0432_jtag}
478 @* Axiom AXM-0432 Link @url{http://www.axman.com}
481 @section USB JLINK based
482 There are several OEM versions of the Segger @b{JLINK} adapter. It is
483 an example of a micro controller based JTAG adapter, it uses an
484 AT91SAM764 internally.
487 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
488 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
489 @item @b{SEGGER JLINK}
490 @* Link: @url{http://www.segger.com/jlink.html}
492 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
495 @section USB RLINK based
496 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
499 @item @b{Raisonance RLink}
500 @* Link: @url{http://www.raisonance.com/products/RLink.php}
501 @item @b{STM32 Primer}
502 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
503 @item @b{STM32 Primer2}
504 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
510 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
512 @item @b{USB - Presto}
513 @* Link: @url{http://tools.asix.net/prg_presto.htm}
515 @item @b{Versaloon-Link}
516 @* Link: @url{http://www.simonqian.com/en/Versaloon}
518 @item @b{ARM-JTAG-EW}
519 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
522 @section IBM PC Parallel Printer Port Based
524 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
525 and the MacGraigor Wiggler. There are many clones and variations of
530 @item @b{Wiggler} - There are many clones of this.
531 @* Link: @url{http://www.macraigor.com/wiggler.htm}
533 @item @b{DLC5} - From XILINX - There are many clones of this
534 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
535 produced, PDF schematics are easily found and it is easy to make.
537 @item @b{Amontec - JTAG Accelerator}
538 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
541 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
544 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
546 @item @b{Wiggler_ntrst_inverted}
547 @* Yet another variation - See the source code, src/jtag/parport.c
549 @item @b{old_amt_wiggler}
550 @* Unknown - probably not on the market today
553 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
556 @* Link: @url{http://www.amontec.com/chameleon.shtml}
562 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
565 @* From ST Microsystems, link:
566 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
567 Title: FlashLINK JTAG programing cable for PSD and uPSD
575 @* An EP93xx based Linux machine using the GPIO pins directly.
578 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
584 @cindex running OpenOCD
586 @cindex --debug_level
590 The @option{--help} option shows:
594 --help | -h display this help
595 --version | -v display OpenOCD version
596 --file | -f use configuration file <name>
597 --search | -s dir to search for config files and scripts
598 --debug | -d set debug level <0-3>
599 --log_output | -l redirect log output to file <name>
600 --command | -c run <command>
601 --pipe | -p use pipes when talking to gdb
604 By default OpenOCD reads the file configuration file ``openocd.cfg''
605 in the current directory. To specify a different (or multiple)
606 configuration file, you can use the ``-f'' option. For example:
609 openocd -f config1.cfg -f config2.cfg -f config3.cfg
612 Once started, OpenOCD runs as a daemon, waiting for connections from
613 clients (Telnet, GDB, Other).
615 If you are having problems, you can enable internal debug messages via
618 Also it is possible to interleave commands w/config scripts using the
619 @option{-c} command line switch.
621 To enable debug output (when reporting problems or working on OpenOCD
622 itself), use the @option{-d} command line switch. This sets the
623 @option{debug_level} to "3", outputting the most information,
624 including debug messages. The default setting is "2", outputting only
625 informational messages, warnings and errors. You can also change this
626 setting from within a telnet or gdb session using @option{debug_level
627 <n>} @xref{debug_level}.
629 You can redirect all output from the daemon to a file using the
630 @option{-l <logfile>} switch.
632 Search paths for config/script files can be added to OpenOCD by using
633 the @option{-s <search>} switch. The current directory and the OpenOCD
634 target library is in the search path by default.
636 For details on the @option{-p} option. @xref{Connecting to GDB}.
638 Note! OpenOCD will launch the GDB & telnet server even if it can not
639 establish a connection with the target. In general, it is possible for
640 the JTAG controller to be unresponsive until the target is set up
641 correctly via e.g. GDB monitor commands in a GDB init script.
643 @node Simple Configuration Files
644 @chapter Simple Configuration Files
645 @cindex configuration
648 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
651 @item A small openocd.cfg file which ``sources'' other configuration files
652 @item A monolithic openocd.cfg file
653 @item Many -f filename options on the command line
654 @item Your Mixed Solution
657 @section Small configuration file method
659 This is the preferred method. It is simple and works well for many
660 people. The developers of OpenOCD would encourage you to use this
661 method. If you create a new configuration please email new
662 configurations to the development list.
664 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
667 source [find interface/signalyzer.cfg]
669 # Change the default telnet port...
673 # GDB can also flash my flash!
674 gdb_memory_map enable
675 gdb_flash_program enable
677 source [find target/sam7x256.cfg]
680 There are many example configuration scripts you can work with. You
681 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
685 @item @b{board} - eval board level configurations
686 @item @b{interface} - specific dongle configurations
687 @item @b{target} - the target chips
688 @item @b{tcl} - helper scripts
689 @item @b{xscale} - things specific to the xscale.
692 Look first in the ``boards'' area, then the ``targets'' area. Often a board
693 configuration is a good example to work from.
695 @section Many -f filename options
696 Some believe this is a wonderful solution, others find it painful.
698 You can use a series of ``-f filename'' options on the command line,
699 OpenOCD will read each filename in sequence, for example:
702 openocd -f file1.cfg -f file2.cfg -f file2.cfg
705 You can also intermix various commands with the ``-c'' command line
708 @section Monolithic file
709 The ``Monolithic File'' dispenses with all ``source'' statements and
710 puts everything in one self contained (monolithic) file. This is not
713 Please try to ``source'' various files or use the multiple -f
716 @section Advice for you
717 Often, one uses a ``mixed approach''. Where possible, please try to
718 ``source'' common things, and if needed cut/paste parts of the
719 standard distribution configuration files as needed.
721 @b{REMEMBER:} The ``important parts'' of your configuration file are:
724 @item @b{Interface} - Defines the dongle
725 @item @b{Taps} - Defines the JTAG Taps
726 @item @b{GDB Targets} - What GDB talks to
727 @item @b{Flash Programing} - Very Helpful
730 Some key things you should look at and understand are:
733 @item The reset configuration of your debug environment as a whole
734 @item Is there a ``work area'' that OpenOCD can use?
735 @* For ARM - work areas mean up to 10x faster downloads.
736 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
737 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
742 @node Config File Guidelines
743 @chapter Config File Guidelines
745 This section/chapter is aimed at developers and integrators of
746 OpenOCD. These are guidelines for creating new boards and new target
747 configurations as of 28/Nov/2008.
749 However, you, the user of OpenOCD, should be somewhat familiar with
750 this section as it should help explain some of the internals of what
751 you might be looking at.
753 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
757 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
759 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
760 contain initialization items that are specific to a board - for
761 example: The SDRAM initialization sequence for the board, or the type
762 of external flash and what address it is found at. Any initialization
763 sequence to enable that external flash or SDRAM should be found in the
764 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
765 a CPU and an FPGA or CPLD.
767 @* Think chip. The ``target'' directory represents a JTAG tap (or
768 chip) OpenOCD should control, not a board. Two common types of targets
769 are ARM chips and FPGA or CPLD chips.
772 @b{If needed...} The user in their ``openocd.cfg'' file or the board
773 file might override a specific feature in any of the above files by
774 setting a variable or two before sourcing the target file. Or adding
775 various commands specific to their situation.
777 @section Interface Config Files
779 The user should be able to source one of these files via a command like this:
782 source [find interface/FOOBAR.cfg]
784 openocd -f interface/FOOBAR.cfg
787 A preconfigured interface file should exist for every interface in use
788 today, that said, perhaps some interfaces have only been used by the
789 sole developer who created it.
791 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
792 tcl_platform(platform), it should be called jim_platform (because it
793 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
794 ``cygwin'' or ``mingw''
796 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
798 @section Board Config Files
800 @b{Note: BOARD directory NEW as of 28/nov/2008}
802 The user should be able to source one of these files via a command like this:
805 source [find board/FOOBAR.cfg]
807 openocd -f board/FOOBAR.cfg
811 The board file should contain one or more @t{source [find
812 target/FOO.cfg]} statements along with any board specific things.
814 In summary the board files should contain (if present)
817 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
818 @item SDRAM configuration (size, speed, etc.
819 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
820 @item Multiple TARGET source statements
821 @item All things that are not ``inside a chip''
822 @item Things inside a chip go in a 'target' file
825 @section Target Config Files
827 The user should be able to source one of these files via a command like this:
830 source [find target/FOOBAR.cfg]
832 openocd -f target/FOOBAR.cfg
835 In summary the target files should contain
840 @item Reset configuration
842 @item CPU/Chip/CPU-Core specific features
846 @subsection Important variable names
848 By default, the end user should never need to set these
849 variables. However, if the user needs to override a setting they only
850 need to set the variable in a simple way.
854 @* This gives a name to the overall chip, and is used as part of the
855 tap identifier dotted name.
857 @* By default little - unless the chip or board is not normally used that way.
859 @* When OpenOCD examines the JTAG chain, it will attempt to identify
860 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
861 to verify the tap id number verses configuration file and may issue an
862 error or warning like this. The hope is that this will help to pinpoint
863 problems in OpenOCD configurations.
866 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
867 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
868 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
869 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
872 @item @b{_TARGETNAME}
873 @* By convention, this variable is created by the target configuration
874 script. The board configuration file may make use of this variable to
875 configure things like a ``reset init'' script, or other things
876 specific to that board and that target.
878 If the chip has 2 targets, use the names @b{_TARGETNAME0},
879 @b{_TARGETNAME1}, ... etc.
881 @b{Remember:} The ``board file'' may include multiple targets.
883 At no time should the name ``target0'' (the default target name if
884 none was specified) be used. The name ``target0'' is a hard coded name
885 - the next target on the board will be some other number.
886 In the same way, avoid using target numbers even when they are
887 permitted; use the right target name(s) for your board.
889 The user (or board file) should reasonably be able to:
892 source [find target/FOO.cfg]
893 $_TARGETNAME configure ... FOO specific parameters
895 source [find target/BAR.cfg]
896 $_TARGETNAME configure ... BAR specific parameters
901 @subsection Tcl Variables Guide Line
902 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
904 Thus the rule we follow in OpenOCD is this: Variables that begin with
905 a leading underscore are temporary in nature, and can be modified and
906 used at will within a ?TARGET? configuration file.
908 @b{EXAMPLE:} The user should be able to do this:
912 # PXA270 #1 network side, big endian
913 # PXA270 #2 video side, little endian
917 source [find target/pxa270.cfg]
918 # variable: _TARGETNAME = network.cpu
919 # other commands can refer to the "network.cpu" tap.
920 $_TARGETNAME configure .... params for this CPU..
924 source [find target/pxa270.cfg]
925 # variable: _TARGETNAME = video.cpu
926 # other commands can refer to the "video.cpu" tap.
927 $_TARGETNAME configure .... params for this CPU..
931 source [find target/spartan3.cfg]
933 # Since $_TARGETNAME is temporal..
934 # these names still work!
935 network.cpu configure ... params
936 video.cpu configure ... params
940 @subsection Default Value Boiler Plate Code
942 All target configuration files should start with this (or a modified form)
946 if @{ [info exists CHIPNAME] @} @{
947 set _CHIPNAME $CHIPNAME
949 set _CHIPNAME sam7x256
952 if @{ [info exists ENDIAN] @} @{
958 if @{ [info exists CPUTAPID ] @} @{
959 set _CPUTAPID $CPUTAPID
961 set _CPUTAPID 0x3f0f0f0f
966 @subsection Creating Taps
967 After the ``defaults'' are choosen [see above] the taps are created.
969 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
973 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
974 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
979 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
982 @item @b{Unform tap names} - See: Tap Naming Convention
983 @item @b{_TARGETNAME} is created at the end where used.
987 if @{ [info exists FLASHTAPID ] @} @{
988 set _FLASHTAPID $FLASHTAPID
990 set _FLASHTAPID 0x25966041
992 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
994 if @{ [info exists CPUTAPID ] @} @{
995 set _CPUTAPID $CPUTAPID
997 set _CPUTAPID 0x25966041
999 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1002 if @{ [info exists BSTAPID ] @} @{
1003 set _BSTAPID $BSTAPID
1005 set _BSTAPID 0x1457f041
1007 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1009 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1012 @b{Tap Naming Convention}
1014 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1023 @item @b{unknownN} - it happens :-(
1026 @subsection Reset Configuration
1028 Some chips have specific ways the TRST and SRST signals are
1029 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1030 @b{BOARD SPECIFIC} they go in the board file.
1032 @subsection Work Areas
1034 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1035 and to download small snippets of code to program flash chips.
1037 If the chip includes a form of ``on-chip-ram'' - and many do - define
1038 a reasonable work area and use the ``backup'' option.
1040 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1041 inaccessible if/when the application code enables or disables the MMU.
1043 @subsection ARM Core Specific Hacks
1045 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1046 special high speed download features - enable it.
1048 If the chip has an ARM ``vector catch'' feature - by default enable
1049 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1050 user is really writing a handler for those situations - they can
1051 easily disable it. Experiance has shown the ``vector catch'' is
1052 helpful - for common programing errors.
1054 If present, the MMU, the MPU and the CACHE should be disabled.
1056 Some ARM cores are equipped with trace support, which permits
1057 examination of the instruction and data bus activity. Trace
1058 activity is controlled through an ``Embedded Trace Module'' (ETM)
1059 on one of the core's scan chains. The ETM emits voluminous data
1060 through a ``trace port''. The trace port is accessed in one
1061 of two ways. When its signals are pinned out from the chip,
1062 boards may provide a special high speed debugging connector;
1063 software support for this is not configured by default, use
1064 the ``--enable-oocd_trace'' option. Alternatively, trace data
1065 may be stored an on-chip SRAM which is packaged as an ``Embedded
1066 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1067 its associated ARM core. OpenOCD supports the ETM, and your
1068 target configuration should set it up with the relevant trace
1069 port: ``etb'' for chips which use that, else the board-specific
1070 option will be either ``oocd_trace'' or ``dummy''.
1073 etm config $_TARGETNAME 16 normal full etb
1074 etb config $_TARGETNAME $_CHIPNAME.etb
1077 @subsection Internal Flash Configuration
1079 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1081 @b{Never ever} in the ``target configuration file'' define any type of
1082 flash that is external to the chip. (For example a BOOT flash on
1083 Chip Select 0.) Such flash information goes in a board file - not
1084 the TARGET (chip) file.
1088 @item at91sam7x256 - has 256K flash YES enable it.
1089 @item str912 - has flash internal YES enable it.
1090 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1091 @item pxa270 - again - CS0 flash - it goes in the board file.
1095 @chapter About JIM-Tcl
1099 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1100 learn more about JIM here: @url{http://jim.berlios.de}
1103 @item @b{JIM vs. Tcl}
1104 @* JIM-TCL is a stripped down version of the well known Tcl language,
1105 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1106 fewer features. JIM-Tcl is a single .C file and a single .H file and
1107 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1108 4.2 MB .zip file containing 1540 files.
1110 @item @b{Missing Features}
1111 @* Our practice has been: Add/clone the real Tcl feature if/when
1112 needed. We welcome JIM Tcl improvements, not bloat.
1115 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1116 command interpreter today (28/nov/2008) is a mixture of (newer)
1117 JIM-Tcl commands, and (older) the orginal command interpreter.
1120 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1121 can type a Tcl for() loop, set variables, etc.
1123 @item @b{Historical Note}
1124 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1126 @item @b{Need a crash course in Tcl?}
1127 @* See: @xref{Tcl Crash Course}.
1131 @node Daemon Configuration
1132 @chapter Daemon Configuration
1133 The commands here are commonly found in the openocd.cfg file and are
1134 used to specify what TCP/IP ports are used, and how GDB should be
1138 This command terminates the configuration stage and
1139 enters the normal command mode. This can be useful to add commands to
1140 the startup scripts and commands such as resetting the target,
1141 programming flash, etc. To reset the CPU upon startup, add "init" and
1142 "reset" at the end of the config script or at the end of the OpenOCD
1143 command line using the @option{-c} command line switch.
1145 If this command does not appear in any startup/configuration file
1146 OpenOCD executes the command for you after processing all
1147 configuration files and/or command line options.
1149 @b{NOTE:} This command normally occurs at or near the end of your
1150 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1151 targets ready. For example: If your openocd.cfg file needs to
1152 read/write memory on your target - the init command must occur before
1153 the memory read/write commands. This includes @command{nand probe}.
1155 @section TCP/IP Ports
1157 @item @b{telnet_port} <@var{number}>
1159 @*Intended for a human. Port on which to listen for incoming telnet connections.
1161 @item @b{tcl_port} <@var{number}>
1163 @*Intended as a machine interface. Port on which to listen for
1164 incoming Tcl syntax. This port is intended as a simplified RPC
1165 connection that can be used by clients to issue commands and get the
1166 output from the Tcl engine.
1168 @item @b{gdb_port} <@var{number}>
1170 @*First port on which to listen for incoming GDB connections. The GDB port for the
1171 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1176 @item @b{gdb_breakpoint_override} <@var{hard|soft|disable}>
1177 @cindex gdb_breakpoint_override
1178 @anchor{gdb_breakpoint_override}
1179 @*Force breakpoint type for gdb 'break' commands.
1180 The raison d'etre for this option is to support GDB GUI's without
1181 a hard/soft breakpoint concept where the default OpenOCD and
1182 GDB behaviour is not sufficient. Note that GDB will use hardware
1183 breakpoints if the memory map has been set up for flash regions.
1185 This option replaces older arm7_9 target commands that addressed
1188 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
1190 @*Configures what OpenOCD will do when GDB detaches from the daemon.
1191 Default behaviour is <@var{resume}>
1193 @item @b{gdb_memory_map} <@var{enable|disable}>
1194 @cindex gdb_memory_map
1195 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to GDB when
1196 requested. GDB will then know when to set hardware breakpoints, and program flash
1197 using the GDB load command. @option{gdb_flash_program enable} must also be enabled
1198 for flash programming to work.
1199 Default behaviour is <@var{enable}>
1200 @xref{gdb_flash_program}.
1202 @item @b{gdb_flash_program} <@var{enable|disable}>
1203 @cindex gdb_flash_program
1204 @anchor{gdb_flash_program}
1205 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
1206 vFlash packet is received.
1207 Default behaviour is <@var{enable}>
1208 @comment END GDB Items
1211 @node Interface - Dongle Configuration
1212 @chapter Interface - Dongle Configuration
1213 Interface commands are normally found in an interface configuration
1214 file which is sourced by your openocd.cfg file. These commands tell
1215 OpenOCD what type of JTAG dongle you have and how to talk to it.
1216 @section Simple Complete Interface Examples
1217 @b{A Turtelizer FT2232 Based JTAG Dongle}
1221 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1222 ft2232_layout turtelizer2
1223 ft2232_vid_pid 0x0403 0xbdc8
1230 @b{A Raisonance RLink}
1239 parport_cable wiggler
1244 interface arm-jtag-ew
1246 @section Interface Command
1248 The interface command tells OpenOCD what type of JTAG dongle you are
1249 using. Depending on the type of dongle, you may need to have one or
1250 more additional commands.
1254 @item @b{interface} <@var{name}>
1256 @*Use the interface driver <@var{name}> to connect to the
1257 target. Currently supported interfaces are
1262 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1264 @item @b{amt_jtagaccel}
1265 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1269 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1270 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1271 platform. The libftdi uses libusb, and should be portable to all systems that provide
1275 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1278 @* ASIX PRESTO USB JTAG programmer.
1281 @* usbprog is a freely programmable USB adapter.
1284 @* Gateworks GW16012 JTAG programmer.
1287 @* Segger jlink USB adapter
1290 @* Raisonance RLink USB adapter
1293 @* vsllink is part of Versaloon which is a versatile USB programmer.
1295 @item @b{arm-jtag-ew}
1296 @* Olimex ARM-JTAG-EW USB adapter
1297 @comment - End parameters
1299 @comment - End Interface
1301 @subsection parport options
1304 @item @b{parport_port} <@var{number}>
1305 @cindex parport_port
1306 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1307 the @file{/dev/parport} device
1309 When using PPDEV to access the parallel port, use the number of the parallel port:
1310 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1311 you may encounter a problem.
1312 @item @b{parport_cable} <@var{name}>
1313 @cindex parport_cable
1314 @*The layout of the parallel port cable used to connect to the target.
1315 Currently supported cables are
1319 The original Wiggler layout, also supported by several clones, such
1320 as the Olimex ARM-JTAG
1323 Same as original wiggler except an led is fitted on D5.
1324 @item @b{wiggler_ntrst_inverted}
1325 @cindex wiggler_ntrst_inverted
1326 Same as original wiggler except TRST is inverted.
1327 @item @b{old_amt_wiggler}
1328 @cindex old_amt_wiggler
1329 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1330 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1333 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1334 program the Chameleon itself, not a connected target.
1337 The Xilinx Parallel cable III.
1340 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1341 This is also the layout used by the HollyGates design
1342 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1345 The ST Parallel cable.
1348 Same as original wiggler except SRST and TRST connections reversed and
1349 TRST is also inverted.
1352 Altium Universal JTAG cable.
1354 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1355 @cindex parport_write_on_exit
1356 @*This will configure the parallel driver to write a known value to the parallel
1357 interface on exiting OpenOCD
1360 @subsection amt_jtagaccel options
1362 @item @b{parport_port} <@var{number}>
1363 @cindex parport_port
1364 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1365 @file{/dev/parport} device
1367 @subsection ft2232 options
1370 @item @b{ft2232_device_desc} <@var{description}>
1371 @cindex ft2232_device_desc
1372 @*The USB device description of the FTDI FT2232 device. If not
1373 specified, the FTDI default value is used. This setting is only valid
1374 if compiled with FTD2XX support.
1376 @b{TODO:} Confirm the following: On Windows the name needs to end with
1377 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1378 this be added and when must it not be added? Why can't the code in the
1379 interface or in OpenOCD automatically add this if needed? -- Duane.
1381 @item @b{ft2232_serial} <@var{serial-number}>
1382 @cindex ft2232_serial
1383 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1385 @item @b{ft2232_layout} <@var{name}>
1386 @cindex ft2232_layout
1387 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1388 signals. Valid layouts are
1391 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1393 Amontec JTAGkey and JTAGkey-Tiny
1394 @item @b{signalyzer}
1396 @item @b{olimex-jtag}
1399 American Microsystems M5960
1400 @item @b{evb_lm3s811}
1401 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1402 SRST signals on external connector
1405 @item @b{stm32stick}
1406 Hitex STM32 Performance Stick
1407 @item @b{flyswatter}
1408 Tin Can Tools Flyswatter
1409 @item @b{turtelizer2}
1410 egnite Software turtelizer2
1413 @item @b{axm0432_jtag}
1417 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1418 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1419 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1421 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1423 @item @b{ft2232_latency} <@var{ms}>
1424 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1425 ft2232_read() fails to return the expected number of bytes. This can be caused by
1426 USB communication delays and has proved hard to reproduce and debug. Setting the
1427 FT2232 latency timer to a larger value increases delays for short USB packets but it
1428 also reduces the risk of timeouts before receiving the expected number of bytes.
1429 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1432 @subsection ep93xx options
1433 @cindex ep93xx options
1434 Currently, there are no options available for the ep93xx interface.
1438 @item @b{jtag_khz} <@var{reset speed kHz}>
1441 It is debatable if this command belongs here - or in a board
1442 configuration file. In fact, in some situations the JTAG speed is
1443 changed during the target initialisation process (i.e.: (1) slow at
1444 reset, (2) program the CPU clocks, (3) run fast)
1446 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1448 Not all interfaces support ``rtck''. If the interface device can not
1449 support the rate asked for, or can not translate from kHz to
1450 jtag_speed, then an error is returned.
1452 Make sure the JTAG clock is no more than @math{1/6th CPU-Clock}. This is
1453 especially true for synthesized cores (-S). Also see RTCK.
1455 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1456 please use the command: 'jtag_rclk FREQ'. This Tcl proc (in
1457 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1458 the specified frequency.
1461 # Fall back to 3mhz if RCLK is not supported
1465 @item @b{DEPRECATED} @b{jtag_speed} - please use jtag_khz above.
1467 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1468 speed. The actual effect of this option depends on the JTAG interface used.
1470 The speed used during reset can be adjusted using setting jtag_speed during
1471 pre_reset and post_reset events.
1474 @item wiggler: maximum speed / @var{number}
1475 @item ft2232: 6MHz / (@var{number}+1)
1476 @item amt jtagaccel: 8 / 2**@var{number}
1477 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1478 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
1479 @comment end speed list.
1482 @comment END command list
1485 @node Reset Configuration
1486 @chapter Reset Configuration
1487 @cindex Reset Configuration
1489 Every system configuration may require a different reset
1490 configuration. This can also be quite confusing. Please see the
1491 various board files for example.
1493 @section jtag_nsrst_delay <@var{ms}>
1494 @cindex jtag_nsrst_delay
1495 @*How long (in milliseconds) OpenOCD should wait after deasserting
1496 nSRST before starting new JTAG operations.
1498 @section jtag_ntrst_delay <@var{ms}>
1499 @cindex jtag_ntrst_delay
1500 @*Same @b{jtag_nsrst_delay}, but for nTRST
1502 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1503 big resistor/capacitor, reset supervisor, or on-chip features). This
1504 keeps the signal asserted for some time after the external reset got
1507 @section reset_config
1509 @b{Note:} To maintainers and integrators: Where exactly the
1510 ``reset configuration'' goes is a good question. It touches several
1511 things at once. In the end, if you have a board file - the board file
1512 should define it and assume 100% that the DONGLE supports
1513 anything. However, that does not mean the target should not also make
1514 not of something the silicon vendor has done inside the
1515 chip. @i{Grr.... nothing is every pretty.}
1519 @item Every JTAG Dongle is slightly different, some dongles implement reset differently.
1520 @item Every board is also slightly different; some boards tie TRST and SRST together.
1521 @item Every chip is slightly different; some chips internally tie the two signals together.
1522 @item Some may not implement all of the signals the same way.
1523 @item Some signals might be push-pull, others open-drain/collector.
1525 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1526 reset the TAP via TRST and send commands through the JTAG tap to halt
1527 the CPU at the reset vector before the 1st instruction is executed,
1528 and finally release the SRST signal.
1529 @*Depending on your board vendor, chip vendor, etc., these
1530 signals may have slightly different names.
1532 OpenOCD defines these signals in these terms:
1534 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1535 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1541 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1542 @cindex reset_config
1543 @* The @t{reset_config} command tells OpenOCD the reset configuration
1544 of your combination of Dongle, Board, and Chips.
1545 If the JTAG interface provides SRST, but the target doesn't connect
1546 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1547 be @option{none}, @option{trst_only}, @option{srst_only} or
1548 @option{trst_and_srst}.
1550 [@var{combination}] is an optional value specifying broken reset
1551 signal implementations. @option{srst_pulls_trst} states that the
1552 test logic is reset together with the reset of the system (e.g. Philips
1553 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1554 the system is reset together with the test logic (only hypothetical, I
1555 haven't seen hardware with such a bug, and can be worked around).
1556 @option{combined} implies both @option{srst_pulls_trst} and
1557 @option{trst_pulls_srst}. The default behaviour if no option given is
1560 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1561 driver type of the reset lines to be specified. Possible values are
1562 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1563 test reset signal, and @option{srst_open_drain} (default) and
1564 @option{srst_push_pull} for the system reset. These values only affect
1565 JTAG interfaces with support for different drivers, like the Amontec
1566 JTAGkey and JTAGAccelerator.
1568 @comment - end command
1574 @chapter Tap Creation
1575 @cindex tap creation
1576 @cindex tap configuration
1578 In order for OpenOCD to control a target, a JTAG tap must be
1581 Commands to create taps are normally found in a configuration file and
1582 are not normally typed by a human.
1584 When a tap is created a @b{dotted.name} is created for the tap. Other
1585 commands use that dotted.name to manipulate or refer to the tap.
1589 @item @b{Debug Target} A tap can be used by a GDB debug target
1590 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1591 instead of indirectly by making a CPU do it.
1592 @item @b{Boundry Scan} Some chips support boundary scan.
1596 @section jtag newtap
1597 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1602 @cindex tap geometry
1604 @comment START options
1607 @* is a symbolic name of the chip.
1609 @* is a symbol name of a tap present on the chip.
1610 @item @b{Required configparams}
1611 @* Every tap has 3 required configparams, and several ``optional
1612 parameters'', the required parameters are:
1613 @comment START REQUIRED
1615 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1616 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1617 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1618 some devices, there are bits in the IR that aren't used. This lets you mask
1619 them off when doing comparisons. In general, this should just be all ones for
1621 @comment END REQUIRED
1623 An example of a FOOBAR Tap
1625 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1627 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1628 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1629 [6,4,2,0] are checked.
1631 @item @b{Optional configparams}
1632 @comment START Optional
1634 @item @b{-expected-id NUMBER}
1635 @* By default it is zero. If non-zero represents the
1636 expected tap ID used when the JTAG chain is examined. Repeat
1637 the option as many times as required if multiple id's can be
1638 expected. See below.
1641 @* By default not specified the tap is enabled. Some chips have a
1642 JTAG route controller (JRC) that is used to enable and/or disable
1643 specific JTAG taps. You can later enable or disable any JTAG tap via
1644 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1646 @comment END Optional
1649 @comment END OPTIONS
1652 @comment START NOTES
1654 @item @b{Technically}
1655 @* newtap is a sub command of the ``jtag'' command
1656 @item @b{Big Picture Background}
1657 @*GDB Talks to OpenOCD using the GDB protocol via
1658 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1659 control the JTAG chain on your board. Your board has one or more chips
1660 in a @i{daisy chain configuration}. Each chip may have one or more
1661 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1662 @item @b{NAME Rules}
1663 @*Names follow ``C'' symbol name rules (start with alpha ...)
1664 @item @b{TAPNAME - Conventions}
1666 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1667 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1668 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1669 @item @b{bs} - for boundary scan if this is a seperate tap.
1670 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1671 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1672 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1673 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1674 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1676 @item @b{DOTTED.NAME}
1677 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1678 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1679 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1680 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1681 numerous other places to refer to various taps.
1683 @* The order this command appears via the config files is
1685 @item @b{Multi Tap Example}
1686 @* This example is based on the ST Microsystems STR912. See the ST
1687 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1688 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1690 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1691 @*@b{checked: 28/nov/2008}
1693 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1694 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1695 tap which then connects to the TDI pin.
1699 # create tap: 'str912.flash'
1700 jtag newtap str912 flash ... params ...
1701 # create tap: 'str912.cpu'
1702 jtag newtap str912 cpu ... params ...
1703 # create tap: 'str912.bs'
1704 jtag newtap str912 bs ... params ...
1707 @item @b{Note: Deprecated} - Index Numbers
1708 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1709 feature is still present, however its use is highly discouraged and
1710 should not be counted upon. Update all of your scripts to use
1711 TAP names rather than numbers.
1712 @item @b{Multiple chips}
1713 @* If your board has multiple chips, you should be
1714 able to @b{source} two configuration files, in the proper order, and
1715 have the taps created in the proper order.
1718 @comment at command level
1719 @comment DOCUMENT old command
1720 @section jtag_device - REMOVED
1722 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1726 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1727 by the ``jtag newtap'' command. The documentation remains here so that
1728 one can easily convert the old syntax to the new syntax. About the old
1729 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1730 ``irmask''. The new syntax requires named prefixes, and supports
1731 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1732 @b{jtag newtap} command for details.
1734 OLD: jtag_device 8 0x01 0xe3 0xfe
1735 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1738 @section Enable/Disable Taps
1739 @b{Note:} These commands are intended to be used as a machine/script
1740 interface. Humans might find the ``scan_chain'' command more helpful
1741 when querying the state of the JTAG taps.
1743 @b{By default, all taps are enabled}
1746 @item @b{jtag tapenable} @var{DOTTED.NAME}
1747 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1748 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1753 @cindex route controller
1755 These commands are used when your target has a JTAG route controller
1756 that effectively adds or removes a tap from the JTAG chain in a
1759 The ``standard way'' to remove a tap would be to place the tap in
1760 bypass mode. But with the advent of modern chips, this is not always a
1761 good solution. Some taps operate slowly, others operate fast, and
1762 there are other JTAG clock synchronisation problems one must face. To
1763 solve that problem, the JTAG route controller was introduced. Rather
1764 than ``bypass'' the tap, the tap is completely removed from the
1765 circuit and skipped.
1768 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1771 @item @b{Enabled - Not In ByPass} and has a variable bit length
1772 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1773 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1776 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1777 @b{Historical note:} this feature was added 28/nov/2008
1779 @b{jtag tapisenabled DOTTED.NAME}
1781 This command returns 1 if the named tap is currently enabled, 0 if not.
1782 This command exists so that scripts that manipulate a JRC (like the
1783 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1784 enabled or disabled.
1787 @node Target Configuration
1788 @chapter Target Configuration
1790 This chapter discusses how to create a GDB debug target. Before
1791 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1793 @section targets [NAME]
1794 @b{Note:} This command name is PLURAL - not singular.
1796 With NO parameter, this plural @b{targets} command lists all known
1797 targets in a human friendly form.
1799 With a parameter, this plural @b{targets} command sets the current
1800 target to the given name. (i.e.: If there are multiple debug targets)
1805 CmdName Type Endian ChainPos State
1806 -- ---------- ---------- ---------- -------- ----------
1807 0: target0 arm7tdmi little 0 halted
1810 @section target COMMANDS
1811 @b{Note:} This command name is SINGULAR - not plural. It is used to
1812 manipulate specific targets, to create targets and other things.
1814 Once a target is created, a TARGETNAME (object) command is created;
1815 see below for details.
1817 The TARGET command accepts these sub-commands:
1819 @item @b{create} .. parameters ..
1820 @* creates a new target, see below for details.
1822 @* Lists all supported target types (perhaps some are not yet in this document).
1824 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1826 foreach t [target names] {
1827 puts [format "Target: %s\n" $t]
1831 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1832 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1833 @item @b{number} @b{NUMBER}
1834 @* Internally OpenOCD maintains a list of targets - in numerical index
1835 (0..N-1) this command returns the name of the target at index N.
1838 set thename [target number $x]
1839 puts [format "Target %d is: %s\n" $x $thename]
1842 @* Returns the number of targets known to OpenOCD (see number above)
1845 set c [target count]
1846 for { set x 0 } { $x < $c } { incr x } {
1847 # Assuming you have created this function
1848 print_target_details $x
1854 @section TARGETNAME (object) commands
1855 @b{Use:} Once a target is created, an ``object name'' that represents the
1856 target is created. By convention, the target name is identical to the
1857 tap name. In a multiple target system, one can preceed many common
1858 commands with a specific target name and effect only that target.
1860 str912.cpu mww 0x1234 0x42
1861 omap3530.cpu mww 0x5555 123
1864 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1865 good example is a on screen button, once a button is created a button
1866 has a name (a path in Tk terms) and that name is useable as a 1st
1867 class command. For example in Tk, one can create a button and later
1868 configure it like this:
1872 button .foobar -background red -command @{ foo @}
1874 .foobar configure -foreground blue
1876 set x [.foobar cget -background]
1878 puts [format "The button is %s" $x]
1881 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1882 button. Commands available as a ``target object'' are:
1884 @comment START targetobj commands.
1886 @item @b{configure} - configure the target; see Target Config/Cget Options below
1887 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1888 @item @b{curstate} - current target state (running, halt, etc.
1890 @* Intended for a human to see/read the currently configure target events.
1891 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1892 @comment start memory
1902 @item @b{Memory To Array, Array To Memory}
1903 @* These are aimed at a machine interface to memory
1905 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1906 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1908 @* @b{ARRAYNAME} is the name of an array variable
1909 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1910 @* @b{ADDRESS} is the target memory address
1911 @* @b{COUNT} is the number of elements to process
1913 @item @b{Used during ``reset''}
1914 @* These commands are used internally by the OpenOCD scripts to deal
1915 with odd reset situations and are not documented here.
1917 @item @b{arp_examine}
1921 @item @b{arp_waitstate}
1923 @item @b{invoke-event} @b{EVENT-NAME}
1924 @* Invokes the specific event manually for the target
1927 @section Target Events
1928 At various times, certain things can happen, or you want them to happen.
1932 @item What should happen when GDB connects? Should your target reset?
1933 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1934 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
1937 All of the above items are handled by target events.
1939 To specify an event action, either during target creation, or later
1940 via ``$_TARGETNAME configure'' see this example.
1942 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
1943 target event name, and BODY is a Tcl procedure or string of commands
1946 The programmers model is the ``-command'' option used in Tcl/Tk
1947 buttons and events. Below are two identical examples, the first
1948 creates and invokes small procedure. The second inlines the procedure.
1951 proc my_attach_proc @{ @} @{
1955 mychip.cpu configure -event gdb-attach my_attach_proc
1956 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
1959 @section Current Events
1960 The following events are available:
1962 @item @b{debug-halted}
1963 @* The target has halted for debug reasons (i.e.: breakpoint)
1964 @item @b{debug-resumed}
1965 @* The target has resumed (i.e.: gdb said run)
1966 @item @b{early-halted}
1967 @* Occurs early in the halt process
1968 @item @b{examine-end}
1969 @* Currently not used (goal: when JTAG examine completes)
1970 @item @b{examine-start}
1971 @* Currently not used (goal: when JTAG examine starts)
1972 @item @b{gdb-attach}
1973 @* When GDB connects
1974 @item @b{gdb-detach}
1975 @* When GDB disconnects
1977 @* When the taret has halted and GDB is not doing anything (see early halt)
1978 @item @b{gdb-flash-erase-start}
1979 @* Before the GDB flash process tries to erase the flash
1980 @item @b{gdb-flash-erase-end}
1981 @* After the GDB flash process has finished erasing the flash
1982 @item @b{gdb-flash-write-start}
1983 @* Before GDB writes to the flash
1984 @item @b{gdb-flash-write-end}
1985 @* After GDB writes to the flash
1987 @* Before the taret steps, gdb is trying to start/resume the target
1989 @* The target has halted
1990 @item @b{old-gdb_program_config}
1991 @* DO NOT USE THIS: Used internally
1992 @item @b{old-pre_resume}
1993 @* DO NOT USE THIS: Used internally
1994 @item @b{reset-assert-pre}
1995 @* Before reset is asserted on the tap.
1996 @item @b{reset-assert-post}
1997 @* Reset is now asserted on the tap.
1998 @item @b{reset-deassert-pre}
1999 @* Reset is about to be released on the tap
2000 @item @b{reset-deassert-post}
2001 @* Reset has been released on the tap
2003 @* Currently not used.
2004 @item @b{reset-halt-post}
2005 @* Currently not usd
2006 @item @b{reset-halt-pre}
2007 @* Currently not used
2008 @item @b{reset-init}
2009 @* Used by @b{reset init} command for board-specific initialization.
2010 This is where you would configure PLLs and clocking, set up DRAM so
2011 you can download programs that don't fit in on-chip SRAM, set up pin
2012 multiplexing, and so on.
2013 @item @b{reset-start}
2014 @* Currently not used
2015 @item @b{reset-wait-pos}
2016 @* Currently not used
2017 @item @b{reset-wait-pre}
2018 @* Currently not used
2019 @item @b{resume-start}
2020 @* Before any target is resumed
2021 @item @b{resume-end}
2022 @* After all targets have resumed
2026 @* Target has resumed
2027 @item @b{tap-enable}
2028 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2030 jtag configure DOTTED.NAME -event tap-enable @{
2035 @item @b{tap-disable}
2036 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2038 jtag configure DOTTED.NAME -event tap-disable @{
2039 puts "Disabling CPU"
2045 @section target create
2047 @cindex target creation
2050 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2052 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2053 @comment START params
2056 @* Is the name of the debug target. By convention it should be the tap
2057 DOTTED.NAME. This name is also used to create the target object
2058 command, and in other places the target needs to be identified.
2060 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2061 @comment START types
2078 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2079 @comment START mandatory
2081 @item @b{-endian big|little}
2082 @item @b{-chain-position DOTTED.NAME}
2083 @comment end MANDATORY
2088 @section Target Config/Cget Options
2089 These options can be specified when the target is created, or later
2090 via the configure option or to query the target via cget.
2092 You should specify a working area if you can; typically it uses some
2093 on-chip SRAM. Such a working area can speed up many things, including bulk
2094 writes to target memory; flash operations like checking to see if memory needs
2095 to be erased; GDB memory checksumming; and may help perform otherwise
2096 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2098 @item @b{-type} - returns the target type
2099 @item @b{-event NAME BODY} see Target events
2100 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2101 which will be used when an MMU is active.
2102 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2103 which will be used when an MMU is inactive.
2104 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2105 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2106 by default, it doesn't. When possible, use a working_area that doesn't
2107 need to be backed up, since performing a backup slows down operations.
2108 @item @b{-endian [big|little]}
2109 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2110 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2114 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2115 set name [target number $x]
2116 set y [$name cget -endian]
2117 set z [$name cget -type]
2118 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2122 @section Target Variants
2125 @* Unknown (please write me)
2127 @* Unknown (please write me) (similar to arm7tdmi)
2129 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2130 This enables the hardware single-stepping support found on these
2135 @* None (this is also used as the ARM946)
2137 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2138 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2139 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2140 be detected and the normal reset behaviour used.
2142 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2144 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2146 @* Use variant @option{ejtag_srst} when debugging targets that do not
2147 provide a functional SRST line on the EJTAG connector. This causes
2148 OpenOCD to instead use an EJTAG software reset command to reset the
2149 processor. You still need to enable @option{srst} on the reset
2150 configuration command to enable OpenOCD hardware reset functionality.
2151 @comment END variants
2153 @section working_area - Command Removed
2154 @cindex working_area
2155 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2156 @* This documentation remains because there are existing scripts that
2157 still use this that need to be converted.
2159 working_area target# address size backup| [virtualaddress]
2161 @* The target# is a the 0 based target numerical index.
2163 @node Flash Configuration
2164 @chapter Flash programming
2165 @cindex Flash Configuration
2167 OpenOCD has different commands for NOR and NAND flash;
2168 the ``flash'' command works with NOR flash, while
2169 the ``nand'' command works with NAND flash.
2170 This partially reflects different hardware technologies:
2171 NOR flash usually supports direct CPU instruction and data bus access,
2172 while data from a NAND flash must be copied to memory before it can be
2173 used. (SPI flash must also be copied to memory before use.)
2174 However, the documentation also uses ``flash'' as a generic term;
2175 for example, ``Put flash configuration in board-specific files''.
2177 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2178 flash that a micro may boot from. Perhaps you, the reader, would like to
2179 contribute support for this.
2183 @item Configure via the command @b{flash bank}
2184 @* Normally this is done in a configuration file.
2185 @item Operate on the flash via @b{flash SOMECOMMAND}
2186 @* Often commands to manipulate the flash are typed by a human, or run
2187 via a script in some automated way. For example: To program the boot
2188 flash on your board.
2190 @* Flashing via GDB requires the flash be configured via ``flash
2191 bank'', and the GDB flash features be enabled. See the daemon
2192 configuration section for more details.
2195 @section Flash commands
2196 @cindex Flash commands
2197 @subsection flash banks
2200 @*List configured flash banks
2201 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2202 @subsection flash info
2203 @b{flash info} <@var{num}>
2205 @*Print info about flash bank <@option{num}>
2206 @subsection flash probe
2207 @b{flash probe} <@var{num}>
2209 @*Identify the flash, or validate the parameters of the configured flash. Operation
2210 depends on the flash type.
2211 @subsection flash erase_check
2212 @b{flash erase_check} <@var{num}>
2213 @cindex flash erase_check
2214 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2215 updates the erase state information displayed by @option{flash info}. That means you have
2216 to issue an @option{erase_check} command after erasing or programming the device to get
2217 updated information.
2218 @subsection flash protect_check
2219 @b{flash protect_check} <@var{num}>
2220 @cindex flash protect_check
2221 @*Check protection state of sectors in flash bank <num>.
2222 @option{flash erase_sector} using the same syntax.
2223 @subsection flash erase_sector
2224 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2225 @cindex flash erase_sector
2226 @anchor{flash erase_sector}
2227 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2228 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2229 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2231 @subsection flash erase_address
2232 @b{flash erase_address} <@var{address}> <@var{length}>
2233 @cindex flash erase_address
2234 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2235 @subsection flash write_bank
2236 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2237 @cindex flash write_bank
2238 @anchor{flash write_bank}
2239 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2240 <@option{offset}> bytes from the beginning of the bank.
2241 @subsection flash write_image
2242 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2243 @cindex flash write_image
2244 @anchor{flash write_image}
2245 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2246 [@var{offset}] can be specified and the file [@var{type}] can be specified
2247 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2248 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2249 if the @option{erase} parameter is given.
2250 @subsection flash protect
2251 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2252 @cindex flash protect
2253 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2254 <@var{last}> of @option{flash bank} <@var{num}>.
2256 @subsection mFlash commands
2257 @cindex mFlash commands
2259 @item @b{mflash probe}
2260 @cindex mflash probe
2262 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2263 @cindex mflash write
2264 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2265 <@var{offset}> bytes from the beginning of the bank.
2266 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2268 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2272 @section flash bank command
2273 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2276 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2277 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2280 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2281 and <@var{bus_width}> bytes using the selected flash <driver>.
2283 @subsection External Flash - cfi options
2285 CFI flashes are external flash chips - often they are connected to a
2286 specific chip select on the CPU. By default, at hard reset, most
2287 CPUs have the ablity to ``boot'' from some flash chip - typically
2288 attached to the CPU's CS0 pin.
2290 For other chip selects: OpenOCD does not know how to configure, or
2291 access a specific chip select. Instead you, the human, might need to
2292 configure additional chip selects via other commands (like: mww) , or
2293 perhaps configure a GPIO pin that controls the ``write protect'' pin
2296 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2297 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2298 @*CFI flashes require the name or number of the target they're connected to
2300 argument. The CFI driver makes use of a working area (specified for the target)
2301 to significantly speed up operation.
2303 @var{chip_width} and @var{bus_width} are specified in bytes.
2305 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2309 @subsection Internal Flash (Microcontrollers)
2310 @subsubsection lpc2000 options
2311 @cindex lpc2000 options
2313 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2314 <@var{clock}> [@var{calc_checksum}]
2315 @*LPC flashes don't require the chip and bus width to be specified. Additional
2316 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2317 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2318 the name or number of the target this flash belongs to (first is 0),
2319 the frequency at which the core
2320 is currently running (in kHz - must be an integral number), and the optional keyword
2321 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2325 @subsubsection at91sam7 options
2326 @cindex at91sam7 options
2328 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2329 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2330 reading the chip-id and type.
2332 @subsubsection str7 options
2333 @cindex str7 options
2335 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2336 @*variant can be either STR71x, STR73x or STR75x.
2338 @subsubsection str9 options
2339 @cindex str9 options
2341 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2342 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2344 str9x flash_config 0 4 2 0 0x80000
2346 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2348 @subsubsection str9 options (str9xpec driver)
2350 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2351 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2352 @option{enable_turbo} <@var{num>.}
2354 Only use this driver for locking/unlocking the device or configuring the option bytes.
2355 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2357 @subsubsection Stellaris (LM3Sxxx) options
2358 @cindex Stellaris (LM3Sxxx) options
2360 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2361 @*Stellaris flash plugin only require the @var{target}.
2363 @subsubsection stm32x options
2364 @cindex stm32x options
2366 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2367 @*stm32x flash plugin only require the @var{target}.
2369 @subsubsection aduc702x options
2370 @cindex aduc702x options
2372 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2373 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2375 @subsection mFlash Configuration
2376 @cindex mFlash Configuration
2377 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2378 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
2380 @*Configures a mflash for <@var{soc}> host bank at
2381 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2382 order. Pin number format is dependent on host GPIO calling convention.
2383 If WP or DPD pin was not used, write -1. Currently, mflash bank
2384 support s3c2440 and pxa270.
2386 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2388 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2390 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2392 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2395 @section Microcontroller specific Flash Commands
2397 @subsection AT91SAM7 specific commands
2398 @cindex AT91SAM7 specific commands
2399 The flash configuration is deduced from the chip identification register. The flash
2400 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2401 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2402 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2403 that can be erased separatly. Only an EraseAll command is supported by the controller
2404 for each flash plane and this is called with
2406 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2407 @*bulk erase flash planes first_plane to last_plane.
2408 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2409 @cindex at91sam7 gpnvm
2410 @*set or clear a gpnvm bit for the processor
2413 @subsection STR9 specific commands
2414 @cindex STR9 specific commands
2415 @anchor{STR9 specific commands}
2416 These are flash specific commands when using the str9xpec driver.
2418 @item @b{str9xpec enable_turbo} <@var{num}>
2419 @cindex str9xpec enable_turbo
2420 @*enable turbo mode, will simply remove the str9 from the chain and talk
2421 directly to the embedded flash controller.
2422 @item @b{str9xpec disable_turbo} <@var{num}>
2423 @cindex str9xpec disable_turbo
2424 @*restore the str9 into JTAG chain.
2425 @item @b{str9xpec lock} <@var{num}>
2426 @cindex str9xpec lock
2427 @*lock str9 device. The str9 will only respond to an unlock command that will
2429 @item @b{str9xpec unlock} <@var{num}>
2430 @cindex str9xpec unlock
2431 @*unlock str9 device.
2432 @item @b{str9xpec options_read} <@var{num}>
2433 @cindex str9xpec options_read
2434 @*read str9 option bytes.
2435 @item @b{str9xpec options_write} <@var{num}>
2436 @cindex str9xpec options_write
2437 @*write str9 option bytes.
2440 Note: Before using the str9xpec driver here is some background info to help
2441 you better understand how the drivers works. OpenOCD has two flash drivers for
2445 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2446 flash programming as it is faster than the @option{str9xpec} driver.
2448 Direct programming @option{str9xpec} using the flash controller. This is an
2449 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2450 core does not need to be running to program using this flash driver. Typical use
2451 for this driver is locking/unlocking the target and programming the option bytes.
2454 Before we run any commands using the @option{str9xpec} driver we must first disable
2455 the str9 core. This example assumes the @option{str9xpec} driver has been
2456 configured for flash bank 0.
2458 # assert srst, we do not want core running
2459 # while accessing str9xpec flash driver
2461 # turn off target polling
2464 str9xpec enable_turbo 0
2466 str9xpec options_read 0
2467 # re-enable str9 core
2468 str9xpec disable_turbo 0
2472 The above example will read the str9 option bytes.
2473 When performing a unlock remember that you will not be able to halt the str9 - it
2474 has been locked. Halting the core is not required for the @option{str9xpec} driver
2475 as mentioned above, just issue the commands above manually or from a telnet prompt.
2477 @subsection STR9 configuration
2478 @cindex STR9 configuration
2480 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2481 <@var{BBADR}> <@var{NBBADR}>
2482 @cindex str9x flash_config
2483 @*Configure str9 flash controller.
2485 e.g. str9x flash_config 0 4 2 0 0x80000
2487 BBSR - Boot Bank Size register
2488 NBBSR - Non Boot Bank Size register
2489 BBADR - Boot Bank Start Address register
2490 NBBADR - Boot Bank Start Address register
2494 @subsection STR9 option byte configuration
2495 @cindex STR9 option byte configuration
2497 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2498 @cindex str9xpec options_cmap
2499 @*configure str9 boot bank.
2500 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2501 @cindex str9xpec options_lvdthd
2502 @*configure str9 lvd threshold.
2503 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2504 @cindex str9xpec options_lvdsel
2505 @*configure str9 lvd source.
2506 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2507 @cindex str9xpec options_lvdwarn
2508 @*configure str9 lvd reset warning source.
2511 @subsection STM32x specific commands
2512 @cindex STM32x specific commands
2514 These are flash specific commands when using the stm32x driver.
2516 @item @b{stm32x lock} <@var{num}>
2518 @*lock stm32 device.
2519 @item @b{stm32x unlock} <@var{num}>
2520 @cindex stm32x unlock
2521 @*unlock stm32 device.
2522 @item @b{stm32x options_read} <@var{num}>
2523 @cindex stm32x options_read
2524 @*read stm32 option bytes.
2525 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2526 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2527 @cindex stm32x options_write
2528 @*write stm32 option bytes.
2529 @item @b{stm32x mass_erase} <@var{num}>
2530 @cindex stm32x mass_erase
2531 @*mass erase flash memory.
2534 @subsection Stellaris specific commands
2535 @cindex Stellaris specific commands
2537 These are flash specific commands when using the Stellaris driver.
2539 @item @b{stellaris mass_erase} <@var{num}>
2540 @cindex stellaris mass_erase
2541 @*mass erase flash memory.
2544 @node NAND Flash Commands
2545 @chapter NAND Flash Commands
2548 Compared to NOR or SPI flash, NAND devices are inexpensive
2549 and high density. Today's NAND chips, and multi-chip modules,
2550 commonly hold multiple GigaBytes of data.
2552 NAND chips consist of a number of ``erase blocks'' of a given
2553 size (such as 128 KBytes), each of which is divided into a
2554 number of pages (of perhaps 512 or 2048 bytes each). Each
2555 page of a NAND flash has an ``out of band'' (OOB) area to hold
2556 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2557 of OOB for every 512 bytes of page data.
2559 One key characteristic of NAND flash is that its error rate
2560 is higher than that of NOR flash. In normal operation, that
2561 ECC is used to correct and detect errors. However, NAND
2562 blocks can also wear out and become unusable; those blocks
2563 are then marked "bad". NAND chips are even shipped from the
2564 manufacturer with a few bad blocks. The highest density chips
2565 use a technology (MLC) that wears out more quickly, so ECC
2566 support is increasingly important as a way to detect blocks
2567 that have begun to fail, and help to preserve data integrity
2568 with techniques such as wear leveling.
2570 Software is used to manage the ECC. Some controllers don't
2571 support ECC directly; in those cases, software ECC is used.
2572 Other controllers speed up the ECC calculations with hardware.
2573 Single-bit error correction hardware is routine. Controllers
2574 geared for newer MLC chips may correct 4 or more errors for
2575 every 512 bytes of data.
2577 You will need to make sure that any data you write using
2578 OpenOCD includes the apppropriate kind of ECC. For example,
2579 that may mean passing the @code{oob_softecc} flag when
2580 writing NAND data, or ensuring that the correct hardware
2583 The basic steps for using NAND devices include:
2585 @item Declare via the command @command{nand device}
2586 @* Do this in a board-specific configuration file,
2587 passing parameters as needed by the controller.
2588 @item Configure each device using @command{nand probe}.
2589 @* Do this only after the associated target is set up,
2590 such as in its reset-init script or in procures defined
2591 to access that device.
2592 @item Operate on the flash via @command{nand subcommand}
2593 @* Often commands to manipulate the flash are typed by a human, or run
2594 via a script in some automated way. Common task include writing a
2595 boot loader, operating system, or other data needed to initialize or
2599 @section NAND Configuration Commands
2600 @cindex NAND configuration
2602 NAND chips must be declared in configuration scripts,
2603 plus some additional configuration that's done after
2604 OpenOCD has initialized.
2606 @deffn {Config Command} {nand device} controller target [configparams...]
2607 Declares a NAND device, which can be read and written to
2608 after it has been configured through @command{nand probe}.
2609 In OpenOCD, devices are single chips; this is unlike some
2610 operating systems, which may manage multiple chips as if
2611 they were a single (larger) device.
2612 In some cases, configuring a device will activate extra
2613 commands; see the controller-specific documentation.
2615 @b{NOTE:} This command is not available after OpenOCD
2616 initialization has completed. Use it in board specific
2617 configuration files, not interactively.
2620 @item @var{controller} ... identifies a the controller driver
2621 associated with the NAND device being declared.
2622 @xref{NAND Driver List}.
2623 @item @var{target} ... names the target used when issuing
2624 commands to the NAND controller.
2625 @comment Actually, it's currently a controller-specific parameter...
2626 @item @var{configparams} ... controllers may support, or require,
2627 additional parameters. See the controller-specific documentation
2628 for more information.
2632 @deffn Command {nand list}
2633 Prints a one-line summary of each device declared
2634 using @command{nand device}, numbered from zero.
2635 Note that un-probed devices show no details.
2638 @deffn Command {nand probe} num
2639 Probes the specified device to determine key characteristics
2640 like its page and block sizes, and how many blocks it has.
2641 The @var{num} parameter is the value shown by @command{nand list}.
2642 You must (successfully) probe a device before you can use
2643 it with most other NAND commands.
2646 @section Erasing, Reading, Writing to NAND Flash
2648 @deffn Command {nand dump} num filename offset length [oob_option]
2649 @cindex NAND reading
2650 Reads binary data from the NAND device and writes it to the file,
2651 starting at the specified offset.
2652 The @var{num} parameter is the value shown by @command{nand list}.
2654 Use a complete path name for @var{filename}, so you don't depend
2655 on the directory used to start the OpenOCD server.
2657 The @var{offset} and @var{length} must be exact multiples of the
2658 device's page size. They describe a data region; the OOB data
2659 associated with each such page may also be accessed.
2661 @b{NOTE:} At the time this text was written, no error correction
2662 was done on the data that's read, unless raw access was disabled
2663 and the underlying NAND controller driver had a @code{read_page}
2664 method which handled that error correction.
2666 By default, only page data is saved to the specified file.
2667 Use an @var{oob_option} parameter to save OOB data:
2669 @item no oob_* parameter
2670 @*Output file holds only page data; OOB is discarded.
2671 @item @code{oob_raw}
2672 @*Output file interleaves page data and OOB data;
2673 the file will be longer than "length" by the size of the
2674 spare areas associated with each data page.
2675 Note that this kind of "raw" access is different from
2676 what's implied by @command{nand raw_access}, which just
2677 controls whether a hardware-aware access method is used.
2678 @item @code{oob_only}
2679 @*Output file has only raw OOB data, and will
2680 be smaller than "length" since it will contain only the
2681 spare areas associated with each data page.
2685 @deffn Command {nand erase} num ...
2686 @cindex NAND erasing
2687 @b{NOTE:} Syntax is in flux.
2690 @deffn Command {nand write} num filename offset [option...]
2691 @cindex NAND writing
2692 Writes binary data from the file into the specified NAND device,
2693 starting at the specified offset. Those pages should already
2694 have been erased; you can't change zero bits to one bits.
2695 The @var{num} parameter is the value shown by @command{nand list}.
2697 Use a complete path name for @var{filename}, so you don't depend
2698 on the directory used to start the OpenOCD server.
2700 The @var{offset} must be an exact multiple of the device's page size.
2701 All data in the file will be written, assuming it doesn't run
2702 past the end of the device.
2703 Only full pages are written, and any extra space in the last
2704 page will be filled with 0xff bytes. (That includes OOB data,
2705 if that's being written.)
2707 @b{NOTE:} At the time this text was written, bad blocks are
2708 ignored. That is, this routine will not skip bad blocks,
2709 but will instead try to write them. This can cause problems.
2711 Provide at most one @var{option} parameter. With some
2712 NAND drivers, the meanings of these parameters may change
2713 if @command{nand raw_access} was used to disable hardware ECC.
2715 @item no oob_* parameter
2716 @*File has only page data, which is written.
2717 If raw acccess is in use, the OOB area will not be written.
2718 Otherwise, if the underlying NAND controller driver has
2719 a @code{write_page} routine, that routine may write the OOB
2720 with hardware-computed ECC data.
2721 @item @code{oob_only}
2722 @*File has only raw OOB data, which is written to the OOB area.
2723 Each page's data area stays untouched. @i{This can be a dangerous
2724 option}, since it can invalidate the ECC data.
2725 You may need to force raw access to use this mode.
2726 @item @code{oob_raw}
2727 @*File interleaves data and OOB data, both of which are written
2728 If raw access is enabled, the data is written first, then the
2730 Otherwise, if the underlying NAND controller driver has
2731 a @code{write_page} routine, that routine may modify the OOB
2732 before it's written, to include hardware-computed ECC data.
2733 @item @code{oob_softecc}
2734 @*File has only page data, which is written.
2735 The OOB area is filled with 0xff, except for a standard 1-bit
2736 software ECC code stored in conventional locations.
2737 You might need to force raw access to use this mode, to prevent
2738 the underlying driver from applying hardware ECC.
2739 @item @code{oob_softecc_kw}
2740 @*File has only page data, which is written.
2741 The OOB area is filled with 0xff, except for a 4-bit software ECC
2742 specific to the boot ROM in Marvell Kirkwood SoCs.
2743 You might need to force raw access to use this mode, to prevent
2744 the underlying driver from applying hardware ECC.
2748 @section Other NAND commands
2749 @cindex NAND other commands
2751 @deffn Command {nand check_bad} num ...
2752 @b{NOTE:} Syntax is in flux.
2755 @deffn Command {nand info} num
2756 The @var{num} parameter is the value shown by @command{nand list}.
2757 This prints the one-line summary from "nand list", plus for
2758 devices which have been probed this also prints any known
2759 status for each block.
2762 @deffn Command {nand raw_access} num <enable|disable>
2763 Sets or clears an flag affecting how page I/O is done.
2764 The @var{num} parameter is the value shown by @command{nand list}.
2766 This flag is cleared (disabled) by default, but changing that
2767 value won't affect all NAND devices. The key factor is whether
2768 the underlying driver provides @code{read_page} or @code{write_page}
2769 methods. If it doesn't provide those methods, the setting of
2770 this flag is irrelevant; all access is effectively ``raw''.
2772 When those methods exist, they are normally used when reading
2773 data (@command{nand dump} or reading bad block markers) or
2774 writing it (@command{nand write}). However, enabling
2775 raw access (setting the flag) prevents use of those methods,
2776 bypassing hardware ECC logic.
2777 @i{This can be a dangerous option}, since writing blocks
2778 with the wrong ECC data can cause them to be marked as bad.
2781 @section NAND Drivers; Driver-specific Options and Commands
2782 @anchor{NAND Driver List}
2783 As noted above, the @command{nand device} command allows
2784 driver-specific options and behaviors.
2785 Some controllers also activate controller-specific commands.
2787 @deffn {NAND Driver} lpc3180
2788 These controllers require an extra @command{nand device}
2789 parameter: the clock rate used by the controller.
2790 @deffn Command {nand lpc3180 select} num [mlc|slc]
2791 Configures use of the MLC or SLC controller mode.
2792 MLC implies use of hardware ECC.
2793 The @var{num} parameter is the value shown by @command{nand list}.
2796 At this writing, this driver includes @code{write_page}
2797 and @code{read_page} methods. Using @command{nand raw_access}
2798 to disable those methods will prevent use of hardware ECC
2799 in the MLC controller mode, but won't change SLC behavior.
2801 @comment current lpc3180 code won't issue 5-byte address cycles
2803 @deffn {NAND Driver} orion
2804 These controllers require an extra @command{nand device}
2805 parameter: the address of the controller.
2807 nand device orion 0xd8000000
2809 These controllers don't define any specialized commands.
2810 At this writing, their drivers don't include @code{write_page}
2811 or @code{read_page} methods, so @command{nand raw_access} won't
2812 change any behavior.
2815 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2816 These S3C24xx family controllers don't have any special
2817 @command{nand device} options, and don't define any
2818 specialized commands.
2819 At this writing, their drivers don't include @code{write_page}
2820 or @code{read_page} methods, so @command{nand raw_access} won't
2821 change any behavior.
2824 @node General Commands
2825 @chapter General Commands
2828 The commands documented in this chapter here are common commands that
2829 you, as a human, may want to type and see the output of. Configuration type
2830 commands are documented elsewhere.
2834 @item @b{Source Of Commands}
2835 @* OpenOCD commands can occur in a configuration script (discussed
2836 elsewhere) or typed manually by a human or supplied programatically,
2837 or via one of several TCP/IP Ports.
2839 @item @b{From the human}
2840 @* A human should interact with the telnet interface (default port: 4444,
2841 or via GDB, default port 3333)
2843 To issue commands from within a GDB session, use the @option{monitor}
2844 command, e.g. use @option{monitor poll} to issue the @option{poll}
2845 command. All output is relayed through the GDB session.
2847 @item @b{Machine Interface}
2848 The Tcl interface's intent is to be a machine interface. The default Tcl
2853 @section Daemon Commands
2855 @subsection sleep [@var{msec}]
2857 @*Wait for n milliseconds before resuming. Useful in connection with script files
2858 (@var{script} command and @var{target_script} configuration).
2860 @subsection shutdown
2862 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
2864 @subsection debug_level [@var{n}]
2866 @anchor{debug_level}
2867 @*Display or adjust debug level to n<0-3>
2869 @subsection fast [@var{enable|disable}]
2871 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2872 downloads and fast memory access will work if the JTAG interface isn't too fast and
2873 the core doesn't run at a too low frequency. Note that this option only changes the default
2874 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2877 The target specific "dangerous" optimisation tweaking options may come and go
2878 as more robust and user friendly ways are found to ensure maximum throughput
2879 and robustness with a minimum of configuration.
2881 Typically the "fast enable" is specified first on the command line:
2884 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2887 @subsection echo <@var{message}>
2889 @*Output message to stdio. e.g. echo "Programming - please wait"
2891 @subsection log_output <@var{file}>
2893 @*Redirect logging to <file> (default: stderr)
2895 @subsection script <@var{file}>
2897 @*Execute commands from <file>
2898 See also: ``source [find FILENAME]''
2900 @section Target state handling
2901 @subsection power <@var{on}|@var{off}>
2903 @*Turn power switch to target on/off.
2904 No arguments: print status.
2905 Not all interfaces support this.
2907 @subsection reg [@option{#}|@option{name}] [value]
2909 @*Access a single register by its number[@option{#}] or by its [@option{name}].
2910 No arguments: list all available registers for the current target.
2911 Number or name argument: display a register.
2912 Number or name and value arguments: set register value.
2914 @subsection poll [@option{on}|@option{off}]
2916 @*Poll the target for its current state. If the target is in debug mode, architecture
2917 specific information about the current state is printed. An optional parameter
2918 allows continuous polling to be enabled and disabled.
2920 @subsection halt [@option{ms}]
2922 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
2923 Default [@option{ms}] is 5 seconds if no arg given.
2924 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
2925 will stop OpenOCD from waiting.
2927 @subsection wait_halt [@option{ms}]
2929 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
2930 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
2933 @subsection resume [@var{address}]
2935 @*Resume the target at its current code position, or at an optional address.
2936 OpenOCD will wait 5 seconds for the target to resume.
2938 @subsection step [@var{address}]
2940 @*Single-step the target at its current code position, or at an optional address.
2942 @subsection reset [@option{run}|@option{halt}|@option{init}]
2944 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
2946 With no arguments a "reset run" is executed
2950 @*Let the target run.
2953 @*Immediately halt the target (works only with certain configurations).
2956 @*Immediately halt the target, and execute the reset script (works only with certain
2960 @subsection soft_reset_halt
2962 @*Requesting target halt and executing a soft reset. This is often used
2963 when a target cannot be reset and halted. The target, after reset is
2964 released begins to execute code. OpenOCD attempts to stop the CPU and
2965 then sets the program counter back to the reset vector. Unfortunately
2966 the code that was executed may have left the hardware in an unknown
2970 @section Memory access commands
2972 display available RAM memory.
2973 @subsection Memory peek/poke type commands
2974 These commands allow accesses of a specific size to the memory
2975 system. Often these are used to configure the current target in some
2976 special way. For example - one may need to write certian values to the
2977 SDRAM controller to enable SDRAM.
2980 @item To change the current target see the ``targets'' (plural) command
2981 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
2985 @item @b{mdw} <@var{addr}> [@var{count}]
2987 @*display memory words (32bit)
2988 @item @b{mdh} <@var{addr}> [@var{count}]
2990 @*display memory half-words (16bit)
2991 @item @b{mdb} <@var{addr}> [@var{count}]
2993 @*display memory bytes (8bit)
2994 @item @b{mww} <@var{addr}> <@var{value}>
2996 @*write memory word (32bit)
2997 @item @b{mwh} <@var{addr}> <@var{value}>
2999 @*write memory half-word (16bit)
3000 @item @b{mwb} <@var{addr}> <@var{value}>
3002 @*write memory byte (8bit)
3005 @section Image loading commands
3006 @subsection load_image
3007 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3010 @*Load image <@var{file}> to target memory at <@var{address}>
3011 @subsection fast_load_image
3012 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3013 @cindex fast_load_image
3014 @anchor{fast_load_image}
3015 @*Normally you should be using @b{load_image} or GDB load. However, for
3016 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3017 host), storing the image in memory and uploading the image to the target
3018 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3019 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3020 memory, i.e. does not affect target. This approach is also useful when profiling
3021 target programming performance as I/O and target programming can easily be profiled
3023 @subsection fast_load
3027 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3028 @subsection dump_image
3029 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3032 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3033 (binary) <@var{file}>.
3034 @subsection verify_image
3035 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3036 @cindex verify_image
3037 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3038 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3041 @section Breakpoint commands
3042 @cindex Breakpoint commands
3044 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3046 @*set breakpoint <address> <length> [hw]
3047 @item @b{rbp} <@var{addr}>
3049 @*remove breakpoint <adress>
3050 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3052 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3053 @item @b{rwp} <@var{addr}>
3055 @*remove watchpoint <adress>
3058 @section Misc Commands
3059 @cindex Other Target Commands
3061 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3063 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3067 @section Target Specific Commands
3068 @cindex Target Specific Commands
3072 @section Architecture Specific Commands
3073 @cindex Architecture Specific Commands
3075 @subsection ARMV4/5 specific commands
3076 @cindex ARMV4/5 specific commands
3078 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3079 or Intel XScale (XScale isn't supported yet).
3081 @item @b{armv4_5 reg}
3083 @*Display a list of all banked core registers, fetching the current value from every
3084 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3086 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3087 @cindex armv4_5 core_mode
3088 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3089 The target is resumed in the currently set @option{core_mode}.
3092 @subsection ARM7/9 specific commands
3093 @cindex ARM7/9 specific commands
3095 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3096 ARM920T or ARM926EJ-S.
3098 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3099 @cindex arm7_9 dbgrq
3100 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3101 safe for all but ARM7TDMI--S cores (like Philips LPC).
3102 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3103 @cindex arm7_9 fast_memory_access
3104 @anchor{arm7_9 fast_memory_access}
3105 @*Allow OpenOCD to read and write memory without checking completion of
3106 the operation. This provides a huge speed increase, especially with USB JTAG
3107 cables (FT2232), but might be unsafe if used with targets running at very low
3108 speeds, like the 32kHz startup clock of an AT91RM9200.
3109 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3110 @cindex arm7_9 dcc_downloads
3111 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3112 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3113 unsafe, especially with targets running at very low speeds. This command was introduced
3114 with OpenOCD rev. 60, and requires a few bytes of working area.
3117 @subsection ARM720T specific commands
3118 @cindex ARM720T specific commands
3121 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3122 @cindex arm720t cp15
3123 @*display/modify cp15 register <@option{num}> [@option{value}].
3124 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3125 @cindex arm720t md<bhw>_phys
3126 @*Display memory at physical address addr.
3127 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3128 @cindex arm720t mw<bhw>_phys
3129 @*Write memory at physical address addr.
3130 @item @b{arm720t virt2phys} <@var{va}>
3131 @cindex arm720t virt2phys
3132 @*Translate a virtual address to a physical address.
3135 @subsection ARM9TDMI specific commands
3136 @cindex ARM9TDMI specific commands
3139 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3140 @cindex arm9tdmi vector_catch
3141 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3142 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3143 @option{irq} @option{fiq}.
3145 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3148 @subsection ARM966E specific commands
3149 @cindex ARM966E specific commands
3152 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3153 @cindex arm966e cp15
3154 @*display/modify cp15 register <@option{num}> [@option{value}].
3157 @subsection ARM920T specific commands
3158 @cindex ARM920T specific commands
3161 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3162 @cindex arm920t cp15
3163 @*display/modify cp15 register <@option{num}> [@option{value}].
3164 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3165 @cindex arm920t cp15i
3166 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3167 @item @b{arm920t cache_info}
3168 @cindex arm920t cache_info
3169 @*Print information about the caches found. This allows to see whether your target
3170 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3171 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3172 @cindex arm920t md<bhw>_phys
3173 @*Display memory at physical address addr.
3174 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3175 @cindex arm920t mw<bhw>_phys
3176 @*Write memory at physical address addr.
3177 @item @b{arm920t read_cache} <@var{filename}>
3178 @cindex arm920t read_cache
3179 @*Dump the content of ICache and DCache to a file.
3180 @item @b{arm920t read_mmu} <@var{filename}>
3181 @cindex arm920t read_mmu
3182 @*Dump the content of the ITLB and DTLB to a file.
3183 @item @b{arm920t virt2phys} <@var{va}>
3184 @cindex arm920t virt2phys
3185 @*Translate a virtual address to a physical address.
3188 @subsection ARM926EJ-S specific commands
3189 @cindex ARM926EJ-S specific commands
3192 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3193 @cindex arm926ejs cp15
3194 @*display/modify cp15 register <@option{num}> [@option{value}].
3195 @item @b{arm926ejs cache_info}
3196 @cindex arm926ejs cache_info
3197 @*Print information about the caches found.
3198 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3199 @cindex arm926ejs md<bhw>_phys
3200 @*Display memory at physical address addr.
3201 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3202 @cindex arm926ejs mw<bhw>_phys
3203 @*Write memory at physical address addr.
3204 @item @b{arm926ejs virt2phys} <@var{va}>
3205 @cindex arm926ejs virt2phys
3206 @*Translate a virtual address to a physical address.
3209 @subsection CORTEX_M3 specific commands
3210 @cindex CORTEX_M3 specific commands
3213 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3214 @cindex cortex_m3 maskisr
3215 @*Enable masking (disabling) interrupts during target step/resume.
3219 @section Debug commands
3220 @cindex Debug commands
3221 The following commands give direct access to the core, and are most likely
3222 only useful while debugging OpenOCD.
3224 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3225 @cindex arm7_9 write_xpsr
3226 @*Immediately write either the current program status register (CPSR) or the saved
3227 program status register (SPSR), without changing the register cache (as displayed
3228 by the @option{reg} and @option{armv4_5 reg} commands).
3229 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3230 <@var{0=cpsr},@var{1=spsr}>
3231 @cindex arm7_9 write_xpsr_im8
3232 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3233 operation (similar to @option{write_xpsr}).
3234 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3235 @cindex arm7_9 write_core_reg
3236 @*Write a core register, without changing the register cache (as displayed by the
3237 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3238 encoding of the [M4:M0] bits of the PSR.
3241 @section Target Requests
3242 @cindex Target Requests
3243 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3244 See libdcc in the contrib dir for more details.
3246 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3247 @cindex target_request debugmsgs
3248 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3252 @chapter JTAG Commands
3253 @cindex JTAG Commands
3254 Generally most people will not use the bulk of these commands. They
3255 are mostly used by the OpenOCD developers or those who need to
3256 directly manipulate the JTAG taps.
3258 In general these commands control JTAG taps at a very low level. For
3259 example if you need to control a JTAG Route Controller (i.e.: the
3260 OMAP3530 on the Beagle Board has one) you might use these commands in
3261 a script or an event procedure.
3265 @item @b{scan_chain}
3267 @*Print current scan chain configuration.
3268 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3270 @*Toggle reset lines.
3271 @item @b{endstate} <@var{tap_state}>
3273 @*Finish JTAG operations in <@var{tap_state}>.
3274 @item @b{runtest} <@var{num_cycles}>
3276 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3277 @item @b{statemove} [@var{tap_state}]
3279 @*Move to current endstate or [@var{tap_state}]
3280 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3282 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3283 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3285 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3286 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3287 @cindex verify_ircapture
3288 @*Verify value captured during Capture-IR. Default is enabled.
3289 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3291 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3292 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3294 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3299 Available tap_states are:
3339 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3340 be used to access files on PCs (either the developer's PC or some other PC).
3342 The way this works on the ZY1000 is to prefix a filename by
3343 "/tftp/ip/" and append the TFTP path on the TFTP
3344 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3345 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3346 if the file was hosted on the embedded host.
3348 In order to achieve decent performance, you must choose a TFTP server
3349 that supports a packet size bigger than the default packet size (512 bytes). There
3350 are numerous TFTP servers out there (free and commercial) and you will have to do
3351 a bit of googling to find something that fits your requirements.
3353 @node Sample Scripts
3354 @chapter Sample Scripts
3357 This page shows how to use the Target Library.
3359 The configuration script can be divided into the following sections:
3361 @item Daemon configuration
3363 @item JTAG scan chain
3364 @item Target configuration
3365 @item Flash configuration
3368 Detailed information about each section can be found at OpenOCD configuration.
3370 @section AT91R40008 example
3371 @cindex AT91R40008 example
3372 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3373 the CPU upon startup of the OpenOCD daemon.
3375 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3379 @node GDB and OpenOCD
3380 @chapter GDB and OpenOCD
3381 @cindex GDB and OpenOCD
3382 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3383 to debug remote targets.
3385 @section Connecting to GDB
3386 @cindex Connecting to GDB
3387 @anchor{Connecting to GDB}
3388 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3389 instance GDB 6.3 has a known bug that produces bogus memory access
3390 errors, which has since been fixed: look up 1836 in
3391 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3393 @*OpenOCD can communicate with GDB in two ways:
3396 A socket (TCP/IP) connection is typically started as follows:
3398 target remote localhost:3333
3400 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3402 A pipe connection is typically started as follows:
3404 target remote | openocd --pipe
3406 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3407 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3411 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3414 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3415 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3416 packet size and the device's memory map.
3418 Previous versions of OpenOCD required the following GDB options to increase
3419 the packet size and speed up GDB communication:
3421 set remote memory-write-packet-size 1024
3422 set remote memory-write-packet-size fixed
3423 set remote memory-read-packet-size 1024
3424 set remote memory-read-packet-size fixed
3426 This is now handled in the @option{qSupported} PacketSize and should not be required.
3428 @section Programming using GDB
3429 @cindex Programming using GDB
3431 By default the target memory map is sent to GDB. This can be disabled by
3432 the following OpenOCD configuration option:
3434 gdb_memory_map disable
3436 For this to function correctly a valid flash configuration must also be set
3437 in OpenOCD. For faster performance you should also configure a valid
3440 Informing GDB of the memory map of the target will enable GDB to protect any
3441 flash areas of the target and use hardware breakpoints by default. This means
3442 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
3443 using a memory map. @xref{gdb_breakpoint_override}.
3445 To view the configured memory map in GDB, use the GDB command @option{info mem}
3446 All other unassigned addresses within GDB are treated as RAM.
3448 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3449 This can be changed to the old behaviour by using the following GDB command
3451 set mem inaccessible-by-default off
3454 If @option{gdb_flash_program enable} is also used, GDB will be able to
3455 program any flash memory using the vFlash interface.
3457 GDB will look at the target memory map when a load command is given, if any
3458 areas to be programmed lie within the target flash area the vFlash packets
3461 If the target needs configuring before GDB programming, an event
3462 script can be executed:
3464 $_TARGETNAME configure -event EVENTNAME BODY
3467 To verify any flash programming the GDB command @option{compare-sections}
3470 @node Tcl Scripting API
3471 @chapter Tcl Scripting API
3472 @cindex Tcl Scripting API
3476 The commands are stateless. E.g. the telnet command line has a concept
3477 of currently active target, the Tcl API proc's take this sort of state
3478 information as an argument to each proc.
3480 There are three main types of return values: single value, name value
3481 pair list and lists.
3483 Name value pair. The proc 'foo' below returns a name/value pair
3489 > set foo(you) Oyvind
3490 > set foo(mouse) Micky
3491 > set foo(duck) Donald
3499 me Duane you Oyvind mouse Micky duck Donald
3501 Thus, to get the names of the associative array is easy:
3503 foreach { name value } [set foo] {
3504 puts "Name: $name, Value: $value"
3508 Lists returned must be relatively small. Otherwise a range
3509 should be passed in to the proc in question.
3511 @section Internal low-level Commands
3513 By low-level, the intent is a human would not directly use these commands.
3515 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3516 is the low level API upon which "flash banks" is implemented.
3519 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3521 Read memory and return as a Tcl array for script processing
3522 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3524 Convert a Tcl array to memory locations and write the values
3525 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3527 Return information about the flash banks
3530 OpenOCD commands can consist of two words, e.g. "flash banks". The
3531 startup.tcl "unknown" proc will translate this into a Tcl proc
3532 called "flash_banks".
3534 @section OpenOCD specific Global Variables
3538 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3539 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3540 holds one of the following values:
3543 @item @b{winxx} Built using Microsoft Visual Studio
3544 @item @b{linux} Linux is the underlying operating sytem
3545 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3546 @item @b{cygwin} Running under Cygwin
3547 @item @b{mingw32} Running under MingW32
3548 @item @b{other} Unknown, none of the above.
3551 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3554 @chapter Deprecated/Removed Commands
3555 @cindex Deprecated/Removed Commands
3556 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3559 @item @b{arm7_9 fast_writes}
3560 @cindex arm7_9 fast_writes
3561 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3562 @item @b{arm7_9 force_hw_bkpts}
3563 @cindex arm7_9 force_hw_bkpts
3564 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3565 for flash if the GDB memory map has been set up(default when flash is declared in
3566 target configuration). @xref{gdb_breakpoint_override}.
3567 @item @b{arm7_9 sw_bkpts}
3568 @cindex arm7_9 sw_bkpts
3569 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
3570 @item @b{daemon_startup}
3571 @cindex daemon_startup
3572 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3573 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3574 and @option{target cortex_m3 little reset_halt 0}.
3575 @item @b{dump_binary}
3577 @*use @option{dump_image} command with same args. @xref{dump_image}.
3578 @item @b{flash erase}
3580 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3581 @item @b{flash write}
3583 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3584 @item @b{flash write_binary}
3585 @cindex flash write_binary
3586 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3587 @item @b{flash auto_erase}
3588 @cindex flash auto_erase
3589 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3590 @item @b{load_binary}
3592 @*use @option{load_image} command with same args. @xref{load_image}.
3593 @item @b{run_and_halt_time}
3594 @cindex run_and_halt_time
3595 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3602 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3604 @*use the create subcommand of @option{target}.
3605 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3606 @cindex target_script
3607 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3608 @item @b{working_area}
3609 @cindex working_area
3610 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3617 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3619 @cindex adaptive clocking
3622 In digital circuit design it is often refered to as ``clock
3623 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3624 operating at some speed, your target is operating at another. The two
3625 clocks are not synchronised, they are ``asynchronous''
3627 In order for the two to work together they must be synchronised. Otherwise
3628 the two systems will get out of sync with each other and nothing will
3629 work. There are 2 basic options:
3632 Use a special circuit.
3634 One clock must be some multiple slower than the other.
3637 @b{Does this really matter?} For some chips and some situations, this
3638 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3639 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3640 program/enable the oscillators and eventually the main clock. It is in
3641 those critical times you must slow the JTAG clock to sometimes 1 to
3644 Imagine debugging a 500MHz ARM926 hand held battery powered device
3645 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3648 @b{Solution #1 - A special circuit}
3650 In order to make use of this, your JTAG dongle must support the RTCK
3651 feature. Not all dongles support this - keep reading!
3653 The RTCK signal often found in some ARM chips is used to help with
3654 this problem. ARM has a good description of the problem described at
3655 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3656 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3657 work? / how does adaptive clocking work?''.
3659 The nice thing about adaptive clocking is that ``battery powered hand
3660 held device example'' - the adaptiveness works perfectly all the
3661 time. One can set a break point or halt the system in the deep power
3662 down code, slow step out until the system speeds up.
3664 @b{Solution #2 - Always works - but may be slower}
3666 Often this is a perfectly acceptable solution.
3668 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3669 the target clock speed. But what that ``magic division'' is varies
3670 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3671 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3672 1/12 the clock speed.
3674 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3676 You can still debug the 'low power' situations - you just need to
3677 manually adjust the clock speed at every step. While painful and
3678 tedious, it is not always practical.
3680 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3681 have a special debug mode in your application that does a ``high power
3682 sleep''. If you are careful - 98% of your problems can be debugged
3685 To set the JTAG frequency use the command:
3693 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3695 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3696 around Windows filenames.
3709 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3711 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3712 claims to come with all the necessary DLLs. When using Cygwin, try launching
3713 OpenOCD from the Cygwin shell.
3715 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3716 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3717 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3719 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3720 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3721 software breakpoints consume one of the two available hardware breakpoints.
3723 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3725 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3726 clock at the time you're programming the flash. If you've specified the crystal's
3727 frequency, make sure the PLL is disabled. If you've specified the full core speed
3728 (e.g. 60MHz), make sure the PLL is enabled.
3730 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3731 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3732 out while waiting for end of scan, rtck was disabled".
3734 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3735 settings in your PC BIOS (ECP, EPP, and different versions of those).
3737 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3738 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3739 memory read caused data abort".
3741 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3742 beyond the last valid frame. It might be possible to prevent this by setting up
3743 a proper "initial" stack frame, if you happen to know what exactly has to
3744 be done, feel free to add this here.
3746 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3747 stack before calling main(). What GDB is doing is ``climbing'' the run
3748 time stack by reading various values on the stack using the standard
3749 call frame for the target. GDB keeps going - until one of 2 things
3750 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3751 stackframes have been processed. By pushing zeros on the stack, GDB
3754 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3755 your C code, do the same - artifically push some zeros onto the stack,
3756 remember to pop them off when the ISR is done.
3758 @b{Also note:} If you have a multi-threaded operating system, they
3759 often do not @b{in the intrest of saving memory} waste these few
3763 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3764 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3766 This warning doesn't indicate any serious problem, as long as you don't want to
3767 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3768 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3769 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3770 independently. With this setup, it's not possible to halt the core right out of
3771 reset, everything else should work fine.
3773 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3774 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3775 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3776 quit with an error message. Is there a stability issue with OpenOCD?
3778 No, this is not a stability issue concerning OpenOCD. Most users have solved
3779 this issue by simply using a self-powered USB hub, which they connect their
3780 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3781 supply stable enough for the Amontec JTAGkey to be operated.
3783 @b{Laptops running on battery have this problem too...}
3785 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3786 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3787 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3788 What does that mean and what might be the reason for this?
3790 First of all, the reason might be the USB power supply. Try using a self-powered
3791 hub instead of a direct connection to your computer. Secondly, the error code 4
3792 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3793 chip ran into some sort of error - this points us to a USB problem.
3795 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3796 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3797 What does that mean and what might be the reason for this?
3799 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3800 has closed the connection to OpenOCD. This might be a GDB issue.
3802 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3803 are described, there is a parameter for specifying the clock frequency
3804 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3805 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3806 specified in kilohertz. However, I do have a quartz crystal of a
3807 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3808 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3811 No. The clock frequency specified here must be given as an integral number.
3812 However, this clock frequency is used by the In-Application-Programming (IAP)
3813 routines of the LPC2000 family only, which seems to be very tolerant concerning
3814 the given clock frequency, so a slight difference between the specified clock
3815 frequency and the actual clock frequency will not cause any trouble.
3817 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3819 Well, yes and no. Commands can be given in arbitrary order, yet the
3820 devices listed for the JTAG scan chain must be given in the right
3821 order (jtag newdevice), with the device closest to the TDO-Pin being
3822 listed first. In general, whenever objects of the same type exist
3823 which require an index number, then these objects must be given in the
3824 right order (jtag newtap, targets and flash banks - a target
3825 references a jtag newtap and a flash bank references a target).
3827 You can use the ``scan_chain'' command to verify and display the tap order.
3829 Also, some commands can't execute until after @command{init} has been
3830 processed. Such commands include @command{nand probe} and everything
3831 else that needs to write to controller registers, perhaps for setting
3832 up DRAM and loading it with code.
3834 @item @b{JTAG Tap Order} JTAG tap order - command order
3836 Many newer devices have multiple JTAG taps. For example: ST
3837 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3838 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
3839 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3840 connected to the boundary scan tap, which then connects to the
3841 Cortex-M3 tap, which then connects to the TDO pin.
3843 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
3844 (2) The boundary scan tap. If your board includes an additional JTAG
3845 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3846 place it before or after the STM32 chip in the chain. For example:
3849 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3850 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
3851 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
3852 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3853 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3856 The ``jtag device'' commands would thus be in the order shown below. Note:
3859 @item jtag newtap Xilinx tap -irlen ...
3860 @item jtag newtap stm32 cpu -irlen ...
3861 @item jtag newtap stm32 bs -irlen ...
3862 @item # Create the debug target and say where it is
3863 @item target create stm32.cpu -chain-position stm32.cpu ...
3867 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3868 log file, I can see these error messages: Error: arm7_9_common.c:561
3869 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3875 @node Tcl Crash Course
3876 @chapter Tcl Crash Course
3879 Not everyone knows Tcl - this is not intended to be a replacement for
3880 learning Tcl, the intent of this chapter is to give you some idea of
3881 how the Tcl scripts work.
3883 This chapter is written with two audiences in mind. (1) OpenOCD users
3884 who need to understand a bit more of how JIM-Tcl works so they can do
3885 something useful, and (2) those that want to add a new command to
3888 @section Tcl Rule #1
3889 There is a famous joke, it goes like this:
3891 @item Rule #1: The wife is always correct
3892 @item Rule #2: If you think otherwise, See Rule #1
3895 The Tcl equal is this:
3898 @item Rule #1: Everything is a string
3899 @item Rule #2: If you think otherwise, See Rule #1
3902 As in the famous joke, the consequences of Rule #1 are profound. Once
3903 you understand Rule #1, you will understand Tcl.
3905 @section Tcl Rule #1b
3906 There is a second pair of rules.
3908 @item Rule #1: Control flow does not exist. Only commands
3909 @* For example: the classic FOR loop or IF statement is not a control
3910 flow item, they are commands, there is no such thing as control flow
3912 @item Rule #2: If you think otherwise, See Rule #1
3913 @* Actually what happens is this: There are commands that by
3914 convention, act like control flow key words in other languages. One of
3915 those commands is the word ``for'', another command is ``if''.
3918 @section Per Rule #1 - All Results are strings
3919 Every Tcl command results in a string. The word ``result'' is used
3920 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
3921 Everything is a string}
3923 @section Tcl Quoting Operators
3924 In life of a Tcl script, there are two important periods of time, the
3925 difference is subtle.
3928 @item Evaluation Time
3931 The two key items here are how ``quoted things'' work in Tcl. Tcl has
3932 three primary quoting constructs, the [square-brackets] the
3933 @{curly-braces@} and ``double-quotes''
3935 By now you should know $VARIABLES always start with a $DOLLAR
3936 sign. BTW: To set a variable, you actually use the command ``set'', as
3937 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
3938 = 1'' statement, but without the equal sign.
3941 @item @b{[square-brackets]}
3942 @* @b{[square-brackets]} are command substitutions. It operates much
3943 like Unix Shell `back-ticks`. The result of a [square-bracket]
3944 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
3945 string}. These two statements are roughly identical:
3949 echo "The Date is: $X"
3952 puts "The Date is: $X"
3954 @item @b{``double-quoted-things''}
3955 @* @b{``double-quoted-things''} are just simply quoted
3956 text. $VARIABLES and [square-brackets] are expanded in place - the
3957 result however is exactly 1 string. @i{Remember Rule #1 - Everything
3961 puts "It is now \"[date]\", $x is in 1 hour"
3963 @item @b{@{Curly-Braces@}}
3964 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
3965 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
3966 'single-quote' operators in BASH shell scripts, with the added
3967 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
3968 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
3969 28/nov/2008, Jim/OpenOCD does not have a date command.
3972 @section Consequences of Rule 1/2/3/4
3974 The consequences of Rule 1 are profound.
3976 @subsection Tokenisation & Execution.
3978 Of course, whitespace, blank lines and #comment lines are handled in
3981 As a script is parsed, each (multi) line in the script file is
3982 tokenised and according to the quoting rules. After tokenisation, that
3983 line is immedatly executed.
3985 Multi line statements end with one or more ``still-open''
3986 @{curly-braces@} which - eventually - closes a few lines later.
3988 @subsection Command Execution
3990 Remember earlier: There are no ``control flow''
3991 statements in Tcl. Instead there are COMMANDS that simply act like
3992 control flow operators.
3994 Commands are executed like this:
3997 @item Parse the next line into (argc) and (argv[]).
3998 @item Look up (argv[0]) in a table and call its function.
3999 @item Repeat until End Of File.
4002 It sort of works like this:
4005 ReadAndParse( &argc, &argv );
4007 cmdPtr = LookupCommand( argv[0] );
4009 (*cmdPtr->Execute)( argc, argv );
4013 When the command ``proc'' is parsed (which creates a procedure
4014 function) it gets 3 parameters on the command line. @b{1} the name of
4015 the proc (function), @b{2} the list of parameters, and @b{3} the body
4016 of the function. Not the choice of words: LIST and BODY. The PROC
4017 command stores these items in a table somewhere so it can be found by
4020 @subsection The FOR command
4022 The most interesting command to look at is the FOR command. In Tcl,
4023 the FOR command is normally implemented in C. Remember, FOR is a
4024 command just like any other command.
4026 When the ascii text containing the FOR command is parsed, the parser
4027 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
4031 @item The ascii text 'for'
4032 @item The start text
4033 @item The test expression
4038 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
4039 Remember @i{Rule #1 - Everything is a string.} The key point is this:
4040 Often many of those parameters are in @{curly-braces@} - thus the
4041 variables inside are not expanded or replaced until later.
4043 Remember that every Tcl command looks like the classic ``main( argc,
4044 argv )'' function in C. In JimTCL - they actually look like this:
4048 MyCommand( Jim_Interp *interp,
4050 Jim_Obj * const *argvs );
4053 Real Tcl is nearly identical. Although the newer versions have
4054 introduced a byte-code parser and intepreter, but at the core, it
4055 still operates in the same basic way.
4057 @subsection FOR command implementation
4059 To understand Tcl it is perhaps most helpful to see the FOR
4060 command. Remember, it is a COMMAND not a control flow structure.
4062 In Tcl there are two underlying C helper functions.
4064 Remember Rule #1 - You are a string.
4066 The @b{first} helper parses and executes commands found in an ascii
4067 string. Commands can be seperated by semicolons, or newlines. While
4068 parsing, variables are expanded via the quoting rules.
4070 The @b{second} helper evaluates an ascii string as a numerical
4071 expression and returns a value.
4073 Here is an example of how the @b{FOR} command could be
4074 implemented. The pseudo code below does not show error handling.
4076 void Execute_AsciiString( void *interp, const char *string );
4078 int Evaluate_AsciiExpression( void *interp, const char *string );
4081 MyForCommand( void *interp,
4086 SetResult( interp, "WRONG number of parameters");
4090 // argv[0] = the ascii string just like C
4092 // Execute the start statement.
4093 Execute_AsciiString( interp, argv[1] );
4097 i = Evaluate_AsciiExpression(interp, argv[2]);
4102 Execute_AsciiString( interp, argv[3] );
4104 // Execute the LOOP part
4105 Execute_AsciiString( interp, argv[4] );
4109 SetResult( interp, "" );
4114 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
4115 in the same basic way.
4117 @section OpenOCD Tcl Usage
4119 @subsection source and find commands
4120 @b{Where:} In many configuration files
4121 @* Example: @b{ source [find FILENAME] }
4122 @*Remember the parsing rules
4124 @item The FIND command is in square brackets.
4125 @* The FIND command is executed with the parameter FILENAME. It should
4126 find the full path to the named file. The RESULT is a string, which is
4127 substituted on the orginal command line.
4128 @item The command source is executed with the resulting filename.
4129 @* SOURCE reads a file and executes as a script.
4131 @subsection format command
4132 @b{Where:} Generally occurs in numerous places.
4133 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
4139 puts [format "The answer: %d" [expr $x * $y]]
4142 @item The SET command creates 2 variables, X and Y.
4143 @item The double [nested] EXPR command performs math
4144 @* The EXPR command produces numerical result as a string.
4146 @item The format command is executed, producing a single string
4147 @* Refer to Rule #1.
4148 @item The PUTS command outputs the text.
4150 @subsection Body or Inlined Text
4151 @b{Where:} Various TARGET scripts.
4154 proc someproc @{@} @{
4155 ... multiple lines of stuff ...
4157 $_TARGETNAME configure -event FOO someproc
4158 #2 Good - no variables
4159 $_TARGETNAME confgure -event foo "this ; that;"
4160 #3 Good Curly Braces
4161 $_TARGETNAME configure -event FOO @{
4164 #4 DANGER DANGER DANGER
4165 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
4168 @item The $_TARGETNAME is an OpenOCD variable convention.
4169 @*@b{$_TARGETNAME} represents the last target created, the value changes
4170 each time a new target is created. Remember the parsing rules. When
4171 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
4172 the name of the target which happens to be a TARGET (object)
4174 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
4175 @*There are 4 examples:
4177 @item The TCLBODY is a simple string that happens to be a proc name
4178 @item The TCLBODY is several simple commands seperated by semicolons
4179 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
4180 @item The TCLBODY is a string with variables that get expanded.
4183 In the end, when the target event FOO occurs the TCLBODY is
4184 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
4185 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
4187 Remember the parsing rules. In case #3, @{curly-braces@} mean the
4188 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
4189 and the text is evaluated. In case #4, they are replaced before the
4190 ``Target Object Command'' is executed. This occurs at the same time
4191 $_TARGETNAME is replaced. In case #4 the date will never
4192 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
4193 Jim/OpenOCD does not have a date command@}
4195 @subsection Global Variables
4196 @b{Where:} You might discover this when writing your own procs @* In
4197 simple terms: Inside a PROC, if you need to access a global variable
4198 you must say so. See also ``upvar''. Example:
4200 proc myproc @{ @} @{
4201 set y 0 #Local variable Y
4202 global x #Global variable X
4203 puts [format "X=%d, Y=%d" $x $y]
4206 @section Other Tcl Hacks
4207 @b{Dynamic variable creation}
4209 # Dynamically create a bunch of variables.
4210 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
4212 set vn [format "BIT%d" $x]
4216 set $vn [expr (1 << $x)]
4219 @b{Dynamic proc/command creation}
4221 # One "X" function - 5 uart functions.
4222 foreach who @{A B C D E@}
4223 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
4227 @node Target Library
4228 @chapter Target Library
4229 @cindex Target Library
4231 OpenOCD comes with a target configuration script library. These scripts can be
4232 used as-is or serve as a starting point.
4234 The target library is published together with the OpenOCD executable and
4235 the path to the target library is in the OpenOCD script search path.
4236 Similarly there are example scripts for configuring the JTAG interface.
4238 The command line below uses the example parport configuration script
4239 that ship with OpenOCD, then configures the str710.cfg target and
4240 finally issues the init and reset commands. The communication speed
4241 is set to 10kHz for reset and 8MHz for post reset.
4244 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
4247 To list the target scripts available:
4250 $ ls /usr/local/lib/openocd/target
4252 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
4253 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
4254 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
4255 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
4260 @node OpenOCD Concept Index
4261 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
4262 @comment case issue with ``Index.html'' and ``index.html''
4263 @comment Occurs when creating ``--html --no-split'' output
4264 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
4265 @unnumbered OpenOCD Concept Index
4269 @node OpenOCD Command Index
4270 @unnumbered OpenOCD Command Index