1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}@*
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
54 * GDB and OpenOCD:: Using GDB and OpenOCD
55 * TCL and OpenOCD:: Using TCL and OpenOCD
56 * TCL scripting API:: Tcl scripting API
57 * Upgrading:: Deprecated/Removed Commands
58 * FAQ:: Frequently Asked Questions
59 * License:: GNU Free Documentation License
67 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
68 and boundary-scan testing for embedded target devices. The targets are interfaced
69 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
70 connection types in the future.
72 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
73 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
74 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
75 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
77 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
78 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
79 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
85 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
86 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
87 Others interested in improving the state of free and open debug and testing technology
88 are welcome to participate.
90 Other developers have contributed support for additional targets and flashes as well
91 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
93 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
97 @cindex building OpenOCD
99 If you are interested in getting actual work done rather than building
100 OpenOCD, then check if your interface supplier provides binaries for
101 you. Chances are that that binary is from some SVN version that is more
102 stable than SVN trunk where bleeding edge development takes place.
105 You can download the current SVN version with SVN client of your choice from the
106 following repositories:
108 (@uref{svn://svn.berlios.de/openocd/trunk})
112 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
114 Using the SVN command line client, you can use the following command to fetch the
115 latest version (make sure there is no (non-svn) directory called "openocd" in the
119 svn checkout svn://svn.berlios.de/openocd/trunk openocd
122 Building OpenOCD requires a recent version of the GNU autotools.
123 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
124 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
125 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
126 paths, resulting in obscure dependency errors (This is an observation I've gathered
127 from the logs of one user - correct me if I'm wrong).
129 You further need the appropriate driver files, if you want to build support for
130 a FTDI FT2232 based interface:
132 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
133 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
134 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
135 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
138 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
139 see contrib/libftdi for more details.
141 In general, the D2XX driver provides superior performance (several times as fast),
142 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
143 a kernel module, only a user space library.
145 To build OpenOCD (on both Linux and Cygwin), use the following commands:
149 Bootstrap generates the configure script, and prepares building on your system.
153 Configure generates the Makefiles used to build OpenOCD.
157 Make builds OpenOCD, and places the final executable in ./src/.
159 The configure script takes several options, specifying which JTAG interfaces
164 @option{--enable-parport}
166 @option{--enable-parport_ppdev}
168 @option{--enable-parport_giveio}
170 @option{--enable-amtjtagaccel}
172 @option{--enable-ft2232_ftd2xx}
173 @footnote{Using the latest D2XX drivers from FTDI and following their installation
174 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
177 @option{--enable-ft2232_libftdi}
179 @option{--with-ftd2xx=/path/to/d2xx/}
181 @option{--enable-gw16012}
183 @option{--enable-usbprog}
185 @option{--enable-presto_libftdi}
187 @option{--enable-presto_ftd2xx}
189 @option{--enable-jlink}
192 If you want to access the parallel port using the PPDEV interface you have to specify
193 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
194 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
195 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
197 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
198 absolute path containing no spaces.
200 Linux users should copy the various parts of the D2XX package to the appropriate
201 locations, i.e. /usr/include, /usr/lib.
203 Miscellaneous configure options
207 @option{--enable-gccwarnings} - enable extra gcc warnings during build
212 @cindex running OpenOCD
214 @cindex --debug_level
217 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
218 Run with @option{--help} or @option{-h} to view the available command line switches.
220 It reads its configuration by default from the file openocd.cfg located in the current
221 working directory. This may be overwritten with the @option{-f <configfile>} command line
222 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
223 are executed in order.
225 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
227 To enable debug output (when reporting problems or working on OpenOCD itself), use
228 the @option{-d} command line switch. This sets the @option{debug_level} to "3", outputting
229 the most information, including debug messages. The default setting is "2", outputting
230 only informational messages, warnings and errors. You can also change this setting
231 from within a telnet or gdb session using @option{debug_level <n>} @xref{debug_level}.
233 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
235 Search paths for config/script files can be added to OpenOCD by using
236 the @option{-s <search>} switch. The current directory and the OpenOCD target library
237 is in the search path by default.
239 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
240 with the target. In general, it is possible for the JTAG controller to be unresponsive until
241 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
244 @chapter Configuration
245 @cindex configuration
246 OpenOCD runs as a daemon, and reads it current configuration
247 by default from the file openocd.cfg in the current directory. A different configuration
248 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
250 The configuration file is used to specify on which ports the daemon listens for new
251 connections, the JTAG interface used to connect to the target, the layout of the JTAG
252 chain, the targets that should be debugged, and connected flashes.
254 @section Daemon configuration
258 @*This command terminates the configuration stage and enters the normal
259 command mode. This can be useful to add commands to the startup scripts and commands
260 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
261 add "init" and "reset" at the end of the config script or at the end of the
262 OpenOCD command line using the @option{-c} command line switch.
264 @item @b{telnet_port} <@var{number}>
266 @*Port on which to listen for incoming telnet connections
267 @item @b{tcl_port} <@var{number}>
269 @*Port on which to listen for incoming TCL syntax. This port is intended as
270 a simplified RPC connection that can be used by clients to issue commands
271 and get the output from the TCL engine.
272 @item @b{gdb_port} <@var{number}>
274 @*First port on which to listen for incoming GDB connections. The GDB port for the
275 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
276 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
277 @cindex gdb_breakpoint_override
278 @anchor{gdb_breakpoint_override}
279 @*Force breakpoint type for gdb 'break' commands.
280 The raison d'etre for this option is to support GDB GUI's without
281 a hard/soft breakpoint concept where the default OpenOCD and
282 GDB behaviour is not sufficient. Note that GDB will use hardware
283 breakpoints if the memory map has been set up for flash regions.
285 This option replaces older arm7_9 target commands that addressed
287 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
289 @*Configures what OpenOCD will do when gdb detaches from the daeman.
290 Default behaviour is <@var{resume}>
291 @item @b{gdb_memory_map} <@var{enable|disable}>
292 @cindex gdb_memory_map
293 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
294 requested. gdb will then know when to set hardware breakpoints, and program flash
295 using the gdb load command. @option{gdb_flash_program enable} (@xref{gdb_flash_program})
296 will also need enabling for flash programming to work.
297 Default behaviour is <@var{enable}>
298 @item @b{gdb_flash_program} <@var{enable|disable}>
299 @cindex gdb_flash_program
300 @anchor{gdb_flash_program}
301 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
302 vFlash packet is received.
303 Default behaviour is <@var{enable}>
306 @section JTAG interface configuration
309 @item @b{interface} <@var{name}>
311 @*Use the interface driver <@var{name}> to connect to the target. Currently supported
315 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
318 @item @b{amt_jtagaccel}
319 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
324 FTDI FT2232 based devices using either the open-source libftdi or the binary only
325 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
326 platform. The libftdi uses libusb, and should be portable to all systems that provide
331 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
335 ASIX PRESTO USB JTAG programmer.
339 usbprog is a freely programmable USB adapter.
343 Gateworks GW16012 JTAG programmer.
347 Segger jlink usb adapter
352 @item @b{jtag_speed} <@var{reset speed}>
354 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
355 speed. The actual effect of this option depends on the JTAG interface used.
357 The speed used during reset can be adjusted using setting jtag_speed during
358 pre_reset and post_reset events.
361 @item wiggler: maximum speed / @var{number}
362 @item ft2232: 6MHz / (@var{number}+1)
363 @item amt jtagaccel: 8 / 2**@var{number}
364 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
367 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
368 especially true for synthesized cores (-S).
370 @item @b{jtag_khz} <@var{reset speed kHz}>
372 @*Same as jtag_speed, except that the speed is specified in maximum kHz. If
373 the device can not support the rate asked for, or can not translate from
374 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
375 is not supported, then an error is reported.
377 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
379 @*The configuration of the reset signals available on the JTAG interface AND the target.
380 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
381 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
382 @option{srst_only} or @option{trst_and_srst}.
384 [@var{combination}] is an optional value specifying broken reset signal implementations.
385 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
386 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
387 that the system is reset together with the test logic (only hypothetical, I haven't
388 seen hardware with such a bug, and can be worked around).
389 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
390 The default behaviour if no option given is @option{separate}.
392 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
393 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
394 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
395 (default) and @option{srst_push_pull} for the system reset. These values only affect
396 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
398 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
400 @*Describes the devices that form the JTAG daisy chain, with the first device being
401 the one closest to TDO. The parameters are the length of the instruction register
402 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
403 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
404 The IDCODE instruction will in future be used to query devices for their JTAG
405 identification code. This line is the same for all ARM7 and ARM9 devices.
406 Other devices, like CPLDs, require different parameters. An example configuration
407 line for a Xilinx XC9500 CPLD would look like this:
409 jtag_device 8 0x01 0x0e3 0xfe
411 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
412 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
413 The IDCODE instruction is 0xfe.
415 @item @b{jtag_nsrst_delay} <@var{ms}>
416 @cindex jtag_nsrst_delay
417 @*How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
418 starting new JTAG operations.
419 @item @b{jtag_ntrst_delay} <@var{ms}>
420 @cindex jtag_ntrst_delay
421 @*Same @b{jtag_nsrst_delay}, but for nTRST
423 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
424 or on-chip features) keep a reset line asserted for some time after the external reset
428 @section parport options
431 @item @b{parport_port} <@var{number}>
433 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
434 the @file{/dev/parport} device
436 When using PPDEV to access the parallel port, use the number of the parallel port:
437 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
438 you may encounter a problem.
439 @item @b{parport_cable} <@var{name}>
440 @cindex parport_cable
441 @*The layout of the parallel port cable used to connect to the target.
442 Currently supported cables are
446 The original Wiggler layout, also supported by several clones, such
447 as the Olimex ARM-JTAG
450 Same as original wiggler except an led is fitted on D5.
451 @item @b{wiggler_ntrst_inverted}
452 @cindex wiggler_ntrst_inverted
453 Same as original wiggler except TRST is inverted.
454 @item @b{old_amt_wiggler}
455 @cindex old_amt_wiggler
456 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
457 version available from the website uses the original Wiggler layout ('@var{wiggler}')
460 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
461 program the Chameleon itself, not a connected target.
464 The Xilinx Parallel cable III.
467 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
468 This is also the layout used by the HollyGates design
469 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
472 The ST Parallel cable.
475 Same as original wiggler except SRST and TRST connections reversed and
476 TRST is also inverted.
479 Altium Universal JTAG cable.
481 @item @b{parport_write_on_exit} <@var{on|off}>
482 @cindex parport_write_on_exit
483 @*This will configure the parallel driver to write a known value to the parallel
484 interface on exiting OpenOCD
487 @section amt_jtagaccel options
489 @item @b{parport_port} <@var{number}>
491 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
492 @file{/dev/parport} device
494 @section ft2232 options
497 @item @b{ft2232_device_desc} <@var{description}>
498 @cindex ft2232_device_desc
499 @*The USB device description of the FTDI FT2232 device. If not specified, the FTDI
500 default value is used. This setting is only valid if compiled with FTD2XX support.
501 @item @b{ft2232_layout} <@var{name}>
502 @cindex ft2232_layout
503 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
504 signals. Valid layouts are
507 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
509 Amontec JTAGkey and JTAGkey-tiny
512 @item @b{olimex-jtag}
515 American Microsystems M5960
516 @item @b{evb_lm3s811}
517 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
518 SRST signals on external connector
522 Hitex STM32 Performance Stick
524 Tin Can Tools Flyswatter
525 @item @b{turtelizer2}
526 egnite Software turtelizer2
531 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
532 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
533 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
535 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
537 @item @b{ft2232_latency} <@var{ms}>
538 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
539 ft2232_read() fails to return the expected number of bytes. This can be caused by
540 USB communication delays and has proved hard to reproduce and debug. Setting the
541 FT2232 latency timer to a larger value increases delays for short USB packages but it
542 also reduces the risk of timeouts before receiving the expected number of bytes.
543 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
546 @section ep93xx options
547 @cindex ep93xx options
548 Currently, there are no options available for the ep93xx interface.
551 @section Target configuration
554 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
557 @*Defines a target that should be debugged. Currently supported types are:
572 If you want to use a target board that is not on this list, see Adding a new
575 Endianess may be @option{little} or @option{big}.
577 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
578 @cindex target_script
579 @*Event is one of the following:
580 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
581 @option{pre_resume} or @option{gdb_program_config}.
582 @option{post_reset} and @option{reset} will produce the same results.
584 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
585 <@var{backup}|@var{nobackup}>
587 @*Specifies a working area for the debugger to use. This may be used to speed-up
588 downloads to target memory and flash operations, or to perform otherwise unavailable
589 operations (some coprocessor operations on ARM7/9 systems, for example). The last
590 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
591 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
594 @subsection arm7tdmi options
595 @cindex arm7tdmi options
596 target arm7tdmi <@var{endianess}> <@var{jtag#}>
597 @*The arm7tdmi target definition requires at least one additional argument, specifying
598 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
599 The optional [@var{variant}] parameter has been removed in recent versions.
600 The correct feature set is determined at runtime.
602 @subsection arm720t options
603 @cindex arm720t options
604 ARM720t options are similar to ARM7TDMI options.
606 @subsection arm9tdmi options
607 @cindex arm9tdmi options
608 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
609 @option{arm920t}, @option{arm922t} and @option{arm940t}.
610 This enables the hardware single-stepping support found on these cores.
612 @subsection arm920t options
613 @cindex arm920t options
614 ARM920t options are similar to ARM9TDMI options.
616 @subsection arm966e options
617 @cindex arm966e options
618 ARM966e options are similar to ARM9TDMI options.
620 @subsection cortex_m3 options
621 @cindex cortex_m3 options
622 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
623 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
624 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
625 be detected and the normal reset behaviour used.
627 @subsection xscale options
628 @cindex xscale options
629 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
630 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
632 @section Flash configuration
633 @cindex Flash configuration
636 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
637 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
639 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
640 and <@var{bus_width}> bytes using the selected flash <driver>.
643 @subsection lpc2000 options
644 @cindex lpc2000 options
646 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
647 <@var{clock}> [@var{calc_checksum}]
648 @*LPC flashes don't require the chip and bus width to be specified. Additional
649 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
650 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
651 of the target this flash belongs to (first is 0), the frequency at which the core
652 is currently running (in kHz - must be an integral number), and the optional keyword
653 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
656 @subsection cfi options
659 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
660 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
661 @*CFI flashes require the number of the target they're connected to as an additional
662 argument. The CFI driver makes use of a working area (specified for the target)
663 to significantly speed up operation.
665 @var{chip_width} and @var{bus_width} are specified in bytes.
667 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
671 @subsection at91sam7 options
672 @cindex at91sam7 options
674 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
675 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
676 reading the chip-id and type.
678 @subsection str7 options
681 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
682 @*variant can be either STR71x, STR73x or STR75x.
684 @subsection str9 options
687 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
688 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
690 str9x flash_config 0 4 2 0 0x80000
692 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
694 @subsection str9 options (str9xpec driver)
696 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
697 @*Before using the flash commands the turbo mode will need enabling using str9xpec
698 @option{enable_turbo} <@var{num>.}
700 Only use this driver for locking/unlocking the device or configuring the option bytes.
701 Use the standard str9 driver for programming.
703 @subsection stellaris (LM3Sxxx) options
704 @cindex stellaris (LM3Sxxx) options
706 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
707 @*stellaris flash plugin only require the @var{target#}.
709 @subsection stm32x options
710 @cindex stm32x options
712 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
713 @*stm32x flash plugin only require the @var{target#}.
715 @subsection aduc702x options
716 @cindex aduc702x options
718 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
719 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
721 @section mFlash configuration
722 @cindex mFlash configuration
725 @item @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
726 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
728 @*Configures a mflash for <@var{soc}> host bank at <@var{base}>. <@var{chip_width}> and
729 <@var{bus_width}> are bytes order. Pin number format is dependent on host GPIO calling convention.
730 If WP or DPD pin was not used, write -1. Currently, mflash bank support s3c2440 and pxa270.
732 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
734 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
736 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
738 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
742 @chapter Target library
743 @cindex Target library
745 OpenOCD comes with a target configuration script library. These scripts can be
746 used as-is or serve as a starting point.
748 The target library is published together with the openocd executable and
749 the path to the target library is in the OpenOCD script search path.
750 Similarly there are example scripts for configuring the JTAG interface.
752 The command line below uses the example parport configuration scripts
753 that ship with OpenOCD, then configures the str710.cfg target and
754 finally issues the init and reset command. The communication speed
755 is set to 10kHz for reset and 8MHz for post reset.
759 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
763 To list the target scripts available:
766 $ ls /usr/local/lib/openocd/target
768 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
769 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
770 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
771 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
779 OpenOCD allows user interaction through a GDB server (default: port 3333),
780 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
781 is available from both the telnet interface and a GDB session. To issue commands to the
782 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
783 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
786 The TCL interface is used as a simplified RPC mechanism that feeds all the
787 input into the TCL interpreter and returns the output from the evaluation of
793 @item @b{sleep} <@var{msec}>
795 @*Wait for n milliseconds before resuming. Useful in connection with script files
796 (@var{script} command and @var{target_script} configuration).
800 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
802 @item @b{debug_level} [@var{n}]
805 @*Display or adjust debug level to n<0-3>
807 @item @b{fast} [@var{enable|disable}]
809 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
810 downloads and fast memory access will work if the JTAG interface isn't too fast and
811 the core doesn't run at a too low frequency. Note that this option only changes the default
812 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
815 The target specific "dangerous" optimisation tweaking options may come and go
816 as more robust and user friendly ways are found to ensure maximum throughput
817 and robustness with a minimum of configuration.
819 Typically the "fast enable" is specified first on the command line:
822 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
825 @item @b{log_output} <@var{file}>
827 @*Redirect logging to <file> (default: stderr)
829 @item @b{script} <@var{file}>
831 @*Execute commands from <file>
835 @subsection Target state handling
837 @item @b{poll} [@option{on}|@option{off}]
839 @*Poll the target for its current state. If the target is in debug mode, architecture
840 specific information about the current state is printed. An optional parameter
841 allows continuous polling to be enabled and disabled.
843 @item @b{halt} [@option{ms}]
845 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
846 Default [@option{ms}] is 5 seconds if no arg given.
847 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
848 will stop OpenOCD from waiting.
850 @item @b{wait_halt} [@option{ms}]
852 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
853 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
856 @item @b{resume} [@var{address}]
858 @*Resume the target at its current code position, or at an optional address.
859 OpenOCD will wait 5 seconds for the target to resume.
861 @item @b{step} [@var{address}]
863 @*Single-step the target at its current code position, or at an optional address.
865 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
867 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
869 With no arguments a "reset run" is executed
873 @*Let the target run.
876 @*Immediately halt the target (works only with certain configurations).
879 @*Immediately halt the target, and execute the reset script (works only with certain
884 @subsection Memory access commands
885 These commands allow accesses of a specific size to the memory system:
887 @item @b{mdw} <@var{addr}> [@var{count}]
889 @*display memory words
890 @item @b{mdh} <@var{addr}> [@var{count}]
892 @*display memory half-words
893 @item @b{mdb} <@var{addr}> [@var{count}]
895 @*display memory bytes
896 @item @b{mww} <@var{addr}> <@var{value}>
899 @item @b{mwh} <@var{addr}> <@var{value}>
901 @*write memory half-word
902 @item @b{mwb} <@var{addr}> <@var{value}>
906 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
909 @*Load image <@var{file}> to target memory at <@var{address}>
910 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
913 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
914 (binary) <@var{file}>.
915 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
917 @*Verify <@var{file}> against target memory starting at <@var{address}>.
918 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
921 @subsection Flash commands
922 @cindex Flash commands
924 @item @b{flash banks}
926 @*List configured flash banks
927 @item @b{flash info} <@var{num}>
929 @*Print info about flash bank <@option{num}>
930 @item @b{flash probe} <@var{num}>
932 @*Identify the flash, or validate the parameters of the configured flash. Operation
933 depends on the flash type.
934 @item @b{flash erase_check} <@var{num}>
935 @cindex flash erase_check
936 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
937 updates the erase state information displayed by @option{flash info}. That means you have
938 to issue an @option{erase_check} command after erasing or programming the device to get
940 @item @b{flash protect_check} <@var{num}>
941 @cindex flash protect_check
942 @*Check protection state of sectors in flash bank <num>.
943 @option{flash erase_sector} using the same syntax.
944 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
945 @cindex flash erase_sector
946 @anchor{flash erase_sector}
947 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
948 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
949 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
951 @item @b{flash erase_address} <@var{address}> <@var{length}>
952 @cindex flash erase_address
953 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
954 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
955 @cindex flash write_bank
956 @anchor{flash write_bank}
957 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
958 <@option{offset}> bytes from the beginning of the bank.
959 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
960 @cindex flash write_image
961 @anchor{flash write_image}
962 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
963 [@var{offset}] can be specified and the file [@var{type}] can be specified
964 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
965 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
966 if the @option{erase} parameter is given.
967 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
968 @cindex flash protect
969 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
970 <@var{last}> of @option{flash bank} <@var{num}>.
973 @subsection mFlash commands
974 @cindex mFlash commands
976 @item @b{mflash probe}
979 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
981 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
982 <@var{offset}> bytes from the beginning of the bank.
983 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
985 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
990 @section Target Commands
991 @cindex Target Commands
995 Pre "TCL" - many commands in OpenOCD where implemented as C functions. Post "TCL"
996 (Jim-Tcl to be more exact, June 2008) TCL became a bigger part of OpenOCD.
998 One of the biggest changes is the introduction of 'target specific'
999 commands. When every time you create a target, a special command name is
1000 created specifically for that target.
1001 For example - in TCL/TK - if you create a button (or any other screen object) you
1002 can specify various "button configuration parameters". One of those parameters is
1003 the "object cmd/name" [ In TK - this is referred to as the object path ]. Later
1004 you can use that 'path' as a command to modify the button, for example to make it
1005 "grey", or change the color. In effect, the "path" function is an 'object
1006 oriented command'. The TCL change in OpenOCD follows the same principle, you create
1007 a target, and a specific "targetname" command is created.
1009 There are two methods of creating a target:
1013 Using the old syntax (deprecated). Target names are autogenerated as:
1014 "target0", "target1", etc.;
1017 Using the new syntax, you can specify the name of the target.
1021 As most users will have a single JTAG target, and by default the command name will
1022 probably default to "target0", thus for reasons of simplicity the instructions below
1023 use the name "target0".
1025 @subsection Commands
1027 OpenOCD has the following 'target' or 'target-like' commands:
1031 @b{targets (plural)} - lists all known targets and a little bit of information about each
1032 target, most importantly the target *COMMAND*NAME* (it also lists the target number);
1035 @b{target (singular)} - used to create, configure list, etc the targets;
1038 @b{target0} - the command object for the first target. Unless you specified another name.
1042 @subsubsection Targets Command
1043 @cindex Targets Command
1044 The "targets" command has 2 functions:
1048 With a parameter, you can change the current command line target.
1050 NOTE: "with a parameter" is really only useful with 'multiple JTAG targets' not something
1051 you normally encounter (ie: If you had 2 arm chips - sharing the same JTAG chain).
1053 # using a target name.
1054 (gdb) mon targets target0
1055 # or a target by number.
1058 @cindex with a parameter
1060 Plain, without any parameter lists targets, for example:
1064 CmdName Type Endian ChainPos State
1065 -- ---------- ---------- ---------- -------- ----------
1066 0: target0 arm7tdmi little 0 halted
1072 in this example, a single target;
1074 target number 0 (1st column);
1076 the 'object name' is target0 (the default name);
1082 the position in the JTAG chain;
1084 and is currently halted.
1086 @cindex without any parameter
1089 @subsubsection Target Command
1090 @cindex Target Command
1092 The "target" command has the following options:
1098 target create CMDNAME TYPE ... config options ...
1101 argv[2] = the 'object command'
1102 (normally, target0, see (3) above)
1103 argv[3] = the target type, ie: arm7tdmi
1104 argv[4..N] = configuration parameters
1109 Lists all supported target types; ie: arm7tdmi, xscale, fericon, cortex-m3.
1110 The result TCL list of all known target types (and is human readable).
1114 Returns a TCL list of all known target commands (and is human readable).
1118 foreach t [target names] {
1119 puts [format "Target: %s\n" $t]
1125 Returns the TCL command name of the current target.
1129 set ct [target current]
1130 set t [$ct cget -type]
1132 puts "Current target name is: $ct, and is a: $t"
1135 target number <VALUE>
1137 Returns the TCL command name of the specified target.
1141 set thename [target number $x]
1142 puts [format "Target %d is: %s\n" $x $thename]
1144 For instance, assuming the defaults
1148 Would return 'target0' (or whatever you called it)
1152 Returns the larget+1 target number.
1156 set c [target count]
1157 for { set x 0 } { $x < $c } { incr x } {
1158 # Assuming you have this function..
1159 print_target_details $x
1164 @subsubsection Target0 Command
1165 @cindex Target0 Command
1166 The "target0" command (the "Target Object" command):
1168 Once a target is 'created' a command object by that targets name is created, for example
1170 target create BiGRed arm7tdmi -endian little -chain-position 3
1173 Would create a [case sensitive] "command" BiGRed
1175 If you use the old [deprecated] syntax, the name is automatically
1176 generated and is in the form:
1178 target0, target1, target2, target3, ... etc.
1181 @subsubsection Target CREATE, CONFIGURE and CGET Options Command
1182 @cindex Target CREATE, CONFIGURE and CGET Options Command
1185 target create CMDNAME TYPE [configure-options]
1186 CMDNAME configure [configure-options]
1187 CMDNAME cget [configure-options]
1191 In the 'create' case, one is creating the target and can specify any
1192 number of configuration parameters.
1194 In the 'CMDNAME configure' case, one can change the setting [Not all things can, or should be changed].
1196 In the 'CMDNAME cget' case, the goal is to query the target for a
1197 specific configuration option.
1200 In the above, the "default" name target0 is 'target0'.
1204 From the (gdb) prompt, one can type this:
1207 (gdb) mon target0 configure -endian big
1210 And change target0 to 'big-endian'. This is a contrived example,
1211 specifically for this document - don't expect changing endian
1212 'mid-operation' to work you should set the endian at creation.
1214 Known options [30/august/2008] are:
1217 [Mandatory 'create' Options]
1220 type arm7tdmi|arm720|etc ...
1222 chain-position NUMBER
1230 event EVENTNAME "tcl-action"
1240 work-area-backup BOOLEAN
1243 Hint: To get a list of available options, try this:
1245 (gdb) mon target0 cget -BLAHBLAHBLAH
1248 the above causes an error - and a helpful list of valid options.
1250 One can query any of the above options at run time, for example:
1252 (gdb) mon target0 cget -OPTION [param]
1258 # For all targets...
1259 set c [target count]
1260 for { set x 0 } { $x < $c } { incr x ] {
1261 set n [target number $x]
1262 set t [$n cget -type]
1263 set e [$n cget -endian]
1264 puts [format "%d: %s, %s, endian: %s\n" $x $n $t $n]
1271 0: pic32chip, mips_m4k, endain: little
1272 1: arm7, arm7tdmi, endian: big
1273 2: blackfin, bf534, endian: little
1276 Notice the above example is not target0, target1, target2 Why? Because in this contrived multi-target example -
1277 more human understandable target names might be helpful.
1279 For example these two are the same:
1282 (gdb) mon blackfin configure -event FOO {puts "Hi mom"}
1288 (gdb) mon [target number 2] configure -event FOO {puts "Hi mom"}
1291 In the second case, we use [] to get the command name of target #2, in this contrived example - it is "blackfin".
1293 Two important configuration options are:
1295 "-event" and "-reset"
1297 The "-reset" option specifies what should happen when the chip is reset, for example should it 'halt', 're-init',
1300 The "-event" option less you specify a TCL command to occur when a specific event occurs.
1302 @subsection Target Events
1303 @cindex Target Events
1305 @subsubsection Overview
1307 At various points in time - certain 'target' events happen. You can create a custom event action to occur at that time.
1308 For example - after reset, the PLLs and CLOCKs may need to be reconfigured, or perhaps the SDRAM needs to be re-initialized.
1309 Often the easiest way to do that is to create a simple script file containing the series of (mww [poke memory]) commands
1310 you would type by hand, to reconfigure the target clocks. You could specify the "event action" like this:
1313 (gdb) mon target0 configure -event reset-init "script cfg.clocks"
1316 In the above example, when the event "reset-init" occurs, the "action-string" will be evaluated as if you typed it at the
1319 @item @b{Option1} - The simple approach (above) is to create a script file with lots of "mww" (memory write word) commands
1320 to configure your targets clocks and/or external memory;
1321 @item @b{Option2} - You can instead create a fancy TCL procedure and invoke that procedure instead of sourcing a file [In fact,
1322 "script" is a TCL procedure that loads a file].
1325 @subsubsection Details
1327 There are many events one could use, to get a current list of events type the following invalid command, you'll get a helpful
1328 "runtime error" message, see below [list valid as of 30/august/2008]:
1331 (gdb) mon target0 cget -event FAFA
1332 Runtime error, file "../../../openocd23/src/helper/command.c", line 433:
1333 -event: Unknown: FAFA, try one of: old-pre_reset,
1334 old-gdb_program_config, old-post_reset, halted,
1335 resumed, resume-start, resume-end, reset-start,
1336 reset-assert-pre, reset-assert-post,
1337 reset-deassert-pre, reset-deassert-post,
1338 reset-halt-pre, reset-halt-post, reset-wait-pre,
1339 reset-wait-post, reset-init, reset-end,
1340 examine-start, examine-end, debug-halted,
1341 debug-resumed, gdb-attach, gdb-detach,
1342 gdb-flash-write-start, gdb-flash-write-end,
1343 gdb-flash-erase-start, gdb-flash-erase-end,
1344 resume-start, resume-ok, or resume-end
1347 NOTE: The event-names "old-*" are deprecated and exist only to help old scripts continue to function, and the old "target_script"
1348 command to work. Please do not rely on them.
1350 These are some other important names:
1352 @item gdb-flash-erase-start
1353 @item gdb-flash-erase-end
1354 @item gdb-flash-write-start
1355 @item gdb-flash-write-end
1358 These occur when GDB/OpenOCD attempts to erase & program the FLASH chip via GDB. For example - some PCBs may have a simple GPIO
1359 pin that acts like a "flash write protect" you might need to write a script that disables "write protect".
1361 To get a list of current 'event actions', type the following command:
1364 (gdb) mon target0 eventlist
1366 Event actions for target (0) target0
1369 ------------------------- | ----------------------------------------
1370 old-post_reset | script event/sam7x256_reset.script
1373 Here is a simple example for all targets:
1376 (gdb) mon foreach x [target names] { $x eventlist }
1379 The above uses some TCL tricks:
1381 @item foreach VARIABLE LIST BODY
1382 @item to generate the list, we use [target names]
1383 @item the BODY, contains $x - the loop variable and expands to the target specific name
1386 Recalling the earlier discussion - the "object command" there are other things you can
1387 do besides "configure" the target.
1389 Note: Many of these commands exist as "global" commands, and they also exist as target
1390 specific commands. For example, the "mww" (memory write word) operates on the current
1391 target if you have more then 1 target, you must switch. In contrast to the normal
1392 commands, these commands operate on the specific target. For example, the command "mww"
1393 writes data to the *current* command line target.
1395 Often, you have only a single target - but if you have multiple targets (ie: a PIC32
1396 and an at91sam7 - your reset-init scripts might get a bit more complicated, ie: you must
1397 specify which of the two chips you want to write to. Writing 'pic32' clock configuration
1398 to an at91sam7 does not work).
1400 The commands are [as of 30/august/2008]:
1402 TNAME mww ADDRESS VALUE
1403 TNAME mwh ADDRESS VALUE
1404 TNAME mwb ADDRESS VALUE
1405 Write(poke): 32, 16, 8bit values to memory.
1407 TNAME mdw ADDRESS VALUE
1408 TNAME mdh ADDRESS VALUE
1409 TNAME mdb ADDRESS VALUE
1410 Human 'hexdump' with ascii 32, 16, 8bit values
1412 TNAME mem2array [see mem2array command]
1413 TNAME array2mem [see array2mem command]
1416 Returns the current state of the target.
1419 See 'advanced target reset'
1421 See 'advanced target reset'
1423 See 'advanced target reset'
1424 TNAME reset deassert
1425 See 'advanced target reset'
1427 See 'advanced target reset'
1428 TNAME waitstate STATENAME
1429 See 'advanced target reset'
1433 @section Target Specific Commands
1434 @cindex Target Specific Commands
1436 @subsection AT91SAM7 specific commands
1437 @cindex AT91SAM7 specific commands
1438 The flash configuration is deduced from the chip identification register. The flash
1439 controller handles erases automatically on a page (128/265 byte) basis so erase is
1440 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
1441 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
1442 that can be erased separatly. Only an EraseAll command is supported by the controller
1443 for each flash plane and this is called with
1445 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
1446 @*bulk erase flash planes first_plane to last_plane.
1447 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
1448 @cindex at91sam7 gpnvm
1449 @*set or clear a gpnvm bit for the processor
1452 @subsection STR9 specific commands
1453 @cindex STR9 specific commands
1454 These are flash specific commands when using the str9xpec driver.
1456 @item @b{str9xpec enable_turbo} <@var{num}>
1457 @cindex str9xpec enable_turbo
1458 @*enable turbo mode, simply this will remove the str9 from the chain and talk
1459 directly to the embedded flash controller.
1460 @item @b{str9xpec disable_turbo} <@var{num}>
1461 @cindex str9xpec disable_turbo
1462 @*restore the str9 into jtag chain.
1463 @item @b{str9xpec lock} <@var{num}>
1464 @cindex str9xpec lock
1465 @*lock str9 device. The str9 will only respond to an unlock command that will
1467 @item @b{str9xpec unlock} <@var{num}>
1468 @cindex str9xpec unlock
1469 @*unlock str9 device.
1470 @item @b{str9xpec options_read} <@var{num}>
1471 @cindex str9xpec options_read
1472 @*read str9 option bytes.
1473 @item @b{str9xpec options_write} <@var{num}>
1474 @cindex str9xpec options_write
1475 @*write str9 option bytes.
1478 @subsection STR9 configuration
1479 @cindex STR9 configuration
1481 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
1482 <@var{BBADR}> <@var{NBBADR}>
1483 @cindex str9x flash_config
1484 @*Configure str9 flash controller.
1486 eg. str9x flash_config 0 4 2 0 0x80000
1488 BBSR - Boot Bank Size register
1489 NBBSR - Non Boot Bank Size register
1490 BBADR - Boot Bank Start Address register
1491 NBBADR - Boot Bank Start Address register
1495 @subsection STR9 option byte configuration
1496 @cindex STR9 option byte configuration
1498 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1499 @cindex str9xpec options_cmap
1500 @*configure str9 boot bank.
1501 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1502 @cindex str9xpec options_lvdthd
1503 @*configure str9 lvd threshold.
1504 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1505 @cindex str9xpec options_lvdsel
1506 @*configure str9 lvd source.
1507 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1508 @cindex str9xpec options_lvdwarn
1509 @*configure str9 lvd reset warning source.
1512 @subsection STM32x specific commands
1513 @cindex STM32x specific commands
1515 These are flash specific commands when using the stm32x driver.
1517 @item @b{stm32x lock} <@var{num}>
1519 @*lock stm32 device.
1520 @item @b{stm32x unlock} <@var{num}>
1521 @cindex stm32x unlock
1522 @*unlock stm32 device.
1523 @item @b{stm32x options_read} <@var{num}>
1524 @cindex stm32x options_read
1525 @*read stm32 option bytes.
1526 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1527 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1528 @cindex stm32x options_write
1529 @*write stm32 option bytes.
1530 @item @b{stm32x mass_erase} <@var{num}>
1531 @cindex stm32x mass_erase
1532 @*mass erase flash memory.
1535 @subsection Stellaris specific commands
1536 @cindex Stellaris specific commands
1538 These are flash specific commands when using the Stellaris driver.
1540 @item @b{stellaris mass_erase} <@var{num}>
1541 @cindex stellaris mass_erase
1542 @*mass erase flash memory.
1546 @section Architecture Specific Commands
1547 @cindex Architecture Specific Commands
1549 @subsection ARMV4/5 specific commands
1550 @cindex ARMV4/5 specific commands
1552 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1553 or Intel XScale (XScale isn't supported yet).
1555 @item @b{armv4_5 reg}
1557 @*Display a list of all banked core registers, fetching the current value from every
1558 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1560 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1561 @cindex armv4_5 core_mode
1562 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1563 The target is resumed in the currently set @option{core_mode}.
1566 @subsection ARM7/9 specific commands
1567 @cindex ARM7/9 specific commands
1569 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1570 ARM920t or ARM926EJ-S.
1572 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1573 @cindex arm7_9 dbgrq
1574 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
1575 safe for all but ARM7TDMI--S cores (like Philips LPC).
1576 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1577 @cindex arm7_9 fast_memory_access
1578 @anchor{arm7_9 fast_memory_access}
1579 @*Allow OpenOCD to read and write memory without checking completion of
1580 the operation. This provides a huge speed increase, especially with USB JTAG
1581 cables (FT2232), but might be unsafe if used with targets running at a very low
1582 speed, like the 32kHz startup clock of an AT91RM9200.
1583 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1584 @cindex arm7_9 dcc_downloads
1585 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1586 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1587 unsafe, especially with targets running at a very low speed. This command was introduced
1588 with OpenOCD rev. 60.
1591 @subsection ARM720T specific commands
1592 @cindex ARM720T specific commands
1595 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1596 @cindex arm720t cp15
1597 @*display/modify cp15 register <@option{num}> [@option{value}].
1598 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1599 @cindex arm720t md<bhw>_phys
1600 @*Display memory at physical address addr.
1601 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1602 @cindex arm720t mw<bhw>_phys
1603 @*Write memory at physical address addr.
1604 @item @b{arm720t virt2phys} <@var{va}>
1605 @cindex arm720t virt2phys
1606 @*Translate a virtual address to a physical address.
1609 @subsection ARM9TDMI specific commands
1610 @cindex ARM9TDMI specific commands
1613 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1614 @cindex arm9tdmi vector_catch
1615 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1616 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1617 @option{irq} @option{fiq}.
1619 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1622 @subsection ARM966E specific commands
1623 @cindex ARM966E specific commands
1626 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1627 @cindex arm966e cp15
1628 @*display/modify cp15 register <@option{num}> [@option{value}].
1631 @subsection ARM920T specific commands
1632 @cindex ARM920T specific commands
1635 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1636 @cindex arm920t cp15
1637 @*display/modify cp15 register <@option{num}> [@option{value}].
1638 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1639 @cindex arm920t cp15i
1640 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1641 @item @b{arm920t cache_info}
1642 @cindex arm920t cache_info
1643 @*Print information about the caches found. This allows you to see if your target
1644 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1645 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1646 @cindex arm920t md<bhw>_phys
1647 @*Display memory at physical address addr.
1648 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1649 @cindex arm920t mw<bhw>_phys
1650 @*Write memory at physical address addr.
1651 @item @b{arm920t read_cache} <@var{filename}>
1652 @cindex arm920t read_cache
1653 @*Dump the content of ICache and DCache to a file.
1654 @item @b{arm920t read_mmu} <@var{filename}>
1655 @cindex arm920t read_mmu
1656 @*Dump the content of the ITLB and DTLB to a file.
1657 @item @b{arm920t virt2phys} <@var{va}>
1658 @cindex arm920t virt2phys
1659 @*Translate a virtual address to a physical address.
1662 @subsection ARM926EJS specific commands
1663 @cindex ARM926EJS specific commands
1666 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1667 @cindex arm926ejs cp15
1668 @*display/modify cp15 register <@option{num}> [@option{value}].
1669 @item @b{arm926ejs cache_info}
1670 @cindex arm926ejs cache_info
1671 @*Print information about the caches found.
1672 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1673 @cindex arm926ejs md<bhw>_phys
1674 @*Display memory at physical address addr.
1675 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1676 @cindex arm926ejs mw<bhw>_phys
1677 @*Write memory at physical address addr.
1678 @item @b{arm926ejs virt2phys} <@var{va}>
1679 @cindex arm926ejs virt2phys
1680 @*Translate a virtual address to a physical address.
1684 @section Debug commands
1685 @cindex Debug commands
1686 The following commands give direct access to the core, and are most likely
1687 only useful while debugging OpenOCD.
1689 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1690 @cindex arm7_9 write_xpsr
1691 @*Immediately write either the current program status register (CPSR) or the saved
1692 program status register (SPSR), without changing the register cache (as displayed
1693 by the @option{reg} and @option{armv4_5 reg} commands).
1694 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1695 <@var{0=cpsr},@var{1=spsr}>
1696 @cindex arm7_9 write_xpsr_im8
1697 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1698 operation (similar to @option{write_xpsr}).
1699 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1700 @cindex arm7_9 write_core_reg
1701 @*Write a core register, without changing the register cache (as displayed by the
1702 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1703 encoding of the [M4:M0] bits of the PSR.
1707 @section JTAG commands
1708 @cindex JTAG commands
1710 @item @b{scan_chain}
1712 @*Print current scan chain configuration.
1713 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1715 @*Toggle reset lines.
1716 @item @b{endstate} <@var{tap_state}>
1718 @*Finish JTAG operations in <@var{tap_state}>.
1719 @item @b{runtest} <@var{num_cycles}>
1721 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
1722 @item @b{statemove} [@var{tap_state}]
1724 @*Move to current endstate or [@var{tap_state}]
1725 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1727 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1728 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1730 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1731 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1732 @cindex verify_ircapture
1733 @*Verify value captured during Capture-IR. Default is enabled.
1734 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1736 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1737 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1739 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1743 @section Target Requests
1744 @cindex Target Requests
1745 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1746 See libdcc in the contrib dir for more details.
1748 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1749 @cindex target_request debugmsgs
1750 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1753 @node Sample Scripts
1754 @chapter Sample Scripts
1757 This page shows how to use the target library.
1759 The configuration script can be divided in the following section:
1761 @item daemon configuration
1763 @item jtag scan chain
1764 @item target configuration
1765 @item flash configuration
1768 Detailed information about each section can be found at OpenOCD configuration.
1770 @section AT91R40008 example
1771 @cindex AT91R40008 example
1772 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1773 the CPU upon startup of the OpenOCD daemon.
1775 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1779 @node GDB and OpenOCD
1780 @chapter GDB and OpenOCD
1781 @cindex GDB and OpenOCD
1782 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1783 to debug remote targets.
1785 @section Connecting to gdb
1786 @cindex Connecting to gdb
1787 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
1788 known bug where it produces bogus memory access errors, which has since
1789 been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
1792 A connection is typically started as follows:
1794 target remote localhost:3333
1796 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1798 To see a list of available OpenOCD commands type @option{monitor help} on the
1801 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1802 to be sent by the gdb server (openocd) to gdb. Typical information includes
1803 packet size and device memory map.
1805 Previous versions of OpenOCD required the following gdb options to increase
1806 the packet size and speed up gdb communication.
1808 set remote memory-write-packet-size 1024
1809 set remote memory-write-packet-size fixed
1810 set remote memory-read-packet-size 1024
1811 set remote memory-read-packet-size fixed
1813 This is now handled in the @option{qSupported} PacketSize.
1815 @section Programming using gdb
1816 @cindex Programming using gdb
1818 By default the target memory map is sent to gdb, this can be disabled by
1819 the following OpenOCD config option:
1821 gdb_memory_map disable
1823 For this to function correctly a valid flash config must also be configured
1824 in OpenOCD. For faster performance you should also configure a valid
1827 Informing gdb of the memory map of the target will enable gdb to protect any
1828 flash area of the target and use hardware breakpoints by default. This means
1829 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1830 using a memory map. @xref{gdb_breakpoint_override}
1832 To view the configured memory map in gdb, use the gdb command @option{info mem}
1833 All other unasigned addresses within gdb are treated as RAM.
1835 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1836 this can be changed to the old behaviour by using the following gdb command.
1838 set mem inaccessible-by-default off
1841 If @option{gdb_flash_program enable} is also used, gdb will be able to
1842 program any flash memory using the vFlash interface.
1844 gdb will look at the target memory map when a load command is given, if any
1845 areas to be programmed lie within the target flash area the vFlash packets
1848 If the target needs configuring before gdb programming, a script can be executed.
1850 target_script 0 gdb_program_config config.script
1853 To verify any flash programming the gdb command @option{compare-sections}
1856 @node TCL and OpenOCD
1857 @chapter TCL and OpenOCD
1858 @cindex TCL and OpenOCD
1859 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1862 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1864 The command and file interfaces are fairly straightforward, while the network
1865 port is geared toward intergration with external clients. A small example
1866 of an external TCL script that can connect to openocd is shown below.
1869 # Simple tcl client to connect to openocd
1870 puts "Use empty line to exit"
1871 set fo [socket 127.0.0.1 6666]
1872 puts -nonewline stdout "> "
1874 while {[gets stdin line] >= 0} {
1875 if {$line eq {}} break
1880 puts -nonewline stdout "> "
1886 This script can easily be modified to front various GUIs or be a sub
1887 component of a larger framework for control and interaction.
1890 @node TCL scripting API
1891 @chapter TCL scripting API
1892 @cindex TCL scripting API
1895 The commands are stateless. E.g. the telnet command line has a concept
1896 of currently active target, the Tcl API proc's take this sort of state
1897 information as an argument to each proc.
1899 There are three main types of return values: single value, name value
1900 pair list and lists.
1902 Name value pair. The proc 'foo' below returns a name/value pair
1908 > set foo(you) Oyvind
1909 > set foo(mouse) Micky
1910 > set foo(duck) Donald
1918 me Duane you Oyvind mouse Micky duck Donald
1920 Thus, to get the names of the associative array is easy:
1922 foreach { name value } [set foo] {
1923 puts "Name: $name, Value: $value"
1927 Lists returned must be relatively small. Otherwise a range
1928 should be passed in to the proc in question.
1930 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1931 is the low level API upon which "flash banks" is implemented.
1933 OpenOCD commands can consist of two words, e.g. "flash banks". The
1934 startup.tcl "unknown" proc will translate this into a tcl proc
1935 called "flash_banks".
1939 @chapter Deprecated/Removed Commands
1940 @cindex Deprecated/Removed Commands
1941 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1944 @item @b{load_binary}
1946 @*use @option{load_image} command with same args. @xref{load_image}
1949 @*@option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
1950 always does a @option{reset run} when passed no arguments.
1951 @item @b{dump_binary}
1953 @*use @option{dump_image} command with same args. @xref{dump_image}
1954 @item @b{flash erase}
1956 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}
1957 @item @b{flash write}
1959 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}
1960 @item @b{flash write_binary}
1961 @cindex flash write_binary
1962 @*use @option{flash write_bank} command with same args
1963 @item @b{arm7_9 fast_writes}
1964 @cindex arm7_9 fast_writes
1965 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}
1966 @item @b{flash auto_erase}
1967 @cindex flash auto_erase
1968 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}
1969 @item @b{daemon_startup}
1970 @cindex daemon_startup
1971 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
1972 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1973 and @option{target cortex_m3 little reset_halt 0}.
1974 @item @b{arm7_9 sw_bkpts}
1975 @cindex arm7_9 sw_bkpts
1976 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}
1977 @item @b{arm7_9 force_hw_bkpts}
1978 @cindex arm7_9 force_hw_bkpts
1979 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
1980 for flash if the gdb memory map has been set up(default when flash is declared in
1981 target configuration). @xref{gdb_breakpoint_override}
1982 @item @b{run_and_halt_time}
1983 @cindex run_and_halt_time
1984 @*This command has been removed for simpler reset behaviour, it can be simulated with the
1997 @item OpenOCD complains about a missing cygwin1.dll.
1999 Make sure you have Cygwin installed, or at least a version of OpenOCD that
2000 claims to come with all the necessary dlls. When using Cygwin, try launching
2001 OpenOCD from the Cygwin shell.
2003 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
2004 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
2005 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
2007 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
2008 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
2009 software breakpoints consume one of the two available hardware breakpoints.
2011 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
2012 and works sometimes fine.
2014 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
2015 clock at the time you're programming the flash. If you've specified the crystal's
2016 frequency, make sure the PLL is disabled, if you've specified the full core speed
2017 (e.g. 60MHz), make sure the PLL is enabled.
2019 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
2020 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
2021 out while waiting for end of scan, rtck was disabled".
2023 Make sure your PC's parallel port operates in EPP mode. You might have to try several
2024 settings in your PC BIOS (ECP, EPP, and different versions of those).
2026 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
2027 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
2028 memory read caused data abort".
2030 The errors are non-fatal, and are the result of GDB trying to trace stack frames
2031 beyond the last valid frame. It might be possible to prevent this by setting up
2032 a proper "initial" stack frame, if you happen to know what exactly has to
2033 be done, feel free to add this here.
2035 @item I get the following message in the OpenOCD console (or log file):
2036 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
2038 This warning doesn't indicate any serious problem, as long as you don't want to
2039 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
2040 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
2041 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
2042 independently. With this setup, it's not possible to halt the core right out of
2043 reset, everything else should work fine.
2045 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
2046 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
2047 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
2048 quit with an error message. Is there a stability issue with OpenOCD?
2050 No, this is not a stability issue concerning OpenOCD. Most users have solved
2051 this issue by simply using a self-powered USB hub, which they connect their
2052 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
2053 supply stable enough for the Amontec JTAGkey to be operated.
2055 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
2056 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
2057 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
2058 What does that mean and what might be the reason for this?
2060 First of all, the reason might be the USB power supply. Try using a self-powered
2061 hub instead of a direct connection to your computer. Secondly, the error code 4
2062 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
2063 chip ran into some sort of error - this points us to a USB problem.
2065 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
2066 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
2067 What does that mean and what might be the reason for this?
2069 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
2070 has closed the connection to OpenOCD. This might be a GDB issue.
2072 @item In the configuration file in the section where flash device configurations
2073 are described, there is a parameter for specifying the clock frequency for
2074 LPC2000 internal flash devices (e.g.
2075 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
2076 which must be specified in kilohertz. However, I do have a quartz crystal of a
2077 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
2078 Is it possible to specify real numbers for the clock frequency?
2080 No. The clock frequency specified here must be given as an integral number.
2081 However, this clock frequency is used by the In-Application-Programming (IAP)
2082 routines of the LPC2000 family only, which seems to be very tolerant concerning
2083 the given clock frequency, so a slight difference between the specified clock
2084 frequency and the actual clock frequency will not cause any trouble.
2086 @item Do I have to keep a specific order for the commands in the configuration file?
2088 Well, yes and no. Commands can be given in arbitrary order, yet the devices
2089 listed for the JTAG scan chain must be given in the right order (jtag_device),
2090 with the device closest to the TDO-Pin being listed first. In general,
2091 whenever objects of the same type exist which require an index number, then
2092 these objects must be given in the right order (jtag_devices, targets and flash
2093 banks - a target references a jtag_device and a flash bank references a target).
2095 @item Sometimes my debugging session terminates with an error. When I look into the
2096 log file, I can see these error messages: Error: arm7_9_common.c:561
2097 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP