1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * Building OpenOCD:: Building OpenOCD From SVN
65 * JTAG Hardware Dongles:: JTAG Hardware Dongles
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * About JIM-Tcl:: About JIM-Tcl
70 * Daemon Configuration:: Daemon Configuration
71 * Interface - Dongle Configuration:: Interface - Dongle Configuration
72 * Reset Configuration:: Reset Configuration
73 * TAP Declaration:: TAP Declaration
74 * CPU Configuration:: CPU Configuration
75 * Flash Commands:: Flash Commands
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 The ``Building From Source'' section provides instructions to retrieve
177 and and build the latest version of the OpenOCD source code.
178 @xref{Building OpenOCD}.
180 Developers that want to contribute patches to the OpenOCD system are
181 @b{strongly} encouraged to base their work off of the most recent trunk
182 revision. Patches created against older versions may require additional
183 work from their submitter in order to be updated for newer releases.
185 @section Doxygen Developer Manual
187 During the development of the 0.2.0 release, the OpenOCD project began
188 providing a Doxygen reference manual. This document contains more
189 technical information about the software internals, development
190 processes, and similar documentation:
192 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
194 This document is a work-in-progress, but contributions would be welcome
195 to fill in the gaps. All of the source files are provided in-tree,
196 listed in the Doxyfile configuration in the top of the repository trunk.
198 @section OpenOCD Developer Mailing List
200 The OpenOCD Developer Mailing List provides the primary means of
201 communication between developers:
203 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
205 All drivers developers are enouraged to also subscribe to the list of
206 SVN commits to keep pace with the ongoing changes:
208 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
211 @node Building OpenOCD
212 @chapter Building OpenOCD
215 @section Pre-Built Tools
216 If you are interested in getting actual work done rather than building
217 OpenOCD, then check if your interface supplier provides binaries for
218 you. Chances are that that binary is from some SVN version that is more
219 stable than SVN trunk where bleeding edge development takes place.
221 @section Packagers Please Read!
223 You are a @b{PACKAGER} of OpenOCD if you
226 @item @b{Sell dongles} and include pre-built binaries
227 @item @b{Supply tools} i.e.: A complete development solution
228 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
229 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
232 As a @b{PACKAGER}, you will experience first reports of most issues.
233 When you fix those problems for your users, your solution may help
234 prevent hundreds (if not thousands) of other questions from other users.
236 If something does not work for you, please work to inform the OpenOCD
237 developers know how to improve the system or documentation to avoid
238 future problems, and follow-up to help us ensure the issue will be fully
239 resolved in our future releases.
241 That said, the OpenOCD developers would also like you to follow a few
245 @item Send patches, including config files, upstream.
246 @item Always build with printer ports enabled.
247 @item Use libftdi + libusb for FT2232 support.
250 @section Building From Source
252 You can download the current SVN version with an SVN client of your choice from the
253 following repositories:
255 @uref{svn://svn.berlios.de/openocd/trunk}
259 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
261 Using the SVN command line client, you can use the following command to fetch the
262 latest version (make sure there is no (non-svn) directory called "openocd" in the
266 svn checkout svn://svn.berlios.de/openocd/trunk openocd
269 If you prefer GIT based tools, the @command{git-svn} package works too:
272 git svn clone -s svn://svn.berlios.de/openocd
275 Building OpenOCD from a repository requires a recent version of the
276 GNU autotools (autoconf >= 2.59 and automake >= 1.9).
277 For building on Windows,
278 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
279 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
280 paths, resulting in obscure dependency errors (This is an observation I've gathered
281 from the logs of one user - correct me if I'm wrong).
283 You further need the appropriate driver files, if you want to build support for
284 a FTDI FT2232 based interface:
287 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
288 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}),
289 or the Amontec version (from @uref{http://www.amontec.com}),
290 for easier support of JTAGkey's vendor and product IDs.
293 libftdi is supported under Windows. Do not use versions earlier than 0.14.
294 To use the newer FT2232H chips, supporting RTCK and USB high speed (480 Mbps),
295 you need libftdi version 0.16 or newer.
297 Some people say that FTDI's libftd2xx code provides better performance.
298 However, it is binary-only, while OpenOCD is licenced according
299 to GNU GPLv2 without any exceptions.
300 That means that @emph{distributing} copies of OpenOCD built with
301 the FTDI code would violate the OpenOCD licensing terms.
302 You may, however, build such copies for personal use.
304 To build OpenOCD (on both Linux and Cygwin), use the following commands:
310 Bootstrap generates the configure script, and prepares building on your system.
313 ./configure [options, see below]
316 Configure generates the Makefiles used to build OpenOCD.
323 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
325 The configure script takes several options, specifying which JTAG interfaces
326 should be included (among other things):
330 @option{--enable-parport} - Enable building the PC parallel port driver.
332 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
334 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
336 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
338 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
340 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
342 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
344 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
346 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
348 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
350 @option{--enable-ft2232_ftd2xx} - Support FT2232-family chips using
351 the closed-source library from FTDICHIP.COM
352 (result not for re-distribution).
354 @option{--enable-ft2232_libftdi} - Support FT2232-family chips using
355 a GPL'd ft2232 support library (result OK for re-distribution).
357 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
358 give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
360 @option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
361 on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
363 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static.
364 Specifies how the FTDICHIP.COM libftd2xx driver should be linked.
365 Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}.
366 The 'shared' value is supported, however you must manually install the required
367 header files and shared libraries in an appropriate place.
369 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
371 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
373 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
375 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
377 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
379 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
381 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
383 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
385 @option{--enable-dummy} - Enable building the dummy port driver.
388 @section Parallel Port Dongles
390 If you want to access the parallel port using the PPDEV interface you have to specify
391 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
392 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
393 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
395 The same is true for the @option{--enable-parport_giveio} option, you have to
396 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
398 @section FT2232C Based USB Dongles
400 There are 2 methods of using the FTD2232, either (1) using the
401 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
402 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster,
403 which is the motivation for supporting it even though its licensing
404 restricts it to non-redistributable OpenOCD binaries, and it is
405 not available for all operating systems used with OpenOCD.
407 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
408 TAR.GZ file. You must unpack them ``some where'' convient. As of this
409 writing FTDICHIP does not supply means to install these
410 files ``in an appropriate place''.
411 As a result, there are two
412 ``./configure'' options that help.
414 Below is an example build process:
417 @item Check out the latest version of ``openocd'' from SVN.
419 @item If you are using the FTDICHIP.COM driver, download
420 and unpack the Windows or Linux FTD2xx drivers
421 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
422 If you are using the libftdi driver, install that package
423 (e.g. @command{apt-get install libftdi} on systems with APT).
426 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents
427 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
430 @item Configure with options resembling the following.
433 @item Cygwin FTDICHIP solution:
435 ./configure --prefix=/home/duane/mytools \
436 --enable-ft2232_ftd2xx \
437 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
440 @item Linux FTDICHIP solution:
442 ./configure --prefix=/home/duane/mytools \
443 --enable-ft2232_ftd2xx \
444 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
447 @item Cygwin/Linux LIBFTDI solution ... assuming that
449 @item For Windows -- that the Windows port of LIBUSB is in place.
450 @item For Linux -- that libusb has been built/installed and is in place.
451 @item That libftdi has been built and installed (relies on libusb).
454 Then configure the libftdi solution like this:
457 ./configure --prefix=/home/duane/mytools \
458 --enable-ft2232_libftdi
462 @item Then just type ``make'', and perhaps ``make install''.
466 @section Miscellaneous Configure Options
470 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
472 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
475 @option{--enable-release} - Enable building of an OpenOCD release, generally
476 this is for developers. It simply omits the svn version string when the
477 openocd @option{-v} is executed.
480 @node JTAG Hardware Dongles
481 @chapter JTAG Hardware Dongles
490 Defined: @b{dongle}: A small device that plugins into a computer and serves as
491 an adapter .... [snip]
493 In the OpenOCD case, this generally refers to @b{a small adapater} one
494 attaches to your computer via USB or the Parallel Printer Port. The
495 execption being the Zylin ZY1000 which is a small box you attach via
496 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
497 require any drivers to be installed on the developer PC. It also has
498 a built in web interface. It supports RTCK/RCLK or adaptive clocking
499 and has a built in relay to power cycle targets remotely.
502 @section Choosing a Dongle
504 There are three things you should keep in mind when choosing a dongle.
507 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
508 @item @b{Connection} Printer Ports - Does your computer have one?
509 @item @b{Connection} Is that long printer bit-bang cable practical?
510 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
513 @section Stand alone Systems
515 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
516 dongle, but a standalone box. The ZY1000 has the advantage that it does
517 not require any drivers installed on the developer PC. It also has
518 a built in web interface. It supports RTCK/RCLK or adaptive clocking
519 and has a built in relay to power cycle targets remotely.
521 @section USB FT2232 Based
523 There are many USB JTAG dongles on the market, many of them are based
524 on a chip from ``Future Technology Devices International'' (FTDI)
525 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
526 See: @url{http://www.ftdichip.com} for more information.
527 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
528 chips are starting to become available in JTAG adapters.
532 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
534 @* See: @url{http://www.amontec.com/jtagkey.shtml}
536 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
538 @* See: @url{http://www.signalyzer.com}
539 @item @b{evb_lm3s811}
540 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
541 @item @b{olimex-jtag}
542 @* See: @url{http://www.olimex.com}
544 @* See: @url{http://www.tincantools.com}
545 @item @b{turtelizer2}
547 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
548 @url{http://www.ethernut.de}
550 @* Link: @url{http://www.hitex.com/index.php?id=383}
552 @* Link @url{http://www.hitex.com/stm32-stick}
553 @item @b{axm0432_jtag}
554 @* Axiom AXM-0432 Link @url{http://www.axman.com}
556 @* Link @url{http://www.hitex.com/index.php?id=cortino}
559 @section USB JLINK based
560 There are several OEM versions of the Segger @b{JLINK} adapter. It is
561 an example of a micro controller based JTAG adapter, it uses an
562 AT91SAM764 internally.
565 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
566 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
567 @item @b{SEGGER JLINK}
568 @* Link: @url{http://www.segger.com/jlink.html}
570 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
573 @section USB RLINK based
574 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
577 @item @b{Raisonance RLink}
578 @* Link: @url{http://www.raisonance.com/products/RLink.php}
579 @item @b{STM32 Primer}
580 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
581 @item @b{STM32 Primer2}
582 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
588 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
590 @item @b{USB - Presto}
591 @* Link: @url{http://tools.asix.net/prg_presto.htm}
593 @item @b{Versaloon-Link}
594 @* Link: @url{http://www.simonqian.com/en/Versaloon}
596 @item @b{ARM-JTAG-EW}
597 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
600 @section IBM PC Parallel Printer Port Based
602 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
603 and the MacGraigor Wiggler. There are many clones and variations of
608 @item @b{Wiggler} - There are many clones of this.
609 @* Link: @url{http://www.macraigor.com/wiggler.htm}
611 @item @b{DLC5} - From XILINX - There are many clones of this
612 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
613 produced, PDF schematics are easily found and it is easy to make.
615 @item @b{Amontec - JTAG Accelerator}
616 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
619 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
622 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
623 Improved parallel-port wiggler-style JTAG adapter}
625 @item @b{Wiggler_ntrst_inverted}
626 @* Yet another variation - See the source code, src/jtag/parport.c
628 @item @b{old_amt_wiggler}
629 @* Unknown - probably not on the market today
632 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
635 @* Link: @url{http://www.amontec.com/chameleon.shtml}
641 @* ispDownload from Lattice Semiconductor
642 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
645 @* From ST Microsystems;
646 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
647 FlashLINK JTAG programing cable for PSD and uPSD}
655 @* An EP93xx based Linux machine using the GPIO pins directly.
658 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
664 @cindex command line options
666 @cindex directory search
668 The @option{--help} option shows:
672 --help | -h display this help
673 --version | -v display OpenOCD version
674 --file | -f use configuration file <name>
675 --search | -s dir to search for config files and scripts
676 --debug | -d set debug level <0-3>
677 --log_output | -l redirect log output to file <name>
678 --command | -c run <command>
679 --pipe | -p use pipes when talking to gdb
682 By default OpenOCD reads the file configuration file ``openocd.cfg''
683 in the current directory. To specify a different (or multiple)
684 configuration file, you can use the ``-f'' option. For example:
687 openocd -f config1.cfg -f config2.cfg -f config3.cfg
690 Once started, OpenOCD runs as a daemon, waiting for connections from
691 clients (Telnet, GDB, Other).
693 If you are having problems, you can enable internal debug messages via
696 Also it is possible to interleave commands w/config scripts using the
697 @option{-c} command line switch.
699 To enable debug output (when reporting problems or working on OpenOCD
700 itself), use the @option{-d} command line switch. This sets the
701 @option{debug_level} to "3", outputting the most information,
702 including debug messages. The default setting is "2", outputting only
703 informational messages, warnings and errors. You can also change this
704 setting from within a telnet or gdb session using @command{debug_level
705 <n>} (@pxref{debug_level}).
707 You can redirect all output from the daemon to a file using the
708 @option{-l <logfile>} switch.
710 Search paths for config/script files can be added to OpenOCD by using
711 the @option{-s <search>} switch. The current directory and the OpenOCD
712 target library is in the search path by default.
714 For details on the @option{-p} option. @xref{Connecting to GDB}.
716 Note! OpenOCD will launch the GDB & telnet server even if it can not
717 establish a connection with the target. In general, it is possible for
718 the JTAG controller to be unresponsive until the target is set up
719 correctly via e.g. GDB monitor commands in a GDB init script.
721 @node OpenOCD Project Setup
722 @chapter OpenOCD Project Setup
724 To use OpenOCD with your development projects, you need to do more than
725 just connecting the JTAG adapter hardware (dongle) to your development board
726 and then starting the OpenOCD server.
727 You also need to configure that server so that it knows
728 about that adapter and board, and helps your work.
730 @section Hooking up the JTAG Adapter
732 Today's most common case is a dongle with a JTAG cable on one side
733 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
734 and a USB cable on the other.
735 Instead of USB, some cables use Ethernet;
736 older ones may use a PC parallel port, or even a serial port.
739 @item @emph{Start with power to your target board turned off},
740 and nothing connected to your JTAG adapter.
741 If you're particularly paranoid, unplug power to the board.
742 It's important to have the ground signal properly set up,
743 unless you are using a JTAG adapter which provides
744 galvanic isolation between the target board and the
747 @item @emph{Be sure it's the right kind of JTAG connector.}
748 If your dongle has a 20-pin ARM connector, you need some kind
749 of adapter (or octopus, see below) to hook it up to
750 boards using 14-pin or 10-pin connectors ... or to 20-pin
751 connectors which don't use ARM's pinout.
753 In the same vein, make sure the voltage levels are compatible.
754 Not all JTAG adapters have the level shifters needed to work
755 with 1.2 Volt boards.
757 @item @emph{Be certain the cable is properly oriented} or you might
758 damage your board. In most cases there are only two possible
759 ways to connect the cable.
760 Connect the JTAG cable from your adapter to the board.
761 Be sure it's firmly connected.
763 In the best case, the connector is keyed to physically
764 prevent you from inserting it wrong.
765 This is most often done using a slot on the board's male connector
766 housing, which must match a key on the JTAG cable's female connector.
767 If there's no housing, then you must look carefully and
768 make sure pin 1 on the cable hooks up to pin 1 on the board.
769 Ribbon cables are frequently all grey except for a wire on one
770 edge, which is red. The red wire is pin 1.
772 Sometimes dongles provide cables where one end is an ``octopus'' of
773 color coded single-wire connectors, instead of a connector block.
774 These are great when converting from one JTAG pinout to another,
775 but are tedious to set up.
776 Use these with connector pinout diagrams to help you match up the
777 adapter signals to the right board pins.
779 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
780 A USB, parallel, or serial port connector will go to the host which
781 you are using to run OpenOCD.
782 For Ethernet, consult the documentation and your network administrator.
784 For USB based JTAG adapters you have an easy sanity check at this point:
785 does the host operating system see the JTAG adapter?
787 @item @emph{Connect the adapter's power supply, if needed.}
788 This step is primarily for non-USB adapters,
789 but sometimes USB adapters need extra power.
791 @item @emph{Power up the target board.}
792 Unless you just let the magic smoke escape,
793 you're now ready to set up the OpenOCD server
794 so you can use JTAG to work with that board.
798 Talk with the OpenOCD server using
799 telnet (@code{telnet localhost 4444} on many systems) or GDB.
800 @xref{GDB and OpenOCD}.
802 @section Project Directory
804 There are many ways you can configure OpenOCD and start it up.
806 A simple way to organize them all involves keeping a
807 single directory for your work with a given board.
808 When you start OpenOCD from that directory,
809 it searches there first for configuration files
810 and for code you upload to the target board.
811 It is also be the natural place to write files,
812 such as log files and data you download from the board.
814 @section Configuration Basics
816 There are two basic ways of configuring OpenOCD, and
817 a variety of ways you can mix them.
818 Think of the difference as just being how you start the server:
821 @item Many @option{-f file} or @option{-c command} options on the command line
822 @item No options, but a @dfn{user config file}
823 in the current directory named @file{openocd.cfg}
826 Here is an example @file{openocd.cfg} file for a setup
827 using a Signalyzer FT2232-based JTAG adapter to talk to
828 a board with an Atmel AT91SAM7X256 microcontroller:
831 source [find interface/signalyzer.cfg]
833 # GDB can also flash my flash!
834 gdb_memory_map enable
835 gdb_flash_program enable
837 source [find target/sam7x256.cfg]
840 Here is the command line equivalent of that configuration:
843 openocd -f interface/signalyzer.cfg \
844 -c "gdb_memory_map enable" \
845 -c "gdb_flash_program enable" \
846 -f target/sam7x256.cfg
849 You could wrap such long command lines in shell scripts,
850 each supporting a different development task.
851 One might re-flash the board with specific firmware version.
852 Another might set up a particular debugging or run-time environment.
854 Here we will focus on the simpler solution: one user config
855 file, including basic configuration plus any TCL procedures
856 to simplify your work.
858 @section User Config Files
859 @cindex config file, user
860 @cindex user config file
861 @cindex config file, overview
863 A user configuration file ties together all the parts of a project
865 One of the following will match your situation best:
868 @item Ideally almost everything comes from configuration files
869 provided by someone else.
870 For example, OpenOCD distributes a @file{scripts} directory
871 (probably in @file{/usr/share/openocd/scripts} on Linux).
872 Board and tool vendors can provide these too, as can individual
873 user sites; the @option{-s} command line option lets you say
874 where to find these files. (@xref{Running}.)
875 The AT91SAM7X256 example above works this way.
877 Three main types of non-user configuration file each have their
878 own subdirectory in the @file{scripts} directory:
881 @item @b{interface} -- one for each kind of JTAG adapter/dongle
882 @item @b{board} -- one for each different board
883 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
886 Best case: include just two files, and they handle everything else.
887 The first is an interface config file.
888 The second is board-specific, and it sets up the JTAG TAPs and
889 their GDB targets (by deferring to some @file{target.cfg} file),
890 declares all flash memory, and leaves you nothing to do except
894 source [find interface/olimex-jtag-tiny.cfg]
895 source [find board/csb337.cfg]
898 Boards with a single microcontroller often won't need more
899 than the target config file, as in the AT91SAM7X256 example.
900 That's because there is no external memory (flash, DDR RAM), and
901 the board differences are encapsulated by application code.
903 @item You can often reuse some standard config files but
904 need to write a few new ones, probably a @file{board.cfg} file.
905 You will be using commands described later in this User's Guide,
906 and working with the guidelines in the next chapter.
908 For example, there may be configuration files for your JTAG adapter
909 and target chip, but you need a new board-specific config file
910 giving access to your particular flash chips.
911 Or you might need to write another target chip configuration file
912 for a new chip built around the Cortex M3 core.
915 When you write new configuration files, please submit
916 them for inclusion in the next OpenOCD release.
917 For example, a @file{board/newboard.cfg} file will help the
918 next users of that board, and a @file{target/newcpu.cfg}
919 will help support users of any board using that chip.
923 You may may need to write some C code.
924 It may be as simple as a supporting a new new ft2232 or parport
925 based dongle; a bit more involved, like a NAND or NOR flash
926 controller driver; or a big piece of work like supporting
927 a new chip architecture.
930 Reuse the existing config files when you can.
931 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
932 You may find a board configuration that's a good example to follow.
934 When you write config files, separate the reusable parts
935 (things every user of that interface, chip, or board needs)
936 from ones specific to your environment and debugging approach.
938 For example, a @code{gdb-attach} event handler that invokes
939 the @command{reset init} command will interfere with debugging
940 early boot code, which performs some of the same actions
941 that the @code{reset-init} event handler does.
942 Likewise, the @command{arm9tdmi vector_catch} command (or
943 its @command{xscale vector_catch} sibling) can be a timesaver
944 during some debug sessions, but don't make everyone use that either.
945 Keep those kinds of debugging aids in your user config file.
947 TCP/IP port configuration is another example of something which
948 is environment-specific, and should only appear in
949 a user config file. @xref{TCP/IP Ports}.
951 @section Project-Specific Utilities
953 A few project-specific utility
954 routines may well speed up your work.
955 Write them, and keep them in your project's user config file.
957 For example, if you are making a boot loader work on a
958 board, it's nice to be able to debug the ``after it's
959 loaded to RAM'' parts separately from the finicky early
960 code which sets up the DDR RAM controller and clocks.
961 A script like this one, or a more GDB-aware sibling,
965 proc ramboot @{ @} @{
966 # Reset, running the target's "reset-init" scripts
967 # to initialize clocks and the DDR RAM controller.
968 # Leave the CPU halted.
971 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
972 load_image u-boot.bin 0x20000000
979 Then once that code is working you will need to make it
980 boot from NOR flash; a different utility would help.
981 Alternatively, some developers write to flash using GDB.
982 (You might use a similar script if you're working with a flash
983 based microcontroller application instead of a boot loader.)
986 proc newboot @{ @} @{
987 # Reset, leaving the CPU halted. The "reset-init" event
988 # proc gives faster access to the CPU and to NOR flash;
989 # "reset halt" would be slower.
992 # Write standard version of U-Boot into the first two
993 # sectors of NOR flash ... the standard version should
994 # do the same lowlevel init as "reset-init".
995 flash protect 0 0 1 off
996 flash erase_sector 0 0 1
997 flash write_bank 0 u-boot.bin 0x0
998 flash protect 0 0 1 on
1000 # Reboot from scratch using that new boot loader.
1005 You may need more complicated utility procedures when booting
1007 That often involves an extra bootloader stage,
1008 running from on-chip SRAM to perform DDR RAM setup so it can load
1009 the main bootloader code (which won't fit into that SRAM).
1011 Other helper scripts might be used to write production system images,
1012 involving considerably more than just a three stage bootloader.
1015 @node Config File Guidelines
1016 @chapter Config File Guidelines
1018 This chapter is aimed at any user who needs to write a config file,
1019 including developers and integrators of OpenOCD and any user who
1020 needs to get a new board working smoothly.
1021 It provides guidelines for creating those files.
1023 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
1026 @item @file{interface} ...
1027 think JTAG Dongle. Files that configure JTAG adapters go here.
1028 @item @file{board} ...
1029 think Circuit Board, PWA, PCB, they go by many names. Board files
1030 contain initialization items that are specific to a board. For
1031 example, the SDRAM initialization sequence for the board, or the type
1032 of external flash and what address it uses. Any initialization
1033 sequence to enable that external flash or SDRAM should be found in the
1034 board file. Boards may also contain multiple targets: two CPUs; or
1035 a CPU and an FPGA or CPLD.
1036 @item @file{target} ...
1037 think chip. The ``target'' directory represents the JTAG TAPs
1039 which OpenOCD should control, not a board. Two common types of targets
1040 are ARM chips and FPGA or CPLD chips.
1041 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1042 the target config file defines all of them.
1045 The @file{openocd.cfg} user config
1046 file may override features in any of the above files by
1047 setting variables before sourcing the target file, or by adding
1048 commands specific to their situation.
1050 @section Interface Config Files
1052 The user config file
1053 should be able to source one of these files with a command like this:
1056 source [find interface/FOOBAR.cfg]
1059 A preconfigured interface file should exist for every interface in use
1060 today, that said, perhaps some interfaces have only been used by the
1061 sole developer who created it.
1063 A separate chapter gives information about how to set these up.
1064 @xref{Interface - Dongle Configuration}.
1065 Read the OpenOCD source code if you have a new kind of hardware interface
1066 and need to provide a driver for it.
1068 @section Board Config Files
1069 @cindex config file, board
1070 @cindex board config file
1072 The user config file
1073 should be able to source one of these files with a command like this:
1076 source [find board/FOOBAR.cfg]
1079 The point of a board config file is to package everything
1080 about a given board that user config files need to know.
1081 In summary the board files should contain (if present)
1084 @item One or more @command{source [target/...cfg]} statements
1085 @item NOR flash configuration (@pxref{NOR Configuration})
1086 @item NAND flash configuration (@pxref{NAND Configuration})
1087 @item Target @code{reset} handlers for SDRAM and I/O configuration
1088 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1089 @item All things that are not ``inside a chip''
1092 Generic things inside target chips belong in target config files,
1093 not board config files. So for example a @code{reset-init} event
1094 handler should know board-specific oscillator and PLL parameters,
1095 which it passes to target-specific utility code.
1097 The most complex task of a board config file is creating such a
1098 @code{reset-init} event handler.
1099 Define those handlers last, after you verify the rest of the board
1100 configuration works.
1102 @subsection Communication Between Config files
1104 In addition to target-specific utility code, another way that
1105 board and target config files communicate is by following a
1106 convention on how to use certain variables.
1108 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1109 Thus the rule we follow in OpenOCD is this: Variables that begin with
1110 a leading underscore are temporary in nature, and can be modified and
1111 used at will within a target configuration file.
1113 Complex board config files can do the things like this,
1114 for a board with three chips:
1117 # Chip #1: PXA270 for network side, big endian
1118 set CHIPNAME network
1120 source [find target/pxa270.cfg]
1121 # on return: _TARGETNAME = network.cpu
1122 # other commands can refer to the "network.cpu" target.
1123 $_TARGETNAME configure .... events for this CPU..
1125 # Chip #2: PXA270 for video side, little endian
1128 source [find target/pxa270.cfg]
1129 # on return: _TARGETNAME = video.cpu
1130 # other commands can refer to the "video.cpu" target.
1131 $_TARGETNAME configure .... events for this CPU..
1133 # Chip #3: Xilinx FPGA for glue logic
1136 source [find target/spartan3.cfg]
1139 That example is oversimplified because it doesn't show any flash memory,
1140 or the @code{reset-init} event handlers to initialize external DRAM
1141 or (assuming it needs it) load a configuration into the FPGA.
1142 Such features are usually needed for low-level work with many boards,
1143 where ``low level'' implies that the board initialization software may
1144 not be working. (That's a common reason to need JTAG tools. Another
1145 is to enable working with microcontroller-based systems, which often
1146 have no debugging support except a JTAG connector.)
1148 Target config files may also export utility functions to board and user
1149 config files. Such functions should use name prefixes, to help avoid
1152 Board files could also accept input variables from user config files.
1153 For example, there might be a @code{J4_JUMPER} setting used to identify
1154 what kind of flash memory a development board is using, or how to set
1155 up other clocks and peripherals.
1157 @subsection Variable Naming Convention
1158 @cindex variable names
1160 Most boards have only one instance of a chip.
1161 However, it should be easy to create a board with more than
1162 one such chip (as shown above).
1163 Accordingly, we encourage these conventions for naming
1164 variables associated with different @file{target.cfg} files,
1165 to promote consistency and
1166 so that board files can override target defaults.
1168 Inputs to target config files include:
1171 @item @code{CHIPNAME} ...
1172 This gives a name to the overall chip, and is used as part of
1173 tap identifier dotted names.
1174 While the default is normally provided by the chip manufacturer,
1175 board files may need to distinguish between instances of a chip.
1176 @item @code{ENDIAN} ...
1177 By default @option{little} - although chips may hard-wire @option{big}.
1178 Chips that can't change endianness don't need to use this variable.
1179 @item @code{CPUTAPID} ...
1180 When OpenOCD examines the JTAG chain, it can be told verify the
1181 chips against the JTAG IDCODE register.
1182 The target file will hold one or more defaults, but sometimes the
1183 chip in a board will use a different ID (perhaps a newer revision).
1186 Outputs from target config files include:
1189 @item @code{_TARGETNAME} ...
1190 By convention, this variable is created by the target configuration
1191 script. The board configuration file may make use of this variable to
1192 configure things like a ``reset init'' script, or other things
1193 specific to that board and that target.
1194 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1195 @code{_TARGETNAME1}, ... etc.
1198 @subsection The reset-init Event Handler
1199 @cindex event, reset-init
1200 @cindex reset-init handler
1202 Board config files run in the OpenOCD configuration stage;
1203 they can't use TAPs or targets, since they haven't been
1205 This means you can't write memory or access chip registers;
1206 you can't even verify that a flash chip is present.
1207 That's done later in event handlers, of which the target @code{reset-init}
1208 handler is one of the most important.
1210 Except on microcontrollers, the basic job of @code{reset-init} event
1211 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1212 Microcontrollers rarely use boot loaders; they run right out of their
1213 on-chip flash and SRAM memory. But they may want to use one of these
1214 handlers too, if just for developer convenience.
1217 Because this is so very board-specific, and chip-specific, no examples
1219 Instead, look at the board config files distributed with OpenOCD.
1220 If you have a boot loader, its source code may also be useful.
1223 Some of this code could probably be shared between different boards.
1224 For example, setting up a DRAM controller often doesn't differ by
1225 much except the bus width (16 bits or 32?) and memory timings, so a
1226 reusable TCL procedure loaded by the @file{target.cfg} file might take
1227 those as parameters.
1228 Similarly with oscillator, PLL, and clock setup;
1229 and disabling the watchdog.
1230 Structure the code cleanly, and provide comments to help
1231 the next developer doing such work.
1232 (@emph{You might be that next person} trying to reuse init code!)
1234 The last thing normally done in a @code{reset-init} handler is probing
1235 whatever flash memory was configured. For most chips that needs to be
1236 done while the associated target is halted, either because JTAG memory
1237 access uses the CPU or to prevent conflicting CPU access.
1239 @subsection JTAG Clock Rate
1241 Before your @code{reset-init} handler has set up
1242 the PLLs and clocking, you may need to use
1243 a low JTAG clock rate; then you'd increase it later.
1244 (The rule of thumb for ARM-based processors is 1/8 the CPU clock.)
1245 If the board supports adaptive clocking, use the @command{jtag_rclk}
1246 command, in case your board is used with JTAG adapter which
1247 also supports it. Otherwise use @command{jtag_khz}.
1248 Set the slow rate at the beginning of the reset sequence,
1249 and the faster rate as soon as the clocks are at full speed.
1251 @section Target Config Files
1252 @cindex config file, target
1253 @cindex target config file
1255 Board config files communicate with target config files using
1256 naming conventions as described above, and may source one or
1257 more target config files like this:
1260 source [find target/FOOBAR.cfg]
1263 The point of a target config file is to package everything
1264 about a given chip that board config files need to know.
1265 In summary the target files should contain
1269 @item Add TAPs to the scan chain
1270 @item Add CPU targets (includes GDB support)
1271 @item CPU/Chip/CPU-Core specific features
1275 As a rule of thumb, a target file sets up only one chip.
1276 For a microcontroller, that will often include a single TAP,
1277 which is a CPU needing a GDB target, and its on-chip flash.
1279 More complex chips may include multiple TAPs, and the target
1280 config file may need to define them all before OpenOCD
1281 can talk to the chip.
1282 For example, some phone chips have JTAG scan chains that include
1283 an ARM core for operating system use, a DSP,
1284 another ARM core embedded in an image processing engine,
1285 and other processing engines.
1287 @subsection Default Value Boiler Plate Code
1289 All target configuration files should start with code like this,
1290 letting board config files express environment-specific
1291 differences in how things should be set up.
1294 # Boards may override chip names, perhaps based on role,
1295 # but the default should match what the vendor uses
1296 if @{ [info exists CHIPNAME] @} @{
1297 set _CHIPNAME $CHIPNAME
1299 set _CHIPNAME sam7x256
1302 # ONLY use ENDIAN with targets that can change it.
1303 if @{ [info exists ENDIAN] @} @{
1309 # TAP identifiers may change as chips mature, for example with
1310 # new revision fields (the "3" here). Pick a good default; you
1311 # can pass several such identifiers to the "jtag newtap" command.
1312 if @{ [info exists CPUTAPID ] @} @{
1313 set _CPUTAPID $CPUTAPID
1315 set _CPUTAPID 0x3f0f0f0f
1319 @emph{Remember:} Board config files may include multiple target
1320 config files, or the same target file multiple times
1321 (changing at least @code{CHIPNAME}).
1323 Likewise, the target configuration file should define
1324 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1325 use it later on when defining debug targets:
1328 set _TARGETNAME $_CHIPNAME.cpu
1329 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1332 @subsection Adding TAPs to the Scan Chain
1333 After the ``defaults'' are set up,
1334 add the TAPs on each chip to the JTAG scan chain.
1335 @xref{TAP Declaration}, and the naming convention
1338 In the simplest case the chip has only one TAP,
1339 probably for a CPU or FPGA.
1340 The config file for the Atmel AT91SAM7X256
1341 looks (in part) like this:
1344 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1345 -expected-id $_CPUTAPID
1348 A board with two such at91sam7 chips would be able
1349 to source such a config file twice, with different
1350 values for @code{CHIPNAME}, so
1351 it adds a different TAP each time.
1353 If there are one or more nonzero @option{-expected-id} values,
1354 OpenOCD attempts to verify the actual tap id against those values.
1355 It will issue error messages if there is mismatch, which
1356 can help to pinpoint problems in OpenOCD configurations.
1359 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1360 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1361 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1362 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1363 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1366 There are more complex examples too, with chips that have
1367 multiple TAPs. Ones worth looking at include:
1370 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1371 plus a JRC to enable them
1372 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1373 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1374 is not currently used)
1377 @subsection Add CPU targets
1379 After adding a TAP for a CPU, you should set it up so that
1380 GDB and other commands can use it.
1381 @xref{CPU Configuration}.
1382 For the at91sam7 example above, the command can look like this;
1383 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1384 to little endian, and this chip doesn't support changing that.
1387 set _TARGETNAME $_CHIPNAME.cpu
1388 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1391 Work areas are small RAM areas associated with CPU targets.
1392 They are used by OpenOCD to speed up downloads,
1393 and to download small snippets of code to program flash chips.
1394 If the chip includes a form of ``on-chip-ram'' - and many do - define
1395 a work area if you can.
1396 Again using the at91sam7 as an example, this can look like:
1399 $_TARGETNAME configure -work-area-phys 0x00200000 \
1400 -work-area-size 0x4000 -work-area-backup 0
1403 @subsection Chip Reset Setup
1405 As a rule, you should put the @command{reset_config} command
1406 into the board file. Most things you think you know about a
1407 chip can be tweaked by the board.
1409 Some chips have specific ways the TRST and SRST signals are
1410 managed. In the unusual case that these are @emph{chip specific}
1411 and can never be changed by board wiring, they could go here.
1413 Some chips need special attention during reset handling if
1414 they're going to be used with JTAG.
1415 An example might be needing to send some commands right
1416 after the target's TAP has been reset, providing a
1417 @code{reset-deassert-post} event handler that writes a chip
1418 register to report that JTAG debugging is being done.
1420 @subsection ARM Core Specific Hacks
1422 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1423 special high speed download features - enable it.
1425 If present, the MMU, the MPU and the CACHE should be disabled.
1427 Some ARM cores are equipped with trace support, which permits
1428 examination of the instruction and data bus activity. Trace
1429 activity is controlled through an ``Embedded Trace Module'' (ETM)
1430 on one of the core's scan chains. The ETM emits voluminous data
1431 through a ``trace port''. (@xref{ARM Tracing}.)
1432 If you are using an external trace port,
1433 configure it in your board config file.
1434 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1435 configure it in your target config file.
1438 etm config $_TARGETNAME 16 normal full etb
1439 etb config $_TARGETNAME $_CHIPNAME.etb
1442 @subsection Internal Flash Configuration
1444 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1446 @b{Never ever} in the ``target configuration file'' define any type of
1447 flash that is external to the chip. (For example a BOOT flash on
1448 Chip Select 0.) Such flash information goes in a board file - not
1449 the TARGET (chip) file.
1453 @item at91sam7x256 - has 256K flash YES enable it.
1454 @item str912 - has flash internal YES enable it.
1455 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1456 @item pxa270 - again - CS0 flash - it goes in the board file.
1460 @chapter About JIM-Tcl
1464 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1465 learn more about JIM here: @url{http://jim.berlios.de}
1468 @item @b{JIM vs. Tcl}
1469 @* JIM-TCL is a stripped down version of the well known Tcl language,
1470 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1471 fewer features. JIM-Tcl is a single .C file and a single .H file and
1472 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1473 4.2 MB .zip file containing 1540 files.
1475 @item @b{Missing Features}
1476 @* Our practice has been: Add/clone the real Tcl feature if/when
1477 needed. We welcome JIM Tcl improvements, not bloat.
1480 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1481 command interpreter today is a mixture of (newer)
1482 JIM-Tcl commands, and (older) the orginal command interpreter.
1485 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1486 can type a Tcl for() loop, set variables, etc.
1488 @item @b{Historical Note}
1489 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1491 @item @b{Need a crash course in Tcl?}
1492 @*@xref{Tcl Crash Course}.
1495 @node Daemon Configuration
1496 @chapter Daemon Configuration
1497 @cindex initialization
1498 The commands here are commonly found in the openocd.cfg file and are
1499 used to specify what TCP/IP ports are used, and how GDB should be
1502 @section Configuration Stage
1503 @cindex configuration stage
1504 @cindex configuration command
1506 When the OpenOCD server process starts up, it enters a
1507 @emph{configuration stage} which is the only time that
1508 certain commands, @emph{configuration commands}, may be issued.
1509 Those configuration commands include declaration of TAPs
1510 and other basic setup.
1511 The server must leave the configuration stage before it
1512 may access or activate TAPs.
1513 After it leaves this stage, configuration commands may no
1516 @deffn {Config Command} init
1517 This command terminates the configuration stage and
1518 enters the normal command mode. This can be useful to add commands to
1519 the startup scripts and commands such as resetting the target,
1520 programming flash, etc. To reset the CPU upon startup, add "init" and
1521 "reset" at the end of the config script or at the end of the OpenOCD
1522 command line using the @option{-c} command line switch.
1524 If this command does not appear in any startup/configuration file
1525 OpenOCD executes the command for you after processing all
1526 configuration files and/or command line options.
1528 @b{NOTE:} This command normally occurs at or near the end of your
1529 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1530 targets ready. For example: If your openocd.cfg file needs to
1531 read/write memory on your target, @command{init} must occur before
1532 the memory read/write commands. This includes @command{nand probe}.
1535 @anchor{TCP/IP Ports}
1536 @section TCP/IP Ports
1541 The OpenOCD server accepts remote commands in several syntaxes.
1542 Each syntax uses a different TCP/IP port, which you may specify
1543 only during configuration (before those ports are opened).
1545 For reasons including security, you may wish to prevent remote
1546 access using one or more of these ports.
1547 In such cases, just specify the relevant port number as zero.
1548 If you disable all access through TCP/IP, you will need to
1549 use the command line @option{-pipe} option.
1551 @deffn {Command} gdb_port (number)
1553 Specify or query the first port used for incoming GDB connections.
1554 The GDB port for the
1555 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1556 When not specified during the configuration stage,
1557 the port @var{number} defaults to 3333.
1558 When specified as zero, this port is not activated.
1561 @deffn {Command} tcl_port (number)
1562 Specify or query the port used for a simplified RPC
1563 connection that can be used by clients to issue TCL commands and get the
1564 output from the Tcl engine.
1565 Intended as a machine interface.
1566 When not specified during the configuration stage,
1567 the port @var{number} defaults to 6666.
1568 When specified as zero, this port is not activated.
1571 @deffn {Command} telnet_port (number)
1572 Specify or query the
1573 port on which to listen for incoming telnet connections.
1574 This port is intended for interaction with one human through TCL commands.
1575 When not specified during the configuration stage,
1576 the port @var{number} defaults to 4444.
1577 When specified as zero, this port is not activated.
1580 @anchor{GDB Configuration}
1581 @section GDB Configuration
1583 @cindex GDB configuration
1584 You can reconfigure some GDB behaviors if needed.
1585 The ones listed here are static and global.
1586 @xref{Target Configuration}, about configuring individual targets.
1587 @xref{Target Events}, about configuring target-specific event handling.
1589 @anchor{gdb_breakpoint_override}
1590 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1591 Force breakpoint type for gdb @command{break} commands.
1592 This option supports GDB GUIs which don't
1593 distinguish hard versus soft breakpoints, if the default OpenOCD and
1594 GDB behaviour is not sufficient. GDB normally uses hardware
1595 breakpoints if the memory map has been set up for flash regions.
1598 @deffn {Config command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1599 Configures what OpenOCD will do when GDB detaches from the daemon.
1600 Default behaviour is @option{resume}.
1603 @anchor{gdb_flash_program}
1604 @deffn {Config command} gdb_flash_program (@option{enable}|@option{disable})
1605 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1606 vFlash packet is received.
1607 The default behaviour is @option{enable}.
1610 @deffn {Config command} gdb_memory_map (@option{enable}|@option{disable})
1611 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1612 requested. GDB will then know when to set hardware breakpoints, and program flash
1613 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1614 for flash programming to work.
1615 Default behaviour is @option{enable}.
1616 @xref{gdb_flash_program}.
1619 @deffn {Config command} gdb_report_data_abort (@option{enable}|@option{disable})
1620 Specifies whether data aborts cause an error to be reported
1621 by GDB memory read packets.
1622 The default behaviour is @option{disable};
1623 use @option{enable} see these errors reported.
1626 @anchor{Event Polling}
1627 @section Event Polling
1629 Hardware debuggers are parts of asynchronous systems,
1630 where significant events can happen at any time.
1631 The OpenOCD server needs to detect some of these events,
1632 so it can report them to through TCL command line
1635 Examples of such events include:
1638 @item One of the targets can stop running ... maybe it triggers
1639 a code breakpoint or data watchpoint, or halts itself.
1640 @item Messages may be sent over ``debug message'' channels ... many
1641 targets support such messages sent over JTAG,
1642 for receipt by the person debugging or tools.
1643 @item Loss of power ... some adapters can detect these events.
1644 @item Resets not issued through JTAG ... such reset sources
1645 can include button presses or other system hardware, sometimes
1646 including the target itself (perhaps through a watchdog).
1647 @item Debug instrumentation sometimes supports event triggering
1648 such as ``trace buffer full'' (so it can quickly be emptied)
1649 or other signals (to correlate with code behavior).
1652 None of those events are signaled through standard JTAG signals.
1653 However, most conventions for JTAG connectors include voltage
1654 level and system reset (SRST) signal detection.
1655 Some connectors also include instrumentation signals, which
1656 can imply events when those signals are inputs.
1658 In general, OpenOCD needs to periodically check for those events,
1659 either by looking at the status of signals on the JTAG connector
1660 or by sending synchronous ``tell me your status'' JTAG requests
1661 to the various active targets.
1662 There is a command to manage and monitor that polling,
1663 which is normally done in the background.
1665 @deffn Command poll [@option{on}|@option{off}]
1666 Poll the current target for its current state.
1667 (Also, @pxref{target curstate}.)
1668 If that target is in debug mode, architecture
1669 specific information about the current state is printed.
1670 An optional parameter
1671 allows background polling to be enabled and disabled.
1673 You could use this from the TCL command shell, or
1674 from GDB using @command{monitor poll} command.
1677 background polling: on
1678 target state: halted
1679 target halted in ARM state due to debug-request, \
1680 current mode: Supervisor
1681 cpsr: 0x800000d3 pc: 0x11081bfc
1682 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1687 @node Interface - Dongle Configuration
1688 @chapter Interface - Dongle Configuration
1689 @cindex config file, interface
1690 @cindex interface config file
1692 JTAG Adapters/Interfaces/Dongles are normally configured
1693 through commands in an interface configuration
1694 file which is sourced by your @file{openocd.cfg} file, or
1695 through a command line @option{-f interface/....cfg} option.
1698 source [find interface/olimex-jtag-tiny.cfg]
1702 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1703 A few cases are so simple that you only need to say what driver to use:
1710 Most adapters need a bit more configuration than that.
1713 @section Interface Configuration
1715 The interface command tells OpenOCD what type of JTAG dongle you are
1716 using. Depending on the type of dongle, you may need to have one or
1717 more additional commands.
1719 @deffn {Config Command} {interface} name
1720 Use the interface driver @var{name} to connect to the
1724 @deffn Command {interface_list}
1725 List the interface drivers that have been built into
1726 the running copy of OpenOCD.
1729 @deffn Command {jtag interface}
1730 Returns the name of the interface driver being used.
1733 @section Interface Drivers
1735 Each of the interface drivers listed here must be explicitly
1736 enabled when OpenOCD is configured, in order to be made
1737 available at run time.
1739 @deffn {Interface Driver} {amt_jtagaccel}
1740 Amontec Chameleon in its JTAG Accelerator configuration,
1741 connected to a PC's EPP mode parallel port.
1742 This defines some driver-specific commands:
1744 @deffn {Config Command} {parport_port} number
1745 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1746 the number of the @file{/dev/parport} device.
1749 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1750 Displays status of RTCK option.
1751 Optionally sets that option first.
1755 @deffn {Interface Driver} {arm-jtag-ew}
1756 Olimex ARM-JTAG-EW USB adapter
1757 This has one driver-specific command:
1759 @deffn Command {armjtagew_info}
1764 @deffn {Interface Driver} {at91rm9200}
1765 Supports bitbanged JTAG from the local system,
1766 presuming that system is an Atmel AT91rm9200
1767 and a specific set of GPIOs is used.
1768 @c command: at91rm9200_device NAME
1769 @c chooses among list of bit configs ... only one option
1772 @deffn {Interface Driver} {dummy}
1773 A dummy software-only driver for debugging.
1776 @deffn {Interface Driver} {ep93xx}
1777 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1780 @deffn {Interface Driver} {ft2232}
1781 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1782 These interfaces have several commands, used to configure the driver
1783 before initializing the JTAG scan chain:
1785 @deffn {Config Command} {ft2232_device_desc} description
1786 Provides the USB device description (the @emph{iProduct string})
1787 of the FTDI FT2232 device. If not
1788 specified, the FTDI default value is used. This setting is only valid
1789 if compiled with FTD2XX support.
1792 @deffn {Config Command} {ft2232_serial} serial-number
1793 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1794 in case the vendor provides unique IDs and more than one FT2232 device
1795 is connected to the host.
1796 If not specified, serial numbers are not considered.
1799 @deffn {Config Command} {ft2232_layout} name
1800 Each vendor's FT2232 device can use different GPIO signals
1801 to control output-enables, reset signals, and LEDs.
1802 Currently valid layout @var{name} values include:
1804 @item @b{axm0432_jtag} Axiom AXM-0432
1805 @item @b{comstick} Hitex STR9 comstick
1806 @item @b{cortino} Hitex Cortino JTAG interface
1807 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1808 either for the local Cortex-M3 (SRST only)
1809 or in a passthrough mode (neither SRST nor TRST)
1810 @item @b{flyswatter} Tin Can Tools Flyswatter
1811 @item @b{icebear} ICEbear JTAG adapter from Section 5
1812 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1813 @item @b{m5960} American Microsystems M5960
1814 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1815 @item @b{oocdlink} OOCDLink
1816 @c oocdlink ~= jtagkey_prototype_v1
1817 @item @b{sheevaplug} Marvell Sheevaplug development kit
1818 @item @b{signalyzer} Xverve Signalyzer
1819 @item @b{stm32stick} Hitex STM32 Performance Stick
1820 @item @b{turtelizer2} egnite Software turtelizer2
1821 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1825 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1826 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1827 default values are used.
1828 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1830 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1834 @deffn {Config Command} {ft2232_latency} ms
1835 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1836 ft2232_read() fails to return the expected number of bytes. This can be caused by
1837 USB communication delays and has proved hard to reproduce and debug. Setting the
1838 FT2232 latency timer to a larger value increases delays for short USB packets but it
1839 also reduces the risk of timeouts before receiving the expected number of bytes.
1840 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1843 For example, the interface config file for a
1844 Turtelizer JTAG Adapter looks something like this:
1848 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1849 ft2232_layout turtelizer2
1850 ft2232_vid_pid 0x0403 0xbdc8
1854 @deffn {Interface Driver} {gw16012}
1855 Gateworks GW16012 JTAG programmer.
1856 This has one driver-specific command:
1858 @deffn {Config Command} {parport_port} number
1859 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1860 the number of the @file{/dev/parport} device.
1864 @deffn {Interface Driver} {jlink}
1865 Segger jlink USB adapter
1866 @c command: jlink_info
1868 @c command: jlink_hw_jtag (2|3)
1869 @c sets version 2 or 3
1872 @deffn {Interface Driver} {parport}
1873 Supports PC parallel port bit-banging cables:
1874 Wigglers, PLD download cable, and more.
1875 These interfaces have several commands, used to configure the driver
1876 before initializing the JTAG scan chain:
1878 @deffn {Config Command} {parport_cable} name
1879 The layout of the parallel port cable used to connect to the target.
1880 Currently valid cable @var{name} values include:
1883 @item @b{altium} Altium Universal JTAG cable.
1884 @item @b{arm-jtag} Same as original wiggler except SRST and
1885 TRST connections reversed and TRST is also inverted.
1886 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1887 in configuration mode. This is only used to
1888 program the Chameleon itself, not a connected target.
1889 @item @b{dlc5} The Xilinx Parallel cable III.
1890 @item @b{flashlink} The ST Parallel cable.
1891 @item @b{lattice} Lattice ispDOWNLOAD Cable
1892 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1894 Amontec's Chameleon Programmer. The new version available from
1895 the website uses the original Wiggler layout ('@var{wiggler}')
1896 @item @b{triton} The parallel port adapter found on the
1897 ``Karo Triton 1 Development Board''.
1898 This is also the layout used by the HollyGates design
1899 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1900 @item @b{wiggler} The original Wiggler layout, also supported by
1901 several clones, such as the Olimex ARM-JTAG
1902 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1903 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1907 @deffn {Config Command} {parport_port} number
1908 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1909 the @file{/dev/parport} device
1911 When using PPDEV to access the parallel port, use the number of the parallel port:
1912 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1913 you may encounter a problem.
1916 @deffn {Config Command} {parport_write_on_exit} (on|off)
1917 This will configure the parallel driver to write a known
1918 cable-specific value to the parallel interface on exiting OpenOCD
1921 For example, the interface configuration file for a
1922 classic ``Wiggler'' cable might look something like this:
1927 parport_cable wiggler
1931 @deffn {Interface Driver} {presto}
1932 ASIX PRESTO USB JTAG programmer.
1933 @c command: presto_serial str
1934 @c sets serial number
1937 @deffn {Interface Driver} {rlink}
1938 Raisonance RLink USB adapter
1941 @deffn {Interface Driver} {usbprog}
1942 usbprog is a freely programmable USB adapter.
1945 @deffn {Interface Driver} {vsllink}
1946 vsllink is part of Versaloon which is a versatile USB programmer.
1949 This defines quite a few driver-specific commands,
1950 which are not currently documented here.
1954 @deffn {Interface Driver} {ZY1000}
1955 This is the Zylin ZY1000 JTAG debugger.
1958 This defines some driver-specific commands,
1959 which are not currently documented here.
1962 @deffn Command power [@option{on}|@option{off}]
1963 Turn power switch to target on/off.
1964 No arguments: print status.
1971 JTAG clock setup is part of system setup.
1972 It @emph{does not belong with interface setup} since any interface
1973 only knows a few of the constraints for the JTAG clock speed.
1974 Sometimes the JTAG speed is
1975 changed during the target initialization process: (1) slow at
1976 reset, (2) program the CPU clocks, (3) run fast.
1977 Both the "slow" and "fast" clock rates are functions of the
1978 oscillators used, the chip, the board design, and sometimes
1979 power management software that may be active.
1981 The speed used during reset can be adjusted using pre_reset
1982 and post_reset event handlers.
1983 @xref{Target Events}.
1985 If your system supports adaptive clocking (RTCK), configuring
1986 JTAG to use that is probably the most robust approach.
1987 However, it introduces delays to synchronize clocks; so it
1988 may not be the fastest solution.
1990 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1991 instead of @command{jtag_khz}.
1993 @deffn {Command} jtag_khz max_speed_kHz
1994 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1995 JTAG interfaces usually support a limited number of
1996 speeds. The speed actually used won't be faster
1997 than the speed specified.
1999 As a rule of thumb, if you specify a clock rate make
2000 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
2001 This is especially true for synthesized cores (ARMxxx-S).
2003 Speed 0 (khz) selects RTCK method.
2005 If your system uses RTCK, you won't need to change the
2006 JTAG clocking after setup.
2007 Not all interfaces, boards, or targets support ``rtck''.
2008 If the interface device can not
2009 support it, an error is returned when you try to use RTCK.
2012 @defun jtag_rclk fallback_speed_kHz
2014 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
2015 If that fails (maybe the interface, board, or target doesn't
2016 support it), falls back to the specified frequency.
2018 # Fall back to 3mhz if RTCK is not supported
2023 @node Reset Configuration
2024 @chapter Reset Configuration
2025 @cindex Reset Configuration
2027 Every system configuration may require a different reset
2028 configuration. This can also be quite confusing.
2029 Resets also interact with @var{reset-init} event handlers,
2030 which do things like setting up clocks and DRAM, and
2031 JTAG clock rates. (@xref{JTAG Speed}.)
2032 They can also interact with JTAG routers.
2033 Please see the various board files for examples.
2036 To maintainers and integrators:
2037 Reset configuration touches several things at once.
2038 Normally the board configuration file
2039 should define it and assume that the JTAG adapter supports
2040 everything that's wired up to the board's JTAG connector.
2042 However, the target configuration file could also make note
2043 of something the silicon vendor has done inside the chip,
2044 which will be true for most (or all) boards using that chip.
2045 And when the JTAG adapter doesn't support everything, the
2046 user configuration file will need to override parts of
2047 the reset configuration provided by other files.
2050 @section Types of Reset
2052 There are many kinds of reset possible through JTAG, but
2053 they may not all work with a given board and adapter.
2054 That's part of why reset configuration can be error prone.
2058 @emph{System Reset} ... the @emph{SRST} hardware signal
2059 resets all chips connected to the JTAG adapter, such as processors,
2060 power management chips, and I/O controllers. Normally resets triggered
2061 with this signal behave exactly like pressing a RESET button.
2063 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2064 just the TAP controllers connected to the JTAG adapter.
2065 Such resets should not be visible to the rest of the system; resetting a
2066 device's the TAP controller just puts that controller into a known state.
2068 @emph{Emulation Reset} ... many devices can be reset through JTAG
2069 commands. These resets are often distinguishable from system
2070 resets, either explicitly (a "reset reason" register says so)
2071 or implicitly (not all parts of the chip get reset).
2073 @emph{Other Resets} ... system-on-chip devices often support
2074 several other types of reset.
2075 You may need to arrange that a watchdog timer stops
2076 while debugging, preventing a watchdog reset.
2077 There may be individual module resets.
2080 In the best case, OpenOCD can hold SRST, then reset
2081 the TAPs via TRST and send commands through JTAG to halt the
2082 CPU at the reset vector before the 1st instruction is executed.
2083 Then when it finally releases the SRST signal, the system is
2084 halted under debugger control before any code has executed.
2085 This is the behavior required to support the @command{reset halt}
2086 and @command{reset init} commands; after @command{reset init} a
2087 board-specific script might do things like setting up DRAM.
2088 (@xref{Reset Command}.)
2090 @anchor{SRST and TRST Issues}
2091 @section SRST and TRST Issues
2093 Because SRST and TRST are hardware signals, they can have a
2094 variety of system-specific constraints. Some of the most
2099 @item @emph{Signal not available} ... Some boards don't wire
2100 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2101 support such signals even if they are wired up.
2102 Use the @command{reset_config} @var{signals} options to say
2103 when either of those signals is not connected.
2104 When SRST is not available, your code might not be able to rely
2105 on controllers having been fully reset during code startup.
2106 Missing TRST is not a problem, since JTAG level resets can
2107 be triggered using with TMS signaling.
2109 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2110 adapter will connect SRST to TRST, instead of keeping them separate.
2111 Use the @command{reset_config} @var{combination} options to say
2112 when those signals aren't properly independent.
2114 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2115 delay circuit, reset supervisor, or on-chip features can extend
2116 the effect of a JTAG adapter's reset for some time after the adapter
2117 stops issuing the reset. For example, there may be chip or board
2118 requirements that all reset pulses last for at least a
2119 certain amount of time; and reset buttons commonly have
2120 hardware debouncing.
2121 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2122 commands to say when extra delays are needed.
2124 @item @emph{Drive type} ... Reset lines often have a pullup
2125 resistor, letting the JTAG interface treat them as open-drain
2126 signals. But that's not a requirement, so the adapter may need
2127 to use push/pull output drivers.
2128 Also, with weak pullups it may be advisable to drive
2129 signals to both levels (push/pull) to minimize rise times.
2130 Use the @command{reset_config} @var{trst_type} and
2131 @var{srst_type} parameters to say how to drive reset signals.
2133 @item @emph{Special initialization} ... Targets sometimes need
2134 special JTAG initialization sequences to handle chip-specific
2135 issues (not limited to errata).
2136 For example, certain JTAG commands might need to be issued while
2137 the system as a whole is in a reset state (SRST active)
2138 but the JTAG scan chain is usable (TRST inactive).
2139 (@xref{JTAG Commands}, where the @command{jtag_reset}
2140 command is presented.)
2143 There can also be other issues.
2144 Some devices don't fully conform to the JTAG specifications.
2145 Trivial system-specific differences are common, such as
2146 SRST and TRST using slightly different names.
2147 There are also vendors who distribute key JTAG documentation for
2148 their chips only to developers who have signed a Non-Disclosure
2151 Sometimes there are chip-specific extensions like a requirement to use
2152 the normally-optional TRST signal (precluding use of JTAG adapters which
2153 don't pass TRST through), or needing extra steps to complete a TAP reset.
2155 In short, SRST and especially TRST handling may be very finicky,
2156 needing to cope with both architecture and board specific constraints.
2158 @section Commands for Handling Resets
2160 @deffn {Command} jtag_nsrst_delay milliseconds
2161 How long (in milliseconds) OpenOCD should wait after deasserting
2162 nSRST (active-low system reset) before starting new JTAG operations.
2163 When a board has a reset button connected to SRST line it will
2164 probably have hardware debouncing, implying you should use this.
2167 @deffn {Command} jtag_ntrst_delay milliseconds
2168 How long (in milliseconds) OpenOCD should wait after deasserting
2169 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2172 @deffn {Command} reset_config mode_flag ...
2173 This command tells OpenOCD the reset configuration
2174 of your combination of JTAG board and target in target
2175 configuration scripts.
2177 Information earlier in this section describes the kind of problems
2178 the command is intended to address (@pxref{SRST and TRST Issues}).
2179 As a rule this command belongs only in board config files,
2180 describing issues like @emph{board doesn't connect TRST};
2181 or in user config files, addressing limitations derived
2182 from a particular combination of interface and board.
2183 (An unlikely example would be using a TRST-only adapter
2184 with a board that only wires up SRST.)
2186 The @var{mode_flag} options can be specified in any order, but only one
2187 of each type -- @var{signals}, @var{combination}, @var{trst_type},
2188 and @var{srst_type} -- may be specified at a time.
2189 If you don't provide a new value for a given type, its previous
2190 value (perhaps the default) is unchanged.
2191 For example, this means that you don't need to say anything at all about
2192 TRST just to declare that if the JTAG adapter should want to drive SRST,
2193 it must explicitly be driven high (@option{srst_push_pull}).
2195 @var{signals} can specify which of the reset signals are connected.
2196 For example, If the JTAG interface provides SRST, but the board doesn't
2197 connect that signal properly, then OpenOCD can't use it.
2198 Possible values are @option{none} (the default), @option{trst_only},
2199 @option{srst_only} and @option{trst_and_srst}.
2202 If your board provides SRST or TRST through the JTAG connector,
2203 you must declare that or else those signals will not be used.
2206 The @var{combination} is an optional value specifying broken reset
2207 signal implementations.
2208 The default behaviour if no option given is @option{separate},
2209 indicating everything behaves normally.
2210 @option{srst_pulls_trst} states that the
2211 test logic is reset together with the reset of the system (e.g. Philips
2212 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2213 the system is reset together with the test logic (only hypothetical, I
2214 haven't seen hardware with such a bug, and can be worked around).
2215 @option{combined} implies both @option{srst_pulls_trst} and
2216 @option{trst_pulls_srst}.
2218 The optional @var{trst_type} and @var{srst_type} parameters allow the
2219 driver mode of each reset line to be specified. These values only affect
2220 JTAG interfaces with support for different driver modes, like the Amontec
2221 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2222 relevant signal (TRST or SRST) is not connected.
2224 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2225 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2226 Most boards connect this signal to a pulldown, so the JTAG TAPs
2227 never leave reset unless they are hooked up to a JTAG adapter.
2229 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2230 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2231 Most boards connect this signal to a pullup, and allow the
2232 signal to be pulled low by various events including system
2233 powerup and pressing a reset button.
2237 @node TAP Declaration
2238 @chapter TAP Declaration
2239 @cindex TAP declaration
2240 @cindex TAP configuration
2242 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2243 TAPs serve many roles, including:
2246 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2247 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2248 Others do it indirectly, making a CPU do it.
2249 @item @b{Program Download} Using the same CPU support GDB uses,
2250 you can initialize a DRAM controller, download code to DRAM, and then
2251 start running that code.
2252 @item @b{Boundary Scan} Most chips support boundary scan, which
2253 helps test for board assembly problems like solder bridges
2254 and missing connections
2257 OpenOCD must know about the active TAPs on your board(s).
2258 Setting up the TAPs is the core task of your configuration files.
2259 Once those TAPs are set up, you can pass their names to code
2260 which sets up CPUs and exports them as GDB targets,
2261 probes flash memory, performs low-level JTAG operations, and more.
2263 @section Scan Chains
2266 TAPs are part of a hardware @dfn{scan chain},
2267 which is daisy chain of TAPs.
2268 They also need to be added to
2269 OpenOCD's software mirror of that hardware list,
2270 giving each member a name and associating other data with it.
2271 Simple scan chains, with a single TAP, are common in
2272 systems with a single microcontroller or microprocessor.
2273 More complex chips may have several TAPs internally.
2274 Very complex scan chains might have a dozen or more TAPs:
2275 several in one chip, more in the next, and connecting
2276 to other boards with their own chips and TAPs.
2278 You can display the list with the @command{scan_chain} command.
2279 (Don't confuse this with the list displayed by the @command{targets}
2280 command, presented in the next chapter.
2281 That only displays TAPs for CPUs which are configured as
2283 Here's what the scan chain might look like for a chip more than one TAP:
2286 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2287 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2288 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2289 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2290 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2293 Unfortunately those TAPs can't always be autoconfigured,
2294 because not all devices provide good support for that.
2295 JTAG doesn't require supporting IDCODE instructions, and
2296 chips with JTAG routers may not link TAPs into the chain
2297 until they are told to do so.
2299 The configuration mechanism currently supported by OpenOCD
2300 requires explicit configuration of all TAP devices using
2301 @command{jtag newtap} commands, as detailed later in this chapter.
2302 A command like this would declare one tap and name it @code{chip1.cpu}:
2305 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2308 Each target configuration file lists the TAPs provided
2310 Board configuration files combine all the targets on a board,
2312 Note that @emph{the order in which TAPs are declared is very important.}
2313 It must match the order in the JTAG scan chain, both inside
2314 a single chip and between them.
2315 @xref{FAQ TAP Order}.
2317 For example, the ST Microsystems STR912 chip has
2318 three separate TAPs@footnote{See the ST
2319 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2320 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2321 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2322 To configure those taps, @file{target/str912.cfg}
2323 includes commands something like this:
2326 jtag newtap str912 flash ... params ...
2327 jtag newtap str912 cpu ... params ...
2328 jtag newtap str912 bs ... params ...
2331 Actual config files use a variable instead of literals like
2332 @option{str912}, to support more than one chip of each type.
2333 @xref{Config File Guidelines}.
2335 At this writing there is only a single command to work with
2336 scan chains, and there is no support for enumerating
2337 TAPs or examining their attributes.
2339 @deffn Command {scan_chain}
2340 Displays the TAPs in the scan chain configuration,
2342 The set of TAPs listed by this command is fixed by
2343 exiting the OpenOCD configuration stage,
2344 but systems with a JTAG router can
2345 enable or disable TAPs dynamically.
2346 In addition to the enable/disable status, the contents of
2347 each TAP's instruction register can also change.
2350 @c FIXME! there should be commands to enumerate TAPs
2351 @c and get their attributes, like there are for targets.
2352 @c "jtag cget ..." will handle attributes.
2353 @c "jtag names" for enumerating TAPs, maybe.
2355 @c Probably want "jtag eventlist", and a "tap-reset" event
2356 @c (on entry to RESET state).
2361 When TAP objects are declared with @command{jtag newtap},
2362 a @dfn{dotted.name} is created for the TAP, combining the
2363 name of a module (usually a chip) and a label for the TAP.
2364 For example: @code{xilinx.tap}, @code{str912.flash},
2365 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2366 Many other commands use that dotted.name to manipulate or
2367 refer to the TAP. For example, CPU configuration uses the
2368 name, as does declaration of NAND or NOR flash banks.
2370 The components of a dotted name should follow ``C'' symbol
2371 name rules: start with an alphabetic character, then numbers
2372 and underscores are OK; while others (including dots!) are not.
2375 In older code, JTAG TAPs were numbered from 0..N.
2376 This feature is still present.
2377 However its use is highly discouraged, and
2378 should not be counted upon.
2379 Update all of your scripts to use TAP names rather than numbers.
2380 Using TAP numbers in target configuration scripts prevents
2381 reusing those scripts on boards with multiple targets.
2384 @section TAP Declaration Commands
2386 @c shouldn't this be(come) a {Config Command}?
2387 @anchor{jtag newtap}
2388 @deffn Command {jtag newtap} chipname tapname configparams...
2389 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2390 and configured according to the various @var{configparams}.
2392 The @var{chipname} is a symbolic name for the chip.
2393 Conventionally target config files use @code{$_CHIPNAME},
2394 defaulting to the model name given by the chip vendor but
2397 @cindex TAP naming convention
2398 The @var{tapname} reflects the role of that TAP,
2399 and should follow this convention:
2402 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2403 @item @code{cpu} -- The main CPU of the chip, alternatively
2404 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2405 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2406 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2407 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2408 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2409 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2410 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2412 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2413 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2414 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2415 a JTAG TAP; that TAP should be named @code{sdma}.
2418 Every TAP requires at least the following @var{configparams}:
2421 @item @code{-ircapture} @var{NUMBER}
2422 @*The IDCODE capture command, such as 0x01.
2423 @item @code{-irlen} @var{NUMBER}
2424 @*The length in bits of the
2425 instruction register, such as 4 or 5 bits.
2426 @item @code{-irmask} @var{NUMBER}
2427 @*A mask for the IR register.
2428 For some devices, there are bits in the IR that aren't used.
2429 This lets OpenOCD mask them off when doing IDCODE comparisons.
2430 In general, this should just be all ones for the size of the IR.
2433 A TAP may also provide optional @var{configparams}:
2436 @item @code{-disable} (or @code{-enable})
2437 @*Use the @code{-disable} parameter to flag a TAP which is not
2438 linked in to the scan chain after a reset using either TRST
2439 or the JTAG state machine's @sc{reset} state.
2440 You may use @code{-enable} to highlight the default state
2441 (the TAP is linked in).
2442 @xref{Enabling and Disabling TAPs}.
2443 @item @code{-expected-id} @var{number}
2444 @*A non-zero value represents the expected 32-bit IDCODE
2445 found when the JTAG chain is examined.
2446 These codes are not required by all JTAG devices.
2447 @emph{Repeat the option} as many times as required if more than one
2448 ID code could appear (for example, multiple versions).
2452 @c @deffn Command {jtag arp_init-reset}
2453 @c ... more or less "init" ?
2455 @anchor{Enabling and Disabling TAPs}
2456 @section Enabling and Disabling TAPs
2458 @cindex JTAG Route Controller
2461 In some systems, a @dfn{JTAG Route Controller} (JRC)
2462 is used to enable and/or disable specific JTAG TAPs.
2463 Many ARM based chips from Texas Instruments include
2464 an ``ICEpick'' module, which is a JRC.
2465 Such chips include DaVinci and OMAP3 processors.
2467 A given TAP may not be visible until the JRC has been
2468 told to link it into the scan chain; and if the JRC
2469 has been told to unlink that TAP, it will no longer
2471 Such routers address problems that JTAG ``bypass mode''
2475 @item The scan chain can only go as fast as its slowest TAP.
2476 @item Having many TAPs slows instruction scans, since all
2477 TAPs receive new instructions.
2478 @item TAPs in the scan chain must be powered up, which wastes
2479 power and prevents debugging some power management mechanisms.
2482 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2483 as implied by the existence of JTAG routers.
2484 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2485 does include a kind of JTAG router functionality.
2487 @c (a) currently the event handlers don't seem to be able to
2488 @c fail in a way that could lead to no-change-of-state.
2489 @c (b) eventually non-event configuration should be possible,
2490 @c in which case some this documentation must move.
2492 @deffn Command {jtag cget} dotted.name @option{-event} name
2493 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2494 At this writing this mechanism is used only for event handling,
2495 and the only two events relate to TAP enabling and disabling.
2497 The @code{configure} subcommand assigns an event handler,
2498 a TCL string which is evaluated when the event is triggered.
2499 The @code{cget} subcommand returns that handler.
2500 The two possible values for an event @var{name}
2501 are @option{tap-disable} and @option{tap-enable}.
2503 So for example, when defining a TAP for a CPU connected to
2504 a JTAG router, you should define TAP event handlers using
2505 code that looks something like this:
2508 jtag configure CHIP.cpu -event tap-enable @{
2509 echo "Enabling CPU TAP"
2510 ... jtag operations using CHIP.jrc
2512 jtag configure CHIP.cpu -event tap-disable @{
2513 echo "Disabling CPU TAP"
2514 ... jtag operations using CHIP.jrc
2519 @deffn Command {jtag tapdisable} dotted.name
2520 @deffnx Command {jtag tapenable} dotted.name
2521 @deffnx Command {jtag tapisenabled} dotted.name
2522 These three commands all return the string "1" if the tap
2523 specified by @var{dotted.name} is enabled,
2524 and "0" if it is disbabled.
2525 The @command{tapenable} variant first enables the tap
2526 by sending it a @option{tap-enable} event.
2527 The @command{tapdisable} variant first disables the tap
2528 by sending it a @option{tap-disable} event.
2531 Humans will find the @command{scan_chain} command more helpful
2532 than the script-oriented @command{tapisenabled}
2533 for querying the state of the JTAG taps.
2537 @node CPU Configuration
2538 @chapter CPU Configuration
2541 This chapter discusses how to set up GDB debug targets for CPUs.
2542 You can also access these targets without GDB
2543 (@pxref{Architecture and Core Commands},
2544 and @ref{Target State handling}) and
2545 through various kinds of NAND and NOR flash commands.
2546 If you have multiple CPUs you can have multiple such targets.
2548 We'll start by looking at how to examine the targets you have,
2549 then look at how to add one more target and how to configure it.
2551 @section Target List
2552 @cindex target, current
2553 @cindex target, list
2555 All targets that have been set up are part of a list,
2556 where each member has a name.
2557 That name should normally be the same as the TAP name.
2558 You can display the list with the @command{targets}
2560 This display often has only one CPU; here's what it might
2561 look like with more than one:
2563 TargetName Type Endian TapName State
2564 -- ------------------ ---------- ------ ------------------ ------------
2565 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2566 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2569 One member of that list is the @dfn{current target}, which
2570 is implicitly referenced by many commands.
2571 It's the one marked with a @code{*} near the target name.
2572 In particular, memory addresses often refer to the address
2573 space seen by that current target.
2574 Commands like @command{mdw} (memory display words)
2575 and @command{flash erase_address} (erase NOR flash blocks)
2576 are examples; and there are many more.
2578 Several commands let you examine the list of targets:
2580 @deffn Command {target count}
2581 Returns the number of targets, @math{N}.
2582 The highest numbered target is @math{N - 1}.
2584 set c [target count]
2585 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2586 # Assuming you have created this function
2587 print_target_details $x
2592 @deffn Command {target current}
2593 Returns the name of the current target.
2596 @deffn Command {target names}
2597 Lists the names of all current targets in the list.
2599 foreach t [target names] @{
2600 puts [format "Target: %s\n" $t]
2605 @deffn Command {target number} number
2606 The list of targets is numbered starting at zero.
2607 This command returns the name of the target at index @var{number}.
2609 set thename [target number $x]
2610 puts [format "Target %d is: %s\n" $x $thename]
2614 @c yep, "target list" would have been better.
2615 @c plus maybe "target setdefault".
2617 @deffn Command targets [name]
2618 @emph{Note: the name of this command is plural. Other target
2619 command names are singular.}
2621 With no parameter, this command displays a table of all known
2622 targets in a user friendly form.
2624 With a parameter, this command sets the current target to
2625 the given target with the given @var{name}; this is
2626 only relevant on boards which have more than one target.
2629 @section Target CPU Types and Variants
2634 Each target has a @dfn{CPU type}, as shown in the output of
2635 the @command{targets} command. You need to specify that type
2636 when calling @command{target create}.
2637 The CPU type indicates more than just the instruction set.
2638 It also indicates how that instruction set is implemented,
2639 what kind of debug support it integrates,
2640 whether it has an MMU (and if so, what kind),
2641 what core-specific commands may be available
2642 (@pxref{Architecture and Core Commands}),
2645 For some CPU types, OpenOCD also defines @dfn{variants} which
2646 indicate differences that affect their handling.
2647 For example, a particular implementation bug might need to be
2648 worked around in some chip versions.
2650 It's easy to see what target types are supported,
2651 since there's a command to list them.
2652 However, there is currently no way to list what target variants
2653 are supported (other than by reading the OpenOCD source code).
2655 @anchor{target types}
2656 @deffn Command {target types}
2657 Lists all supported target types.
2658 At this writing, the supported CPU types and variants are:
2661 @item @code{arm11} -- this is a generation of ARMv6 cores
2662 @item @code{arm720t} -- this is an ARMv4 core
2663 @item @code{arm7tdmi} -- this is an ARMv4 core
2664 @item @code{arm920t} -- this is an ARMv5 core
2665 @item @code{arm926ejs} -- this is an ARMv5 core
2666 @item @code{arm966e} -- this is an ARMv5 core
2667 @item @code{arm9tdmi} -- this is an ARMv4 core
2668 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2669 (Support for this is preliminary and incomplete.)
2670 @item @code{cortex_a8} -- this is an ARMv7 core
2671 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2672 compact Thumb2 instruction set. It supports one variant:
2674 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2675 This will cause OpenOCD to use a software reset rather than asserting
2676 SRST, to avoid a issue with clearing the debug registers.
2677 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2678 be detected and the normal reset behaviour used.
2680 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2681 @item @code{feroceon} -- resembles arm926
2682 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2684 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2685 provide a functional SRST line on the EJTAG connector. This causes
2686 OpenOCD to instead use an EJTAG software reset command to reset the
2688 You still need to enable @option{srst} on the @command{reset_config}
2689 command to enable OpenOCD hardware reset functionality.
2691 @item @code{xscale} -- this is actually an architecture,
2692 not a CPU type. It is based on the ARMv5 architecture.
2693 There are several variants defined:
2695 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2696 @code{pxa27x} ... instruction register length is 7 bits
2697 @item @code{pxa250}, @code{pxa255},
2698 @code{pxa26x} ... instruction register length is 5 bits
2703 To avoid being confused by the variety of ARM based cores, remember
2704 this key point: @emph{ARM is a technology licencing company}.
2705 (See: @url{http://www.arm.com}.)
2706 The CPU name used by OpenOCD will reflect the CPU design that was
2707 licenced, not a vendor brand which incorporates that design.
2708 Name prefixes like arm7, arm9, arm11, and cortex
2709 reflect design generations;
2710 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2711 reflect an architecture version implemented by a CPU design.
2713 @anchor{Target Configuration}
2714 @section Target Configuration
2716 Before creating a ``target'', you must have added its TAP to the scan chain.
2717 When you've added that TAP, you will have a @code{dotted.name}
2718 which is used to set up the CPU support.
2719 The chip-specific configuration file will normally configure its CPU(s)
2720 right after it adds all of the chip's TAPs to the scan chain.
2722 Although you can set up a target in one step, it's often clearer if you
2723 use shorter commands and do it in two steps: create it, then configure
2725 All operations on the target after it's created will use a new
2726 command, created as part of target creation.
2728 The two main things to configure after target creation are
2729 a work area, which usually has target-specific defaults even
2730 if the board setup code overrides them later;
2731 and event handlers (@pxref{Target Events}), which tend
2732 to be much more board-specific.
2733 The key steps you use might look something like this
2736 target create MyTarget cortex_m3 -chain-position mychip.cpu
2737 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2738 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2739 $MyTarget configure -event reset-init @{ myboard_reinit @}
2742 You should specify a working area if you can; typically it uses some
2744 Such a working area can speed up many things, including bulk
2745 writes to target memory;
2746 flash operations like checking to see if memory needs to be erased;
2747 GDB memory checksumming;
2751 On more complex chips, the work area can become
2752 inaccessible when application code
2753 (such as an operating system)
2754 enables or disables the MMU.
2755 For example, the particular MMU context used to acess the virtual
2756 address will probably matter ... and that context might not have
2757 easy access to other addresses needed.
2758 At this writing, OpenOCD doesn't have much MMU intelligence.
2761 It's often very useful to define a @code{reset-init} event handler.
2762 For systems that are normally used with a boot loader,
2763 common tasks include updating clocks and initializing memory
2765 That may be needed to let you write the boot loader into flash,
2766 in order to ``de-brick'' your board; or to load programs into
2767 external DDR memory without having run the boot loader.
2769 @deffn Command {target create} target_name type configparams...
2770 This command creates a GDB debug target that refers to a specific JTAG tap.
2771 It enters that target into a list, and creates a new
2772 command (@command{@var{target_name}}) which is used for various
2773 purposes including additional configuration.
2776 @item @var{target_name} ... is the name of the debug target.
2777 By convention this should be the same as the @emph{dotted.name}
2778 of the TAP associated with this target, which must be specified here
2779 using the @code{-chain-position @var{dotted.name}} configparam.
2781 This name is also used to create the target object command,
2782 referred to here as @command{$target_name},
2783 and in other places the target needs to be identified.
2784 @item @var{type} ... specifies the target type. @xref{target types}.
2785 @item @var{configparams} ... all parameters accepted by
2786 @command{$target_name configure} are permitted.
2787 If the target is big-endian, set it here with @code{-endian big}.
2788 If the variant matters, set it here with @code{-variant}.
2790 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2794 @deffn Command {$target_name configure} configparams...
2795 The options accepted by this command may also be
2796 specified as parameters to @command{target create}.
2797 Their values can later be queried one at a time by
2798 using the @command{$target_name cget} command.
2800 @emph{Warning:} changing some of these after setup is dangerous.
2801 For example, moving a target from one TAP to another;
2802 and changing its endianness or variant.
2806 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2807 used to access this target.
2809 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2810 whether the CPU uses big or little endian conventions
2812 @item @code{-event} @var{event_name} @var{event_body} --
2813 @xref{Target Events}.
2814 Note that this updates a list of named event handlers.
2815 Calling this twice with two different event names assigns
2816 two different handlers, but calling it twice with the
2817 same event name assigns only one handler.
2819 @item @code{-variant} @var{name} -- specifies a variant of the target,
2820 which OpenOCD needs to know about.
2822 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2823 whether the work area gets backed up; by default, it doesn't.
2824 When possible, use a working_area that doesn't need to be backed up,
2825 since performing a backup slows down operations.
2827 @item @code{-work-area-size} @var{size} -- specify/set the work area
2829 @item @code{-work-area-phys} @var{address} -- set the work area
2830 base @var{address} to be used when no MMU is active.
2832 @item @code{-work-area-virt} @var{address} -- set the work area
2833 base @var{address} to be used when an MMU is active.
2838 @section Other $target_name Commands
2839 @cindex object command
2841 The Tcl/Tk language has the concept of object commands,
2842 and OpenOCD adopts that same model for targets.
2844 A good Tk example is a on screen button.
2845 Once a button is created a button
2846 has a name (a path in Tk terms) and that name is useable as a first
2847 class command. For example in Tk, one can create a button and later
2848 configure it like this:
2852 button .foobar -background red -command @{ foo @}
2854 .foobar configure -foreground blue
2856 set x [.foobar cget -background]
2858 puts [format "The button is %s" $x]
2861 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2862 button, and its object commands are invoked the same way.
2865 str912.cpu mww 0x1234 0x42
2866 omap3530.cpu mww 0x5555 123
2869 The commands supported by OpenOCD target objects are:
2871 @deffn Command {$target_name arp_examine}
2872 @deffnx Command {$target_name arp_halt}
2873 @deffnx Command {$target_name arp_poll}
2874 @deffnx Command {$target_name arp_reset}
2875 @deffnx Command {$target_name arp_waitstate}
2876 Internal OpenOCD scripts (most notably @file{startup.tcl})
2877 use these to deal with specific reset cases.
2878 They are not otherwise documented here.
2881 @deffn Command {$target_name array2mem} arrayname width address count
2882 @deffnx Command {$target_name mem2array} arrayname width address count
2883 These provide an efficient script-oriented interface to memory.
2884 The @code{array2mem} primitive writes bytes, halfwords, or words;
2885 while @code{mem2array} reads them.
2886 In both cases, the TCL side uses an array, and
2887 the target side uses raw memory.
2889 The efficiency comes from enabling the use of
2890 bulk JTAG data transfer operations.
2891 The script orientation comes from working with data
2892 values that are packaged for use by TCL scripts;
2893 @command{mdw} type primitives only print data they retrieve,
2894 and neither store nor return those values.
2897 @item @var{arrayname} ... is the name of an array variable
2898 @item @var{width} ... is 8/16/32 - indicating the memory access size
2899 @item @var{address} ... is the target memory address
2900 @item @var{count} ... is the number of elements to process
2904 @deffn Command {$target_name cget} queryparm
2905 Each configuration parameter accepted by
2906 @command{$target_name configure}
2907 can be individually queried, to return its current value.
2908 The @var{queryparm} is a parameter name
2909 accepted by that command, such as @code{-work-area-phys}.
2910 There are a few special cases:
2913 @item @code{-event} @var{event_name} -- returns the handler for the
2914 event named @var{event_name}.
2915 This is a special case because setting a handler requires
2917 @item @code{-type} -- returns the target type.
2918 This is a special case because this is set using
2919 @command{target create} and can't be changed
2920 using @command{$target_name configure}.
2923 For example, if you wanted to summarize information about
2924 all the targets you might use something like this:
2927 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2928 set name [target number $x]
2929 set y [$name cget -endian]
2930 set z [$name cget -type]
2931 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2937 @anchor{target curstate}
2938 @deffn Command {$target_name curstate}
2939 Displays the current target state:
2940 @code{debug-running},
2943 @code{running}, or @code{unknown}.
2944 (Also, @pxref{Event Polling}.)
2947 @deffn Command {$target_name eventlist}
2948 Displays a table listing all event handlers
2949 currently associated with this target.
2950 @xref{Target Events}.
2953 @deffn Command {$target_name invoke-event} event_name
2954 Invokes the handler for the event named @var{event_name}.
2955 (This is primarily intended for use by OpenOCD framework
2956 code, for example by the reset code in @file{startup.tcl}.)
2959 @deffn Command {$target_name mdw} addr [count]
2960 @deffnx Command {$target_name mdh} addr [count]
2961 @deffnx Command {$target_name mdb} addr [count]
2962 Display contents of address @var{addr}, as
2963 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2964 or 8-bit bytes (@command{mdb}).
2965 If @var{count} is specified, displays that many units.
2966 (If you want to manipulate the data instead of displaying it,
2967 see the @code{mem2array} primitives.)
2970 @deffn Command {$target_name mww} addr word
2971 @deffnx Command {$target_name mwh} addr halfword
2972 @deffnx Command {$target_name mwb} addr byte
2973 Writes the specified @var{word} (32 bits),
2974 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2975 at the specified address @var{addr}.
2978 @anchor{Target Events}
2979 @section Target Events
2981 At various times, certain things can happen, or you want them to happen.
2984 @item What should happen when GDB connects? Should your target reset?
2985 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2986 @item During reset, do you need to write to certain memory locations
2987 to set up system clocks or
2988 to reconfigure the SDRAM?
2991 All of the above items can be addressed by target event handlers.
2992 These are set up by @command{$target_name configure -event} or
2993 @command{target create ... -event}.
2995 The programmer's model matches the @code{-command} option used in Tcl/Tk
2996 buttons and events. The two examples below act the same, but one creates
2997 and invokes a small procedure while the other inlines it.
3000 proc my_attach_proc @{ @} @{
3004 mychip.cpu configure -event gdb-attach my_attach_proc
3005 mychip.cpu configure -event gdb-attach @{
3011 The following target events are defined:
3014 @item @b{debug-halted}
3015 @* The target has halted for debug reasons (i.e.: breakpoint)
3016 @item @b{debug-resumed}
3017 @* The target has resumed (i.e.: gdb said run)
3018 @item @b{early-halted}
3019 @* Occurs early in the halt process
3021 @item @b{examine-end}
3022 @* Currently not used (goal: when JTAG examine completes)
3023 @item @b{examine-start}
3024 @* Currently not used (goal: when JTAG examine starts)
3026 @item @b{gdb-attach}
3027 @* When GDB connects
3028 @item @b{gdb-detach}
3029 @* When GDB disconnects
3031 @* When the target has halted and GDB is not doing anything (see early halt)
3032 @item @b{gdb-flash-erase-start}
3033 @* Before the GDB flash process tries to erase the flash
3034 @item @b{gdb-flash-erase-end}
3035 @* After the GDB flash process has finished erasing the flash
3036 @item @b{gdb-flash-write-start}
3037 @* Before GDB writes to the flash
3038 @item @b{gdb-flash-write-end}
3039 @* After GDB writes to the flash
3041 @* Before the target steps, gdb is trying to start/resume the target
3043 @* The target has halted
3045 @item @b{old-gdb_program_config}
3046 @* DO NOT USE THIS: Used internally
3047 @item @b{old-pre_resume}
3048 @* DO NOT USE THIS: Used internally
3050 @item @b{reset-assert-pre}
3051 @* Issued as part of @command{reset} processing
3052 after SRST and/or TRST were activated and deactivated,
3053 but before reset is asserted on the tap.
3054 @item @b{reset-assert-post}
3055 @* Issued as part of @command{reset} processing
3056 when reset is asserted on the tap.
3057 @item @b{reset-deassert-pre}
3058 @* Issued as part of @command{reset} processing
3059 when reset is about to be released on the tap.
3061 For some chips, this may be a good place to make sure
3062 the JTAG clock is slow enough to work before the PLL
3063 has been set up to allow faster JTAG speeds.
3064 @item @b{reset-deassert-post}
3065 @* Issued as part of @command{reset} processing
3066 when reset has been released on the tap.
3068 @* Issued as the final step in @command{reset} processing.
3070 @item @b{reset-halt-post}
3071 @* Currently not used
3072 @item @b{reset-halt-pre}
3073 @* Currently not used
3075 @item @b{reset-init}
3076 @* Used by @b{reset init} command for board-specific initialization.
3077 This event fires after @emph{reset-deassert-post}.
3079 This is where you would configure PLLs and clocking, set up DRAM so
3080 you can download programs that don't fit in on-chip SRAM, set up pin
3081 multiplexing, and so on.
3082 @item @b{reset-start}
3083 @* Issued as part of @command{reset} processing
3084 before either SRST or TRST are activated.
3086 @item @b{reset-wait-pos}
3087 @* Currently not used
3088 @item @b{reset-wait-pre}
3089 @* Currently not used
3091 @item @b{resume-start}
3092 @* Before any target is resumed
3093 @item @b{resume-end}
3094 @* After all targets have resumed
3098 @* Target has resumed
3102 @node Flash Commands
3103 @chapter Flash Commands
3105 OpenOCD has different commands for NOR and NAND flash;
3106 the ``flash'' command works with NOR flash, while
3107 the ``nand'' command works with NAND flash.
3108 This partially reflects different hardware technologies:
3109 NOR flash usually supports direct CPU instruction and data bus access,
3110 while data from a NAND flash must be copied to memory before it can be
3111 used. (SPI flash must also be copied to memory before use.)
3112 However, the documentation also uses ``flash'' as a generic term;
3113 for example, ``Put flash configuration in board-specific files''.
3117 @item Configure via the command @command{flash bank}
3118 @* Do this in a board-specific configuration file,
3119 passing parameters as needed by the driver.
3120 @item Operate on the flash via @command{flash subcommand}
3121 @* Often commands to manipulate the flash are typed by a human, or run
3122 via a script in some automated way. Common tasks include writing a
3123 boot loader, operating system, or other data.
3125 @* Flashing via GDB requires the flash be configured via ``flash
3126 bank'', and the GDB flash features be enabled.
3127 @xref{GDB Configuration}.
3130 Many CPUs have the ablity to ``boot'' from the first flash bank.
3131 This means that misprogramming that bank can ``brick'' a system,
3132 so that it can't boot.
3133 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3134 board by (re)installing working boot firmware.
3136 @anchor{NOR Configuration}
3137 @section Flash Configuration Commands
3138 @cindex flash configuration
3140 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3141 Configures a flash bank which provides persistent storage
3142 for addresses from @math{base} to @math{base + size - 1}.
3143 These banks will often be visible to GDB through the target's memory map.
3144 In some cases, configuring a flash bank will activate extra commands;
3145 see the driver-specific documentation.
3148 @item @var{driver} ... identifies the controller driver
3149 associated with the flash bank being declared.
3150 This is usually @code{cfi} for external flash, or else
3151 the name of a microcontroller with embedded flash memory.
3152 @xref{Flash Driver List}.
3153 @item @var{base} ... Base address of the flash chip.
3154 @item @var{size} ... Size of the chip, in bytes.
3155 For some drivers, this value is detected from the hardware.
3156 @item @var{chip_width} ... Width of the flash chip, in bytes;
3157 ignored for most microcontroller drivers.
3158 @item @var{bus_width} ... Width of the data bus used to access the
3159 chip, in bytes; ignored for most microcontroller drivers.
3160 @item @var{target} ... Names the target used to issue
3161 commands to the flash controller.
3162 @comment Actually, it's currently a controller-specific parameter...
3163 @item @var{driver_options} ... drivers may support, or require,
3164 additional parameters. See the driver-specific documentation
3165 for more information.
3168 This command is not available after OpenOCD initialization has completed.
3169 Use it in board specific configuration files, not interactively.
3173 @comment the REAL name for this command is "ocd_flash_banks"
3174 @comment less confusing would be: "flash list" (like "nand list")
3175 @deffn Command {flash banks}
3176 Prints a one-line summary of each device declared
3177 using @command{flash bank}, numbered from zero.
3178 Note that this is the @emph{plural} form;
3179 the @emph{singular} form is a very different command.
3182 @deffn Command {flash probe} num
3183 Identify the flash, or validate the parameters of the configured flash. Operation
3184 depends on the flash type.
3185 The @var{num} parameter is a value shown by @command{flash banks}.
3186 Most flash commands will implicitly @emph{autoprobe} the bank;
3187 flash drivers can distinguish between probing and autoprobing,
3188 but most don't bother.
3191 @section Erasing, Reading, Writing to Flash
3192 @cindex flash erasing
3193 @cindex flash reading
3194 @cindex flash writing
3195 @cindex flash programming
3197 One feature distinguishing NOR flash from NAND or serial flash technologies
3198 is that for read access, it acts exactly like any other addressible memory.
3199 This means you can use normal memory read commands like @command{mdw} or
3200 @command{dump_image} with it, with no special @command{flash} subcommands.
3201 @xref{Memory access}, and @ref{Image access}.
3203 Write access works differently. Flash memory normally needs to be erased
3204 before it's written. Erasing a sector turns all of its bits to ones, and
3205 writing can turn ones into zeroes. This is why there are special commands
3206 for interactive erasing and writing, and why GDB needs to know which parts
3207 of the address space hold NOR flash memory.
3210 Most of these erase and write commands leverage the fact that NOR flash
3211 chips consume target address space. They implicitly refer to the current
3212 JTAG target, and map from an address in that target's address space
3213 back to a flash bank.
3214 @comment In May 2009, those mappings may fail if any bank associated
3215 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3216 A few commands use abstract addressing based on bank and sector numbers,
3217 and don't depend on searching the current target and its address space.
3218 Avoid confusing the two command models.
3221 Some flash chips implement software protection against accidental writes,
3222 since such buggy writes could in some cases ``brick'' a system.
3223 For such systems, erasing and writing may require sector protection to be
3225 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3226 and AT91SAM7 on-chip flash.
3227 @xref{flash protect}.
3229 @anchor{flash erase_sector}
3230 @deffn Command {flash erase_sector} num first last
3231 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3232 @var{last}. Sector numbering starts at 0.
3233 The @var{num} parameter is a value shown by @command{flash banks}.
3236 @deffn Command {flash erase_address} address length
3237 Erase sectors starting at @var{address} for @var{length} bytes.
3238 The flash bank to use is inferred from the @var{address}, and
3239 the specified length must stay within that bank.
3240 As a special case, when @var{length} is zero and @var{address} is
3241 the start of the bank, the whole flash is erased.
3244 @deffn Command {flash fillw} address word length
3245 @deffnx Command {flash fillh} address halfword length
3246 @deffnx Command {flash fillb} address byte length
3247 Fills flash memory with the specified @var{word} (32 bits),
3248 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3249 starting at @var{address} and continuing
3250 for @var{length} units (word/halfword/byte).
3251 No erasure is done before writing; when needed, that must be done
3252 before issuing this command.
3253 Writes are done in blocks of up to 1024 bytes, and each write is
3254 verified by reading back the data and comparing it to what was written.
3255 The flash bank to use is inferred from the @var{address} of
3256 each block, and the specified length must stay within that bank.
3258 @comment no current checks for errors if fill blocks touch multiple banks!
3260 @anchor{flash write_bank}
3261 @deffn Command {flash write_bank} num filename offset
3262 Write the binary @file{filename} to flash bank @var{num},
3263 starting at @var{offset} bytes from the beginning of the bank.
3264 The @var{num} parameter is a value shown by @command{flash banks}.
3267 @anchor{flash write_image}
3268 @deffn Command {flash write_image} [erase] filename [offset] [type]
3269 Write the image @file{filename} to the current target's flash bank(s).
3270 A relocation @var{offset} may be specified, in which case it is added
3271 to the base address for each section in the image.
3272 The file [@var{type}] can be specified
3273 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3274 @option{elf} (ELF file), @option{s19} (Motorola s19).
3275 @option{mem}, or @option{builder}.
3276 The relevant flash sectors will be erased prior to programming
3277 if the @option{erase} parameter is given.
3278 The flash bank to use is inferred from the @var{address} of
3282 @section Other Flash commands
3283 @cindex flash protection
3285 @deffn Command {flash erase_check} num
3286 Check erase state of sectors in flash bank @var{num},
3287 and display that status.
3288 The @var{num} parameter is a value shown by @command{flash banks}.
3289 This is the only operation that
3290 updates the erase state information displayed by @option{flash info}. That means you have
3291 to issue an @command{flash erase_check} command after erasing or programming the device
3292 to get updated information.
3293 (Code execution may have invalidated any state records kept by OpenOCD.)
3296 @deffn Command {flash info} num
3297 Print info about flash bank @var{num}
3298 The @var{num} parameter is a value shown by @command{flash banks}.
3299 The information includes per-sector protect status.
3302 @anchor{flash protect}
3303 @deffn Command {flash protect} num first last (on|off)
3304 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3305 @var{first} to @var{last} of flash bank @var{num}.
3306 The @var{num} parameter is a value shown by @command{flash banks}.
3309 @deffn Command {flash protect_check} num
3310 Check protection state of sectors in flash bank @var{num}.
3311 The @var{num} parameter is a value shown by @command{flash banks}.
3312 @comment @option{flash erase_sector} using the same syntax.
3315 @anchor{Flash Driver List}
3316 @section Flash Drivers, Options, and Commands
3317 As noted above, the @command{flash bank} command requires a driver name,
3318 and allows driver-specific options and behaviors.
3319 Some drivers also activate driver-specific commands.
3321 @subsection External Flash
3323 @deffn {Flash Driver} cfi
3324 @cindex Common Flash Interface
3326 The ``Common Flash Interface'' (CFI) is the main standard for
3327 external NOR flash chips, each of which connects to a
3328 specific external chip select on the CPU.
3329 Frequently the first such chip is used to boot the system.
3330 Your board's @code{reset-init} handler might need to
3331 configure additional chip selects using other commands (like: @command{mww} to
3332 configure a bus and its timings) , or
3333 perhaps configure a GPIO pin that controls the ``write protect'' pin
3335 The CFI driver can use a target-specific working area to significantly
3338 The CFI driver can accept the following optional parameters, in any order:
3341 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3342 like AM29LV010 and similar types.
3343 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3346 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3347 wide on a sixteen bit bus:
3350 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3351 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3355 @subsection Internal Flash (Microcontrollers)
3357 @deffn {Flash Driver} aduc702x
3358 The ADUC702x analog microcontrollers from ST Micro
3359 include internal flash and use ARM7TDMI cores.
3360 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3361 The setup command only requires the @var{target} argument
3362 since all devices in this family have the same memory layout.
3365 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3369 @deffn {Flash Driver} at91sam7
3370 All members of the AT91SAM7 microcontroller family from Atmel
3371 include internal flash and use ARM7TDMI cores.
3372 The driver automatically recognizes a number of these chips using
3373 the chip identification register, and autoconfigures itself.
3376 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3379 For chips which are not recognized by the controller driver, you must
3380 provide additional parameters in the following order:
3383 @item @var{chip_model} ... label used with @command{flash info}
3385 @item @var{sectors_per_bank}
3386 @item @var{pages_per_sector}
3387 @item @var{pages_size}
3388 @item @var{num_nvm_bits}
3389 @item @var{freq_khz} ... required if an external clock is provided,
3390 optional (but recommended) when the oscillator frequency is known
3393 It is recommended that you provide zeroes for all of those values
3394 except the clock frequency, so that everything except that frequency
3395 will be autoconfigured.
3396 Knowing the frequency helps ensure correct timings for flash access.
3398 The flash controller handles erases automatically on a page (128/256 byte)
3399 basis, so explicit erase commands are not necessary for flash programming.
3400 However, there is an ``EraseAll`` command that can erase an entire flash
3401 plane (of up to 256KB), and it will be used automatically when you issue
3402 @command{flash erase_sector} or @command{flash erase_address} commands.
3404 @deffn Command {at91sam7 gpnvm} bitnum (set|clear)
3405 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3406 bit for the processor. Each processor has a number of such bits,
3407 used for controlling features such as brownout detection (so they
3408 are not truly general purpose).
3410 This assumes that the first flash bank (number 0) is associated with
3411 the appropriate at91sam7 target.
3416 @deffn {Flash Driver} avr
3417 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3418 @emph{The current implementation is incomplete.}
3419 @comment - defines mass_erase ... pointless given flash_erase_address
3422 @deffn {Flash Driver} ecosflash
3423 @emph{No idea what this is...}
3424 The @var{ecosflash} driver defines one mandatory parameter,
3425 the name of a modules of target code which is downloaded
3429 @deffn {Flash Driver} lpc2000
3430 Most members of the LPC2000 microcontroller family from NXP
3431 include internal flash and use ARM7TDMI cores.
3432 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3433 which must appear in the following order:
3436 @item @var{variant} ... required, may be
3437 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3438 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3439 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3440 at which the core is running
3441 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3442 telling the driver to calculate a valid checksum for the exception vector table.
3445 LPC flashes don't require the chip and bus width to be specified.
3448 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3449 lpc2000_v2 14765 calc_checksum
3453 @deffn {Flash Driver} lpc288x
3454 The LPC2888 microcontroller from NXP needs slightly different flash
3455 support from its lpc2000 siblings.
3456 The @var{lpc288x} driver defines one mandatory parameter,
3457 the programming clock rate in Hz.
3458 LPC flashes don't require the chip and bus width to be specified.
3461 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3465 @deffn {Flash Driver} ocl
3466 @emph{No idea what this is, other than using some arm7/arm9 core.}
3469 flash bank ocl 0 0 0 0 $_TARGETNAME
3473 @deffn {Flash Driver} pic32mx
3474 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3475 and integrate flash memory.
3476 @emph{The current implementation is incomplete.}
3479 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3482 @comment numerous *disabled* commands are defined:
3483 @comment - chip_erase ... pointless given flash_erase_address
3484 @comment - lock, unlock ... pointless given protect on/off (yes?)
3485 @comment - pgm_word ... shouldn't bank be deduced from address??
3486 Some pic32mx-specific commands are defined:
3487 @deffn Command {pic32mx pgm_word} address value bank
3488 Programs the specified 32-bit @var{value} at the given @var{address}
3489 in the specified chip @var{bank}.
3493 @deffn {Flash Driver} stellaris
3494 All members of the Stellaris LM3Sxxx microcontroller family from
3496 include internal flash and use ARM Cortex M3 cores.
3497 The driver automatically recognizes a number of these chips using
3498 the chip identification register, and autoconfigures itself.
3499 @footnote{Currently there is a @command{stellaris mass_erase} command.
3500 That seems pointless since the same effect can be had using the
3501 standard @command{flash erase_address} command.}
3504 flash bank stellaris 0 0 0 0 $_TARGETNAME
3508 @deffn {Flash Driver} stm32x
3509 All members of the STM32 microcontroller family from ST Microelectronics
3510 include internal flash and use ARM Cortex M3 cores.
3511 The driver automatically recognizes a number of these chips using
3512 the chip identification register, and autoconfigures itself.
3515 flash bank stm32x 0 0 0 0 $_TARGETNAME
3518 Some stm32x-specific commands
3519 @footnote{Currently there is a @command{stm32x mass_erase} command.
3520 That seems pointless since the same effect can be had using the
3521 standard @command{flash erase_address} command.}
3524 @deffn Command {stm32x lock} num
3525 Locks the entire stm32 device.
3526 The @var{num} parameter is a value shown by @command{flash banks}.
3529 @deffn Command {stm32x unlock} num
3530 Unlocks the entire stm32 device.
3531 The @var{num} parameter is a value shown by @command{flash banks}.
3534 @deffn Command {stm32x options_read} num
3535 Read and display the stm32 option bytes written by
3536 the @command{stm32x options_write} command.
3537 The @var{num} parameter is a value shown by @command{flash banks}.
3540 @deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
3541 Writes the stm32 option byte with the specified values.
3542 The @var{num} parameter is a value shown by @command{flash banks}.
3546 @deffn {Flash Driver} str7x
3547 All members of the STR7 microcontroller family from ST Microelectronics
3548 include internal flash and use ARM7TDMI cores.
3549 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3550 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3553 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3557 @deffn {Flash Driver} str9x
3558 Most members of the STR9 microcontroller family from ST Microelectronics
3559 include internal flash and use ARM966E cores.
3560 The str9 needs the flash controller to be configured using
3561 the @command{str9x flash_config} command prior to Flash programming.
3564 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3565 str9x flash_config 0 4 2 0 0x80000
3568 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3569 Configures the str9 flash controller.
3570 The @var{num} parameter is a value shown by @command{flash banks}.
3573 @item @var{bbsr} - Boot Bank Size register
3574 @item @var{nbbsr} - Non Boot Bank Size register
3575 @item @var{bbadr} - Boot Bank Start Address register
3576 @item @var{nbbadr} - Boot Bank Start Address register
3582 @deffn {Flash Driver} tms470
3583 Most members of the TMS470 microcontroller family from Texas Instruments
3584 include internal flash and use ARM7TDMI cores.
3585 This driver doesn't require the chip and bus width to be specified.
3587 Some tms470-specific commands are defined:
3589 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3590 Saves programming keys in a register, to enable flash erase and write commands.
3593 @deffn Command {tms470 osc_mhz} clock_mhz
3594 Reports the clock speed, which is used to calculate timings.
3597 @deffn Command {tms470 plldis} (0|1)
3598 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3603 @subsection str9xpec driver
3606 Here is some background info to help
3607 you better understand how this driver works. OpenOCD has two flash drivers for
3611 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3612 flash programming as it is faster than the @option{str9xpec} driver.
3614 Direct programming @option{str9xpec} using the flash controller. This is an
3615 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3616 core does not need to be running to program using this flash driver. Typical use
3617 for this driver is locking/unlocking the target and programming the option bytes.
3620 Before we run any commands using the @option{str9xpec} driver we must first disable
3621 the str9 core. This example assumes the @option{str9xpec} driver has been
3622 configured for flash bank 0.
3624 # assert srst, we do not want core running
3625 # while accessing str9xpec flash driver
3627 # turn off target polling
3630 str9xpec enable_turbo 0
3632 str9xpec options_read 0
3633 # re-enable str9 core
3634 str9xpec disable_turbo 0
3638 The above example will read the str9 option bytes.
3639 When performing a unlock remember that you will not be able to halt the str9 - it
3640 has been locked. Halting the core is not required for the @option{str9xpec} driver
3641 as mentioned above, just issue the commands above manually or from a telnet prompt.
3643 @deffn {Flash Driver} str9xpec
3644 Only use this driver for locking/unlocking the device or configuring the option bytes.
3645 Use the standard str9 driver for programming.
3646 Before using the flash commands the turbo mode must be enabled using the
3647 @command{str9xpec enable_turbo} command.
3649 Several str9xpec-specific commands are defined:
3651 @deffn Command {str9xpec disable_turbo} num
3652 Restore the str9 into JTAG chain.
3655 @deffn Command {str9xpec enable_turbo} num
3656 Enable turbo mode, will simply remove the str9 from the chain and talk
3657 directly to the embedded flash controller.
3660 @deffn Command {str9xpec lock} num
3661 Lock str9 device. The str9 will only respond to an unlock command that will
3665 @deffn Command {str9xpec part_id} num
3666 Prints the part identifier for bank @var{num}.
3669 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3670 Configure str9 boot bank.
3673 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3674 Configure str9 lvd source.
3677 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3678 Configure str9 lvd threshold.
3681 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3682 Configure str9 lvd reset warning source.
3685 @deffn Command {str9xpec options_read} num
3686 Read str9 option bytes.
3689 @deffn Command {str9xpec options_write} num
3690 Write str9 option bytes.
3693 @deffn Command {str9xpec unlock} num
3702 @subsection mFlash Configuration
3703 @cindex mFlash Configuration
3705 @deffn {Config Command} {mflash bank} soc base RST_pin target
3706 Configures a mflash for @var{soc} host bank at
3708 The pin number format depends on the host GPIO naming convention.
3709 Currently, the mflash driver supports s3c2440 and pxa270.
3711 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3714 mflash bank s3c2440 0x10000000 1b 0
3717 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3720 mflash bank pxa270 0x08000000 43 0
3724 @subsection mFlash commands
3725 @cindex mFlash commands
3727 @deffn Command {mflash config pll} frequency
3728 Configure mflash PLL.
3729 The @var{frequency} is the mflash input frequency, in Hz.
3730 Issuing this command will erase mflash's whole internal nand and write new pll.
3731 After this command, mflash needs power-on-reset for normal operation.
3732 If pll was newly configured, storage and boot(optional) info also need to be update.
3735 @deffn Command {mflash config boot}
3736 Configure bootable option.
3737 If bootable option is set, mflash offer the first 8 sectors
3741 @deffn Command {mflash config storage}
3742 Configure storage information.
3743 For the normal storage operation, this information must be
3747 @deffn Command {mflash dump} num filename offset size
3748 Dump @var{size} bytes, starting at @var{offset} bytes from the
3749 beginning of the bank @var{num}, to the file named @var{filename}.
3752 @deffn Command {mflash probe}
3756 @deffn Command {mflash write} num filename offset
3757 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3758 @var{offset} bytes from the beginning of the bank.
3761 @node NAND Flash Commands
3762 @chapter NAND Flash Commands
3765 Compared to NOR or SPI flash, NAND devices are inexpensive
3766 and high density. Today's NAND chips, and multi-chip modules,
3767 commonly hold multiple GigaBytes of data.
3769 NAND chips consist of a number of ``erase blocks'' of a given
3770 size (such as 128 KBytes), each of which is divided into a
3771 number of pages (of perhaps 512 or 2048 bytes each). Each
3772 page of a NAND flash has an ``out of band'' (OOB) area to hold
3773 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3774 of OOB for every 512 bytes of page data.
3776 One key characteristic of NAND flash is that its error rate
3777 is higher than that of NOR flash. In normal operation, that
3778 ECC is used to correct and detect errors. However, NAND
3779 blocks can also wear out and become unusable; those blocks
3780 are then marked "bad". NAND chips are even shipped from the
3781 manufacturer with a few bad blocks. The highest density chips
3782 use a technology (MLC) that wears out more quickly, so ECC
3783 support is increasingly important as a way to detect blocks
3784 that have begun to fail, and help to preserve data integrity
3785 with techniques such as wear leveling.
3787 Software is used to manage the ECC. Some controllers don't
3788 support ECC directly; in those cases, software ECC is used.
3789 Other controllers speed up the ECC calculations with hardware.
3790 Single-bit error correction hardware is routine. Controllers
3791 geared for newer MLC chips may correct 4 or more errors for
3792 every 512 bytes of data.
3794 You will need to make sure that any data you write using
3795 OpenOCD includes the apppropriate kind of ECC. For example,
3796 that may mean passing the @code{oob_softecc} flag when
3797 writing NAND data, or ensuring that the correct hardware
3800 The basic steps for using NAND devices include:
3802 @item Declare via the command @command{nand device}
3803 @* Do this in a board-specific configuration file,
3804 passing parameters as needed by the controller.
3805 @item Configure each device using @command{nand probe}.
3806 @* Do this only after the associated target is set up,
3807 such as in its reset-init script or in procures defined
3808 to access that device.
3809 @item Operate on the flash via @command{nand subcommand}
3810 @* Often commands to manipulate the flash are typed by a human, or run
3811 via a script in some automated way. Common task include writing a
3812 boot loader, operating system, or other data needed to initialize or
3816 @b{NOTE:} At the time this text was written, the largest NAND
3817 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3818 This is because the variables used to hold offsets and lengths
3819 are only 32 bits wide.
3820 (Larger chips may work in some cases, unless an offset or length
3821 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3822 Some larger devices will work, since they are actually multi-chip
3823 modules with two smaller chips and individual chipselect lines.
3825 @anchor{NAND Configuration}
3826 @section NAND Configuration Commands
3827 @cindex NAND configuration
3829 NAND chips must be declared in configuration scripts,
3830 plus some additional configuration that's done after
3831 OpenOCD has initialized.
3833 @deffn {Config Command} {nand device} controller target [configparams...]
3834 Declares a NAND device, which can be read and written to
3835 after it has been configured through @command{nand probe}.
3836 In OpenOCD, devices are single chips; this is unlike some
3837 operating systems, which may manage multiple chips as if
3838 they were a single (larger) device.
3839 In some cases, configuring a device will activate extra
3840 commands; see the controller-specific documentation.
3842 @b{NOTE:} This command is not available after OpenOCD
3843 initialization has completed. Use it in board specific
3844 configuration files, not interactively.
3847 @item @var{controller} ... identifies the controller driver
3848 associated with the NAND device being declared.
3849 @xref{NAND Driver List}.
3850 @item @var{target} ... names the target used when issuing
3851 commands to the NAND controller.
3852 @comment Actually, it's currently a controller-specific parameter...
3853 @item @var{configparams} ... controllers may support, or require,
3854 additional parameters. See the controller-specific documentation
3855 for more information.
3859 @deffn Command {nand list}
3860 Prints a one-line summary of each device declared
3861 using @command{nand device}, numbered from zero.
3862 Note that un-probed devices show no details.
3865 @deffn Command {nand probe} num
3866 Probes the specified device to determine key characteristics
3867 like its page and block sizes, and how many blocks it has.
3868 The @var{num} parameter is the value shown by @command{nand list}.
3869 You must (successfully) probe a device before you can use
3870 it with most other NAND commands.
3873 @section Erasing, Reading, Writing to NAND Flash
3875 @deffn Command {nand dump} num filename offset length [oob_option]
3876 @cindex NAND reading
3877 Reads binary data from the NAND device and writes it to the file,
3878 starting at the specified offset.
3879 The @var{num} parameter is the value shown by @command{nand list}.
3881 Use a complete path name for @var{filename}, so you don't depend
3882 on the directory used to start the OpenOCD server.
3884 The @var{offset} and @var{length} must be exact multiples of the
3885 device's page size. They describe a data region; the OOB data
3886 associated with each such page may also be accessed.
3888 @b{NOTE:} At the time this text was written, no error correction
3889 was done on the data that's read, unless raw access was disabled
3890 and the underlying NAND controller driver had a @code{read_page}
3891 method which handled that error correction.
3893 By default, only page data is saved to the specified file.
3894 Use an @var{oob_option} parameter to save OOB data:
3896 @item no oob_* parameter
3897 @*Output file holds only page data; OOB is discarded.
3898 @item @code{oob_raw}
3899 @*Output file interleaves page data and OOB data;
3900 the file will be longer than "length" by the size of the
3901 spare areas associated with each data page.
3902 Note that this kind of "raw" access is different from
3903 what's implied by @command{nand raw_access}, which just
3904 controls whether a hardware-aware access method is used.
3905 @item @code{oob_only}
3906 @*Output file has only raw OOB data, and will
3907 be smaller than "length" since it will contain only the
3908 spare areas associated with each data page.
3912 @deffn Command {nand erase} num offset length
3913 @cindex NAND erasing
3914 @cindex NAND programming
3915 Erases blocks on the specified NAND device, starting at the
3916 specified @var{offset} and continuing for @var{length} bytes.
3917 Both of those values must be exact multiples of the device's
3918 block size, and the region they specify must fit entirely in the chip.
3919 The @var{num} parameter is the value shown by @command{nand list}.
3921 @b{NOTE:} This command will try to erase bad blocks, when told
3922 to do so, which will probably invalidate the manufacturer's bad
3924 For the remainder of the current server session, @command{nand info}
3925 will still report that the block ``is'' bad.
3928 @deffn Command {nand write} num filename offset [option...]
3929 @cindex NAND writing
3930 @cindex NAND programming
3931 Writes binary data from the file into the specified NAND device,
3932 starting at the specified offset. Those pages should already
3933 have been erased; you can't change zero bits to one bits.
3934 The @var{num} parameter is the value shown by @command{nand list}.
3936 Use a complete path name for @var{filename}, so you don't depend
3937 on the directory used to start the OpenOCD server.
3939 The @var{offset} must be an exact multiple of the device's page size.
3940 All data in the file will be written, assuming it doesn't run
3941 past the end of the device.
3942 Only full pages are written, and any extra space in the last
3943 page will be filled with 0xff bytes. (That includes OOB data,
3944 if that's being written.)
3946 @b{NOTE:} At the time this text was written, bad blocks are
3947 ignored. That is, this routine will not skip bad blocks,
3948 but will instead try to write them. This can cause problems.
3950 Provide at most one @var{option} parameter. With some
3951 NAND drivers, the meanings of these parameters may change
3952 if @command{nand raw_access} was used to disable hardware ECC.
3954 @item no oob_* parameter
3955 @*File has only page data, which is written.
3956 If raw acccess is in use, the OOB area will not be written.
3957 Otherwise, if the underlying NAND controller driver has
3958 a @code{write_page} routine, that routine may write the OOB
3959 with hardware-computed ECC data.
3960 @item @code{oob_only}
3961 @*File has only raw OOB data, which is written to the OOB area.
3962 Each page's data area stays untouched. @i{This can be a dangerous
3963 option}, since it can invalidate the ECC data.
3964 You may need to force raw access to use this mode.
3965 @item @code{oob_raw}
3966 @*File interleaves data and OOB data, both of which are written
3967 If raw access is enabled, the data is written first, then the
3969 Otherwise, if the underlying NAND controller driver has
3970 a @code{write_page} routine, that routine may modify the OOB
3971 before it's written, to include hardware-computed ECC data.
3972 @item @code{oob_softecc}
3973 @*File has only page data, which is written.
3974 The OOB area is filled with 0xff, except for a standard 1-bit
3975 software ECC code stored in conventional locations.
3976 You might need to force raw access to use this mode, to prevent
3977 the underlying driver from applying hardware ECC.
3978 @item @code{oob_softecc_kw}
3979 @*File has only page data, which is written.
3980 The OOB area is filled with 0xff, except for a 4-bit software ECC
3981 specific to the boot ROM in Marvell Kirkwood SoCs.
3982 You might need to force raw access to use this mode, to prevent
3983 the underlying driver from applying hardware ECC.
3987 @section Other NAND commands
3988 @cindex NAND other commands
3990 @deffn Command {nand check_bad_blocks} [offset length]
3991 Checks for manufacturer bad block markers on the specified NAND
3992 device. If no parameters are provided, checks the whole
3993 device; otherwise, starts at the specified @var{offset} and
3994 continues for @var{length} bytes.
3995 Both of those values must be exact multiples of the device's
3996 block size, and the region they specify must fit entirely in the chip.
3997 The @var{num} parameter is the value shown by @command{nand list}.
3999 @b{NOTE:} Before using this command you should force raw access
4000 with @command{nand raw_access enable} to ensure that the underlying
4001 driver will not try to apply hardware ECC.
4004 @deffn Command {nand info} num
4005 The @var{num} parameter is the value shown by @command{nand list}.
4006 This prints the one-line summary from "nand list", plus for
4007 devices which have been probed this also prints any known
4008 status for each block.
4011 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4012 Sets or clears an flag affecting how page I/O is done.
4013 The @var{num} parameter is the value shown by @command{nand list}.
4015 This flag is cleared (disabled) by default, but changing that
4016 value won't affect all NAND devices. The key factor is whether
4017 the underlying driver provides @code{read_page} or @code{write_page}
4018 methods. If it doesn't provide those methods, the setting of
4019 this flag is irrelevant; all access is effectively ``raw''.
4021 When those methods exist, they are normally used when reading
4022 data (@command{nand dump} or reading bad block markers) or
4023 writing it (@command{nand write}). However, enabling
4024 raw access (setting the flag) prevents use of those methods,
4025 bypassing hardware ECC logic.
4026 @i{This can be a dangerous option}, since writing blocks
4027 with the wrong ECC data can cause them to be marked as bad.
4030 @anchor{NAND Driver List}
4031 @section NAND Drivers, Options, and Commands
4032 As noted above, the @command{nand device} command allows
4033 driver-specific options and behaviors.
4034 Some controllers also activate controller-specific commands.
4036 @deffn {NAND Driver} davinci
4037 This driver handles the NAND controllers found on DaVinci family
4038 chips from Texas Instruments.
4039 It takes three extra parameters:
4040 address of the NAND chip;
4041 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
4042 address of the AEMIF controller on this processor.
4044 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4046 All DaVinci processors support the single-bit ECC hardware,
4047 and newer ones also support the four-bit ECC hardware.
4048 The @code{write_page} and @code{read_page} methods are used
4049 to implement those ECC modes, unless they are disabled using
4050 the @command{nand raw_access} command.
4053 @deffn {NAND Driver} lpc3180
4054 These controllers require an extra @command{nand device}
4055 parameter: the clock rate used by the controller.
4056 @deffn Command {lpc3180 select} num [mlc|slc]
4057 Configures use of the MLC or SLC controller mode.
4058 MLC implies use of hardware ECC.
4059 The @var{num} parameter is the value shown by @command{nand list}.
4062 At this writing, this driver includes @code{write_page}
4063 and @code{read_page} methods. Using @command{nand raw_access}
4064 to disable those methods will prevent use of hardware ECC
4065 in the MLC controller mode, but won't change SLC behavior.
4067 @comment current lpc3180 code won't issue 5-byte address cycles
4069 @deffn {NAND Driver} orion
4070 These controllers require an extra @command{nand device}
4071 parameter: the address of the controller.
4073 nand device orion 0xd8000000
4075 These controllers don't define any specialized commands.
4076 At this writing, their drivers don't include @code{write_page}
4077 or @code{read_page} methods, so @command{nand raw_access} won't
4078 change any behavior.
4081 @deffn {NAND Driver} s3c2410
4082 @deffnx {NAND Driver} s3c2412
4083 @deffnx {NAND Driver} s3c2440
4084 @deffnx {NAND Driver} s3c2443
4085 These S3C24xx family controllers don't have any special
4086 @command{nand device} options, and don't define any
4087 specialized commands.
4088 At this writing, their drivers don't include @code{write_page}
4089 or @code{read_page} methods, so @command{nand raw_access} won't
4090 change any behavior.
4093 @node PLD/FPGA Commands
4094 @chapter PLD/FPGA Commands
4098 Programmable Logic Devices (PLDs) and the more flexible
4099 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4100 OpenOCD can support programming them.
4101 Although PLDs are generally restrictive (cells are less functional, and
4102 there are no special purpose cells for memory or computational tasks),
4103 they share the same OpenOCD infrastructure.
4104 Accordingly, both are called PLDs here.
4106 @section PLD/FPGA Configuration and Commands
4108 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4109 OpenOCD maintains a list of PLDs available for use in various commands.
4110 Also, each such PLD requires a driver.
4112 They are referenced by the number shown by the @command{pld devices} command,
4113 and new PLDs are defined by @command{pld device driver_name}.
4115 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4116 Defines a new PLD device, supported by driver @var{driver_name},
4117 using the TAP named @var{tap_name}.
4118 The driver may make use of any @var{driver_options} to configure its
4122 @deffn {Command} {pld devices}
4123 Lists the PLDs and their numbers.
4126 @deffn {Command} {pld load} num filename
4127 Loads the file @file{filename} into the PLD identified by @var{num}.
4128 The file format must be inferred by the driver.
4131 @section PLD/FPGA Drivers, Options, and Commands
4133 Drivers may support PLD-specific options to the @command{pld device}
4134 definition command, and may also define commands usable only with
4135 that particular type of PLD.
4137 @deffn {FPGA Driver} virtex2
4138 Virtex-II is a family of FPGAs sold by Xilinx.
4139 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4140 No driver-specific PLD definition options are used,
4141 and one driver-specific command is defined.
4143 @deffn {Command} {virtex2 read_stat} num
4144 Reads and displays the Virtex-II status register (STAT)
4149 @node General Commands
4150 @chapter General Commands
4153 The commands documented in this chapter here are common commands that
4154 you, as a human, may want to type and see the output of. Configuration type
4155 commands are documented elsewhere.
4159 @item @b{Source Of Commands}
4160 @* OpenOCD commands can occur in a configuration script (discussed
4161 elsewhere) or typed manually by a human or supplied programatically,
4162 or via one of several TCP/IP Ports.
4164 @item @b{From the human}
4165 @* A human should interact with the telnet interface (default port: 4444)
4166 or via GDB (default port 3333).
4168 To issue commands from within a GDB session, use the @option{monitor}
4169 command, e.g. use @option{monitor poll} to issue the @option{poll}
4170 command. All output is relayed through the GDB session.
4172 @item @b{Machine Interface}
4173 The Tcl interface's intent is to be a machine interface. The default Tcl
4178 @section Daemon Commands
4180 @deffn Command sleep msec [@option{busy}]
4181 Wait for at least @var{msec} milliseconds before resuming.
4182 If @option{busy} is passed, busy-wait instead of sleeping.
4183 (This option is strongly discouraged.)
4184 Useful in connection with script files
4185 (@command{script} command and @command{target_name} configuration).
4188 @deffn Command shutdown
4189 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4192 @anchor{debug_level}
4193 @deffn Command debug_level [n]
4194 @cindex message level
4195 Display debug level.
4196 If @var{n} (from 0..3) is provided, then set it to that level.
4197 This affects the kind of messages sent to the server log.
4198 Level 0 is error messages only;
4199 level 1 adds warnings;
4200 level 2 adds informational messages;
4201 and level 3 adds debugging messages.
4202 The default is level 2, but that can be overridden on
4203 the command line along with the location of that log
4204 file (which is normally the server's standard output).
4208 @deffn Command fast (@option{enable}|@option{disable})
4210 Set default behaviour of OpenOCD to be "fast and dangerous".
4212 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4213 fast memory access, and DCC downloads. Those parameters may still be
4214 individually overridden.
4216 The target specific "dangerous" optimisation tweaking options may come and go
4217 as more robust and user friendly ways are found to ensure maximum throughput
4218 and robustness with a minimum of configuration.
4220 Typically the "fast enable" is specified first on the command line:
4223 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4227 @deffn Command echo message
4228 Logs a message at "user" priority.
4229 Output @var{message} to stdout.
4231 echo "Downloading kernel -- please wait"
4235 @deffn Command log_output [filename]
4236 Redirect logging to @var{filename};
4237 the initial log output channel is stderr.
4240 @anchor{Target State handling}
4241 @section Target State handling
4244 @cindex target initialization
4246 In this section ``target'' refers to a CPU configured as
4247 shown earlier (@pxref{CPU Configuration}).
4248 These commands, like many, implicitly refer to
4249 a current target which is used to perform the
4250 various operations. The current target may be changed
4251 by using @command{targets} command with the name of the
4252 target which should become current.
4254 @deffn Command reg [(number|name) [value]]
4255 Access a single register by @var{number} or by its @var{name}.
4257 @emph{With no arguments}:
4258 list all available registers for the current target,
4259 showing number, name, size, value, and cache status.
4261 @emph{With number/name}: display that register's value.
4263 @emph{With both number/name and value}: set register's value.
4265 Cores may have surprisingly many registers in their
4266 Debug and trace infrastructure:
4270 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4271 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4272 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4274 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4275 0x00000000 (dirty: 0, valid: 0)
4280 @deffn Command halt [ms]
4281 @deffnx Command wait_halt [ms]
4282 The @command{halt} command first sends a halt request to the target,
4283 which @command{wait_halt} doesn't.
4284 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4285 or 5 seconds if there is no parameter, for the target to halt
4286 (and enter debug mode).
4287 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4290 @deffn Command resume [address]
4291 Resume the target at its current code position,
4292 or the optional @var{address} if it is provided.
4293 OpenOCD will wait 5 seconds for the target to resume.
4296 @deffn Command step [address]
4297 Single-step the target at its current code position,
4298 or the optional @var{address} if it is provided.
4301 @anchor{Reset Command}
4302 @deffn Command reset
4303 @deffnx Command {reset run}
4304 @deffnx Command {reset halt}
4305 @deffnx Command {reset init}
4306 Perform as hard a reset as possible, using SRST if possible.
4307 @emph{All defined targets will be reset, and target
4308 events will fire during the reset sequence.}
4310 The optional parameter specifies what should
4311 happen after the reset.
4312 If there is no parameter, a @command{reset run} is executed.
4313 The other options will not work on all systems.
4314 @xref{Reset Configuration}.
4317 @item @b{run} Let the target run
4318 @item @b{halt} Immediately halt the target
4319 @item @b{init} Immediately halt the target, and execute the reset-init script
4323 @deffn Command soft_reset_halt
4324 Requesting target halt and executing a soft reset. This is often used
4325 when a target cannot be reset and halted. The target, after reset is
4326 released begins to execute code. OpenOCD attempts to stop the CPU and
4327 then sets the program counter back to the reset vector. Unfortunately
4328 the code that was executed may have left the hardware in an unknown
4332 @section I/O Utilities
4334 These commands are available when
4335 OpenOCD is built with @option{--enable-ioutil}.
4336 They are mainly useful on embedded targets;
4337 PC type hosts have complementary tools.
4339 @emph{Note:} there are several more such commands.
4341 @deffn Command meminfo
4342 Display available RAM memory on OpenOCD host.
4343 Used in OpenOCD regression testing scripts.
4346 @anchor{Memory access}
4347 @section Memory access commands
4348 @cindex memory access
4350 These commands allow accesses of a specific size to the memory
4351 system. Often these are used to configure the current target in some
4352 special way. For example - one may need to write certain values to the
4353 SDRAM controller to enable SDRAM.
4356 @item Use the @command{targets} (plural) command
4357 to change the current target.
4358 @item In system level scripts these commands are deprecated.
4359 Please use their TARGET object siblings to avoid making assumptions
4360 about what TAP is the current target, or about MMU configuration.
4363 @deffn Command mdw addr [count]
4364 @deffnx Command mdh addr [count]
4365 @deffnx Command mdb addr [count]
4366 Display contents of address @var{addr}, as
4367 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4368 or 8-bit bytes (@command{mdb}).
4369 If @var{count} is specified, displays that many units.
4370 (If you want to manipulate the data instead of displaying it,
4371 see the @code{mem2array} primitives.)
4374 @deffn Command mww addr word
4375 @deffnx Command mwh addr halfword
4376 @deffnx Command mwb addr byte
4377 Writes the specified @var{word} (32 bits),
4378 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4379 at the specified address @var{addr}.
4383 @anchor{Image access}
4384 @section Image loading commands
4385 @cindex image loading
4386 @cindex image dumping
4389 @deffn Command {dump_image} filename address size
4390 Dump @var{size} bytes of target memory starting at @var{address} to the
4391 binary file named @var{filename}.
4394 @deffn Command {fast_load}
4395 Loads an image stored in memory by @command{fast_load_image} to the
4396 current target. Must be preceeded by fast_load_image.
4399 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4400 Normally you should be using @command{load_image} or GDB load. However, for
4401 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4402 host), storing the image in memory and uploading the image to the target
4403 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4404 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4405 memory, i.e. does not affect target. This approach is also useful when profiling
4406 target programming performance as I/O and target programming can easily be profiled
4411 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4412 Load image from file @var{filename} to target memory at @var{address}.
4413 The file format may optionally be specified
4414 (@option{bin}, @option{ihex}, or @option{elf})
4417 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4418 Verify @var{filename} against target memory starting at @var{address}.
4419 The file format may optionally be specified
4420 (@option{bin}, @option{ihex}, or @option{elf})
4421 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4425 @section Breakpoint and Watchpoint commands
4429 CPUs often make debug modules accessible through JTAG, with
4430 hardware support for a handful of code breakpoints and data
4432 In addition, CPUs almost always support software breakpoints.
4434 @deffn Command {bp} [address len [@option{hw}]]
4435 With no parameters, lists all active breakpoints.
4436 Else sets a breakpoint on code execution starting
4437 at @var{address} for @var{length} bytes.
4438 This is a software breakpoint, unless @option{hw} is specified
4439 in which case it will be a hardware breakpoint.
4441 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4442 for similar mechanisms that do not consume hardware breakpoints.)
4445 @deffn Command {rbp} address
4446 Remove the breakpoint at @var{address}.
4449 @deffn Command {rwp} address
4450 Remove data watchpoint on @var{address}
4453 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4454 With no parameters, lists all active watchpoints.
4455 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4456 The watch point is an "access" watchpoint unless
4457 the @option{r} or @option{w} parameter is provided,
4458 defining it as respectively a read or write watchpoint.
4459 If a @var{value} is provided, that value is used when determining if
4460 the watchpoint should trigger. The value may be first be masked
4461 using @var{mask} to mark ``don't care'' fields.
4464 @section Misc Commands
4467 @deffn Command {profile} seconds filename
4468 Profiling samples the CPU's program counter as quickly as possible,
4469 which is useful for non-intrusive stochastic profiling.
4470 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4473 @node Architecture and Core Commands
4474 @chapter Architecture and Core Commands
4475 @cindex Architecture Specific Commands
4476 @cindex Core Specific Commands
4478 Most CPUs have specialized JTAG operations to support debugging.
4479 OpenOCD packages most such operations in its standard command framework.
4480 Some of those operations don't fit well in that framework, so they are
4481 exposed here as architecture or implementation (core) specific commands.
4483 @anchor{ARM Tracing}
4484 @section ARM Tracing
4488 CPUs based on ARM cores may include standard tracing interfaces,
4489 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4490 address and data bus trace records to a ``Trace Port''.
4494 Development-oriented boards will sometimes provide a high speed
4495 trace connector for collecting that data, when the particular CPU
4496 supports such an interface.
4497 (The standard connector is a 38-pin Mictor, with both JTAG
4498 and trace port support.)
4499 Those trace connectors are supported by higher end JTAG adapters
4500 and some logic analyzer modules; frequently those modules can
4501 buffer several megabytes of trace data.
4502 Configuring an ETM coupled to such an external trace port belongs
4503 in the board-specific configuration file.
4505 If the CPU doesn't provide an external interface, it probably
4506 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4507 dedicated SRAM. 4KBytes is one common ETB size.
4508 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4509 (target) configuration file, since it works the same on all boards.
4512 ETM support in OpenOCD doesn't seem to be widely used yet.
4515 ETM support may be buggy, and at least some @command{etm config}
4516 parameters should be detected by asking the ETM for them.
4517 It seems like a GDB hookup should be possible,
4518 as well as triggering trace on specific events
4519 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4520 There should be GUI tools to manipulate saved trace data and help
4521 analyse it in conjunction with the source code.
4522 It's unclear how much of a common interface is shared
4523 with the current XScale trace support, or should be
4524 shared with eventual Nexus-style trace module support.
4527 @subsection ETM Configuration
4528 ETM setup is coupled with the trace port driver configuration.
4530 @deffn {Config Command} {etm config} target width mode clocking driver
4531 Declares the ETM associated with @var{target}, and associates it
4532 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4534 Several of the parameters must reflect the trace port configuration.
4535 The @var{width} must be either 4, 8, or 16.
4536 The @var{mode} must be @option{normal}, @option{multiplexted},
4537 or @option{demultiplexted}.
4538 The @var{clocking} must be @option{half} or @option{full}.
4541 You can see the ETM registers using the @command{reg} command, although
4542 not all of those possible registers are present in every ETM.
4546 @deffn Command {etm info}
4547 Displays information about the current target's ETM.
4550 @deffn Command {etm status}
4551 Displays status of the current target's ETM:
4552 is the ETM idle, or is it collecting data?
4553 Did trace data overflow?
4557 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4558 Displays what data that ETM will collect.
4559 If arguments are provided, first configures that data.
4560 When the configuration changes, tracing is stopped
4561 and any buffered trace data is invalidated.
4564 @item @var{type} ... one of
4565 @option{none} (save nothing),
4566 @option{data} (save data),
4567 @option{address} (save addresses),
4568 @option{all} (save data and addresses)
4569 @item @var{context_id_bits} ... 0, 8, 16, or 32
4570 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4571 @item @var{branch_output} ... @option{enable} or @option{disable}
4575 @deffn Command {etm trigger_percent} percent
4576 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4579 @subsection ETM Trace Operation
4581 After setting up the ETM, you can use it to collect data.
4582 That data can be exported to files for later analysis.
4583 It can also be parsed with OpenOCD, for basic sanity checking.
4585 @deffn Command {etm analyze}
4586 Reads trace data into memory, if it wasn't already present.
4587 Decodes and prints the data that was collected.
4590 @deffn Command {etm dump} filename
4591 Stores the captured trace data in @file{filename}.
4594 @deffn Command {etm image} filename [base_address] [type]
4595 Opens an image file.
4598 @deffn Command {etm load} filename
4599 Loads captured trace data from @file{filename}.
4602 @deffn Command {etm start}
4603 Starts trace data collection.
4606 @deffn Command {etm stop}
4607 Stops trace data collection.
4610 @anchor{Trace Port Drivers}
4611 @subsection Trace Port Drivers
4613 To use an ETM trace port it must be associated with a driver.
4615 @deffn {Trace Port Driver} dummy
4616 Use the @option{dummy} driver if you are configuring an ETM that's
4617 not connected to anything (on-chip ETB or off-chip trace connector).
4618 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4619 any trace data collection.}
4620 @deffn {Config Command} {etm_dummy config} target
4621 Associates the ETM for @var{target} with a dummy driver.
4625 @deffn {Trace Port Driver} etb
4626 Use the @option{etb} driver if you are configuring an ETM
4627 to use on-chip ETB memory.
4628 @deffn {Config Command} {etb config} target etb_tap
4629 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4630 You can see the ETB registers using the @command{reg} command.
4634 @deffn {Trace Port Driver} oocd_trace
4635 This driver isn't available unless OpenOCD was explicitly configured
4636 with the @option{--enable-oocd_trace} option. You probably don't want
4637 to configure it unless you've built the appropriate prototype hardware;
4638 it's @emph{proof-of-concept} software.
4640 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4641 connected to an off-chip trace connector.
4643 @deffn {Config Command} {oocd_trace config} target tty
4644 Associates the ETM for @var{target} with a trace driver which
4645 collects data through the serial port @var{tty}.
4648 @deffn Command {oocd_trace resync}
4649 Re-synchronizes with the capture clock.
4652 @deffn Command {oocd_trace status}
4653 Reports whether the capture clock is locked or not.
4658 @section ARMv4 and ARMv5 Architecture
4662 These commands are specific to ARM architecture v4 and v5,
4663 including all ARM7 or ARM9 systems and Intel XScale.
4664 They are available in addition to other core-specific
4665 commands that may be available.
4667 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4668 Displays the core_state, optionally changing it to process
4669 either @option{arm} or @option{thumb} instructions.
4670 The target may later be resumed in the currently set core_state.
4671 (Processors may also support the Jazelle state, but
4672 that is not currently supported in OpenOCD.)
4675 @deffn Command {armv4_5 disassemble} address count [thumb]
4677 Disassembles @var{count} instructions starting at @var{address}.
4678 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
4679 else ARM (32-bit) instructions are used.
4680 (Processors may also support the Jazelle state, but
4681 those instructions are not currently understood by OpenOCD.)
4684 @deffn Command {armv4_5 reg}
4685 Display a table of all banked core registers, fetching the current value from every
4686 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4690 @subsection ARM7 and ARM9 specific commands
4694 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4695 ARM9TDMI, ARM920T or ARM926EJ-S.
4696 They are available in addition to the ARMv4/5 commands,
4697 and any other core-specific commands that may be available.
4699 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4700 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4701 instead of breakpoints. This should be
4702 safe for all but ARM7TDMI--S cores (like Philips LPC).
4705 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4707 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4708 amounts of memory. DCC downloads offer a huge speed increase, but might be
4709 unsafe, especially with targets running at very low speeds. This command was introduced
4710 with OpenOCD rev. 60, and requires a few bytes of working area.
4713 @anchor{arm7_9 fast_memory_access}
4714 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4715 Enable or disable memory writes and reads that don't check completion of
4716 the operation. This provides a huge speed increase, especially with USB JTAG
4717 cables (FT2232), but might be unsafe if used with targets running at very low
4718 speeds, like the 32kHz startup clock of an AT91RM9200.
4721 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4722 @emph{This is intended for use while debugging OpenOCD; you probably
4725 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4726 as used in the specified @var{mode}
4727 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4728 the M4..M0 bits of the PSR).
4729 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4730 Register 16 is the mode-specific SPSR,
4731 unless the specified mode is 0xffffffff (32-bit all-ones)
4732 in which case register 16 is the CPSR.
4733 The write goes directly to the CPU, bypassing the register cache.
4736 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4737 @emph{This is intended for use while debugging OpenOCD; you probably
4740 If the second parameter is zero, writes @var{word} to the
4741 Current Program Status register (CPSR).
4742 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4743 In both cases, this bypasses the register cache.
4746 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4747 @emph{This is intended for use while debugging OpenOCD; you probably
4750 Writes eight bits to the CPSR or SPSR,
4751 first rotating them by @math{2*rotate} bits,
4752 and bypassing the register cache.
4753 This has lower JTAG overhead than writing the entire CPSR or SPSR
4754 with @command{arm7_9 write_xpsr}.
4757 @subsection ARM720T specific commands
4760 These commands are available to ARM720T based CPUs,
4761 which are implementations of the ARMv4T architecture
4762 based on the ARM7TDMI-S integer core.
4763 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4765 @deffn Command {arm720t cp15} regnum [value]
4766 Display cp15 register @var{regnum};
4767 else if a @var{value} is provided, that value is written to that register.
4770 @deffn Command {arm720t mdw_phys} addr [count]
4771 @deffnx Command {arm720t mdh_phys} addr [count]
4772 @deffnx Command {arm720t mdb_phys} addr [count]
4773 Display contents of physical address @var{addr}, as
4774 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4775 or 8-bit bytes (@command{mdb_phys}).
4776 If @var{count} is specified, displays that many units.
4779 @deffn Command {arm720t mww_phys} addr word
4780 @deffnx Command {arm720t mwh_phys} addr halfword
4781 @deffnx Command {arm720t mwb_phys} addr byte
4782 Writes the specified @var{word} (32 bits),
4783 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4784 at the specified physical address @var{addr}.
4787 @deffn Command {arm720t virt2phys} va
4788 Translate a virtual address @var{va} to a physical address
4789 and display the result.
4792 @subsection ARM9TDMI specific commands
4795 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
4796 or processors resembling ARM9TDMI, and can use these commands.
4797 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4799 @c 9-june-2009: tried this on arm920t, it didn't work.
4800 @c no-params always lists nothing caught, and that's how it acts.
4802 @anchor{arm9tdmi vector_catch}
4803 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
4804 Vector Catch hardware provides a sort of dedicated breakpoint
4805 for hardware events such as reset, interrupt, and abort.
4806 You can use this to conserve normal breakpoint resources,
4807 so long as you're not concerned with code that branches directly
4808 to those hardware vectors.
4810 This always finishes by listing the current configuration.
4811 If parameters are provided, it first reconfigures the
4812 vector catch hardware to intercept
4813 @option{all} of the hardware vectors,
4814 @option{none} of them,
4815 or a list with one or more of the following:
4816 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4817 @option{irq} @option{fiq}.
4820 @subsection ARM920T specific commands
4823 These commands are available to ARM920T based CPUs,
4824 which are implementations of the ARMv4T architecture
4825 built using the ARM9TDMI integer core.
4826 They are available in addition to the ARMv4/5, ARM7/ARM9,
4827 and ARM9TDMI commands.
4829 @deffn Command {arm920t cache_info}
4830 Print information about the caches found. This allows to see whether your target
4831 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
4834 @deffn Command {arm920t cp15} regnum [value]
4835 Display cp15 register @var{regnum};
4836 else if a @var{value} is provided, that value is written to that register.
4839 @deffn Command {arm920t cp15i} opcode [value [address]]
4840 Interpreted access using cp15 @var{opcode}.
4841 If no @var{value} is provided, the result is displayed.
4842 Else if that value is written using the specified @var{address},
4843 or using zero if no other address is not provided.
4846 @deffn Command {arm920t mdw_phys} addr [count]
4847 @deffnx Command {arm920t mdh_phys} addr [count]
4848 @deffnx Command {arm920t mdb_phys} addr [count]
4849 Display contents of physical address @var{addr}, as
4850 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4851 or 8-bit bytes (@command{mdb_phys}).
4852 If @var{count} is specified, displays that many units.
4855 @deffn Command {arm920t mww_phys} addr word
4856 @deffnx Command {arm920t mwh_phys} addr halfword
4857 @deffnx Command {arm920t mwb_phys} addr byte
4858 Writes the specified @var{word} (32 bits),
4859 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4860 at the specified physical address @var{addr}.
4863 @deffn Command {arm920t read_cache} filename
4864 Dump the content of ICache and DCache to a file named @file{filename}.
4867 @deffn Command {arm920t read_mmu} filename
4868 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4871 @deffn Command {arm920t virt2phys} va
4872 Translate a virtual address @var{va} to a physical address
4873 and display the result.
4876 @subsection ARM926ej-s specific commands
4879 These commands are available to ARM926ej-s based CPUs,
4880 which are implementations of the ARMv5TEJ architecture
4881 based on the ARM9EJ-S integer core.
4882 They are available in addition to the ARMv4/5, ARM7/ARM9,
4883 and ARM9TDMI commands.
4885 The Feroceon cores also support these commands, although
4886 they are not built from ARM926ej-s designs.
4888 @deffn Command {arm926ejs cache_info}
4889 Print information about the caches found.
4892 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4893 Accesses cp15 register @var{regnum} using
4894 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4895 If a @var{value} is provided, that value is written to that register.
4896 Else that register is read and displayed.
4899 @deffn Command {arm926ejs mdw_phys} addr [count]
4900 @deffnx Command {arm926ejs mdh_phys} addr [count]
4901 @deffnx Command {arm926ejs mdb_phys} addr [count]
4902 Display contents of physical address @var{addr}, as
4903 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4904 or 8-bit bytes (@command{mdb_phys}).
4905 If @var{count} is specified, displays that many units.
4908 @deffn Command {arm926ejs mww_phys} addr word
4909 @deffnx Command {arm926ejs mwh_phys} addr halfword
4910 @deffnx Command {arm926ejs mwb_phys} addr byte
4911 Writes the specified @var{word} (32 bits),
4912 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4913 at the specified physical address @var{addr}.
4916 @deffn Command {arm926ejs virt2phys} va
4917 Translate a virtual address @var{va} to a physical address
4918 and display the result.
4921 @subsection ARM966E specific commands
4924 These commands are available to ARM966 based CPUs,
4925 which are implementations of the ARMv5TE architecture.
4926 They are available in addition to the ARMv4/5, ARM7/ARM9,
4927 and ARM9TDMI commands.
4929 @deffn Command {arm966e cp15} regnum [value]
4930 Display cp15 register @var{regnum};
4931 else if a @var{value} is provided, that value is written to that register.
4934 @subsection XScale specific commands
4937 These commands are available to XScale based CPUs,
4938 which are implementations of the ARMv5TE architecture.
4940 @deffn Command {xscale analyze_trace}
4941 Displays the contents of the trace buffer.
4944 @deffn Command {xscale cache_clean_address} address
4945 Changes the address used when cleaning the data cache.
4948 @deffn Command {xscale cache_info}
4949 Displays information about the CPU caches.
4952 @deffn Command {xscale cp15} regnum [value]
4953 Display cp15 register @var{regnum};
4954 else if a @var{value} is provided, that value is written to that register.
4957 @deffn Command {xscale debug_handler} target address
4958 Changes the address used for the specified target's debug handler.
4961 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
4962 Enables or disable the CPU's data cache.
4965 @deffn Command {xscale dump_trace} filename
4966 Dumps the raw contents of the trace buffer to @file{filename}.
4969 @deffn Command {xscale icache} (@option{enable}|@option{disable})
4970 Enables or disable the CPU's instruction cache.
4973 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
4974 Enables or disable the CPU's memory management unit.
4977 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
4978 Enables or disables the trace buffer,
4979 and controls how it is emptied.
4982 @deffn Command {xscale trace_image} filename [offset [type]]
4983 Opens a trace image from @file{filename}, optionally rebasing
4984 its segment addresses by @var{offset}.
4985 The image @var{type} may be one of
4986 @option{bin} (binary), @option{ihex} (Intel hex),
4987 @option{elf} (ELF file), @option{s19} (Motorola s19),
4988 @option{mem}, or @option{builder}.
4991 @anchor{xscale vector_catch}
4992 @deffn Command {xscale vector_catch} [mask]
4993 Display a bitmask showing the hardware vectors to catch.
4994 If the optional parameter is provided, first set the bitmask to that value.
4997 @section ARMv6 Architecture
5000 @subsection ARM11 specific commands
5003 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
5004 Read coprocessor register
5007 @deffn Command {arm11 memwrite burst} [value]
5008 Displays the value of the memwrite burst-enable flag,
5009 which is enabled by default.
5010 If @var{value} is defined, first assigns that.
5013 @deffn Command {arm11 memwrite error_fatal} [value]
5014 Displays the value of the memwrite error_fatal flag,
5015 which is enabled by default.
5016 If @var{value} is defined, first assigns that.
5019 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
5020 Write coprocessor register
5023 @deffn Command {arm11 no_increment} [value]
5024 Displays the value of the flag controlling whether
5025 some read or write operations increment the pointer
5026 (the default behavior) or not (acting like a FIFO).
5027 If @var{value} is defined, first assigns that.
5030 @deffn Command {arm11 step_irq_enable} [value]
5031 Displays the value of the flag controlling whether
5032 IRQs are enabled during single stepping;
5033 they is disabled by default.
5034 If @var{value} is defined, first assigns that.
5037 @section ARMv7 Architecture
5040 @subsection ARMv7 Debug Access Port (DAP) specific commands
5041 @cindex Debug Access Port
5043 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5044 included on cortex-m3 and cortex-a8 systems.
5045 They are available in addition to other core-specific commands that may be available.
5047 @deffn Command {dap info} [num]
5048 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5051 @deffn Command {dap apsel} [num]
5052 Select AP @var{num}, defaulting to 0.
5055 @deffn Command {dap apid} [num]
5056 Displays id register from AP @var{num},
5057 defaulting to the currently selected AP.
5060 @deffn Command {dap baseaddr} [num]
5061 Displays debug base address from AP @var{num},
5062 defaulting to the currently selected AP.
5065 @deffn Command {dap memaccess} [value]
5066 Displays the number of extra tck for mem-ap memory bus access [0-255].
5067 If @var{value} is defined, first assigns that.
5070 @subsection Cortex-M3 specific commands
5073 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5074 Control masking (disabling) interrupts during target step/resume.
5077 @section Target DCC Requests
5078 @cindex Linux-ARM DCC support
5081 OpenOCD can handle certain target requests; currently debugmsgs
5082 @command{target_request debugmsgs}
5083 are only supported for arm7_9 and cortex_m3.
5085 See libdcc in the contrib dir for more details.
5086 Linux-ARM kernels have a ``Kernel low-level debugging
5087 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5088 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5089 deliver messages before a serial console can be activated.
5091 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5092 Displays current handling of target DCC message requests.
5093 These messages may be sent to the debugger while the target is running.
5094 The optional @option{enable} and @option{charmsg} parameters
5095 both enable the messages, while @option{disable} disables them.
5096 With @option{charmsg} the DCC words each contain one character,
5097 as used by Linux with CONFIG_DEBUG_ICEDCC;
5098 otherwise the libdcc format is used.
5102 @chapter JTAG Commands
5103 @cindex JTAG Commands
5104 Most general purpose JTAG commands have been presented earlier.
5105 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5106 Lower level JTAG commands, as presented here,
5107 may be needed to work with targets which require special
5108 attention during operations such as reset or initialization.
5110 To use these commands you will need to understand some
5111 of the basics of JTAG, including:
5114 @item A JTAG scan chain consists of a sequence of individual TAP
5115 devices such as a CPUs.
5116 @item Control operations involve moving each TAP through the same
5117 standard state machine (in parallel)
5118 using their shared TMS and clock signals.
5119 @item Data transfer involves shifting data through the chain of
5120 instruction or data registers of each TAP, writing new register values
5121 while the reading previous ones.
5122 @item Data register sizes are a function of the instruction active in
5123 a given TAP, while instruction register sizes are fixed for each TAP.
5124 All TAPs support a BYPASS instruction with a single bit data register.
5125 @item The way OpenOCD differentiates between TAP devices is by
5126 shifting different instructions into (and out of) their instruction
5130 @section Low Level JTAG Commands
5132 These commands are used by developers who need to access
5133 JTAG instruction or data registers, possibly controlling
5134 the order of TAP state transitions.
5135 If you're not debugging OpenOCD internals, or bringing up a
5136 new JTAG adapter or a new type of TAP device (like a CPU or
5137 JTAG router), you probably won't need to use these commands.
5139 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5140 Loads the data register of @var{tap} with a series of bit fields
5141 that specify the entire register.
5142 Each field is @var{numbits} bits long with
5143 a numeric @var{value} (hexadecimal encouraged).
5144 The return value holds the original value of each
5147 For example, a 38 bit number might be specified as one
5148 field of 32 bits then one of 6 bits.
5149 @emph{For portability, never pass fields which are more
5150 than 32 bits long. Many OpenOCD implementations do not
5151 support 64-bit (or larger) integer values.}
5153 All TAPs other than @var{tap} must be in BYPASS mode.
5154 The single bit in their data registers does not matter.
5156 When @var{tap_state} is specified, the JTAG state machine is left
5158 For example @sc{drpause} might be specified, so that more
5159 instructions can be issued before re-entering the @sc{run/idle} state.
5160 If the end state is not specified, the @sc{run/idle} state is entered.
5163 OpenOCD does not record information about data register lengths,
5164 so @emph{it is important that you get the bit field lengths right}.
5165 Remember that different JTAG instructions refer to different
5166 data registers, which may have different lengths.
5167 Moreover, those lengths may not be fixed;
5168 the SCAN_N instruction can change the length of
5169 the register accessed by the INTEST instruction
5170 (by connecting a different scan chain).
5174 @deffn Command {flush_count}
5175 Returns the number of times the JTAG queue has been flushed.
5176 This may be used for performance tuning.
5178 For example, flushing a queue over USB involves a
5179 minimum latency, often several milliseconds, which does
5180 not change with the amount of data which is written.
5181 You may be able to identify performance problems by finding
5182 tasks which waste bandwidth by flushing small transfers too often,
5183 instead of batching them into larger operations.
5186 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5187 For each @var{tap} listed, loads the instruction register
5188 with its associated numeric @var{instruction}.
5189 (The number of bits in that instruction may be displayed
5190 using the @command{scan_chain} command.)
5191 For other TAPs, a BYPASS instruction is loaded.
5193 When @var{tap_state} is specified, the JTAG state machine is left
5195 For example @sc{irpause} might be specified, so the data register
5196 can be loaded before re-entering the @sc{run/idle} state.
5197 If the end state is not specified, the @sc{run/idle} state is entered.
5200 OpenOCD currently supports only a single field for instruction
5201 register values, unlike data register values.
5202 For TAPs where the instruction register length is more than 32 bits,
5203 portable scripts currently must issue only BYPASS instructions.
5207 @deffn Command {jtag_reset} trst srst
5208 Set values of reset signals.
5209 The @var{trst} and @var{srst} parameter values may be
5210 @option{0}, indicating that reset is inactive (pulled or driven high),
5211 or @option{1}, indicating it is active (pulled or driven low).
5212 The @command{reset_config} command should already have been used
5213 to configure how the board and JTAG adapter treat these two
5214 signals, and to say if either signal is even present.
5215 @xref{Reset Configuration}.
5218 @deffn Command {runtest} @var{num_cycles}
5219 Move to the @sc{run/idle} state, and execute at least
5220 @var{num_cycles} of the JTAG clock (TCK).
5221 Instructions often need some time
5222 to execute before they take effect.
5225 @c tms_sequence (short|long)
5226 @c ... temporary, debug-only, probably gone before 0.2 ships
5228 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5229 Verify values captured during @sc{ircapture} and returned
5230 during IR scans. Default is enabled, but this can be
5231 overridden by @command{verify_jtag}.
5234 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5235 Enables verification of DR and IR scans, to help detect
5236 programming errors. For IR scans, @command{verify_ircapture}
5237 must also be enabled.
5241 @section TAP state names
5242 @cindex TAP state names
5244 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5245 and @command{irscan} commands are:
5248 @item @b{RESET} ... should act as if TRST were active
5249 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5252 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5254 @item @b{DRPAUSE} ... data register ready for update or more shifting
5259 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5261 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5266 Note that only six of those states are fully ``stable'' in the
5267 face of TMS fixed (low except for @sc{reset})
5268 and a free-running JTAG clock. For all the
5269 others, the next TCK transition changes to a new state.
5272 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5273 produce side effects by changing register contents. The values
5274 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5275 may not be as expected.
5276 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5277 choices after @command{drscan} or @command{irscan} commands,
5278 since they are free of JTAG side effects.
5279 However, @sc{run/idle} may have side effects that appear at other
5280 levels, such as advancing the ARM9E-S instruction pipeline.
5281 Consult the documentation for the TAP(s) you are working with.
5287 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5288 be used to access files on PCs (either the developer's PC or some other PC).
5290 The way this works on the ZY1000 is to prefix a filename by
5291 "/tftp/ip/" and append the TFTP path on the TFTP
5292 server (tftpd). For example,
5295 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5298 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5299 if the file was hosted on the embedded host.
5301 In order to achieve decent performance, you must choose a TFTP server
5302 that supports a packet size bigger than the default packet size (512 bytes). There
5303 are numerous TFTP servers out there (free and commercial) and you will have to do
5304 a bit of googling to find something that fits your requirements.
5306 @node GDB and OpenOCD
5307 @chapter GDB and OpenOCD
5309 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5310 to debug remote targets.
5312 @anchor{Connecting to GDB}
5313 @section Connecting to GDB
5314 @cindex Connecting to GDB
5315 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5316 instance GDB 6.3 has a known bug that produces bogus memory access
5317 errors, which has since been fixed: look up 1836 in
5318 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5320 OpenOCD can communicate with GDB in two ways:
5324 A socket (TCP/IP) connection is typically started as follows:
5326 target remote localhost:3333
5328 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5330 A pipe connection is typically started as follows:
5332 target remote | openocd --pipe
5334 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5335 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5339 To list the available OpenOCD commands type @command{monitor help} on the
5342 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5343 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5344 packet size and the device's memory map.
5346 Previous versions of OpenOCD required the following GDB options to increase
5347 the packet size and speed up GDB communication:
5349 set remote memory-write-packet-size 1024
5350 set remote memory-write-packet-size fixed
5351 set remote memory-read-packet-size 1024
5352 set remote memory-read-packet-size fixed
5354 This is now handled in the @option{qSupported} PacketSize and should not be required.
5356 @section Programming using GDB
5357 @cindex Programming using GDB
5359 By default the target memory map is sent to GDB. This can be disabled by
5360 the following OpenOCD configuration option:
5362 gdb_memory_map disable
5364 For this to function correctly a valid flash configuration must also be set
5365 in OpenOCD. For faster performance you should also configure a valid
5368 Informing GDB of the memory map of the target will enable GDB to protect any
5369 flash areas of the target and use hardware breakpoints by default. This means
5370 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5371 using a memory map. @xref{gdb_breakpoint_override}.
5373 To view the configured memory map in GDB, use the GDB command @option{info mem}
5374 All other unassigned addresses within GDB are treated as RAM.
5376 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5377 This can be changed to the old behaviour by using the following GDB command
5379 set mem inaccessible-by-default off
5382 If @command{gdb_flash_program enable} is also used, GDB will be able to
5383 program any flash memory using the vFlash interface.
5385 GDB will look at the target memory map when a load command is given, if any
5386 areas to be programmed lie within the target flash area the vFlash packets
5389 If the target needs configuring before GDB programming, an event
5390 script can be executed:
5392 $_TARGETNAME configure -event EVENTNAME BODY
5395 To verify any flash programming the GDB command @option{compare-sections}
5398 @node Tcl Scripting API
5399 @chapter Tcl Scripting API
5400 @cindex Tcl Scripting API
5404 The commands are stateless. E.g. the telnet command line has a concept
5405 of currently active target, the Tcl API proc's take this sort of state
5406 information as an argument to each proc.
5408 There are three main types of return values: single value, name value
5409 pair list and lists.
5411 Name value pair. The proc 'foo' below returns a name/value pair
5417 > set foo(you) Oyvind
5418 > set foo(mouse) Micky
5419 > set foo(duck) Donald
5427 me Duane you Oyvind mouse Micky duck Donald
5429 Thus, to get the names of the associative array is easy:
5431 foreach { name value } [set foo] {
5432 puts "Name: $name, Value: $value"
5436 Lists returned must be relatively small. Otherwise a range
5437 should be passed in to the proc in question.
5439 @section Internal low-level Commands
5441 By low-level, the intent is a human would not directly use these commands.
5443 Low-level commands are (should be) prefixed with "ocd_", e.g.
5444 @command{ocd_flash_banks}
5445 is the low level API upon which @command{flash banks} is implemented.
5448 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5450 Read memory and return as a Tcl array for script processing
5451 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
5453 Convert a Tcl array to memory locations and write the values
5454 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
5456 Return information about the flash banks
5459 OpenOCD commands can consist of two words, e.g. "flash banks". The
5460 startup.tcl "unknown" proc will translate this into a Tcl proc
5461 called "flash_banks".
5463 @section OpenOCD specific Global Variables
5467 Real Tcl has ::tcl_platform(), and platform::identify, and many other
5468 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
5469 holds one of the following values:
5472 @item @b{winxx} Built using Microsoft Visual Studio
5473 @item @b{linux} Linux is the underlying operating sytem
5474 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
5475 @item @b{cygwin} Running under Cygwin
5476 @item @b{mingw32} Running under MingW32
5477 @item @b{other} Unknown, none of the above.
5480 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5483 We should add support for a variable like Tcl variable
5484 @code{tcl_platform(platform)}, it should be called
5485 @code{jim_platform} (because it
5486 is jim, not real tcl).
5490 @chapter Deprecated/Removed Commands
5491 @cindex Deprecated/Removed Commands
5492 Certain OpenOCD commands have been deprecated or
5493 removed during the various revisions.
5495 Upgrade your scripts as soon as possible.
5496 These descriptions for old commands may be removed
5497 a year after the command itself was removed.
5498 This means that in January 2010 this chapter may
5499 become much shorter.
5502 @item @b{arm7_9 fast_writes}
5503 @cindex arm7_9 fast_writes
5504 @*Use @command{arm7_9 fast_memory_access} instead.
5507 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5508 @xref{arm7_9 fast_memory_access}.
5509 @item @b{arm7_9 force_hw_bkpts}
5510 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5511 for flash if the GDB memory map has been set up(default when flash is declared in
5512 target configuration). @xref{gdb_breakpoint_override}.
5513 @item @b{arm7_9 sw_bkpts}
5514 @*On by default. @xref{gdb_breakpoint_override}.
5515 @item @b{daemon_startup}
5516 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5517 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5518 and @option{target cortex_m3 little reset_halt 0}.
5519 @item @b{dump_binary}
5520 @*use @option{dump_image} command with same args. @xref{dump_image}.
5521 @item @b{flash erase}
5522 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5523 @item @b{flash write}
5524 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5525 @item @b{flash write_binary}
5526 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5527 @item @b{flash auto_erase}
5528 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5530 @item @b{jtag_device}
5531 @*use the @command{jtag newtap} command, converting from positional syntax
5532 to named prefixes, and naming the TAP.
5534 Note that if you try to use the old command, a message will tell you the
5535 right new command to use; and that the fourth parameter in the old syntax
5536 was never actually used.
5538 OLD: jtag_device 8 0x01 0xe3 0xfe
5539 NEW: jtag newtap CHIPNAME TAPNAME \
5540 -irlen 8 -ircapture 0x01 -irmask 0xe3
5543 @item @b{jtag_speed} value
5544 @*@xref{JTAG Speed}.
5545 Usually, a value of zero means maximum
5546 speed. The actual effect of this option depends on the JTAG interface used.
5548 @item wiggler: maximum speed / @var{number}
5549 @item ft2232: 6MHz / (@var{number}+1)
5550 @item amt jtagaccel: 8 / 2**@var{number}
5551 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5552 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5553 @comment end speed list.
5556 @item @b{load_binary}
5557 @*use @option{load_image} command with same args. @xref{load_image}.
5558 @item @b{run_and_halt_time}
5559 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5566 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5567 @*use the create subcommand of @option{target}.
5568 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5569 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5570 @item @b{working_area}
5571 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5579 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5581 @cindex adaptive clocking
5584 In digital circuit design it is often refered to as ``clock
5585 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5586 operating at some speed, your target is operating at another. The two
5587 clocks are not synchronised, they are ``asynchronous''
5589 In order for the two to work together they must be synchronised. Otherwise
5590 the two systems will get out of sync with each other and nothing will
5591 work. There are 2 basic options:
5594 Use a special circuit.
5596 One clock must be some multiple slower than the other.
5599 @b{Does this really matter?} For some chips and some situations, this
5600 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
5601 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
5602 program/enable the oscillators and eventually the main clock. It is in
5603 those critical times you must slow the JTAG clock to sometimes 1 to
5606 Imagine debugging a 500MHz ARM926 hand held battery powered device
5607 that ``deep sleeps'' at 32kHz between every keystroke. It can be
5610 @b{Solution #1 - A special circuit}
5612 In order to make use of this, your JTAG dongle must support the RTCK
5613 feature. Not all dongles support this - keep reading!
5615 The RTCK signal often found in some ARM chips is used to help with
5616 this problem. ARM has a good description of the problem described at
5617 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
5618 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
5619 work? / how does adaptive clocking work?''.
5621 The nice thing about adaptive clocking is that ``battery powered hand
5622 held device example'' - the adaptiveness works perfectly all the
5623 time. One can set a break point or halt the system in the deep power
5624 down code, slow step out until the system speeds up.
5626 @b{Solution #2 - Always works - but may be slower}
5628 Often this is a perfectly acceptable solution.
5630 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
5631 the target clock speed. But what that ``magic division'' is varies
5632 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
5633 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
5634 1/12 the clock speed.
5636 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
5638 You can still debug the 'low power' situations - you just need to
5639 manually adjust the clock speed at every step. While painful and
5640 tedious, it is not always practical.
5642 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
5643 have a special debug mode in your application that does a ``high power
5644 sleep''. If you are careful - 98% of your problems can be debugged
5647 To set the JTAG frequency use the command:
5655 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
5657 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
5658 around Windows filenames.
5671 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
5673 Make sure you have Cygwin installed, or at least a version of OpenOCD that
5674 claims to come with all the necessary DLLs. When using Cygwin, try launching
5675 OpenOCD from the Cygwin shell.
5677 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
5678 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
5679 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
5681 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
5682 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
5683 software breakpoints consume one of the two available hardware breakpoints.
5685 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
5687 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
5688 clock at the time you're programming the flash. If you've specified the crystal's
5689 frequency, make sure the PLL is disabled. If you've specified the full core speed
5690 (e.g. 60MHz), make sure the PLL is enabled.
5692 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
5693 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
5694 out while waiting for end of scan, rtck was disabled".
5696 Make sure your PC's parallel port operates in EPP mode. You might have to try several
5697 settings in your PC BIOS (ECP, EPP, and different versions of those).
5699 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
5700 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
5701 memory read caused data abort".
5703 The errors are non-fatal, and are the result of GDB trying to trace stack frames
5704 beyond the last valid frame. It might be possible to prevent this by setting up
5705 a proper "initial" stack frame, if you happen to know what exactly has to
5706 be done, feel free to add this here.
5708 @b{Simple:} In your startup code - push 8 registers of zeros onto the
5709 stack before calling main(). What GDB is doing is ``climbing'' the run
5710 time stack by reading various values on the stack using the standard
5711 call frame for the target. GDB keeps going - until one of 2 things
5712 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
5713 stackframes have been processed. By pushing zeros on the stack, GDB
5716 @b{Debugging Interrupt Service Routines} - In your ISR before you call
5717 your C code, do the same - artifically push some zeros onto the stack,
5718 remember to pop them off when the ISR is done.
5720 @b{Also note:} If you have a multi-threaded operating system, they
5721 often do not @b{in the intrest of saving memory} waste these few
5725 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
5726 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
5728 This warning doesn't indicate any serious problem, as long as you don't want to
5729 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
5730 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
5731 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
5732 independently. With this setup, it's not possible to halt the core right out of
5733 reset, everything else should work fine.
5735 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
5736 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
5737 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
5738 quit with an error message. Is there a stability issue with OpenOCD?
5740 No, this is not a stability issue concerning OpenOCD. Most users have solved
5741 this issue by simply using a self-powered USB hub, which they connect their
5742 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
5743 supply stable enough for the Amontec JTAGkey to be operated.
5745 @b{Laptops running on battery have this problem too...}
5747 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
5748 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
5749 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
5750 What does that mean and what might be the reason for this?
5752 First of all, the reason might be the USB power supply. Try using a self-powered
5753 hub instead of a direct connection to your computer. Secondly, the error code 4
5754 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
5755 chip ran into some sort of error - this points us to a USB problem.
5757 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
5758 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
5759 What does that mean and what might be the reason for this?
5761 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
5762 has closed the connection to OpenOCD. This might be a GDB issue.
5764 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
5765 are described, there is a parameter for specifying the clock frequency
5766 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
5767 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
5768 specified in kilohertz. However, I do have a quartz crystal of a
5769 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
5770 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
5773 No. The clock frequency specified here must be given as an integral number.
5774 However, this clock frequency is used by the In-Application-Programming (IAP)
5775 routines of the LPC2000 family only, which seems to be very tolerant concerning
5776 the given clock frequency, so a slight difference between the specified clock
5777 frequency and the actual clock frequency will not cause any trouble.
5779 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
5781 Well, yes and no. Commands can be given in arbitrary order, yet the
5782 devices listed for the JTAG scan chain must be given in the right
5783 order (jtag newdevice), with the device closest to the TDO-Pin being
5784 listed first. In general, whenever objects of the same type exist
5785 which require an index number, then these objects must be given in the
5786 right order (jtag newtap, targets and flash banks - a target
5787 references a jtag newtap and a flash bank references a target).
5789 You can use the ``scan_chain'' command to verify and display the tap order.
5791 Also, some commands can't execute until after @command{init} has been
5792 processed. Such commands include @command{nand probe} and everything
5793 else that needs to write to controller registers, perhaps for setting
5794 up DRAM and loading it with code.
5796 @anchor{FAQ TAP Order}
5797 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
5800 Yes; whenever you have more than one, you must declare them in
5801 the same order used by the hardware.
5803 Many newer devices have multiple JTAG TAPs. For example: ST
5804 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
5805 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
5806 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
5807 connected to the boundary scan TAP, which then connects to the
5808 Cortex-M3 TAP, which then connects to the TDO pin.
5810 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
5811 (2) The boundary scan TAP. If your board includes an additional JTAG
5812 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
5813 place it before or after the STM32 chip in the chain. For example:
5816 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
5817 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
5818 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
5819 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
5820 @item Xilinx TDO Pin -> OpenOCD TDO (input)
5823 The ``jtag device'' commands would thus be in the order shown below. Note:
5826 @item jtag newtap Xilinx tap -irlen ...
5827 @item jtag newtap stm32 cpu -irlen ...
5828 @item jtag newtap stm32 bs -irlen ...
5829 @item # Create the debug target and say where it is
5830 @item target create stm32.cpu -chain-position stm32.cpu ...
5834 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
5835 log file, I can see these error messages: Error: arm7_9_common.c:561
5836 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
5842 @node Tcl Crash Course
5843 @chapter Tcl Crash Course
5846 Not everyone knows Tcl - this is not intended to be a replacement for
5847 learning Tcl, the intent of this chapter is to give you some idea of
5848 how the Tcl scripts work.
5850 This chapter is written with two audiences in mind. (1) OpenOCD users
5851 who need to understand a bit more of how JIM-Tcl works so they can do
5852 something useful, and (2) those that want to add a new command to
5855 @section Tcl Rule #1
5856 There is a famous joke, it goes like this:
5858 @item Rule #1: The wife is always correct
5859 @item Rule #2: If you think otherwise, See Rule #1
5862 The Tcl equal is this:
5865 @item Rule #1: Everything is a string
5866 @item Rule #2: If you think otherwise, See Rule #1
5869 As in the famous joke, the consequences of Rule #1 are profound. Once
5870 you understand Rule #1, you will understand Tcl.
5872 @section Tcl Rule #1b
5873 There is a second pair of rules.
5875 @item Rule #1: Control flow does not exist. Only commands
5876 @* For example: the classic FOR loop or IF statement is not a control
5877 flow item, they are commands, there is no such thing as control flow
5879 @item Rule #2: If you think otherwise, See Rule #1
5880 @* Actually what happens is this: There are commands that by
5881 convention, act like control flow key words in other languages. One of
5882 those commands is the word ``for'', another command is ``if''.
5885 @section Per Rule #1 - All Results are strings
5886 Every Tcl command results in a string. The word ``result'' is used
5887 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
5888 Everything is a string}
5890 @section Tcl Quoting Operators
5891 In life of a Tcl script, there are two important periods of time, the
5892 difference is subtle.
5895 @item Evaluation Time
5898 The two key items here are how ``quoted things'' work in Tcl. Tcl has
5899 three primary quoting constructs, the [square-brackets] the
5900 @{curly-braces@} and ``double-quotes''
5902 By now you should know $VARIABLES always start with a $DOLLAR
5903 sign. BTW: To set a variable, you actually use the command ``set'', as
5904 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
5905 = 1'' statement, but without the equal sign.
5908 @item @b{[square-brackets]}
5909 @* @b{[square-brackets]} are command substitutions. It operates much
5910 like Unix Shell `back-ticks`. The result of a [square-bracket]
5911 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
5912 string}. These two statements are roughly identical:
5916 echo "The Date is: $X"
5919 puts "The Date is: $X"
5921 @item @b{``double-quoted-things''}
5922 @* @b{``double-quoted-things''} are just simply quoted
5923 text. $VARIABLES and [square-brackets] are expanded in place - the
5924 result however is exactly 1 string. @i{Remember Rule #1 - Everything
5928 puts "It is now \"[date]\", $x is in 1 hour"
5930 @item @b{@{Curly-Braces@}}
5931 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
5932 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
5933 'single-quote' operators in BASH shell scripts, with the added
5934 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
5935 nested 3 times@}@}@} NOTE: [date] is a bad example;
5936 at this writing, Jim/OpenOCD does not have a date command.
5939 @section Consequences of Rule 1/2/3/4
5941 The consequences of Rule 1 are profound.
5943 @subsection Tokenisation & Execution.
5945 Of course, whitespace, blank lines and #comment lines are handled in
5948 As a script is parsed, each (multi) line in the script file is
5949 tokenised and according to the quoting rules. After tokenisation, that
5950 line is immedatly executed.
5952 Multi line statements end with one or more ``still-open''
5953 @{curly-braces@} which - eventually - closes a few lines later.
5955 @subsection Command Execution
5957 Remember earlier: There are no ``control flow''
5958 statements in Tcl. Instead there are COMMANDS that simply act like
5959 control flow operators.
5961 Commands are executed like this:
5964 @item Parse the next line into (argc) and (argv[]).
5965 @item Look up (argv[0]) in a table and call its function.
5966 @item Repeat until End Of File.
5969 It sort of works like this:
5972 ReadAndParse( &argc, &argv );
5974 cmdPtr = LookupCommand( argv[0] );
5976 (*cmdPtr->Execute)( argc, argv );
5980 When the command ``proc'' is parsed (which creates a procedure
5981 function) it gets 3 parameters on the command line. @b{1} the name of
5982 the proc (function), @b{2} the list of parameters, and @b{3} the body
5983 of the function. Not the choice of words: LIST and BODY. The PROC
5984 command stores these items in a table somewhere so it can be found by
5987 @subsection The FOR command
5989 The most interesting command to look at is the FOR command. In Tcl,
5990 the FOR command is normally implemented in C. Remember, FOR is a
5991 command just like any other command.
5993 When the ascii text containing the FOR command is parsed, the parser
5994 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
5998 @item The ascii text 'for'
5999 @item The start text
6000 @item The test expression
6005 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6006 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6007 Often many of those parameters are in @{curly-braces@} - thus the
6008 variables inside are not expanded or replaced until later.
6010 Remember that every Tcl command looks like the classic ``main( argc,
6011 argv )'' function in C. In JimTCL - they actually look like this:
6015 MyCommand( Jim_Interp *interp,
6017 Jim_Obj * const *argvs );
6020 Real Tcl is nearly identical. Although the newer versions have
6021 introduced a byte-code parser and intepreter, but at the core, it
6022 still operates in the same basic way.
6024 @subsection FOR command implementation
6026 To understand Tcl it is perhaps most helpful to see the FOR
6027 command. Remember, it is a COMMAND not a control flow structure.
6029 In Tcl there are two underlying C helper functions.
6031 Remember Rule #1 - You are a string.
6033 The @b{first} helper parses and executes commands found in an ascii
6034 string. Commands can be seperated by semicolons, or newlines. While
6035 parsing, variables are expanded via the quoting rules.
6037 The @b{second} helper evaluates an ascii string as a numerical
6038 expression and returns a value.
6040 Here is an example of how the @b{FOR} command could be
6041 implemented. The pseudo code below does not show error handling.
6043 void Execute_AsciiString( void *interp, const char *string );
6045 int Evaluate_AsciiExpression( void *interp, const char *string );
6048 MyForCommand( void *interp,
6053 SetResult( interp, "WRONG number of parameters");
6057 // argv[0] = the ascii string just like C
6059 // Execute the start statement.
6060 Execute_AsciiString( interp, argv[1] );
6064 i = Evaluate_AsciiExpression(interp, argv[2]);
6069 Execute_AsciiString( interp, argv[3] );
6071 // Execute the LOOP part
6072 Execute_AsciiString( interp, argv[4] );
6076 SetResult( interp, "" );
6081 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6082 in the same basic way.
6084 @section OpenOCD Tcl Usage
6086 @subsection source and find commands
6087 @b{Where:} In many configuration files
6088 @* Example: @b{ source [find FILENAME] }
6089 @*Remember the parsing rules
6091 @item The FIND command is in square brackets.
6092 @* The FIND command is executed with the parameter FILENAME. It should
6093 find the full path to the named file. The RESULT is a string, which is
6094 substituted on the orginal command line.
6095 @item The command source is executed with the resulting filename.
6096 @* SOURCE reads a file and executes as a script.
6098 @subsection format command
6099 @b{Where:} Generally occurs in numerous places.
6100 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6106 puts [format "The answer: %d" [expr $x * $y]]
6109 @item The SET command creates 2 variables, X and Y.
6110 @item The double [nested] EXPR command performs math
6111 @* The EXPR command produces numerical result as a string.
6113 @item The format command is executed, producing a single string
6114 @* Refer to Rule #1.
6115 @item The PUTS command outputs the text.
6117 @subsection Body or Inlined Text
6118 @b{Where:} Various TARGET scripts.
6121 proc someproc @{@} @{
6122 ... multiple lines of stuff ...
6124 $_TARGETNAME configure -event FOO someproc
6125 #2 Good - no variables
6126 $_TARGETNAME confgure -event foo "this ; that;"
6127 #3 Good Curly Braces
6128 $_TARGETNAME configure -event FOO @{
6131 #4 DANGER DANGER DANGER
6132 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6135 @item The $_TARGETNAME is an OpenOCD variable convention.
6136 @*@b{$_TARGETNAME} represents the last target created, the value changes
6137 each time a new target is created. Remember the parsing rules. When
6138 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6139 the name of the target which happens to be a TARGET (object)
6141 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6142 @*There are 4 examples:
6144 @item The TCLBODY is a simple string that happens to be a proc name
6145 @item The TCLBODY is several simple commands seperated by semicolons
6146 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6147 @item The TCLBODY is a string with variables that get expanded.
6150 In the end, when the target event FOO occurs the TCLBODY is
6151 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6152 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6154 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6155 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6156 and the text is evaluated. In case #4, they are replaced before the
6157 ``Target Object Command'' is executed. This occurs at the same time
6158 $_TARGETNAME is replaced. In case #4 the date will never
6159 change. @{BTW: [date] is a bad example; at this writing,
6160 Jim/OpenOCD does not have a date command@}
6162 @subsection Global Variables
6163 @b{Where:} You might discover this when writing your own procs @* In
6164 simple terms: Inside a PROC, if you need to access a global variable
6165 you must say so. See also ``upvar''. Example:
6167 proc myproc @{ @} @{
6168 set y 0 #Local variable Y
6169 global x #Global variable X
6170 puts [format "X=%d, Y=%d" $x $y]
6173 @section Other Tcl Hacks
6174 @b{Dynamic variable creation}
6176 # Dynamically create a bunch of variables.
6177 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6179 set vn [format "BIT%d" $x]
6183 set $vn [expr (1 << $x)]
6186 @b{Dynamic proc/command creation}
6188 # One "X" function - 5 uart functions.
6189 foreach who @{A B C D E@}
6190 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6194 @node Target Library
6195 @chapter Target Library
6196 @cindex Target Library
6198 OpenOCD comes with a target configuration script library. These scripts can be
6199 used as-is or serve as a starting point.
6201 The target library is published together with the OpenOCD executable and
6202 the path to the target library is in the OpenOCD script search path.
6203 Similarly there are example scripts for configuring the JTAG interface.
6205 The command line below uses the example parport configuration script
6206 that ship with OpenOCD, then configures the str710.cfg target and
6207 finally issues the init and reset commands. The communication speed
6208 is set to 10kHz for reset and 8MHz for post reset.
6211 openocd -f interface/parport.cfg -f target/str710.cfg \
6212 -c "init" -c "reset"
6215 To list the target scripts available:
6218 $ ls /usr/local/lib/openocd/target
6220 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6221 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6222 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6223 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6228 @node OpenOCD Concept Index
6229 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6230 @comment case issue with ``Index.html'' and ``index.html''
6231 @comment Occurs when creating ``--html --no-split'' output
6232 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6233 @unnumbered OpenOCD Concept Index
6237 @node Command and Driver Index
6238 @unnumbered Command and Driver Index