1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}@*
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
55 * GDB and OpenOCD:: Using GDB and OpenOCD
56 * TCL and OpenOCD:: Using TCL and OpenOCD
57 * TCL scripting API:: Tcl scripting API
58 * Upgrading:: Deprecated/Removed Commands
59 * FAQ:: Frequently Asked Questions
60 * License:: GNU Free Documentation License
68 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
69 and boundary-scan testing for embedded target devices. The targets are interfaced
70 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
71 connection types in the future.
73 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
74 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
75 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
76 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
78 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
79 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
80 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
86 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
87 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
88 Others interested in improving the state of free and open debug and testing technology
89 are welcome to participate.
91 Other developers have contributed support for additional targets and flashes as well
92 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
94 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
98 @cindex building OpenOCD
100 If you are interested in getting actual work done rather than building
101 OpenOCD, then check if your interface supplier provides binaries for
102 you. Chances are that that binary is from some SVN version that is more
103 stable than SVN trunk where bleeding edge development takes place.
106 You can download the current SVN version with SVN client of your choice from the
107 following repositories:
109 (@uref{svn://svn.berlios.de/openocd/trunk})
113 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
115 Using the SVN command line client, you can use the following command to fetch the
116 latest version (make sure there is no (non-svn) directory called "openocd" in the
120 svn checkout svn://svn.berlios.de/openocd/trunk openocd
123 Building OpenOCD requires a recent version of the GNU autotools.
124 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
125 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
126 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
127 paths, resulting in obscure dependency errors (This is an observation I've gathered
128 from the logs of one user - correct me if I'm wrong).
130 You further need the appropriate driver files, if you want to build support for
131 a FTDI FT2232 based interface:
133 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
134 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
135 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
136 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
139 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
140 see contrib/libftdi for more details.
142 In general, the D2XX driver provides superior performance (several times as fast),
143 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
144 a kernel module, only a user space library.
146 To build OpenOCD (on both Linux and Cygwin), use the following commands:
150 Bootstrap generates the configure script, and prepares building on your system.
154 Configure generates the Makefiles used to build OpenOCD.
158 Make builds OpenOCD, and places the final executable in ./src/.
160 The configure script takes several options, specifying which JTAG interfaces
165 @option{--enable-parport}
167 @option{--enable-parport_ppdev}
169 @option{--enable-parport_giveio}
171 @option{--enable-amtjtagaccel}
173 @option{--enable-ft2232_ftd2xx}
174 @footnote{Using the latest D2XX drivers from FTDI and following their installation
175 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
178 @option{--enable-ft2232_libftdi}
180 @option{--with-ftd2xx=/path/to/d2xx/}
182 @option{--enable-gw16012}
184 @option{--enable-usbprog}
186 @option{--enable-presto_libftdi}
188 @option{--enable-presto_ftd2xx}
190 @option{--enable-jlink}
193 If you want to access the parallel port using the PPDEV interface you have to specify
194 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
195 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
196 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
198 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
199 absolute path containing no spaces.
201 Linux users should copy the various parts of the D2XX package to the appropriate
202 locations, i.e. /usr/include, /usr/lib.
204 Miscellaneous configure options
208 @option{--enable-gccwarnings} - enable extra gcc warnings during build
213 @cindex running OpenOCD
215 @cindex --debug_level
218 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
219 Run with @option{--help} or @option{-h} to view the available command line switches.
221 It reads its configuration by default from the file openocd.cfg located in the current
222 working directory. This may be overwritten with the @option{-f <configfile>} command line
223 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
224 are executed in order.
226 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
228 To enable debug output (when reporting problems or working on OpenOCD itself), use
229 the @option{-d} command line switch. This sets the @option{debug_level} to "3", outputting
230 the most information, including debug messages. The default setting is "2", outputting
231 only informational messages, warnings and errors. You can also change this setting
232 from within a telnet or gdb session using @option{debug_level <n>} @xref{debug_level}.
234 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
236 Search paths for config/script files can be added to OpenOCD by using
237 the @option{-s <search>} switch. The current directory and the OpenOCD target library
238 is in the search path by default.
240 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
241 with the target. In general, it is possible for the JTAG controller to be unresponsive until
242 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
245 @chapter Configuration
246 @cindex configuration
247 OpenOCD runs as a daemon, and reads it current configuration
248 by default from the file openocd.cfg in the current directory. A different configuration
249 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
251 The configuration file is used to specify on which ports the daemon listens for new
252 connections, the JTAG interface used to connect to the target, the layout of the JTAG
253 chain, the targets that should be debugged, and connected flashes.
255 @section Daemon configuration
259 @*This command terminates the configuration stage and enters the normal
260 command mode. This can be useful to add commands to the startup scripts and commands
261 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
262 add "init" and "reset" at the end of the config script or at the end of the
263 OpenOCD command line using the @option{-c} command line switch.
265 @item @b{telnet_port} <@var{number}>
267 @*Port on which to listen for incoming telnet connections
268 @item @b{telnet_async} <@var{enable/disable}>
270 @*Enable/disable asynchronous messages. Default off. Slows down debugging
271 if enabled and telnet session is open while stepping.
272 @item @b{tcl_port} <@var{number}>
274 @*Port on which to listen for incoming TCL syntax. This port is intended as
275 a simplified RPC connection that can be used by clients to issue commands
276 and get the output from the TCL engine.
277 @item @b{gdb_port} <@var{number}>
279 @*First port on which to listen for incoming GDB connections. The GDB port for the
280 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
281 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
282 @cindex gdb_breakpoint_override
283 @anchor{gdb_breakpoint_override}
284 @*Force breakpoint type for gdb 'break' commands.
285 The raison d'etre for this option is to support GDB GUI's without
286 a hard/soft breakpoint concept where the default OpenOCD and
287 GDB behaviour is not sufficient. Note that GDB will use hardware
288 breakpoints if the memory map has been set up for flash regions.
290 This option replaces older arm7_9 target commands that addressed
292 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
294 @*Configures what OpenOCD will do when gdb detaches from the daeman.
295 Default behaviour is <@var{resume}>
296 @item @b{gdb_memory_map} <@var{enable|disable}>
297 @cindex gdb_memory_map
298 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
299 requested. gdb will then know when to set hardware breakpoints, and program flash
300 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
301 for flash programming to work.
302 Default behaviour is <@var{enable}>
303 @xref{gdb_flash_program}.
304 @item @b{gdb_flash_program} <@var{enable|disable}>
305 @cindex gdb_flash_program
306 @anchor{gdb_flash_program}
307 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
308 vFlash packet is received.
309 Default behaviour is <@var{enable}>
312 @section JTAG interface configuration
315 @item @b{interface} <@var{name}>
317 @*Use the interface driver <@var{name}> to connect to the target. Currently supported
321 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
324 @item @b{amt_jtagaccel}
325 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
330 FTDI FT2232 based devices using either the open-source libftdi or the binary only
331 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
332 platform. The libftdi uses libusb, and should be portable to all systems that provide
337 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
341 ASIX PRESTO USB JTAG programmer.
345 usbprog is a freely programmable USB adapter.
349 Gateworks GW16012 JTAG programmer.
353 Segger jlink usb adapter
358 @item @b{jtag_speed} <@var{reset speed}>
360 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
361 speed. The actual effect of this option depends on the JTAG interface used.
363 The speed used during reset can be adjusted using setting jtag_speed during
364 pre_reset and post_reset events.
367 @item wiggler: maximum speed / @var{number}
368 @item ft2232: 6MHz / (@var{number}+1)
369 @item amt jtagaccel: 8 / 2**@var{number}
370 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
373 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
374 especially true for synthesized cores (-S).
376 @item @b{jtag_khz} <@var{reset speed kHz}>
378 @*Same as jtag_speed, except that the speed is specified in maximum kHz. If
379 the device can not support the rate asked for, or can not translate from
380 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
381 is not supported, then an error is reported.
383 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
385 @*The configuration of the reset signals available on the JTAG interface AND the target.
386 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
387 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
388 @option{srst_only} or @option{trst_and_srst}.
390 [@var{combination}] is an optional value specifying broken reset signal implementations.
391 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
392 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
393 that the system is reset together with the test logic (only hypothetical, I haven't
394 seen hardware with such a bug, and can be worked around).
395 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
396 The default behaviour if no option given is @option{separate}.
398 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
399 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
400 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
401 (default) and @option{srst_push_pull} for the system reset. These values only affect
402 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
404 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
406 @*Describes the devices that form the JTAG daisy chain, with the first device being
407 the one closest to TDO. The parameters are the length of the instruction register
408 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
409 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
410 The IDCODE instruction will in future be used to query devices for their JTAG
411 identification code. This line is the same for all ARM7 and ARM9 devices.
412 Other devices, like CPLDs, require different parameters. An example configuration
413 line for a Xilinx XC9500 CPLD would look like this:
415 jtag_device 8 0x01 0x0e3 0xfe
417 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
418 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
419 The IDCODE instruction is 0xfe.
421 @item @b{jtag_nsrst_delay} <@var{ms}>
422 @cindex jtag_nsrst_delay
423 @*How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
424 starting new JTAG operations.
425 @item @b{jtag_ntrst_delay} <@var{ms}>
426 @cindex jtag_ntrst_delay
427 @*Same @b{jtag_nsrst_delay}, but for nTRST
429 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
430 or on-chip features) keep a reset line asserted for some time after the external reset
434 @section parport options
437 @item @b{parport_port} <@var{number}>
439 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
440 the @file{/dev/parport} device
442 When using PPDEV to access the parallel port, use the number of the parallel port:
443 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
444 you may encounter a problem.
445 @item @b{parport_cable} <@var{name}>
446 @cindex parport_cable
447 @*The layout of the parallel port cable used to connect to the target.
448 Currently supported cables are
452 The original Wiggler layout, also supported by several clones, such
453 as the Olimex ARM-JTAG
456 Same as original wiggler except an led is fitted on D5.
457 @item @b{wiggler_ntrst_inverted}
458 @cindex wiggler_ntrst_inverted
459 Same as original wiggler except TRST is inverted.
460 @item @b{old_amt_wiggler}
461 @cindex old_amt_wiggler
462 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
463 version available from the website uses the original Wiggler layout ('@var{wiggler}')
466 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
467 program the Chameleon itself, not a connected target.
470 The Xilinx Parallel cable III.
473 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
474 This is also the layout used by the HollyGates design
475 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
478 The ST Parallel cable.
481 Same as original wiggler except SRST and TRST connections reversed and
482 TRST is also inverted.
485 Altium Universal JTAG cable.
487 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
488 @cindex parport_write_on_exit
489 @*This will configure the parallel driver to write a known value to the parallel
490 interface on exiting OpenOCD
493 @section amt_jtagaccel options
495 @item @b{parport_port} <@var{number}>
497 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
498 @file{/dev/parport} device
500 @section ft2232 options
503 @item @b{ft2232_device_desc} <@var{description}>
504 @cindex ft2232_device_desc
505 @*The USB device description of the FTDI FT2232 device. If not specified, the FTDI
506 default value is used. This setting is only valid if compiled with FTD2XX support.
507 @item @b{ft2232_serial} <@var{serial-number}>
508 @cindex ft2232_serial
509 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
511 @item @b{ft2232_layout} <@var{name}>
512 @cindex ft2232_layout
513 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
514 signals. Valid layouts are
517 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
519 Amontec JTAGkey and JTAGkey-tiny
522 @item @b{olimex-jtag}
525 American Microsystems M5960
526 @item @b{evb_lm3s811}
527 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
528 SRST signals on external connector
532 Hitex STM32 Performance Stick
534 Tin Can Tools Flyswatter
535 @item @b{turtelizer2}
536 egnite Software turtelizer2
541 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
542 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
543 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
545 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
547 @item @b{ft2232_latency} <@var{ms}>
548 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
549 ft2232_read() fails to return the expected number of bytes. This can be caused by
550 USB communication delays and has proved hard to reproduce and debug. Setting the
551 FT2232 latency timer to a larger value increases delays for short USB packages but it
552 also reduces the risk of timeouts before receiving the expected number of bytes.
553 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
556 @section ep93xx options
557 @cindex ep93xx options
558 Currently, there are no options available for the ep93xx interface.
561 @section Target configuration
564 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
567 @*Defines a target that should be debugged. Currently supported types are:
582 If you want to use a target board that is not on this list, see Adding a new
585 Endianess may be @option{little} or @option{big}.
587 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
588 @cindex target_script
589 @*Event is one of the following:
590 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
591 @option{pre_resume} or @option{gdb_program_config}.
592 @option{post_reset} and @option{reset} will produce the same results.
594 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}> <@var{backup}|@var{nobackup}> [@option{virtual address}]
596 @*Specifies a working area for the debugger to use. This may be used to speed-up
597 downloads to target memory and flash operations, or to perform otherwise unavailable
598 operations (some coprocessor operations on ARM7/9 systems, for example). The last
599 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
600 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
603 @subsection arm7tdmi options
604 @cindex arm7tdmi options
605 target arm7tdmi <@var{endianess}> <@var{jtag#}>
606 @*The arm7tdmi target definition requires at least one additional argument, specifying
607 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
608 The optional [@var{variant}] parameter has been removed in recent versions.
609 The correct feature set is determined at runtime.
611 @subsection arm720t options
612 @cindex arm720t options
613 ARM720t options are similar to ARM7TDMI options.
615 @subsection arm9tdmi options
616 @cindex arm9tdmi options
617 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
618 @option{arm920t}, @option{arm922t} and @option{arm940t}.
619 This enables the hardware single-stepping support found on these cores.
621 @subsection arm920t options
622 @cindex arm920t options
623 ARM920t options are similar to ARM9TDMI options.
625 @subsection arm966e options
626 @cindex arm966e options
627 ARM966e options are similar to ARM9TDMI options.
629 @subsection cortex_m3 options
630 @cindex cortex_m3 options
631 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
632 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
633 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
634 be detected and the normal reset behaviour used.
636 @subsection xscale options
637 @cindex xscale options
638 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
639 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
641 @section Flash configuration
642 @cindex Flash configuration
645 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
646 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
648 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
649 and <@var{bus_width}> bytes using the selected flash <driver>.
652 @subsection lpc2000 options
653 @cindex lpc2000 options
655 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
656 <@var{clock}> [@var{calc_checksum}]
657 @*LPC flashes don't require the chip and bus width to be specified. Additional
658 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
659 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
660 of the target this flash belongs to (first is 0), the frequency at which the core
661 is currently running (in kHz - must be an integral number), and the optional keyword
662 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
665 @subsection cfi options
668 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
669 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
670 @*CFI flashes require the number of the target they're connected to as an additional
671 argument. The CFI driver makes use of a working area (specified for the target)
672 to significantly speed up operation.
674 @var{chip_width} and @var{bus_width} are specified in bytes.
676 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
680 @subsection at91sam7 options
681 @cindex at91sam7 options
683 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
684 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
685 reading the chip-id and type.
687 @subsection str7 options
690 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
691 @*variant can be either STR71x, STR73x or STR75x.
693 @subsection str9 options
696 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
697 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
699 str9x flash_config 0 4 2 0 0x80000
701 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
703 @subsection str9 options (str9xpec driver)
705 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
706 @*Before using the flash commands the turbo mode will need enabling using str9xpec
707 @option{enable_turbo} <@var{num>.}
709 Only use this driver for locking/unlocking the device or configuring the option bytes.
710 Use the standard str9 driver for programming.
712 @subsection stellaris (LM3Sxxx) options
713 @cindex stellaris (LM3Sxxx) options
715 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
716 @*stellaris flash plugin only require the @var{target#}.
718 @subsection stm32x options
719 @cindex stm32x options
721 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
722 @*stm32x flash plugin only require the @var{target#}.
724 @subsection aduc702x options
725 @cindex aduc702x options
727 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
728 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
730 @section mFlash configuration
731 @cindex mFlash configuration
734 @item @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
735 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
737 @*Configures a mflash for <@var{soc}> host bank at <@var{base}>. <@var{chip_width}> and
738 <@var{bus_width}> are bytes order. Pin number format is dependent on host GPIO calling convention.
739 If WP or DPD pin was not used, write -1. Currently, mflash bank support s3c2440 and pxa270.
741 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
743 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
745 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
747 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
751 @chapter Target library
752 @cindex Target library
754 OpenOCD comes with a target configuration script library. These scripts can be
755 used as-is or serve as a starting point.
757 The target library is published together with the openocd executable and
758 the path to the target library is in the OpenOCD script search path.
759 Similarly there are example scripts for configuring the JTAG interface.
761 The command line below uses the example parport configuration scripts
762 that ship with OpenOCD, then configures the str710.cfg target and
763 finally issues the init and reset command. The communication speed
764 is set to 10kHz for reset and 8MHz for post reset.
768 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
772 To list the target scripts available:
775 $ ls /usr/local/lib/openocd/target
777 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
778 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
779 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
780 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
788 OpenOCD allows user interaction through a GDB server (default: port 3333),
789 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
790 is available from both the telnet interface and a GDB session. To issue commands to the
791 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
792 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
795 The TCL interface is used as a simplified RPC mechanism that feeds all the
796 input into the TCL interpreter and returns the output from the evaluation of
802 @item @b{sleep} <@var{msec}>
804 @*Wait for n milliseconds before resuming. Useful in connection with script files
805 (@var{script} command and @var{target_script} configuration).
809 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
811 @item @b{debug_level} [@var{n}]
814 @*Display or adjust debug level to n<0-3>
816 @item @b{fast} [@var{enable|disable}]
818 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
819 downloads and fast memory access will work if the JTAG interface isn't too fast and
820 the core doesn't run at a too low frequency. Note that this option only changes the default
821 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
824 The target specific "dangerous" optimisation tweaking options may come and go
825 as more robust and user friendly ways are found to ensure maximum throughput
826 and robustness with a minimum of configuration.
828 Typically the "fast enable" is specified first on the command line:
831 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
834 @item @b{log_output} <@var{file}>
836 @*Redirect logging to <file> (default: stderr)
838 @item @b{script} <@var{file}>
840 @*Execute commands from <file>
844 @subsection Target state handling
846 @item @b{power} <@var{on}|@var{off}>
848 @*Turn power switch to target on/off.
849 No arguments: print status.
852 @item @b{reg} [@option{#}|@option{name}] [value]
854 @*Access a single register by its number[@option{#}] or by its [@option{name}].
855 No arguments: list all available registers for the current target.
856 Number or name argument: display a register
857 Number or name and value arguments: set register value
859 @item @b{poll} [@option{on}|@option{off}]
861 @*Poll the target for its current state. If the target is in debug mode, architecture
862 specific information about the current state is printed. An optional parameter
863 allows continuous polling to be enabled and disabled.
865 @item @b{halt} [@option{ms}]
867 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
868 Default [@option{ms}] is 5 seconds if no arg given.
869 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
870 will stop OpenOCD from waiting.
872 @item @b{wait_halt} [@option{ms}]
874 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
875 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
878 @item @b{resume} [@var{address}]
880 @*Resume the target at its current code position, or at an optional address.
881 OpenOCD will wait 5 seconds for the target to resume.
883 @item @b{step} [@var{address}]
885 @*Single-step the target at its current code position, or at an optional address.
887 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
889 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
891 With no arguments a "reset run" is executed
895 @*Let the target run.
898 @*Immediately halt the target (works only with certain configurations).
901 @*Immediately halt the target, and execute the reset script (works only with certain
905 @item @b{soft_reset_halt}
907 @*Requesting target halt and executing a soft reset.
910 @subsection Memory access commands
914 display available ram memory.
916 These commands allow accesses of a specific size to the memory system:
918 @item @b{mdw} <@var{addr}> [@var{count}]
920 @*display memory words
921 @item @b{mdh} <@var{addr}> [@var{count}]
923 @*display memory half-words
924 @item @b{mdb} <@var{addr}> [@var{count}]
926 @*display memory bytes
927 @item @b{mww} <@var{addr}> <@var{value}>
930 @item @b{mwh} <@var{addr}> <@var{value}>
932 @*write memory half-word
933 @item @b{mwb} <@var{addr}> <@var{value}>
937 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
940 @*Load image <@var{file}> to target memory at <@var{address}>
941 @item @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
942 @cindex fast_load_image
943 @anchor{fast_load_image}
944 @*Normally you should be using @b{load_image} or GDB load. However, for
945 testing purposes or when IO overhead is significant(OpenOCD running on embedded
946 host), then storing the image in memory and uploading the image to the target
947 can be a way to upload e.g. multiple debug sessions when the binary does not change.
948 Arguments as @b{load_image}, but image is stored in OpenOCD host
949 memory, i.e. does not affect target. This approach is also useful when profiling
950 target programming performance as IO and target programming can easily be profiled
955 @*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
956 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
959 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
960 (binary) <@var{file}>.
961 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
963 @*Verify <@var{file}> against target memory starting at <@var{address}>.
964 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
967 @subsection Breakpoint commands
968 @cindex Breakpoint commands
970 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
972 @*set breakpoint <address> <length> [hw]
973 @item @b{rbp} <@var{addr}>
975 @*remove breakpoint <adress>
976 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
978 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
979 @item @b{rwp} <@var{addr}>
981 @*remove watchpoint <adress>
984 @subsection Flash commands
985 @cindex Flash commands
987 @item @b{flash banks}
989 @*List configured flash banks
990 @item @b{flash info} <@var{num}>
992 @*Print info about flash bank <@option{num}>
993 @item @b{flash probe} <@var{num}>
995 @*Identify the flash, or validate the parameters of the configured flash. Operation
996 depends on the flash type.
997 @item @b{flash erase_check} <@var{num}>
998 @cindex flash erase_check
999 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
1000 updates the erase state information displayed by @option{flash info}. That means you have
1001 to issue an @option{erase_check} command after erasing or programming the device to get
1002 updated information.
1003 @item @b{flash protect_check} <@var{num}>
1004 @cindex flash protect_check
1005 @*Check protection state of sectors in flash bank <num>.
1006 @option{flash erase_sector} using the same syntax.
1007 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
1008 @cindex flash erase_sector
1009 @anchor{flash erase_sector}
1010 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
1011 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
1012 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
1014 @item @b{flash erase_address} <@var{address}> <@var{length}>
1015 @cindex flash erase_address
1016 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
1017 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
1018 @cindex flash write_bank
1019 @anchor{flash write_bank}
1020 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
1021 <@option{offset}> bytes from the beginning of the bank.
1022 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
1023 @cindex flash write_image
1024 @anchor{flash write_image}
1025 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
1026 [@var{offset}] can be specified and the file [@var{type}] can be specified
1027 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
1028 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
1029 if the @option{erase} parameter is given.
1030 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
1031 @cindex flash protect
1032 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
1033 <@var{last}> of @option{flash bank} <@var{num}>.
1036 @subsection mFlash commands
1037 @cindex mFlash commands
1039 @item @b{mflash probe}
1040 @cindex mflash probe
1042 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
1043 @cindex mflash write
1044 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
1045 <@var{offset}> bytes from the beginning of the bank.
1046 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
1048 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
1053 @section Target Commands
1054 @cindex Target Commands
1056 @subsection Overview
1058 Pre "TCL" - many commands in OpenOCD where implemented as C functions. Post "TCL"
1059 (Jim-Tcl to be more exact, June 2008) TCL became a bigger part of OpenOCD.
1061 One of the biggest changes is the introduction of 'target specific'
1062 commands. When every time you create a target, a special command name is
1063 created specifically for that target.
1064 For example - in TCL/TK - if you create a button (or any other screen object) you
1065 can specify various "button configuration parameters". One of those parameters is
1066 the "object cmd/name" [ In TK - this is referred to as the object path ]. Later
1067 you can use that 'path' as a command to modify the button, for example to make it
1068 "grey", or change the color. In effect, the "path" function is an 'object
1069 oriented command'. The TCL change in OpenOCD follows the same principle, you create
1070 a target, and a specific "targetname" command is created.
1072 There are two methods of creating a target:
1076 Using the old syntax (deprecated). Target names are autogenerated as:
1077 "target0", "target1", etc.;
1080 Using the new syntax, you can specify the name of the target.
1084 As most users will have a single JTAG target, and by default the command name will
1085 probably default to "target0", thus for reasons of simplicity the instructions below
1086 use the name "target0".
1088 @subsection Commands
1090 OpenOCD has the following 'target' or 'target-like' commands:
1094 @b{targets (plural)} - lists all known targets and a little bit of information about each
1095 target, most importantly the target *COMMAND*NAME* (it also lists the target number);
1098 @b{target (singular)} - used to create, configure list, etc the targets;
1101 @b{target0} - the command object for the first target. Unless you specified another name.
1105 @subsubsection Targets Command
1106 @cindex Targets Command
1107 The "targets" command has 2 functions:
1111 With a parameter, you can change the current command line target.
1113 NOTE: "with a parameter" is really only useful with 'multiple JTAG targets' not something
1114 you normally encounter (ie: If you had 2 arm chips - sharing the same JTAG chain).
1116 # using a target name.
1117 (gdb) mon targets target0
1118 # or a target by number.
1121 @cindex with a parameter
1123 Plain, without any parameter lists targets, for example:
1127 CmdName Type Endian ChainPos State
1128 -- ---------- ---------- ---------- -------- ----------
1129 0: target0 arm7tdmi little 0 halted
1135 in this example, a single target;
1137 target number 0 (1st column);
1139 the 'object name' is target0 (the default name);
1145 the position in the JTAG chain;
1147 and is currently halted.
1149 @cindex without any parameter
1152 @subsubsection Target Command
1153 @cindex Target Command
1155 The "target" command has the following options:
1161 target create CMDNAME TYPE ... config options ...
1164 argv[2] = the 'object command'
1165 (normally, target0, see (3) above)
1166 argv[3] = the target type, ie: arm7tdmi
1167 argv[4..N] = configuration parameters
1172 Lists all supported target types; ie: arm7tdmi, xscale, fericon, cortex-m3.
1173 The result TCL list of all known target types (and is human readable).
1177 Returns a TCL list of all known target commands (and is human readable).
1181 foreach t [target names] {
1182 puts [format "Target: %s\n" $t]
1188 Returns the TCL command name of the current target.
1192 set ct [target current]
1193 set t [$ct cget -type]
1195 puts "Current target name is: $ct, and is a: $t"
1198 target number <VALUE>
1200 Returns the TCL command name of the specified target.
1204 set thename [target number $x]
1205 puts [format "Target %d is: %s\n" $x $thename]
1207 For instance, assuming the defaults
1211 Would return 'target0' (or whatever you called it)
1215 Returns the larget+1 target number.
1219 set c [target count]
1220 for { set x 0 } { $x < $c } { incr x } {
1221 # Assuming you have this function..
1222 print_target_details $x
1227 @subsubsection Target0 Command
1228 @cindex Target0 Command
1229 The "target0" command (the "Target Object" command):
1231 Once a target is 'created' a command object by that targets name is created, for example
1233 target create BiGRed arm7tdmi -endian little -chain-position 3
1236 Would create a [case sensitive] "command" BiGRed
1238 If you use the old [deprecated] syntax, the name is automatically
1239 generated and is in the form:
1241 target0, target1, target2, target3, ... etc.
1244 @subsubsection Target CREATE, CONFIGURE and CGET Options Command
1245 @cindex Target CREATE, CONFIGURE and CGET Options Command
1248 target create CMDNAME TYPE [configure-options]
1249 CMDNAME configure [configure-options]
1250 CMDNAME cget [configure-options]
1254 In the 'create' case, one is creating the target and can specify any
1255 number of configuration parameters.
1257 In the 'CMDNAME configure' case, one can change the setting [Not all things can, or should be changed].
1259 In the 'CMDNAME cget' case, the goal is to query the target for a
1260 specific configuration option.
1263 In the above, the "default" name target0 is 'target0'.
1267 From the (gdb) prompt, one can type this:
1270 (gdb) mon target0 configure -endian big
1273 And change target0 to 'big-endian'. This is a contrived example,
1274 specifically for this document - don't expect changing endian
1275 'mid-operation' to work you should set the endian at creation.
1277 Known options [30/august/2008] are:
1280 [Mandatory 'create' Options]
1283 type arm7tdmi|arm720|etc ...
1285 chain-position NUMBER
1293 event EVENTNAME "tcl-action"
1303 work-area-backup BOOLEAN
1306 Hint: To get a list of available options, try this:
1308 (gdb) mon target0 cget -BLAHBLAHBLAH
1311 the above causes an error - and a helpful list of valid options.
1313 One can query any of the above options at run time, for example:
1315 (gdb) mon target0 cget -OPTION [param]
1321 # For all targets...
1322 set c [target count]
1323 for { set x 0 } { $x < $c } { incr x ] {
1324 set n [target number $x]
1325 set t [$n cget -type]
1326 set e [$n cget -endian]
1327 puts [format "%d: %s, %s, endian: %s\n" $x $n $t $n]
1334 0: pic32chip, mips_m4k, endain: little
1335 1: arm7, arm7tdmi, endian: big
1336 2: blackfin, bf534, endian: little
1339 Notice the above example is not target0, target1, target2 Why? Because in this contrived multi-target example -
1340 more human understandable target names might be helpful.
1342 For example these two are the same:
1345 (gdb) mon blackfin configure -event FOO {puts "Hi mom"}
1351 (gdb) mon [target number 2] configure -event FOO {puts "Hi mom"}
1354 In the second case, we use [] to get the command name of target #2, in this contrived example - it is "blackfin".
1356 Two important configuration options are:
1358 "-event" and "-reset"
1360 The "-reset" option specifies what should happen when the chip is reset, for example should it 'halt', 're-init',
1363 The "-event" option less you specify a TCL command to occur when a specific event occurs.
1365 @subsubsection Other Target Commands
1366 @cindex Other Target Commands
1368 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
1370 Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
1373 @subsection Target Events
1374 @cindex Target Events
1376 @subsubsection Overview
1378 At various points in time - certain 'target' events happen. You can create a custom event action to occur at that time.
1379 For example - after reset, the PLLs and CLOCKs may need to be reconfigured, or perhaps the SDRAM needs to be re-initialized.
1380 Often the easiest way to do that is to create a simple script file containing the series of (mww [poke memory]) commands
1381 you would type by hand, to reconfigure the target clocks. You could specify the "event action" like this:
1384 (gdb) mon target0 configure -event reset-init "script cfg.clocks"
1387 In the above example, when the event "reset-init" occurs, the "action-string" will be evaluated as if you typed it at the
1390 @item @b{Option1} - The simple approach (above) is to create a script file with lots of "mww" (memory write word) commands
1391 to configure your targets clocks and/or external memory;
1392 @item @b{Option2} - You can instead create a fancy TCL procedure and invoke that procedure instead of sourcing a file [In fact,
1393 "script" is a TCL procedure that loads a file].
1396 @subsubsection Details
1398 There are many events one could use, to get a current list of events type the following invalid command, you'll get a helpful
1399 "runtime error" message, see below [list valid as of 30/august/2008]:
1402 (gdb) mon target0 cget -event FAFA
1403 Runtime error, file "../../../openocd23/src/helper/command.c", line 433:
1404 -event: Unknown: FAFA, try one of: old-pre_reset,
1405 old-gdb_program_config, old-post_reset, halted,
1406 resumed, resume-start, resume-end, reset-start,
1407 reset-assert-pre, reset-assert-post,
1408 reset-deassert-pre, reset-deassert-post,
1409 reset-halt-pre, reset-halt-post, reset-wait-pre,
1410 reset-wait-post, reset-init, reset-end,
1411 examine-start, examine-end, debug-halted,
1412 debug-resumed, gdb-attach, gdb-detach,
1413 gdb-flash-write-start, gdb-flash-write-end,
1414 gdb-flash-erase-start, gdb-flash-erase-end,
1415 resume-start, resume-ok, or resume-end
1418 NOTE: The event-names "old-*" are deprecated and exist only to help old scripts continue to function, and the old "target_script"
1419 command to work. Please do not rely on them.
1421 These are some other important names:
1423 @item gdb-flash-erase-start
1424 @item gdb-flash-erase-end
1425 @item gdb-flash-write-start
1426 @item gdb-flash-write-end
1429 These occur when GDB/OpenOCD attempts to erase & program the FLASH chip via GDB. For example - some PCBs may have a simple GPIO
1430 pin that acts like a "flash write protect" you might need to write a script that disables "write protect".
1432 To get a list of current 'event actions', type the following command:
1435 (gdb) mon target0 eventlist
1437 Event actions for target (0) target0
1440 ------------------------- | ----------------------------------------
1441 old-post_reset | script event/sam7x256_reset.script
1444 Here is a simple example for all targets:
1447 (gdb) mon foreach x [target names] { $x eventlist }
1450 The above uses some TCL tricks:
1452 @item foreach VARIABLE LIST BODY
1453 @item to generate the list, we use [target names]
1454 @item the BODY, contains $x - the loop variable and expands to the target specific name
1457 Recalling the earlier discussion - the "object command" there are other things you can
1458 do besides "configure" the target.
1460 Note: Many of these commands exist as "global" commands, and they also exist as target
1461 specific commands. For example, the "mww" (memory write word) operates on the current
1462 target if you have more then 1 target, you must switch. In contrast to the normal
1463 commands, these commands operate on the specific target. For example, the command "mww"
1464 writes data to the *current* command line target.
1466 Often, you have only a single target - but if you have multiple targets (ie: a PIC32
1467 and an at91sam7 - your reset-init scripts might get a bit more complicated, ie: you must
1468 specify which of the two chips you want to write to. Writing 'pic32' clock configuration
1469 to an at91sam7 does not work).
1471 The commands are [as of 30/august/2008]:
1473 TNAME mww ADDRESS VALUE
1474 TNAME mwh ADDRESS VALUE
1475 TNAME mwb ADDRESS VALUE
1476 Write(poke): 32, 16, 8bit values to memory.
1478 TNAME mdw ADDRESS VALUE
1479 TNAME mdh ADDRESS VALUE
1480 TNAME mdb ADDRESS VALUE
1481 Human 'hexdump' with ascii 32, 16, 8bit values
1483 TNAME mem2array [see mem2array command]
1484 TNAME array2mem [see array2mem command]
1487 Returns the current state of the target.
1490 See 'advanced target reset'
1492 See 'advanced target reset'
1494 See 'advanced target reset'
1495 TNAME reset deassert
1496 See 'advanced target reset'
1498 See 'advanced target reset'
1499 TNAME waitstate STATENAME
1500 See 'advanced target reset'
1504 @section Target Specific Commands
1505 @cindex Target Specific Commands
1507 @subsection AT91SAM7 specific commands
1508 @cindex AT91SAM7 specific commands
1509 The flash configuration is deduced from the chip identification register. The flash
1510 controller handles erases automatically on a page (128/265 byte) basis so erase is
1511 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
1512 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
1513 that can be erased separatly. Only an EraseAll command is supported by the controller
1514 for each flash plane and this is called with
1516 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
1517 @*bulk erase flash planes first_plane to last_plane.
1518 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
1519 @cindex at91sam7 gpnvm
1520 @*set or clear a gpnvm bit for the processor
1523 @subsection STR9 specific commands
1524 @cindex STR9 specific commands
1525 These are flash specific commands when using the str9xpec driver.
1527 @item @b{str9xpec enable_turbo} <@var{num}>
1528 @cindex str9xpec enable_turbo
1529 @*enable turbo mode, simply this will remove the str9 from the chain and talk
1530 directly to the embedded flash controller.
1531 @item @b{str9xpec disable_turbo} <@var{num}>
1532 @cindex str9xpec disable_turbo
1533 @*restore the str9 into jtag chain.
1534 @item @b{str9xpec lock} <@var{num}>
1535 @cindex str9xpec lock
1536 @*lock str9 device. The str9 will only respond to an unlock command that will
1538 @item @b{str9xpec unlock} <@var{num}>
1539 @cindex str9xpec unlock
1540 @*unlock str9 device.
1541 @item @b{str9xpec options_read} <@var{num}>
1542 @cindex str9xpec options_read
1543 @*read str9 option bytes.
1544 @item @b{str9xpec options_write} <@var{num}>
1545 @cindex str9xpec options_write
1546 @*write str9 option bytes.
1549 @subsection STR9 configuration
1550 @cindex STR9 configuration
1552 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
1553 <@var{BBADR}> <@var{NBBADR}>
1554 @cindex str9x flash_config
1555 @*Configure str9 flash controller.
1557 eg. str9x flash_config 0 4 2 0 0x80000
1559 BBSR - Boot Bank Size register
1560 NBBSR - Non Boot Bank Size register
1561 BBADR - Boot Bank Start Address register
1562 NBBADR - Boot Bank Start Address register
1566 @subsection STR9 option byte configuration
1567 @cindex STR9 option byte configuration
1569 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1570 @cindex str9xpec options_cmap
1571 @*configure str9 boot bank.
1572 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1573 @cindex str9xpec options_lvdthd
1574 @*configure str9 lvd threshold.
1575 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1576 @cindex str9xpec options_lvdsel
1577 @*configure str9 lvd source.
1578 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1579 @cindex str9xpec options_lvdwarn
1580 @*configure str9 lvd reset warning source.
1583 @subsection STM32x specific commands
1584 @cindex STM32x specific commands
1586 These are flash specific commands when using the stm32x driver.
1588 @item @b{stm32x lock} <@var{num}>
1590 @*lock stm32 device.
1591 @item @b{stm32x unlock} <@var{num}>
1592 @cindex stm32x unlock
1593 @*unlock stm32 device.
1594 @item @b{stm32x options_read} <@var{num}>
1595 @cindex stm32x options_read
1596 @*read stm32 option bytes.
1597 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1598 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1599 @cindex stm32x options_write
1600 @*write stm32 option bytes.
1601 @item @b{stm32x mass_erase} <@var{num}>
1602 @cindex stm32x mass_erase
1603 @*mass erase flash memory.
1606 @subsection Stellaris specific commands
1607 @cindex Stellaris specific commands
1609 These are flash specific commands when using the Stellaris driver.
1611 @item @b{stellaris mass_erase} <@var{num}>
1612 @cindex stellaris mass_erase
1613 @*mass erase flash memory.
1617 @section Architecture Specific Commands
1618 @cindex Architecture Specific Commands
1620 @subsection ARMV4/5 specific commands
1621 @cindex ARMV4/5 specific commands
1623 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1624 or Intel XScale (XScale isn't supported yet).
1626 @item @b{armv4_5 reg}
1628 @*Display a list of all banked core registers, fetching the current value from every
1629 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1631 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1632 @cindex armv4_5 core_mode
1633 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1634 The target is resumed in the currently set @option{core_mode}.
1637 @subsection ARM7/9 specific commands
1638 @cindex ARM7/9 specific commands
1640 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1641 ARM920t or ARM926EJ-S.
1643 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1644 @cindex arm7_9 dbgrq
1645 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
1646 safe for all but ARM7TDMI--S cores (like Philips LPC).
1647 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1648 @cindex arm7_9 fast_memory_access
1649 @anchor{arm7_9 fast_memory_access}
1650 @*Allow OpenOCD to read and write memory without checking completion of
1651 the operation. This provides a huge speed increase, especially with USB JTAG
1652 cables (FT2232), but might be unsafe if used with targets running at a very low
1653 speed, like the 32kHz startup clock of an AT91RM9200.
1654 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1655 @cindex arm7_9 dcc_downloads
1656 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1657 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1658 unsafe, especially with targets running at a very low speed. This command was introduced
1659 with OpenOCD rev. 60.
1662 @subsection ARM720T specific commands
1663 @cindex ARM720T specific commands
1666 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1667 @cindex arm720t cp15
1668 @*display/modify cp15 register <@option{num}> [@option{value}].
1669 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1670 @cindex arm720t md<bhw>_phys
1671 @*Display memory at physical address addr.
1672 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1673 @cindex arm720t mw<bhw>_phys
1674 @*Write memory at physical address addr.
1675 @item @b{arm720t virt2phys} <@var{va}>
1676 @cindex arm720t virt2phys
1677 @*Translate a virtual address to a physical address.
1680 @subsection ARM9TDMI specific commands
1681 @cindex ARM9TDMI specific commands
1684 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1685 @cindex arm9tdmi vector_catch
1686 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1687 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1688 @option{irq} @option{fiq}.
1690 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1693 @subsection ARM966E specific commands
1694 @cindex ARM966E specific commands
1697 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1698 @cindex arm966e cp15
1699 @*display/modify cp15 register <@option{num}> [@option{value}].
1702 @subsection ARM920T specific commands
1703 @cindex ARM920T specific commands
1706 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1707 @cindex arm920t cp15
1708 @*display/modify cp15 register <@option{num}> [@option{value}].
1709 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1710 @cindex arm920t cp15i
1711 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1712 @item @b{arm920t cache_info}
1713 @cindex arm920t cache_info
1714 @*Print information about the caches found. This allows you to see if your target
1715 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1716 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1717 @cindex arm920t md<bhw>_phys
1718 @*Display memory at physical address addr.
1719 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1720 @cindex arm920t mw<bhw>_phys
1721 @*Write memory at physical address addr.
1722 @item @b{arm920t read_cache} <@var{filename}>
1723 @cindex arm920t read_cache
1724 @*Dump the content of ICache and DCache to a file.
1725 @item @b{arm920t read_mmu} <@var{filename}>
1726 @cindex arm920t read_mmu
1727 @*Dump the content of the ITLB and DTLB to a file.
1728 @item @b{arm920t virt2phys} <@var{va}>
1729 @cindex arm920t virt2phys
1730 @*Translate a virtual address to a physical address.
1733 @subsection ARM926EJS specific commands
1734 @cindex ARM926EJS specific commands
1737 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1738 @cindex arm926ejs cp15
1739 @*display/modify cp15 register <@option{num}> [@option{value}].
1740 @item @b{arm926ejs cache_info}
1741 @cindex arm926ejs cache_info
1742 @*Print information about the caches found.
1743 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1744 @cindex arm926ejs md<bhw>_phys
1745 @*Display memory at physical address addr.
1746 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1747 @cindex arm926ejs mw<bhw>_phys
1748 @*Write memory at physical address addr.
1749 @item @b{arm926ejs virt2phys} <@var{va}>
1750 @cindex arm926ejs virt2phys
1751 @*Translate a virtual address to a physical address.
1755 @section Debug commands
1756 @cindex Debug commands
1757 The following commands give direct access to the core, and are most likely
1758 only useful while debugging OpenOCD.
1760 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1761 @cindex arm7_9 write_xpsr
1762 @*Immediately write either the current program status register (CPSR) or the saved
1763 program status register (SPSR), without changing the register cache (as displayed
1764 by the @option{reg} and @option{armv4_5 reg} commands).
1765 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1766 <@var{0=cpsr},@var{1=spsr}>
1767 @cindex arm7_9 write_xpsr_im8
1768 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1769 operation (similar to @option{write_xpsr}).
1770 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1771 @cindex arm7_9 write_core_reg
1772 @*Write a core register, without changing the register cache (as displayed by the
1773 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1774 encoding of the [M4:M0] bits of the PSR.
1778 @section JTAG commands
1779 @cindex JTAG commands
1781 @item @b{scan_chain}
1783 @*Print current scan chain configuration.
1784 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1786 @*Toggle reset lines.
1787 @item @b{endstate} <@var{tap_state}>
1789 @*Finish JTAG operations in <@var{tap_state}>.
1790 @item @b{runtest} <@var{num_cycles}>
1792 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
1793 @item @b{statemove} [@var{tap_state}]
1795 @*Move to current endstate or [@var{tap_state}]
1796 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1798 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1799 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1801 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1802 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1803 @cindex verify_ircapture
1804 @*Verify value captured during Capture-IR. Default is enabled.
1805 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1807 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1808 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1810 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1814 @section Target Requests
1815 @cindex Target Requests
1816 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1817 See libdcc in the contrib dir for more details.
1819 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1820 @cindex target_request debugmsgs
1821 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1827 If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
1828 be used to access files on PCs(either developer PC or some other PC).
1830 The way this works is to prefix a filename by "/tftp/ip/" and append
1831 the tftp path on the tftp server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf"
1832 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
1833 if the file was hosted on the embedded host.
1835 In order to achieve decent performance, you must choose a tftp server
1836 that supports a packet size bigger than the default packet size(512 bytes). There
1837 are numerous tftp servers out there(free and commercial) and you will have to do
1838 a bit of googling to find something that fits your requirements.
1840 @node Sample Scripts
1841 @chapter Sample Scripts
1844 This page shows how to use the target library.
1846 The configuration script can be divided in the following section:
1848 @item daemon configuration
1850 @item jtag scan chain
1851 @item target configuration
1852 @item flash configuration
1855 Detailed information about each section can be found at OpenOCD configuration.
1857 @section AT91R40008 example
1858 @cindex AT91R40008 example
1859 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1860 the CPU upon startup of the OpenOCD daemon.
1862 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1866 @node GDB and OpenOCD
1867 @chapter GDB and OpenOCD
1868 @cindex GDB and OpenOCD
1869 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1870 to debug remote targets.
1872 @section Connecting to gdb
1873 @cindex Connecting to gdb
1874 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
1875 known bug where it produces bogus memory access errors, which has since
1876 been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
1879 A connection is typically started as follows:
1881 target remote localhost:3333
1883 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1885 To see a list of available OpenOCD commands type @option{monitor help} on the
1888 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1889 to be sent by the gdb server (openocd) to gdb. Typical information includes
1890 packet size and device memory map.
1892 Previous versions of OpenOCD required the following gdb options to increase
1893 the packet size and speed up gdb communication.
1895 set remote memory-write-packet-size 1024
1896 set remote memory-write-packet-size fixed
1897 set remote memory-read-packet-size 1024
1898 set remote memory-read-packet-size fixed
1900 This is now handled in the @option{qSupported} PacketSize.
1902 @section Programming using gdb
1903 @cindex Programming using gdb
1905 By default the target memory map is sent to gdb, this can be disabled by
1906 the following OpenOCD config option:
1908 gdb_memory_map disable
1910 For this to function correctly a valid flash config must also be configured
1911 in OpenOCD. For faster performance you should also configure a valid
1914 Informing gdb of the memory map of the target will enable gdb to protect any
1915 flash area of the target and use hardware breakpoints by default. This means
1916 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1917 using a memory map. @xref{gdb_breakpoint_override}.
1919 To view the configured memory map in gdb, use the gdb command @option{info mem}
1920 All other unasigned addresses within gdb are treated as RAM.
1922 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1923 this can be changed to the old behaviour by using the following gdb command.
1925 set mem inaccessible-by-default off
1928 If @option{gdb_flash_program enable} is also used, gdb will be able to
1929 program any flash memory using the vFlash interface.
1931 gdb will look at the target memory map when a load command is given, if any
1932 areas to be programmed lie within the target flash area the vFlash packets
1935 If the target needs configuring before gdb programming, a script can be executed.
1937 target_script 0 gdb_program_config config.script
1940 To verify any flash programming the gdb command @option{compare-sections}
1943 @node TCL and OpenOCD
1944 @chapter TCL and OpenOCD
1945 @cindex TCL and OpenOCD
1946 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1949 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1951 The command and file interfaces are fairly straightforward, while the network
1952 port is geared toward intergration with external clients. A small example
1953 of an external TCL script that can connect to openocd is shown below.
1956 # Simple tcl client to connect to openocd
1957 puts "Use empty line to exit"
1958 set fo [socket 127.0.0.1 6666]
1959 puts -nonewline stdout "> "
1961 while {[gets stdin line] >= 0} {
1962 if {$line eq {}} break
1967 puts -nonewline stdout "> "
1973 This script can easily be modified to front various GUIs or be a sub
1974 component of a larger framework for control and interaction.
1977 @node TCL scripting API
1978 @chapter TCL scripting API
1979 @cindex TCL scripting API
1982 The commands are stateless. E.g. the telnet command line has a concept
1983 of currently active target, the Tcl API proc's take this sort of state
1984 information as an argument to each proc.
1986 There are three main types of return values: single value, name value
1987 pair list and lists.
1989 Name value pair. The proc 'foo' below returns a name/value pair
1995 > set foo(you) Oyvind
1996 > set foo(mouse) Micky
1997 > set foo(duck) Donald
2005 me Duane you Oyvind mouse Micky duck Donald
2007 Thus, to get the names of the associative array is easy:
2009 foreach { name value } [set foo] {
2010 puts "Name: $name, Value: $value"
2014 Lists returned must be relatively small. Otherwise a range
2015 should be passed in to the proc in question.
2017 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
2018 is the low level API upon which "flash banks" is implemented.
2021 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2023 Read memory and return as a TCL array for script processing
2024 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2026 Convert a TCL array to memory locations and write the values
2027 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
2029 Return information about the flash banks
2032 OpenOCD commands can consist of two words, e.g. "flash banks". The
2033 startup.tcl "unknown" proc will translate this into a tcl proc
2034 called "flash_banks".
2038 @chapter Deprecated/Removed Commands
2039 @cindex Deprecated/Removed Commands
2040 Certain OpenOCD commands have been deprecated/removed during the various revisions.
2043 @item @b{load_binary}
2045 @*use @option{load_image} command with same args. @xref{load_image}.
2048 @*@option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
2049 always does a @option{reset run} when passed no arguments.
2050 @item @b{dump_binary}
2052 @*use @option{dump_image} command with same args. @xref{dump_image}.
2053 @item @b{flash erase}
2055 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
2056 @item @b{flash write}
2058 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2059 @item @b{flash write_binary}
2060 @cindex flash write_binary
2061 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2062 @item @b{arm7_9 fast_writes}
2063 @cindex arm7_9 fast_writes
2064 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
2065 @item @b{flash auto_erase}
2066 @cindex flash auto_erase
2067 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
2068 @item @b{daemon_startup}
2069 @cindex daemon_startup
2070 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
2071 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
2072 and @option{target cortex_m3 little reset_halt 0}.
2073 @item @b{arm7_9 sw_bkpts}
2074 @cindex arm7_9 sw_bkpts
2075 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
2076 @item @b{arm7_9 force_hw_bkpts}
2077 @cindex arm7_9 force_hw_bkpts
2078 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
2079 for flash if the gdb memory map has been set up(default when flash is declared in
2080 target configuration). @xref{gdb_breakpoint_override}.
2081 @item @b{run_and_halt_time}
2082 @cindex run_and_halt_time
2083 @*This command has been removed for simpler reset behaviour, it can be simulated with the
2096 @item OpenOCD complains about a missing cygwin1.dll.
2098 Make sure you have Cygwin installed, or at least a version of OpenOCD that
2099 claims to come with all the necessary dlls. When using Cygwin, try launching
2100 OpenOCD from the Cygwin shell.
2102 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
2103 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
2104 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
2106 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
2107 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
2108 software breakpoints consume one of the two available hardware breakpoints.
2110 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
2111 and works sometimes fine.
2113 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
2114 clock at the time you're programming the flash. If you've specified the crystal's
2115 frequency, make sure the PLL is disabled, if you've specified the full core speed
2116 (e.g. 60MHz), make sure the PLL is enabled.
2118 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
2119 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
2120 out while waiting for end of scan, rtck was disabled".
2122 Make sure your PC's parallel port operates in EPP mode. You might have to try several
2123 settings in your PC BIOS (ECP, EPP, and different versions of those).
2125 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
2126 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
2127 memory read caused data abort".
2129 The errors are non-fatal, and are the result of GDB trying to trace stack frames
2130 beyond the last valid frame. It might be possible to prevent this by setting up
2131 a proper "initial" stack frame, if you happen to know what exactly has to
2132 be done, feel free to add this here.
2134 @item I get the following message in the OpenOCD console (or log file):
2135 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
2137 This warning doesn't indicate any serious problem, as long as you don't want to
2138 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
2139 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
2140 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
2141 independently. With this setup, it's not possible to halt the core right out of
2142 reset, everything else should work fine.
2144 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
2145 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
2146 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
2147 quit with an error message. Is there a stability issue with OpenOCD?
2149 No, this is not a stability issue concerning OpenOCD. Most users have solved
2150 this issue by simply using a self-powered USB hub, which they connect their
2151 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
2152 supply stable enough for the Amontec JTAGkey to be operated.
2154 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
2155 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
2156 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
2157 What does that mean and what might be the reason for this?
2159 First of all, the reason might be the USB power supply. Try using a self-powered
2160 hub instead of a direct connection to your computer. Secondly, the error code 4
2161 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
2162 chip ran into some sort of error - this points us to a USB problem.
2164 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
2165 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
2166 What does that mean and what might be the reason for this?
2168 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
2169 has closed the connection to OpenOCD. This might be a GDB issue.
2171 @item In the configuration file in the section where flash device configurations
2172 are described, there is a parameter for specifying the clock frequency for
2173 LPC2000 internal flash devices (e.g.
2174 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
2175 which must be specified in kilohertz. However, I do have a quartz crystal of a
2176 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
2177 Is it possible to specify real numbers for the clock frequency?
2179 No. The clock frequency specified here must be given as an integral number.
2180 However, this clock frequency is used by the In-Application-Programming (IAP)
2181 routines of the LPC2000 family only, which seems to be very tolerant concerning
2182 the given clock frequency, so a slight difference between the specified clock
2183 frequency and the actual clock frequency will not cause any trouble.
2185 @item Do I have to keep a specific order for the commands in the configuration file?
2187 Well, yes and no. Commands can be given in arbitrary order, yet the devices
2188 listed for the JTAG scan chain must be given in the right order (jtag_device),
2189 with the device closest to the TDO-Pin being listed first. In general,
2190 whenever objects of the same type exist which require an index number, then
2191 these objects must be given in the right order (jtag_devices, targets and flash
2192 banks - a target references a jtag_device and a flash bank references a target).
2194 @item Sometimes my debugging session terminates with an error. When I look into the
2195 log file, I can see these error messages: Error: arm7_9_common.c:561
2196 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP