1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD.
55 * Developers:: OpenOCD developers
56 * Building:: Building OpenOCD
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * General Commands:: General Commands
69 * JTAG Commands:: JTAG Commands
70 * Sample Scripts:: Sample Target Scripts
72 * GDB and OpenOCD:: Using GDB and OpenOCD
73 * TCL scripting API:: Tcl scripting API
74 * Upgrading:: Deprecated/Removed Commands
75 * Target library:: Target library
76 * FAQ:: Frequently Asked Questions
77 * TCL Crash Course:: TCL Crash Course
78 * License:: GNU Free Documentation License
79 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
80 @comment case issue with ``Index.html'' and ``index.html''
81 @comment Occurs when creating ``--html --no-split'' output
82 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
83 * OpenOCD Index:: Main index.
90 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
91 in-system programming and boundary-scan testing for embedded target
94 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
95 with the JTAG (IEEE 1149.1) complient taps on your target board.
97 @b{Dongles:} OpenOCD currently many types of hardware dongles: USB
98 Based, Parallel Port Based, and other standalone boxes that run
99 OpenOCD internally. See the section titled: @xref{JTAG Hardware
102 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t,
103 ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
104 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
105 debugged via the GDB Protocol.
107 @b{Flash Programing:} Flash writing is supported for external CFI
108 compatible flashes (Intel and AMD/Spansion command set) and several
109 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
110 STM32x). Preliminary support for using the LPC3180's NAND flash
111 controller is included.
117 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
118 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
119 Others interested in improving the state of free and open debug and testing technology
120 are welcome to participate.
122 Other developers have contributed support for additional targets and flashes as well
123 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
125 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
129 @cindex building OpenOCD
131 If you are interested in getting actual work done rather than building
132 OpenOCD, then check if your interface supplier provides binaries for
133 you. Chances are that that binary is from some SVN version that is more
134 stable than SVN trunk where bleeding edge development takes place.
137 You can download the current SVN version with SVN client of your choice from the
138 following repositories:
140 (@uref{svn://svn.berlios.de/openocd/trunk})
144 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
146 Using the SVN command line client, you can use the following command to fetch the
147 latest version (make sure there is no (non-svn) directory called "openocd" in the
151 svn checkout svn://svn.berlios.de/openocd/trunk openocd
154 Building OpenOCD requires a recent version of the GNU autotools.
155 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
156 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
157 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
158 paths, resulting in obscure dependency errors (This is an observation I've gathered
159 from the logs of one user - correct me if I'm wrong).
161 You further need the appropriate driver files, if you want to build support for
162 a FTDI FT2232 based interface:
164 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
165 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
166 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
167 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
170 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
171 see contrib/libftdi for more details.
173 In general, the D2XX driver provides superior performance (several times as fast),
174 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
175 a kernel module, only a user space library.
177 To build OpenOCD (on both Linux and Cygwin), use the following commands:
181 Bootstrap generates the configure script, and prepares building on your system.
185 Configure generates the Makefiles used to build OpenOCD.
189 Make builds OpenOCD, and places the final executable in ./src/.
191 The configure script takes several options, specifying which JTAG interfaces
196 @option{--enable-parport}
198 @option{--enable-parport_ppdev}
200 @option{--enable-parport_giveio}
202 @option{--enable-amtjtagaccel}
204 @option{--enable-ft2232_ftd2xx}
205 @footnote{Using the latest D2XX drivers from FTDI and following their installation
206 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
209 @option{--enable-ft2232_libftdi}
211 @option{--with-ftd2xx=/path/to/d2xx/}
213 @option{--enable-gw16012}
215 @option{--enable-usbprog}
217 @option{--enable-presto_libftdi}
219 @option{--enable-presto_ftd2xx}
221 @option{--enable-jlink}
224 If you want to access the parallel port using the PPDEV interface you have to specify
225 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
226 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
227 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
229 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
230 absolute path containing no spaces.
232 Linux users should copy the various parts of the D2XX package to the appropriate
233 locations, i.e. /usr/include, /usr/lib.
235 Miscellaneous configure options
239 @option{--enable-gccwarnings} - enable extra gcc warnings during build
242 @node JTAG Hardware Dongles
243 @chapter JTAG Hardware Dongles
252 Defined: @b{dongle}: A small device that plugins into a computer and serves as
253 an adapter .... [snip]
255 In the OpenOCD case, this generally refers to @b{a small adapater} one
256 attaches to your computer via USB or the Parallel Printer Port. The
257 execption being the Zylin ZY1000 which is a small box you attach via
261 @section Choosing a Dongle
263 There are three things you should keep in mind when choosing a dongle.
266 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
267 @item @b{Connection} Printer Ports - Does your computer have one?
268 @item @b{Connection} Is that long printer bit-bang cable practical?
269 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
272 @section Stand alone Systems
274 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
275 dongle, but a standalone box.
277 @section USB FT2232 Based
279 There are many USB jtag dongles on the market, many of them are based
280 on a chip from ``Future Technology Devices International'' (FTDI)
281 known as the FTDI FT2232.
283 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
285 As of 28/Nov/2008, the following are supported:
289 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
291 @* See: @url{http://www.amontec.com/jtagkey.shtml}
293 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
295 @* See: @url{http://www.signalyzer.com}
296 @item @b{evb_lm3s811}
297 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
303 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
305 @* Link: @url{http://www.hitex.com/index.php?id=383}
307 @* Link @url{http://www.hitex.com/stm32-stick}
308 @item @b{axm0432_jtag}
309 @* Axiom AXM-0432 Link @url{http://www.axman.com}
312 @section USB JLINK based
313 There are several OEM versions of the Segger @b{JLINK} adapter. It is
314 an example of a micro controller based JTAG adapter, it uses an
315 AT91SAM764 internally.
318 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
319 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
320 @item @b{SEGGER JLINK}
321 @* Link: @url{http://www.segger.com/jlink.html}
323 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
329 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
331 @item @b{USB - Presto}
332 @* Link: @url{http://tools.asix.net/prg_presto.htm}
335 @section IBM PC Parallel Printer Port Based
337 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
338 and the MacGraigor Wiggler. There are many clones and variations of
343 @item @b{Wiggler} - There are many clones of this.
344 @* Link: @url{http://www.macraigor.com/wiggler.htm}
346 @item @b{DLC5} - From XILINX - There are many clones of this
347 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
348 produced, PDF schematics are easily found and it is easy to make.
350 @item @b{Amontec - JTAG Accelerator}
351 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
354 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
357 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
359 @item @b{Wiggler_ntrst_inverted}
360 @* Yet another variation - See the source code, src/jtag/parport.c
362 @item @b{old_amt_wiggler}
363 @* Unknown - probably not on the market today
366 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
369 @* Link: @url{http://www.amontec.com/chameleon.shtml}
375 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
378 @* From ST Microsystems, link:
379 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
380 Title: FlashLINK JTAG programing cable for PSD and uPSD
388 @* An EP93xx based linux machine using the GPIO pins directly.
391 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
397 @cindex running OpenOCD
399 @cindex --debug_level
403 The @option{--help} option shows:
407 --help | -h display this help
408 --version | -v display OpenOCD version
409 --file | -f use configuration file <name>
410 --search | -s dir to search for config files and scripts
411 --debug | -d set debug level <0-3>
412 --log_output | -l redirect log output to file <name>
413 --command | -c run <command>
414 --pipe | -p use pipes when talking to gdb
417 By default OpenOCD reads the file configuration file ``openocd.cfg''
418 in the current directory. To specify a different (or multiple)
419 configuration file, you can use the ``-f'' option. For example:
422 openocd -f config1.cfg -f config2.cfg -f config3.cfg
425 Once started, OpenOCD runs as a daemon, waiting for connections from
426 clients (Telnet, GDB, Other).
428 If you are having problems, you can enable internal debug messages via
431 Also it is possible to interleave commands w/config scripts using the
432 @option{-c} command line switch.
434 To enable debug output (when reporting problems or working on OpenOCD
435 itself), use the @option{-d} command line switch. This sets the
436 @option{debug_level} to "3", outputting the most information,
437 including debug messages. The default setting is "2", outputting only
438 informational messages, warnings and errors. You can also change this
439 setting from within a telnet or gdb session using @option{debug_level
440 <n>} @xref{debug_level}.
442 You can redirect all output from the daemon to a file using the
443 @option{-l <logfile>} switch.
445 Search paths for config/script files can be added to OpenOCD by using
446 the @option{-s <search>} switch. The current directory and the OpenOCD
447 target library is in the search path by default.
449 For details on the @option{-p} option. @xref{Connecting to GDB}.
450 Option @option{-p} is not currently supported under native win32.
452 Note! OpenOCD will launch the GDB & telnet server even if it can not
453 establish a connection with the target. In general, it is possible for
454 the JTAG controller to be unresponsive until the target is set up
455 correctly via e.g. GDB monitor commands in a GDB init script.
457 @node Simple Configuration Files
458 @chapter Simple Configuration Files
459 @cindex configuration
462 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
465 @item A small openocd.cfg file which ``sources'' other configuration files
466 @item A monolithic openocd.cfg file
467 @item Many -f filename options on the command line
468 @item Your Mixed Solution
471 @section Small configuration file method
473 This is the prefered method, it is simple and is works well for many
474 people. The developers of OpenOCD would encourage you to use this
475 method. If you create a new configuration please email new
476 configurations to the development list.
478 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
481 source [find interface/signalyzer.cfg]
483 # Change the default telnet port...
487 # GDB can also flash my flash!
488 gdb_memory_map enable
489 gdb_flash_program enable
491 source [find target/sam7x256.cfg]
494 There are many example configuration scripts you can work with. You
495 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
499 @item @b{board} - eval board level configurations
500 @item @b{interface} - specific dongle configurations
501 @item @b{target} - the target chips
502 @item @b{tcl} - helper scripts
503 @item @b{xscale} - things specific to the xscale.
506 Look first in the ``boards'' area, then the ``targets'' area. Often a board
507 configuration is a good example to work from.
509 @section Many -f filename options
510 Some believe this is a wonderful solution, others find it painful.
512 You can use a series of ``-f filename'' options on the command line,
513 OpenOCD will read each filename in sequence, for example:
516 openocd -f file1.cfg -f file2.cfg -f file2.cfg
519 You can also intermix various commands with the ``-c'' command line
522 @section Monolithic file
523 The ``Monolithic File'' dispenses with all ``source'' statements and
524 puts everything in one self contained (monolithic) file. This is not
527 Please try to ``source'' various files or use the multiple -f
530 @section Advice for you
531 Often, one uses a ``mixed approach''. Where possible, please try to
532 ``source'' common things, and if needed cut/paste parts of the
533 standard distribution configuration files as needed.
535 @b{REMEMBER:} The ``important parts'' of your configuration file are:
538 @item @b{Interface} - Defines the dongle
539 @item @b{Taps} - Defines the JTAG Taps
540 @item @b{GDB Targets} - What GDB talks to
541 @item @b{Flash Programing} - Very Helpful
544 Some key things you should look at and understand are:
547 @item The RESET configuration of your debug environment as a hole
548 @item Is there a ``work area'' that that OpenOCD can use?
549 @* For ARM - work areas mean up to 10x faster downloads.
550 @item For MMU/MPU based ARM chips (ie: ARM9 and later) will that work area still be available?
551 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
556 @node Config File Guidelines
557 @chapter Config File Guidelines
559 This section/chapter is aimed at developers and integrators of
560 OpenOCD. These are guidelines for creating new boards and new target
561 configurations as of 28/Nov/2008.
563 However, you the user of OpenOCD should be some what familiar with
564 this section as it should help explain some of the internals of what
565 you might be looking at.
567 The user should find under @t{$(INSTALLDIR)/lib/openocd} the
568 following directories:
572 @*Think JTAG Dongle. Files that configure the jtag dongle go here.
574 @* Thing Circuit Board, PWA, PCB, they go by many names. Board files
575 contain initialization items that are specific to a board - for
576 example: The SDRAM initialization sequence for the board, or the type
577 of external flash and what address it is found at. Any initialization
578 sequence to enable that external flash or sdram should be found in the
579 board file. Boards may also contain multiple targets, ie: Two cpus, or
580 a CPU and an FPGA or CPLD.
582 @* Think CHIP. The ``target'' directory represents a jtag tap (or
583 chip) OpenOCD should control, not a board. Two common types of targets
584 are ARM chips and FPGA or CPLD chips.
587 @b{If needed...} The user in their ``openocd.cfg'' file or the board
588 file might override a specific feature in any of the above files by
589 setting a variable or two before sourcing the target file. Or adding
590 various commands specific to their situation.
592 @section Interface Config Files
594 The user should be able to source one of these files via a command like this:
597 source [find interface/FOOBAR.cfg]
599 openocd -f interface/FOOBAR.cfg
602 A preconfigured interface file should exist for every interface in use
603 today, that said, perhaps some interfaces have only been used by the
604 sole developer who created it.
606 @b{FIXME/NOTE:} We need to add support for a variable like TCL variable
607 tcl_platform(platform), it should be called jim_platform (because it
608 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
609 ``cygwin'' or ``mingw''
611 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
613 @section Board Config Files
615 @b{Note: BOARD directory NEW as of 28/nov/2008}
617 The user should be able to source one of these files via a command like this:
620 source [find board/FOOBAR.cfg]
622 openocd -f board/FOOBAR.cfg
626 The board file should contain one or more @t{source [find
627 target/FOO.cfg]} statements along with any board specific things.
629 In summery the board files should contain (if present)
632 @item External flash configuration (ie: the flash on CS0)
633 @item SDRAM configuration (size, speed, etc)
634 @item Board specific IO configuration (ie: GPIO pins might disable a 2nd flash)
635 @item Multiple TARGET source statements
636 @item All things that are not ``inside a chip''
637 @item Things inside a chip go in a 'target' file
640 @section Target Config Files
642 The user should be able to source one of these files via a command like this:
645 source [find target/FOOBAR.cfg]
647 openocd -f target/FOOBAR.cfg
650 In summery the target files should contain
655 @item Reset Configuration
657 @item CPU/Chip/CPU-Core Specific features
661 @subsection Important variable names
663 By default, the end user should never need to set these
664 variables. However, if the user needs to override a setting they only
665 need to set the variable in a simple way.
669 @* This gives a name to the overall chip, and is used as part of the
670 tap identifier dotted name.
672 @* By default little - unless the chip or board is not normally used that way.
674 @* When OpenOCD examines the JTAG chain, it will attempt to identify
675 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
676 to verify the tap id number verses configuration file and may issue an
677 error or warning like this. The hope is this will help pin point
678 problem OpenOCD configurations.
681 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
682 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
683 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
684 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
687 @item @b{_TARGETNAME}
688 @* By convention, this variable is created by the target configuration
689 script. The board configuration file may make use of this variable to
690 configure things like a ``reset init'' script, or other things
691 specific to that board and that target.
693 If the chip has 2 targets, use the names @b{_TARGETNAME0},
694 @b{_TARGETNAME1}, ... etc.
696 @b{Remember:} The ``board file'' may include multiple targets.
698 At no time should the name ``target0'' (the default target name if
699 none was specified) be used. The name ``target0'' is a hard coded name
700 - the next target on the board will be some other number.
702 The user (or board file) should reasonably be able to:
705 source [find target/FOO.cfg]
706 $_TARGETNAME configure ... FOO specific parameters
708 source [find target/BAR.cfg]
709 $_TARGETNAME configure ... BAR specific parameters
714 @subsection TCL Variables Guide Line
715 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
717 Thus the rule we follow in OpenOCD is this: Variables that begin with
718 a leading underscore are temporal in nature, and can be modified and
719 used at will within a ?TARGET? configuration file
721 @b{EXAMPLE:} The user should be able to do this:
725 # PXA270 #1 network side, big endian
726 # PXA270 #2 video side, little endian
730 source [find target/pxa270.cfg]
731 # variable: _TARGETNAME = network.cpu
732 # other commands can refer to the "network.cpu" tap.
733 $_TARGETNAME configure .... params for this cpu..
737 source [find target/pxa270.cfg]
738 # variable: _TARGETNAME = video.cpu
739 # other commands can refer to the "video.cpu" tap.
740 $_TARGETNAME configure .... params for this cpu..
744 source [find target/spartan3.cfg]
746 # Since $_TARGETNAME is temporal..
747 # these names still work!
748 network.cpu configure ... params
749 video.cpu configure ... params
753 @subsection Default Value Boiler Plate Code
755 All target configuration files should start with this (or a modified form)
759 if @{ [info exists CHIPNAME] @} @{
760 set _CHIPNAME $CHIPNAME
762 set _CHIPNAME sam7x256
765 if @{ [info exists ENDIAN] @} @{
771 if @{ [info exists CPUTAPID ] @} @{
772 set _CPUTAPID $CPUTAPID
774 set _CPUTAPID 0x3f0f0f0f
779 @subsection Creating Taps
780 After the ``defaults'' are choosen, [see above], the taps are created.
782 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
786 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
787 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
792 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
795 @item @b{Unform tap names} - See: Tap Naming Convention
796 @item @b{_TARGETNAME} is created at the end where used.
800 if @{ [info exists FLASHTAPID ] @} @{
801 set _FLASHTAPID $FLASHTAPID
803 set _FLASHTAPID 0x25966041
805 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
807 if @{ [info exists CPUTAPID ] @} @{
808 set _CPUTAPID $CPUTAPID
810 set _CPUTAPID 0x25966041
812 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
815 if @{ [info exists BSTAPID ] @} @{
816 set _BSTAPID $BSTAPID
818 set _BSTAPID 0x1457f041
820 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
822 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
825 @b{Tap Naming Convention}
827 See the command ``jtag newtap'' for detail, but in breif the names you should use are:
835 @item @b{unknownN} - it happens :-(
838 @subsection Reset Configuration
840 Some chips have specific ways the TRST and SRST signals are
841 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
842 @b{BOARD SPECIFIC} they go in the board file.
844 @subsection Work Areas
846 Work areas are small RAM areas used by OpenOCD to speed up downloads,
847 and to download small snippits of code to program flash chips.
849 If the chip includes an form of ``on-chip-ram'' - and many do - define
850 a reasonable work area and use the ``backup'' option.
852 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
853 inaccessable if/when the application code enables or disables the MMU.
855 @subsection ARM Core Specific Hacks
857 If the chip has a DCC, enable it. If the chip is an arm9 with some
858 special high speed download - enable it.
860 If the chip has an ARM ``vector catch'' feature - by defeault enable
861 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
862 user is really writing a handler for those situations - they can
863 easily disable it. Experiance has shown the ``vector catch'' is
864 helpful - for common programing errors.
866 If present, the MMU, the MPU and the CACHE should be disabled.
868 @subsection Internal Flash Configuration
870 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
872 @b{Never ever} in the ``target configuration file'' define any type of
873 flash that is external to the chip. (For example the BOOT flash on
874 Chip Select 0). The BOOT flash information goes in a board file - not
875 the TARGET (chip) file.
879 @item at91sam7x256 - has 256K flash YES enable it.
880 @item str912 - has flash internal YES enable it.
881 @item imx27 - uses boot flash on CS0 - it goes in the board file.
882 @item pxa270 - again - CS0 flash - it goes in the board file.
886 @chapter About JIM-Tcl
890 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
891 learn more about JIM here: @url{http://jim.berlios.de}
894 @item @b{JIM vrs TCL}
895 @* JIM-TCL is a stripped down version of the well known Tcl language,
896 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
897 fewer features. JIM-Tcl is a single .C file and a single .H file and
898 impliments the basic TCL command set along. In contrast: Tcl 8.6 is a
899 4.2MEG zip file containing 1540 files.
901 @item @b{Missing Features}
902 @* Our practice has been: Add/clone the Real TCL feature if/when
903 needed. We welcome JIM Tcl improvements, not bloat.
906 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
907 command interpretor today (28/nov/2008) is a mixture of (newer)
908 JIM-Tcl commands, and (older) the orginal command interpretor.
911 @* At the OpenOCD telnet command line (or via the GDB mon command) one
912 can type a Tcl for() loop, set variables, etc.
914 @item @b{Historical Note}
915 @* JIM-Tcl was introduced to OpenOCD in Spring 2008.
917 @item @b{Need a Crash Course In TCL?}
918 @* See: @xref{TCL Crash Course}.
922 @node Daemon Configuration
923 @chapter Daemon Configuration
924 The commands here are commonly found inthe openocd.cfg file and are
925 used to specify what TCP/IP ports are used, and how GDB should be
929 This command terminates the configuration stage and
930 enters the normal command mode. This can be useful to add commands to
931 the startup scripts and commands such as resetting the target,
932 programming flash, etc. To reset the CPU upon startup, add "init" and
933 "reset" at the end of the config script or at the end of the OpenOCD
934 command line using the @option{-c} command line switch.
936 If this command does not appear in any startup/configuration file
937 OpenOCD executes the command for you after processing all
938 configuration files and/or command line options.
940 @b{NOTE:} This command normally occurs at or near the end of your
941 openocd.cfg file to force OpenOCD to ``initialize'' and make the
942 targets ready. For example: If your openocd.cfg file needs to
943 read/write memory on your target - the init command must occur before
944 the memory read/write commands.
946 @section TCP/IP Ports
948 @item @b{telnet_port} <@var{number}>
950 @*Intended for a human. Port on which to listen for incoming telnet connections.
952 @item @b{tcl_port} <@var{number}>
954 @*Intended as a machine interface. Port on which to listen for
955 incoming TCL syntax. This port is intended as a simplified RPC
956 connection that can be used by clients to issue commands and get the
957 output from the TCL engine.
959 @item @b{gdb_port} <@var{number}>
961 @*First port on which to listen for incoming GDB connections. The GDB port for the
962 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
967 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
968 @cindex gdb_breakpoint_override
969 @anchor{gdb_breakpoint_override}
970 @*Force breakpoint type for gdb 'break' commands.
971 The raison d'etre for this option is to support GDB GUI's without
972 a hard/soft breakpoint concept where the default OpenOCD and
973 GDB behaviour is not sufficient. Note that GDB will use hardware
974 breakpoints if the memory map has been set up for flash regions.
976 This option replaces older arm7_9 target commands that addressed
979 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
981 @*Configures what OpenOCD will do when gdb detaches from the daeman.
982 Default behaviour is <@var{resume}>
984 @item @b{gdb_memory_map} <@var{enable|disable}>
985 @cindex gdb_memory_map
986 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
987 requested. gdb will then know when to set hardware breakpoints, and program flash
988 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
989 for flash programming to work.
990 Default behaviour is <@var{enable}>
991 @xref{gdb_flash_program}.
993 @item @b{gdb_flash_program} <@var{enable|disable}>
994 @cindex gdb_flash_program
995 @anchor{gdb_flash_program}
996 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
997 vFlash packet is received.
998 Default behaviour is <@var{enable}>
999 @comment END GDB Items
1002 @node Interface - Dongle Configuration
1003 @chapter Interface - Dongle Configuration
1004 Interface commands are normally found in an interface configuration
1005 file which is sourced by your openocd.cfg file. These commands tell
1006 OpenOCD what type of JTAG dongle you have and how to talk to it.
1007 @section Simple Complete Interface Examples
1008 @b{A Turtelizer FT2232 Based JTAG Dongle}
1012 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1013 ft2232_layout turtelizer2
1014 ft2232_vid_pid 0x0403 0xbdc8
1025 parport_cable wiggler
1028 @section Interface Conmmand
1030 The interface command tells OpenOCD what type of jtag dongle you are
1031 using. Depending upon the type of dongle, you may need to have one or
1032 more additional commands.
1036 @item @b{interface} <@var{name}>
1038 @*Use the interface driver <@var{name}> to connect to the
1039 target. Currently supported interfaces are
1044 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1046 @item @b{amt_jtagaccel}
1047 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1051 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1052 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1053 platform. The libftdi uses libusb, and should be portable to all systems that provide
1057 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1060 @* ASIX PRESTO USB JTAG programmer.
1063 @* usbprog is a freely programmable USB adapter.
1066 @* Gateworks GW16012 JTAG programmer.
1069 @* Segger jlink usb adapter
1070 @comment - End parameters
1072 @comment - End Interface
1074 @subsection parport options
1077 @item @b{parport_port} <@var{number}>
1078 @cindex parport_port
1079 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1080 the @file{/dev/parport} device
1082 When using PPDEV to access the parallel port, use the number of the parallel port:
1083 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1084 you may encounter a problem.
1085 @item @b{parport_cable} <@var{name}>
1086 @cindex parport_cable
1087 @*The layout of the parallel port cable used to connect to the target.
1088 Currently supported cables are
1092 The original Wiggler layout, also supported by several clones, such
1093 as the Olimex ARM-JTAG
1096 Same as original wiggler except an led is fitted on D5.
1097 @item @b{wiggler_ntrst_inverted}
1098 @cindex wiggler_ntrst_inverted
1099 Same as original wiggler except TRST is inverted.
1100 @item @b{old_amt_wiggler}
1101 @cindex old_amt_wiggler
1102 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1103 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1106 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1107 program the Chameleon itself, not a connected target.
1110 The Xilinx Parallel cable III.
1113 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1114 This is also the layout used by the HollyGates design
1115 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1118 The ST Parallel cable.
1121 Same as original wiggler except SRST and TRST connections reversed and
1122 TRST is also inverted.
1125 Altium Universal JTAG cable.
1127 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1128 @cindex parport_write_on_exit
1129 @*This will configure the parallel driver to write a known value to the parallel
1130 interface on exiting OpenOCD
1133 @subsection amt_jtagaccel options
1135 @item @b{parport_port} <@var{number}>
1136 @cindex parport_port
1137 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1138 @file{/dev/parport} device
1140 @subsection ft2232 options
1143 @item @b{ft2232_device_desc} <@var{description}>
1144 @cindex ft2232_device_desc
1145 @*The USB device description of the FTDI FT2232 device. If not
1146 specified, the FTDI default value is used. This setting is only valid
1147 if compiled with FTD2XX support.
1149 @b{TODO:} Confirm the following: On windows the name needs to end with
1150 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1151 this be added and when must it not be added? Why can't the code in the
1152 interface or in OpenOCD automatically add this if needed? -- Duane.
1154 @item @b{ft2232_serial} <@var{serial-number}>
1155 @cindex ft2232_serial
1156 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1158 @item @b{ft2232_layout} <@var{name}>
1159 @cindex ft2232_layout
1160 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1161 signals. Valid layouts are
1164 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1166 Amontec JTAGkey and JTAGkey-tiny
1167 @item @b{signalyzer}
1169 @item @b{olimex-jtag}
1172 American Microsystems M5960
1173 @item @b{evb_lm3s811}
1174 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1175 SRST signals on external connector
1178 @item @b{stm32stick}
1179 Hitex STM32 Performance Stick
1180 @item @b{flyswatter}
1181 Tin Can Tools Flyswatter
1182 @item @b{turtelizer2}
1183 egnite Software turtelizer2
1186 @item @b{axm0432_jtag}
1190 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1191 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1192 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
1194 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1196 @item @b{ft2232_latency} <@var{ms}>
1197 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
1198 ft2232_read() fails to return the expected number of bytes. This can be caused by
1199 USB communication delays and has proved hard to reproduce and debug. Setting the
1200 FT2232 latency timer to a larger value increases delays for short USB packages but it
1201 also reduces the risk of timeouts before receiving the expected number of bytes.
1202 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1205 @subsection ep93xx options
1206 @cindex ep93xx options
1207 Currently, there are no options available for the ep93xx interface.
1211 @item @b{jtag_khz} <@var{reset speed kHz}>
1214 It is debatable if this command belongs here - or in a board
1215 configuration file. In fact, in some situations the jtag speed is
1216 changed during the target initialization process (ie: (1) slow at
1217 reset, (2) program the cpu clocks, (3) run fast)
1219 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1221 Not all interfaces support ``rtck''. If the interface device can not
1222 support the rate asked for, or can not translate from kHz to
1223 jtag_speed, then an error is returned.
1225 Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
1226 especially true for synthesized cores (-S). Also see RTCK.
1228 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1229 please use the command: 'jtag_rclk FREQ'. This TCL proc (in
1230 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1231 the specified frequency.
1234 # Fall back to 3mhz if RCLK is not supported
1238 @item @b{DEPRICATED} @b{jtag_speed} - please use jtag_khz above.
1240 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1241 speed. The actual effect of this option depends on the JTAG interface used.
1243 The speed used during reset can be adjusted using setting jtag_speed during
1244 pre_reset and post_reset events.
1247 @item wiggler: maximum speed / @var{number}
1248 @item ft2232: 6MHz / (@var{number}+1)
1249 @item amt jtagaccel: 8 / 2**@var{number}
1250 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1251 @comment end speed list.
1254 @comment END command list
1257 @node Reset Configuration
1258 @chapter Reset Configuration
1259 @cindex reset configuration
1261 Every system configuration may require a different reset
1262 configuration. This can also be quite confusing. Please see the
1263 various board files for example.
1265 @section jtag_nsrst_delay <@var{ms}>
1266 @cindex jtag_nsrst_delay
1267 @*How long (in milliseconds) OpenOCD should wait after deasserting
1268 nSRST before starting new JTAG operations.
1270 @section jtag_ntrst_delay <@var{ms}>
1271 @cindex jtag_ntrst_delay
1272 @*Same @b{jtag_nsrst_delay}, but for nTRST
1274 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1275 big resistor/capacitor, reset supervisor, or on-chip features). This
1276 keeps the signal asserted for some time after the external reset got
1279 @section reset_config
1281 @b{Note:} To maintainer types and integrators. Where exactly the
1282 ``reset configuration'' goes is a good question. It touches several
1283 things at once. In the end, if you have a board file - the board file
1284 should define it and assume 100% that the DONGLE supports
1285 anything. However, that does not mean the target should not also make
1286 not of something the silicon vendor has done inside the
1287 chip. @i{Grr.... nothing is every pretty.}
1291 @item Every JTAG Dongle is slightly different, some dongles impliment reset differently.
1292 @item Every board is also slightly different; some boards tie TRST and SRST together.
1293 @item Every chip is slightly different; some chips internally tie the two signals together.
1294 @item Some may not impliment all of the signals the same way.
1295 @item Some signals might be push-pull, others open-drain/collector.
1297 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1298 reset the TAP via TRST and send commands through the JTAG tap to halt
1299 the CPU at the reset vector before the 1st instruction is executed,
1300 and finally release the SRST signal.
1301 @*Depending upon your board vendor, your chip vendor, etc, these
1302 signals may have slightly different names.
1304 OpenOCD defines these signals in these terms:
1306 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1307 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1313 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1314 @cindex reset_config
1315 @* The @t{reset_config} command tells OpenOCD the reset configuration
1316 of your combination of Dongle, Board, and Chips.
1317 If the JTAG interface provides SRST, but the target doesn't connect
1318 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1319 be @option{none}, @option{trst_only}, @option{srst_only} or
1320 @option{trst_and_srst}.
1322 [@var{combination}] is an optional value specifying broken reset
1323 signal implementations. @option{srst_pulls_trst} states that the
1324 testlogic is reset together with the reset of the system (e.g. Philips
1325 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1326 the system is reset together with the test logic (only hypothetical, I
1327 haven't seen hardware with such a bug, and can be worked around).
1328 @option{combined} imples both @option{srst_pulls_trst} and
1329 @option{trst_pulls_srst}. The default behaviour if no option given is
1332 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1333 driver type of the reset lines to be specified. Possible values are
1334 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1335 test reset signal, and @option{srst_open_drain} (default) and
1336 @option{srst_push_pull} for the system reset. These values only affect
1337 JTAG interfaces with support for different drivers, like the Amontec
1338 JTAGkey and JTAGAccelerator.
1340 @comment - end command
1346 @chapter Tap Creation
1347 @cindex tap creation
1348 @cindex tap configuration
1350 In order for OpenOCD to control a target, a JTAG tap must be
1353 Commands to create taps are normally found in a configuration file and
1354 are not normally typed by a human.
1356 When a tap is created a @b{dotted.name} is created for the tap. Other
1357 commands use that dotted.name to manipulate or refer to the tap.
1361 @item @b{Debug Target} A tap can be used by a GDB debug target
1362 @item @b{Flash Programing} Some chips program the flash via JTAG
1363 @item @b{Boundry Scan} Some chips support boundry scan.
1367 @section jtag newtap
1368 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1373 @cindex tap geometry
1375 @comment START options
1378 @* is a symbolic name of the chip.
1380 @* is a symbol name of a tap present on the chip.
1381 @item @b{Required configparams}
1382 @* Every tap has 3 required configparams, and several ``optional
1383 parameters'', the required parameters are:
1384 @comment START REQUIRED
1386 @item @b{-irlen NUMBER} - the length in bits of the instruction register
1387 @item @b{-ircapture NUMBER} - the ID code capture command.
1388 @item @b{-irmask NUMBER} - the corrisponding mask for the ir register.
1389 @comment END REQUIRED
1391 An example of a FOOBAR Tap
1393 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1395 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1396 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1397 [6,4,2,0] are checked.
1399 FIXME: The IDCODE - this was not used in the old code, it should be?
1401 @item @b{Optional configparams}
1402 @comment START Optional
1404 @item @b{-expected-id NUMBER}
1405 @* By default it is zero. If non-zero represents the
1406 expected tap ID used when the Jtag Chain is examined. See below.
1409 @* By default not specified the tap is enabled. Some chips have a
1410 jtag route controller (JRC) that is used to enable and/or disable
1411 specific jtag taps. You can later enable or disable any JTAG tap via
1412 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1414 @comment END Optional
1417 @comment END OPTIONS
1420 @comment START NOTES
1422 @item @b{Technically}
1423 @* newtap is a sub command of the ``jtag'' command
1424 @item @b{Big Picture Background}
1425 @*GDB Talks to OpenOCD using the GDB protocol via
1426 tcpip. OpenOCD then uses the JTAG interface (the dongle) to
1427 control the JTAG chain on your board. Your board has one or more chips
1428 in a @i{daisy chain configuration}. Each chip may have one or more
1429 jtag taps. GDB ends up talking via OpenOCD to one of the taps.
1430 @item @b{NAME Rules}
1431 @*Names follow ``C'' symbol name rules (start with alpha ...)
1432 @item @b{TAPNAME - Conventions}
1434 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1435 @item @b{cpu} - the main cpu of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1436 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1437 @item @b{bs} - for boundary scan if this is a seperate tap.
1438 @item @b{jrc} - for jtag route controller (example: OMAP3530 found on Beagleboards)
1439 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1440 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1441 @item @b{When in doubt} - use the chip makers name in their data sheet.
1443 @item @b{DOTTED.NAME}
1444 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1445 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1446 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1447 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1448 numerous other places to refer to various taps.
1450 @* The order this command appears via the config files is
1452 @item @b{Multi Tap Example}
1453 @* This example is based on the ST Microsystems STR912. See the ST
1454 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1455 28/102, Figure 3: Jtag chaining inside the STR91xFA}.
1457 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1458 @*@b{checked: 28/nov/2008}
1460 The diagram shows the TDO pin connects to the flash tap, flash TDI
1461 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1462 tap which then connects to the TDI pin.
1466 # create tap: 'str912.flash'
1467 jtag newtap str912 flash ... params ...
1468 # create tap: 'str912.cpu'
1469 jtag newtap str912 cpu ... params ...
1470 # create tap: 'str912.bs'
1471 jtag newtap str912 bs ... params ...
1474 @item @b{Note: Deprecated} - Index Numbers
1475 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1476 feature is still present, however its use is highly discouraged and
1477 should not be counted upon.
1478 @item @b{Multiple chips}
1479 @* If your board has multiple chips, you should be
1480 able to @b{source} two configuration files, in the proper order, and
1481 have the taps created in the proper order.
1484 @comment at command level
1485 @comment DOCUMENT old command
1486 @section jtag_device - REMOVED
1488 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1492 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1493 by the ``jtag newtap'' command. The documentation remains here so that
1494 one can easily convert the old syntax to the new syntax. About the old
1495 syntax: The old syntax is positional, ie: The 4th parameter is the
1496 ``irmask'' The new syntax requires named prefixes, and supports
1497 additional options, for example ``-irmask 4'' Please refer to the
1498 @b{jtag newtap} command for deails.
1500 OLD: jtag_device 8 0x01 0x0e3 0xfe
1501 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0xe3 -irmask 0xfe
1504 @section Enable/Disable Taps
1505 @b{Note:} These commands are intended to be used as a machine/script
1506 interface. Humans might find the ``scan_chain'' command more helpful
1507 when querying the state of the JTAG taps.
1509 @b{By default, all taps are enabled}
1512 @item @b{jtag tapenable} @var{DOTTED.NAME}
1513 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1514 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1519 @cindex route controller
1521 These commands are used when your target has a JTAG Route controller
1522 that effectively adds or removes a tap from the jtag chain in a
1525 The ``standard way'' to remove a tap would be to place the tap in
1526 bypass mode. But with the advent of modern chips, this is not always a
1527 good solution. Some taps operate slowly, others operate fast, and
1528 there are other JTAG clock syncronization problems one must face. To
1529 solve that problem, the JTAG Route controller was introduced. Rather
1530 then ``bypass'' the tap, the tap is completely removed from the
1531 circuit and skipped.
1534 From OpenOCD's view point, a JTAG TAP is in one of 3 states:
1537 @item @b{Enabled - Not In ByPass} and has a variable bit length
1538 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1539 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1542 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1543 @b{Historical note:} this feature was added 28/nov/2008
1545 @b{jtag tapisenabled DOTTED.NAME}
1547 This command return 1 if the named tap is currently enabled, 0 if not.
1548 This command exists so that scripts that manipulate a JRC (like the
1549 Omap3530 has) can determine if OpenOCD thinks a tap is presently
1550 enabled, or disabled.
1553 @node Target Configuration
1554 @chapter Target Configuration
1556 This chapter discusses how to create a GDB Debug Target. Before
1557 creating a ``target'' a JTAG Tap DOTTED.NAME must exist first.
1559 @section targets [NAME]
1560 @b{Note:} This command name is PLURAL - not singular.
1562 With NO parameter, this pural @b{targets} command lists all known
1563 targets in a human friendly form.
1565 With a parameter, this pural @b{targets} command sets the current
1566 target to the given name. (ie: If there are multiple debug targets)
1571 CmdName Type Endian ChainPos State
1572 -- ---------- ---------- ---------- -------- ----------
1573 0: target0 arm7tdmi little 0 halted
1576 @section target COMMANDS
1577 @b{Note:} This command name is SINGULAR - not plural. It is used to
1578 manipulate specific targets, to create targets and other things.
1580 Once a target is created, a TARGETNAME (object) command is created;
1581 see below for details.
1583 The TARGET command accepts these sub-commands:
1585 @item @b{create} .. parameters ..
1586 @* creates a new target, See below for details.
1588 @* Lists all supported target types (perhaps some are not yet in this document).
1590 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1592 foreach t [target names] {
1593 puts [format "Target: %s\n" $t]
1597 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1598 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1599 @item @b{number} @b{NUMBER}
1600 @* Internally OpenOCD maintains a list of targets - in numerical index
1601 (0..N-1) this command returns the name of the target at index N.
1604 set thename [target number $x]
1605 puts [format "Target %d is: %s\n" $x $thename]
1608 @* Returns the number of targets known to OpenOCD (see number above)
1611 set c [target count]
1612 for { set x 0 } { $x < $c } { incr x } {
1613 # Assuming you have created this function
1614 print_target_details $x
1620 @section TARGETNAME (object) commands
1621 @b{Use:} Once a target is created, an ``object name'' that represents the
1622 target is created. By convention, the target name is identical to the
1623 tap name. In a multiple target system, one can preceed many common
1624 commands with a specific target name and effect only that target.
1626 str912.cpu mww 0x1234 0x42
1627 omap3530.cpu mww 0x5555 123
1630 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1631 good example is a on screen button, once a button is created a button
1632 has a name (a path in TK terms) and that name is useable as a 1st
1633 class command. For example in TK, one can create a button and later
1634 configure it like this:
1638 button .foobar -background red -command @{ foo @}
1640 .foobar configure -foreground blue
1642 set x [.foobar cget -background]
1644 puts [format "The button is %s" $x]
1647 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1648 button. Commands avaialble as a ``target object'' are:
1650 @comment START targetobj commands.
1652 @item @b{configure} - configure the target; see Target Config/Cget Options below
1653 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1654 @item @b{curstate} - current target state (running, halt, etc)
1656 @* Intended for a human to see/read the currently configure target events.
1657 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1658 @comment start memory
1668 @item @b{Memory To Array, Array To Memory}
1669 @* These are aimed at a machine interface to memory
1671 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1672 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1674 @* @b{ARRAYNAME} is the name of an array variable
1675 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1676 @* @b{ADDRESS} is the target memory address
1677 @* @b{COUNT} is the number of elements to process
1679 @item @b{Used during ``reset''}
1680 @* These commands are used internally by the OpenOCD scripts to deal
1681 with odd reset situations and are not documented here.
1683 @item @b{arp_examine}
1687 @item @b{arp_waitstate}
1689 @item @b{invoke-event} @b{EVENT-NAME}
1690 @* Invokes the specific event manually for the target
1693 @section Target Events
1694 At various times, certian things happen, or you want to happen.
1698 @item What should happen when GDB connects? Should your target reset?
1699 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1700 @item During reset, do you need to write to certian memory locations to reconfigure the SDRAM?
1703 All of the above items are handled by target events.
1705 To specify an event action, either during target creation, or later
1706 via ``$_TARGETNAME configure'' see this example.
1708 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
1709 target event name, and BODY is a tcl procedure or string of commands
1712 The programers model is the: ``-command'' option used in Tcl/Tk
1713 buttons and events. Below are two identical examples, the first
1714 creates and invokes small procedure. The second inlines the procedure.
1717 proc my_attach_proc @{ @} @{
1721 mychip.cpu configure -event gdb-attach my_attach_proc
1722 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
1728 @item @b{debug-halted}
1729 @* The target has halted for debug reasons (ie: breakpoint)
1730 @item @b{debug-resumed}
1731 @* The target has resumed (ie: gdb said run)
1732 @item @b{early-halted}
1733 @* Occurs early in the halt process
1734 @item @b{examine-end}
1735 @* Currently not used (goal: when JTAG examine completes)
1736 @item @b{examine-start}
1737 @* Currently not used (goal: when JTAG examine starts)
1738 @item @b{gdb-attach}
1739 @* When GDB connects
1740 @item @b{gdb-detach}
1741 @* When GDB disconnects
1743 @* When the taret has halted and GDB is not doing anything (see early halt)
1744 @item @b{gdb-flash-erase-start}
1745 @* Before the GDB flash process tries to erase the flash
1746 @item @b{gdb-flash-erase-end}
1747 @* After the GDB flash process has finished erasing the flash
1748 @item @b{gdb-flash-write-start}
1749 @* Before GDB writes to the flash
1750 @item @b{gdb-flash-write-end}
1751 @* After GDB writes to the flash
1753 @* Before the taret steps, gdb is trying to start/resume the tarfget
1755 @* The target has halted
1756 @item @b{old-gdb_program_config}
1757 @* DO NOT USE THIS: Used internally
1758 @item @b{old-pre_resume}
1759 @* DO NOT USE THIS: Used internally
1760 @item @b{reset-assert-pre}
1761 @* Before reset is asserted on the tap.
1762 @item @b{reset-assert-post}
1763 @* Reset is now asserted on the tap.
1764 @item @b{reset-deassert-pre}
1765 @* Reset is about to be released on the tap
1766 @item @b{reset-deassert-post}
1767 @* Reset has been released on the tap
1769 @* Currently not used.
1770 @item @b{reset-halt-post}
1771 @* Currently not usd
1772 @item @b{reset-halt-pre}
1773 @* Currently not used
1774 @item @b{reset-init}
1775 @* Currently not used
1776 @item @b{reset-start}
1777 @* Currently not used
1778 @item @b{reset-wait-pos}
1779 @* Currently not used
1780 @item @b{reset-wait-pre}
1781 @* Currently not used
1782 @item @b{resume-start}
1783 @* Before any target is resumed
1784 @item @b{resume-end}
1785 @* After all targets have resumed
1789 @* Target has resumed
1793 @section target create
1795 @cindex target creation
1798 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
1800 @*This command creates a GDB debug target that refers to a specific JTAG tap.
1801 @comment START params
1804 @* Is the name of the debug target. By convention it should be the tap
1805 DOTTED.NAME, this name is also used to create the target object
1808 @* Specifies the target type, ie: arm7tdmi, or cortexM3. Currently supported targes are:
1809 @comment START types
1826 @*PARAMs are various target configure parameters, the following are manditory
1828 @comment START manditory
1830 @item @b{-endian big|little}
1831 @item @b{-chain-position DOTTED.NAME}
1832 @comment end MANDITORY
1837 @section Target Config/Cget Options
1838 These options can be specified when the target is created, or later
1839 via the configure option or to query the target via cget.
1841 @item @b{-type} - returns the target type
1842 @item @b{-event NAME BODY} see Target events
1843 @item @b{-work-area-virt [ADDRESS]} specify/set the work area
1844 @item @b{-work-area-phys [ADDRESS]} specify/set the work area
1845 @item @b{-work-area-size [ADDRESS]} specify/set the work area
1846 @item @b{-work-area-backup [0|1]} does the work area get backed up
1847 @item @b{-endian [big|little]}
1848 @item @b{-variant [NAME]} some chips have varients OpenOCD needs to know about
1849 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
1853 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
1854 set name [target number $x]
1855 set y [$name cget -endian]
1856 set z [$name cget -type]
1857 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
1861 @section Target Varients
1864 @* Unknown (please write me)
1866 @* Unknown (please write me) (simular to arm7tdmi)
1868 @* Varients: @option{arm920t}, @option{arm922t} and @option{arm940t}
1869 This enables the hardware single-stepping support found on these
1874 @* None (this is also used as the ARM946)
1876 @* use variant <@var{-variant lm3s}> when debugging luminary lm3s targets. This will cause
1877 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
1878 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
1879 be detected and the normal reset behaviour used.
1881 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
1883 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
1885 @* Use variant @option{ejtag_srst} when debugging targets that do not
1886 provide a functional SRST line on the EJTAG connector. This causes
1887 OpenOCD to instead use an EJTAG software reset command to reset the
1888 processor. You still need to enable @option{srst} on the reset
1889 configuration command to enable OpenOCD hardware reset functionality.
1890 @comment END varients
1892 @section working_area - Command Removed
1893 @cindex working_area
1894 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
1895 @* This documentation remains because there are existing scripts that
1896 still use this that need to be converted.
1898 working_area target# address size backup| [virtualaddress]
1900 @* The target# is a the 0 based target numerical index.
1902 This command specifies a working area for the debugger to use. This
1903 may be used to speed-up downloads to target memory and flash
1904 operations, or to perform otherwise unavailable operations (some
1905 coprocessor operations on ARM7/9 systems, for example). The last
1906 parameter decides whether the memory should be preserved
1907 (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
1908 possible, use a working_area that doesn't need to be backed up, as
1909 performing a backup slows down operation.
1911 @node Flash Configuration
1912 @chapter Flash Programing
1913 @cindex Flash Configuration
1915 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
1916 flash that a micro may boot from. Perhaps you the reader would like to
1917 contribute support for this.
1921 @item Configure via the command @b{flash bank}
1922 @* Normally this is done in a configuration file.
1923 @item Operate on the flash via @b{flash SOMECOMMAND}
1924 @* Often commands to manipulate the flash are typed by a human, or run
1925 via a script in some automated way. For example: To program the boot
1926 flash on your board.
1928 @* Flashing via GDB requires the flash be configured via ``flash
1929 bank'', and the GDB flash features be enabled. See the Daemon
1930 configuration section for more details.
1933 @section Flash commands
1934 @cindex Flash commands
1935 @subsection flash banks
1938 @*List configured flash banks
1939 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
1940 @subsection flash info
1941 @b{flash info} <@var{num}>
1943 @*Print info about flash bank <@option{num}>
1944 @subsection flash probe
1945 @b{flash probe} <@var{num}>
1947 @*Identify the flash, or validate the parameters of the configured flash. Operation
1948 depends on the flash type.
1949 @subsection flash erase_check
1950 @b{flash erase_check} <@var{num}>
1951 @cindex flash erase_check
1952 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
1953 updates the erase state information displayed by @option{flash info}. That means you have
1954 to issue an @option{erase_check} command after erasing or programming the device to get
1955 updated information.
1956 @subsection flash protect_check
1957 @b{flash protect_check} <@var{num}>
1958 @cindex flash protect_check
1959 @*Check protection state of sectors in flash bank <num>.
1960 @option{flash erase_sector} using the same syntax.
1961 @subsection flash erase_sector
1962 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
1963 @cindex flash erase_sector
1964 @anchor{flash erase_sector}
1965 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
1966 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
1967 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
1969 @subsection flash erase_address
1970 @b{flash erase_address} <@var{address}> <@var{length}>
1971 @cindex flash erase_address
1972 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
1973 @subsection flash write_bank
1974 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
1975 @cindex flash write_bank
1976 @anchor{flash write_bank}
1977 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
1978 <@option{offset}> bytes from the beginning of the bank.
1979 @subsection flash write_image
1980 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
1981 @cindex flash write_image
1982 @anchor{flash write_image}
1983 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
1984 [@var{offset}] can be specified and the file [@var{type}] can be specified
1985 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
1986 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
1987 if the @option{erase} parameter is given.
1988 @subsection flash protect
1989 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
1990 @cindex flash protect
1991 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
1992 <@var{last}> of @option{flash bank} <@var{num}>.
1994 @subsection mFlash commands
1995 @cindex mFlash commands
1997 @item @b{mflash probe}
1998 @cindex mflash probe
2000 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2001 @cindex mflash write
2002 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2003 <@var{offset}> bytes from the beginning of the bank.
2004 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2006 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2010 @section flash bank command
2011 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2014 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2015 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
2018 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2019 and <@var{bus_width}> bytes using the selected flash <driver>.
2021 @subsection External Flash - cfi options
2023 CFI flash are external flash chips - often they are connected to a
2024 specific chip select on the micro. By default at hard reset most
2025 micros have the ablity to ``boot'' from some flash chip - typically
2026 attached to the chips CS0 pin.
2028 For other chip selects: OpenOCD does not know how to configure, or
2029 access a specific chip select. Instead you the human might need to via
2030 other commands (like: mww) configure additional chip selects, or
2031 perhaps configure a GPIO pin that controls the ``write protect'' pin
2034 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2035 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
2036 @*CFI flashes require the number of the target they're connected to as an additional
2037 argument. The CFI driver makes use of a working area (specified for the target)
2038 to significantly speed up operation.
2040 @var{chip_width} and @var{bus_width} are specified in bytes.
2042 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
2046 @subsection Internal Flash (Micro Controllers)
2047 @subsubsection lpc2000 options
2048 @cindex lpc2000 options
2050 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2051 <@var{clock}> [@var{calc_checksum}]
2052 @*LPC flashes don't require the chip and bus width to be specified. Additional
2053 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2054 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
2055 of the target this flash belongs to (first is 0), the frequency at which the core
2056 is currently running (in kHz - must be an integral number), and the optional keyword
2057 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2061 @subsubsection at91sam7 options
2062 @cindex at91sam7 options
2064 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
2065 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
2066 reading the chip-id and type.
2068 @subsubsection str7 options
2069 @cindex str7 options
2071 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2072 @*variant can be either STR71x, STR73x or STR75x.
2074 @subsubsection str9 options
2075 @cindex str9 options
2077 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2078 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
2080 str9x flash_config 0 4 2 0 0x80000
2082 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2084 @subsubsection str9 options (str9xpec driver)
2086 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2087 @*Before using the flash commands the turbo mode will need enabling using str9xpec
2088 @option{enable_turbo} <@var{num>.}
2090 Only use this driver for locking/unlocking the device or configuring the option bytes.
2091 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2093 @subsubsection stellaris (LM3Sxxx) options
2094 @cindex stellaris (LM3Sxxx) options
2096 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2097 @*stellaris flash plugin only require the @var{target#}.
2099 @subsubsection stm32x options
2100 @cindex stm32x options
2102 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2103 @*stm32x flash plugin only require the @var{target#}.
2105 @subsubsection aduc702x options
2106 @cindex aduc702x options
2108 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2109 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
2111 @subsection mFlash configuration
2112 @cindex mFlash configuration
2113 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2114 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
2116 @*Configures a mflash for <@var{soc}> host bank at
2117 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2118 order. Pin number format is dependent on host GPIO calling convention.
2119 If WP or DPD pin was not used, write -1. Currently, mflash bank
2120 support s3c2440 and pxa270.
2122 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2124 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2126 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2128 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2131 @section Micro Controller Specific Flash Commands
2133 @subsection AT91SAM7 specific commands
2134 @cindex AT91SAM7 specific commands
2135 The flash configuration is deduced from the chip identification register. The flash
2136 controller handles erases automatically on a page (128/265 byte) basis so erase is
2137 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2138 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2139 that can be erased separatly. Only an EraseAll command is supported by the controller
2140 for each flash plane and this is called with
2142 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2143 @*bulk erase flash planes first_plane to last_plane.
2144 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2145 @cindex at91sam7 gpnvm
2146 @*set or clear a gpnvm bit for the processor
2149 @subsection STR9 specific commands
2150 @cindex STR9 specific commands
2151 @anchor{STR9 specific commands}
2152 These are flash specific commands when using the str9xpec driver.
2154 @item @b{str9xpec enable_turbo} <@var{num}>
2155 @cindex str9xpec enable_turbo
2156 @*enable turbo mode, simply this will remove the str9 from the chain and talk
2157 directly to the embedded flash controller.
2158 @item @b{str9xpec disable_turbo} <@var{num}>
2159 @cindex str9xpec disable_turbo
2160 @*restore the str9 into jtag chain.
2161 @item @b{str9xpec lock} <@var{num}>
2162 @cindex str9xpec lock
2163 @*lock str9 device. The str9 will only respond to an unlock command that will
2165 @item @b{str9xpec unlock} <@var{num}>
2166 @cindex str9xpec unlock
2167 @*unlock str9 device.
2168 @item @b{str9xpec options_read} <@var{num}>
2169 @cindex str9xpec options_read
2170 @*read str9 option bytes.
2171 @item @b{str9xpec options_write} <@var{num}>
2172 @cindex str9xpec options_write
2173 @*write str9 option bytes.
2176 Note: Before using the str9xpec driver here is some background info to help
2177 you better understand how the drivers works. OpenOCD has two flash drivers for
2181 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2182 flash programming as it is faster than the @option{str9xpec} driver.
2184 Direct programming @option{str9xpec} using the flash controller, this is
2185 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2186 core does not need to be running to program using this flash driver. Typical use
2187 for this driver is locking/unlocking the target and programming the option bytes.
2190 Before we run any cmds using the @option{str9xpec} driver we must first disable
2191 the str9 core. This example assumes the @option{str9xpec} driver has been
2192 configured for flash bank 0.
2194 # assert srst, we do not want core running
2195 # while accessing str9xpec flash driver
2197 # turn off target polling
2200 str9xpec enable_turbo 0
2202 str9xpec options_read 0
2203 # re-enable str9 core
2204 str9xpec disable_turbo 0
2208 The above example will read the str9 option bytes.
2209 When performing a unlock remember that you will not be able to halt the str9 - it
2210 has been locked. Halting the core is not required for the @option{str9xpec} driver
2211 as mentioned above, just issue the cmds above manually or from a telnet prompt.
2213 @subsection STR9 configuration
2214 @cindex STR9 configuration
2216 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2217 <@var{BBADR}> <@var{NBBADR}>
2218 @cindex str9x flash_config
2219 @*Configure str9 flash controller.
2221 eg. str9x flash_config 0 4 2 0 0x80000
2223 BBSR - Boot Bank Size register
2224 NBBSR - Non Boot Bank Size register
2225 BBADR - Boot Bank Start Address register
2226 NBBADR - Boot Bank Start Address register
2230 @subsection STR9 option byte configuration
2231 @cindex STR9 option byte configuration
2233 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2234 @cindex str9xpec options_cmap
2235 @*configure str9 boot bank.
2236 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2237 @cindex str9xpec options_lvdthd
2238 @*configure str9 lvd threshold.
2239 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2240 @cindex str9xpec options_lvdsel
2241 @*configure str9 lvd source.
2242 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2243 @cindex str9xpec options_lvdwarn
2244 @*configure str9 lvd reset warning source.
2247 @subsection STM32x specific commands
2248 @cindex STM32x specific commands
2250 These are flash specific commands when using the stm32x driver.
2252 @item @b{stm32x lock} <@var{num}>
2254 @*lock stm32 device.
2255 @item @b{stm32x unlock} <@var{num}>
2256 @cindex stm32x unlock
2257 @*unlock stm32 device.
2258 @item @b{stm32x options_read} <@var{num}>
2259 @cindex stm32x options_read
2260 @*read stm32 option bytes.
2261 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2262 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2263 @cindex stm32x options_write
2264 @*write stm32 option bytes.
2265 @item @b{stm32x mass_erase} <@var{num}>
2266 @cindex stm32x mass_erase
2267 @*mass erase flash memory.
2270 @subsection Stellaris specific commands
2271 @cindex Stellaris specific commands
2273 These are flash specific commands when using the Stellaris driver.
2275 @item @b{stellaris mass_erase} <@var{num}>
2276 @cindex stellaris mass_erase
2277 @*mass erase flash memory.
2281 @node General Commands
2282 @chapter General Commands
2285 The commands documented in this chapter here are common commands that
2286 you a human may want to type and see the output of. Configuration type
2287 commands are documented elsewhere.
2291 @item @b{Source Of Commands}
2292 @* OpenOCD commands can occur in a configuration script (discussed
2293 elsewhere) or typed manually by a human or supplied programatically,
2294 or via one of several Tcp/Ip Ports.
2296 @item @b{From the human}
2297 @* A human should interact with the Telnet interface (default port: 4444,
2298 or via GDB, default port 3333)
2300 To issue commands from within a GDB session, use the @option{monitor}
2301 command, e.g. use @option{monitor poll} to issue the @option{poll}
2302 command. All output is relayed through the GDB session.
2304 @item @b{Machine Interface}
2305 The TCL interface intent is to be a machine interface. The default TCL
2310 @section Daemon Commands
2313 @b{sleep} <@var{msec}>
2315 @*Wait for n milliseconds before resuming. Useful in connection with script files
2316 (@var{script} command and @var{target_script} configuration).
2321 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
2323 @subsection debug_level [@var{n}]
2325 @anchor{debug_level}
2326 @*Display or adjust debug level to n<0-3>
2328 @subsection fast [@var{enable|disable}]
2330 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2331 downloads and fast memory access will work if the JTAG interface isn't too fast and
2332 the core doesn't run at a too low frequency. Note that this option only changes the default
2333 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2336 The target specific "dangerous" optimisation tweaking options may come and go
2337 as more robust and user friendly ways are found to ensure maximum throughput
2338 and robustness with a minimum of configuration.
2340 Typically the "fast enable" is specified first on the command line:
2343 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2346 @subsection log_output <@var{file}>
2348 @*Redirect logging to <file> (default: stderr)
2350 @subsection script <@var{file}>
2352 @*Execute commands from <file>
2353 Also see: ``source [find FILENAME]''
2355 @section Target state handling
2356 @subsection power <@var{on}|@var{off}>
2358 @*Turn power switch to target on/off.
2359 No arguments: print status.
2360 Not all interfaces support this.
2362 @subsection reg [@option{#}|@option{name}] [value]
2364 @*Access a single register by its number[@option{#}] or by its [@option{name}].
2365 No arguments: list all available registers for the current target.
2366 Number or name argument: display a register
2367 Number or name and value arguments: set register value
2369 @subsection poll [@option{on}|@option{off}]
2371 @*Poll the target for its current state. If the target is in debug mode, architecture
2372 specific information about the current state is printed. An optional parameter
2373 allows continuous polling to be enabled and disabled.
2375 @subsection halt [@option{ms}]
2377 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
2378 Default [@option{ms}] is 5 seconds if no arg given.
2379 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
2380 will stop OpenOCD from waiting.
2382 @subsection wait_halt [@option{ms}]
2384 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
2385 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
2388 @subsection resume [@var{address}]
2390 @*Resume the target at its current code position, or at an optional address.
2391 OpenOCD will wait 5 seconds for the target to resume.
2393 @subsection step [@var{address}]
2395 @*Single-step the target at its current code position, or at an optional address.
2397 @subsection reset [@option{run}|@option{halt}|@option{init}]
2399 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
2401 With no arguments a "reset run" is executed
2405 @*Let the target run.
2408 @*Immediately halt the target (works only with certain configurations).
2411 @*Immediately halt the target, and execute the reset script (works only with certain
2415 @subsection soft_reset_halt
2417 @*Requesting target halt and executing a soft reset. This often used
2418 when a target cannot be reset and halted. The target, after reset is
2419 released begins to execute code. OpenOCD attempts to stop the CPU and
2420 then sets the Program counter back at the reset vector. Unfortunatlly
2421 that code that was executed may have left hardware in an unknown
2425 @section Memory access commands
2427 display available ram memory.
2428 @subsection Memory Peek/Poke type commands
2429 These commands allow accesses of a specific size to the memory
2430 system. Often these are used to configure the current target in some
2431 special way. For example - one may need to write certian values to the
2432 SDRAM controller to enable SDRAM.
2435 @item To change the current target see the ``targets'' (plural) command
2436 @item In system level scripts these commands are depricated, please use the TARGET object versions.
2440 @item @b{mdw} <@var{addr}> [@var{count}]
2442 @*display memory words (32bit)
2443 @item @b{mdh} <@var{addr}> [@var{count}]
2445 @*display memory half-words (16bit)
2446 @item @b{mdb} <@var{addr}> [@var{count}]
2448 @*display memory bytes (8bit)
2449 @item @b{mww} <@var{addr}> <@var{value}>
2451 @*write memory word (32bit)
2452 @item @b{mwh} <@var{addr}> <@var{value}>
2454 @*write memory half-word (16bit)
2455 @item @b{mwb} <@var{addr}> <@var{value}>
2457 @*write memory byte (8bit)
2460 @section Image Loading Commands
2461 @subsection load_image
2462 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2465 @*Load image <@var{file}> to target memory at <@var{address}>
2466 @subsection fast_load_image
2467 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2468 @cindex fast_load_image
2469 @anchor{fast_load_image}
2470 @*Normally you should be using @b{load_image} or GDB load. However, for
2471 testing purposes or when IO overhead is significant(OpenOCD running on embedded
2472 host), then storing the image in memory and uploading the image to the target
2473 can be a way to upload e.g. multiple debug sessions when the binary does not change.
2474 Arguments as @b{load_image}, but image is stored in OpenOCD host
2475 memory, i.e. does not affect target. This approach is also useful when profiling
2476 target programming performance as IO and target programming can easily be profiled
2478 @subsection fast_load
2482 @*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
2483 @subsection dump_image
2484 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
2487 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
2488 (binary) <@var{file}>.
2489 @subsection verify_image
2490 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2491 @cindex verify_image
2492 @*Verify <@var{file}> against target memory starting at <@var{address}>.
2493 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
2496 @section Breakpoint commands
2497 @cindex Breakpoint commands
2499 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
2501 @*set breakpoint <address> <length> [hw]
2502 @item @b{rbp} <@var{addr}>
2504 @*remove breakpoint <adress>
2505 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
2507 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
2508 @item @b{rwp} <@var{addr}>
2510 @*remove watchpoint <adress>
2513 @section Misc Commands
2514 @cindex Other Target Commands
2516 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
2518 Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
2521 @section Target Specific Commands
2522 @cindex Target Specific Commands
2526 @section Architecture Specific Commands
2527 @cindex Architecture Specific Commands
2529 @subsection ARMV4/5 specific commands
2530 @cindex ARMV4/5 specific commands
2532 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
2533 or Intel XScale (XScale isn't supported yet).
2535 @item @b{armv4_5 reg}
2537 @*Display a list of all banked core registers, fetching the current value from every
2538 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
2540 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
2541 @cindex armv4_5 core_mode
2542 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
2543 The target is resumed in the currently set @option{core_mode}.
2546 @subsection ARM7/9 specific commands
2547 @cindex ARM7/9 specific commands
2549 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
2550 ARM920t or ARM926EJ-S.
2552 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
2553 @cindex arm7_9 dbgrq
2554 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
2555 safe for all but ARM7TDMI--S cores (like Philips LPC).
2556 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
2557 @cindex arm7_9 fast_memory_access
2558 @anchor{arm7_9 fast_memory_access}
2559 @*Allow OpenOCD to read and write memory without checking completion of
2560 the operation. This provides a huge speed increase, especially with USB JTAG
2561 cables (FT2232), but might be unsafe if used with targets running at a very low
2562 speed, like the 32kHz startup clock of an AT91RM9200.
2563 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
2564 @cindex arm7_9 dcc_downloads
2565 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
2566 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
2567 unsafe, especially with targets running at a very low speed. This command was introduced
2568 with OpenOCD rev. 60.
2571 @subsection ARM720T specific commands
2572 @cindex ARM720T specific commands
2575 @item @b{arm720t cp15} <@var{num}> [@var{value}]
2576 @cindex arm720t cp15
2577 @*display/modify cp15 register <@option{num}> [@option{value}].
2578 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
2579 @cindex arm720t md<bhw>_phys
2580 @*Display memory at physical address addr.
2581 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
2582 @cindex arm720t mw<bhw>_phys
2583 @*Write memory at physical address addr.
2584 @item @b{arm720t virt2phys} <@var{va}>
2585 @cindex arm720t virt2phys
2586 @*Translate a virtual address to a physical address.
2589 @subsection ARM9TDMI specific commands
2590 @cindex ARM9TDMI specific commands
2593 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
2594 @cindex arm9tdmi vector_catch
2595 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
2596 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
2597 @option{irq} @option{fiq}.
2599 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
2602 @subsection ARM966E specific commands
2603 @cindex ARM966E specific commands
2606 @item @b{arm966e cp15} <@var{num}> [@var{value}]
2607 @cindex arm966e cp15
2608 @*display/modify cp15 register <@option{num}> [@option{value}].
2611 @subsection ARM920T specific commands
2612 @cindex ARM920T specific commands
2615 @item @b{arm920t cp15} <@var{num}> [@var{value}]
2616 @cindex arm920t cp15
2617 @*display/modify cp15 register <@option{num}> [@option{value}].
2618 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
2619 @cindex arm920t cp15i
2620 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
2621 @item @b{arm920t cache_info}
2622 @cindex arm920t cache_info
2623 @*Print information about the caches found. This allows you to see if your target
2624 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
2625 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
2626 @cindex arm920t md<bhw>_phys
2627 @*Display memory at physical address addr.
2628 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
2629 @cindex arm920t mw<bhw>_phys
2630 @*Write memory at physical address addr.
2631 @item @b{arm920t read_cache} <@var{filename}>
2632 @cindex arm920t read_cache
2633 @*Dump the content of ICache and DCache to a file.
2634 @item @b{arm920t read_mmu} <@var{filename}>
2635 @cindex arm920t read_mmu
2636 @*Dump the content of the ITLB and DTLB to a file.
2637 @item @b{arm920t virt2phys} <@var{va}>
2638 @cindex arm920t virt2phys
2639 @*Translate a virtual address to a physical address.
2642 @subsection ARM926EJS specific commands
2643 @cindex ARM926EJS specific commands
2646 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
2647 @cindex arm926ejs cp15
2648 @*display/modify cp15 register <@option{num}> [@option{value}].
2649 @item @b{arm926ejs cache_info}
2650 @cindex arm926ejs cache_info
2651 @*Print information about the caches found.
2652 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
2653 @cindex arm926ejs md<bhw>_phys
2654 @*Display memory at physical address addr.
2655 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
2656 @cindex arm926ejs mw<bhw>_phys
2657 @*Write memory at physical address addr.
2658 @item @b{arm926ejs virt2phys} <@var{va}>
2659 @cindex arm926ejs virt2phys
2660 @*Translate a virtual address to a physical address.
2663 @subsection CORTEX_M3 specific commands
2664 @cindex CORTEX_M3 specific commands
2667 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
2668 @cindex cortex_m3 maskisr
2669 @*Enable masking (disabling) interrupts during target step/resume.
2673 @section Debug commands
2674 @cindex Debug commands
2675 The following commands give direct access to the core, and are most likely
2676 only useful while debugging OpenOCD.
2678 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
2679 @cindex arm7_9 write_xpsr
2680 @*Immediately write either the current program status register (CPSR) or the saved
2681 program status register (SPSR), without changing the register cache (as displayed
2682 by the @option{reg} and @option{armv4_5 reg} commands).
2683 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
2684 <@var{0=cpsr},@var{1=spsr}>
2685 @cindex arm7_9 write_xpsr_im8
2686 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
2687 operation (similar to @option{write_xpsr}).
2688 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
2689 @cindex arm7_9 write_core_reg
2690 @*Write a core register, without changing the register cache (as displayed by the
2691 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
2692 encoding of the [M4:M0] bits of the PSR.
2695 @section Target Requests
2696 @cindex Target Requests
2697 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
2698 See libdcc in the contrib dir for more details.
2700 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
2701 @cindex target_request debugmsgs
2702 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
2706 @chapter JTAG Commands
2707 @cindex JTAG commands
2708 Generally most people will not use the bulk of these commands. They
2709 are mostly used by the OpenOCD developers or those who need to
2710 directly manipulate the JTAG taps.
2712 In general these commands control JTAG taps at a very low level. For
2713 example if you need to control a JTAG Route Controller (ie: the
2714 OMAP3530 on the Beagle Board has one) you might use these commands in
2715 a script or an event procedure.
2718 @item @b{scan_chain}
2720 @*Print current scan chain configuration.
2721 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
2723 @*Toggle reset lines.
2724 @item @b{endstate} <@var{tap_state}>
2726 @*Finish JTAG operations in <@var{tap_state}>.
2727 @item @b{runtest} <@var{num_cycles}>
2729 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
2730 @item @b{statemove} [@var{tap_state}]
2732 @*Move to current endstate or [@var{tap_state}]
2733 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2735 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2736 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
2738 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
2739 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
2740 @cindex verify_ircapture
2741 @*Verify value captured during Capture-IR. Default is enabled.
2742 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2744 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2745 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
2747 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
2754 If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
2755 be used to access files on PCs(either developer PC or some other PC).
2757 The way this works on the ZY1000 is to prefix a filename by
2758 "/tftp/ip/" and append the tftp path on the tftp
2759 server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
2760 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
2761 if the file was hosted on the embedded host.
2763 In order to achieve decent performance, you must choose a tftp server
2764 that supports a packet size bigger than the default packet size(512 bytes). There
2765 are numerous tftp servers out there(free and commercial) and you will have to do
2766 a bit of googling to find something that fits your requirements.
2768 @node Sample Scripts
2769 @chapter Sample Scripts
2772 This page shows how to use the target library.
2774 The configuration script can be divided in the following section:
2776 @item daemon configuration
2778 @item jtag scan chain
2779 @item target configuration
2780 @item flash configuration
2783 Detailed information about each section can be found at OpenOCD configuration.
2785 @section AT91R40008 example
2786 @cindex AT91R40008 example
2787 To start OpenOCD with a target script for the AT91R40008 CPU and reset
2788 the CPU upon startup of the OpenOCD daemon.
2790 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
2794 @node GDB and OpenOCD
2795 @chapter GDB and OpenOCD
2796 @cindex GDB and OpenOCD
2797 OpenOCD complies with the remote gdbserver protocol, and as such can be used
2798 to debug remote targets.
2800 @section Connecting to GDB
2801 @cindex Connecting to GDB
2802 @anchor{Connecting to GDB}
2803 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
2804 instance 6.3 has a known bug where it produces bogus memory access
2805 errors, which has since been fixed: look up 1836 in
2806 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
2808 @*OpenOCD can communicate with GDB in two ways:
2811 A socket (tcp) connection is typically started as follows:
2813 target remote localhost:3333
2815 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
2817 A pipe connection is typically started as follows:
2819 target remote openocd --pipe
2821 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
2822 Using this method has the advantage of GDB starting/stopping OpenOCD for debug session.
2825 @*To see a list of available OpenOCD commands type @option{monitor help} on the
2828 OpenOCD supports the gdb @option{qSupported} packet, this enables information
2829 to be sent by the gdb server (OpenOCD) to GDB. Typical information includes
2830 packet size and device memory map.
2832 Previous versions of OpenOCD required the following GDB options to increase
2833 the packet size and speed up GDB communication.
2835 set remote memory-write-packet-size 1024
2836 set remote memory-write-packet-size fixed
2837 set remote memory-read-packet-size 1024
2838 set remote memory-read-packet-size fixed
2840 This is now handled in the @option{qSupported} PacketSize and should not be required.
2842 @section Programming using GDB
2843 @cindex Programming using GDB
2845 By default the target memory map is sent to GDB, this can be disabled by
2846 the following OpenOCD config option:
2848 gdb_memory_map disable
2850 For this to function correctly a valid flash config must also be configured
2851 in OpenOCD. For faster performance you should also configure a valid
2854 Informing GDB of the memory map of the target will enable GDB to protect any
2855 flash area of the target and use hardware breakpoints by default. This means
2856 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
2857 using a memory map. @xref{gdb_breakpoint_override}.
2859 To view the configured memory map in GDB, use the gdb command @option{info mem}
2860 All other unasigned addresses within GDB are treated as RAM.
2862 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
2863 this can be changed to the old behaviour by using the following GDB command.
2865 set mem inaccessible-by-default off
2868 If @option{gdb_flash_program enable} is also used, GDB will be able to
2869 program any flash memory using the vFlash interface.
2871 GDB will look at the target memory map when a load command is given, if any
2872 areas to be programmed lie within the target flash area the vFlash packets
2875 If the target needs configuring before GDB programming, an event
2876 script can be executed.
2878 $_TARGETNAME configure -event EVENTNAME BODY
2881 To verify any flash programming the GDB command @option{compare-sections}
2884 @node TCL scripting API
2885 @chapter TCL scripting API
2886 @cindex TCL scripting API
2889 The commands are stateless. E.g. the telnet command line has a concept
2890 of currently active target, the Tcl API proc's take this sort of state
2891 information as an argument to each proc.
2893 There are three main types of return values: single value, name value
2894 pair list and lists.
2896 Name value pair. The proc 'foo' below returns a name/value pair
2902 > set foo(you) Oyvind
2903 > set foo(mouse) Micky
2904 > set foo(duck) Donald
2912 me Duane you Oyvind mouse Micky duck Donald
2914 Thus, to get the names of the associative array is easy:
2916 foreach { name value } [set foo] {
2917 puts "Name: $name, Value: $value"
2921 Lists returned must be relatively small. Otherwise a range
2922 should be passed in to the proc in question.
2924 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
2925 is the low level API upon which "flash banks" is implemented.
2928 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2930 Read memory and return as a TCL array for script processing
2931 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2933 Convert a TCL array to memory locations and write the values
2934 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
2936 Return information about the flash banks
2939 OpenOCD commands can consist of two words, e.g. "flash banks". The
2940 startup.tcl "unknown" proc will translate this into a tcl proc
2941 called "flash_banks".
2945 @chapter Deprecated/Removed Commands
2946 @cindex Deprecated/Removed Commands
2947 Certain OpenOCD commands have been deprecated/removed during the various revisions.
2950 @item @b{arm7_9 fast_writes}
2951 @cindex arm7_9 fast_writes
2952 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
2953 @item @b{arm7_9 force_hw_bkpts}
2954 @cindex arm7_9 force_hw_bkpts
2955 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
2956 for flash if the gdb memory map has been set up(default when flash is declared in
2957 target configuration). @xref{gdb_breakpoint_override}.
2958 @item @b{arm7_9 sw_bkpts}
2959 @cindex arm7_9 sw_bkpts
2960 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
2961 @item @b{daemon_startup}
2962 @cindex daemon_startup
2963 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
2964 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
2965 and @option{target cortex_m3 little reset_halt 0}.
2966 @item @b{dump_binary}
2968 @*use @option{dump_image} command with same args. @xref{dump_image}.
2969 @item @b{flash erase}
2971 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
2972 @item @b{flash write}
2974 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2975 @item @b{flash write_binary}
2976 @cindex flash write_binary
2977 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2978 @item @b{flash auto_erase}
2979 @cindex flash auto_erase
2980 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
2981 @item @b{load_binary}
2983 @*use @option{load_image} command with same args. @xref{load_image}.
2984 @item @b{run_and_halt_time}
2985 @cindex run_and_halt_time
2986 @*This command has been removed for simpler reset behaviour, it can be simulated with the
2993 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
2995 @*use the create subcommand of @option{target}.
2996 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
2997 @cindex target_script
2998 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
2999 @item @b{working_area}
3000 @cindex working_area
3001 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3008 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3010 @cindex adaptive clocking
3013 In digital circuit design it is often refered to as ``clock
3014 syncronization'' the JTAG interface uses one clock (TCK or TCLK)
3015 operating at some speed, your target is operating at another. The two
3016 clocks are not syncronized, they are ``asynchronous''
3018 In order for the two to work together they must syncronize. Otherwise
3019 the two systems will get out of sync with each other and nothing will
3020 work. There are 2 basic options. @b{1.} use a special circuit or
3021 @b{2.} one clock must be some multile slower the the other.
3023 @b{Does this really matter?} For some chips and some situations, this
3024 is a non-issue (ie: A 500mhz ARM926) but for others - for example some
3025 ATMEL SAM7 and SAM9 chips start operation from reset at 32khz -
3026 program/enable the oscillators and eventually the main clock. It is in
3027 those critical times you must slow the jtag clock to sometimes 1 to
3030 Imagine debugging that 500mhz arm926 hand held battery powered device
3031 that ``deep sleeps'' at 32khz between every keystroke. It can be
3034 @b{Solution #1 - A special circuit}
3036 In order to make use of this your jtag dongle must support the RTCK
3037 feature. Not all dongles support this - keep reading!
3039 The RTCK signal often found in some ARM chips is used to help with
3040 this problem. ARM has a good description of the problem described at
3041 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3042 28/nov/2008]. Link title: ``How does the jtag synchronisation logic
3043 work? / how does adaptive clocking working?''.
3045 The nice thing about adaptive clocking is that ``battery powered hand
3046 held device example'' - the adaptiveness works perfectly all the
3047 time. One can set a break point or halt the system in the deep power
3048 down code, slow step out until the system speeds up.
3050 @b{Solution #2 - Always works - but is slower}
3052 Often this is a perfectly acceptable solution.
3054 In the most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3055 the target clock speed. But what is that ``magic division'' it varies
3056 depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM
3057 based systems require an 8:1 division. @b{Xilinx Rule of thumb} is
3058 1/12 the clock speed.
3060 Note: Many FTDI2232C based JTAG dongles are limited to 6mhz.
3062 You can still debug the 'lower power' situations - you just need to
3063 manually adjust the clock speed at every step. While painful and
3064 teadious, it is not always practical.
3066 It is however easy to ``code your way around it'' - ie: Cheat a little
3067 have a special debug mode in your application that does a ``high power
3068 sleep''. If you are careful - 98% of your problems can be debugged
3071 To set the JTAG frequency use the command:
3079 @item @b{Win32 Pathnames} Why does not backslashes in paths under Windows doesn't work?
3081 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3082 around Windows filenames.
3095 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3097 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3098 claims to come with all the necessary dlls. When using Cygwin, try launching
3099 OpenOCD from the Cygwin shell.
3101 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3102 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3103 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3105 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3106 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
3107 software breakpoints consume one of the two available hardware breakpoints.
3109 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
3110 and works sometimes fine.
3112 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3113 clock at the time you're programming the flash. If you've specified the crystal's
3114 frequency, make sure the PLL is disabled, if you've specified the full core speed
3115 (e.g. 60MHz), make sure the PLL is enabled.
3117 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3118 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3119 out while waiting for end of scan, rtck was disabled".
3121 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3122 settings in your PC BIOS (ECP, EPP, and different versions of those).
3124 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3125 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3126 memory read caused data abort".
3128 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3129 beyond the last valid frame. It might be possible to prevent this by setting up
3130 a proper "initial" stack frame, if you happen to know what exactly has to
3131 be done, feel free to add this here.
3133 @b{Simple:} In your startup code - push 8 registers of ZEROs onto the
3134 stack before calling main(). What GDB is doing is ``climbing'' the run
3135 time stack by reading various values on the stack using the standard
3136 call frame for the target. GDB keeps going - until one of 2 things
3137 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3138 stackframes have been processed. By pushing ZEROs on the stack, GDB
3141 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3142 your C code, do the same, artifically push some zeros on to the stack,
3143 remember to pop them off when the ISR is done.
3145 @b{Also note:} If you have a multi-threaded operating system, they
3146 often do not @b{in the intrest of saving memory} waste these few
3150 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3151 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3153 This warning doesn't indicate any serious problem, as long as you don't want to
3154 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3155 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3156 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3157 independently. With this setup, it's not possible to halt the core right out of
3158 reset, everything else should work fine.
3160 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3161 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3162 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3163 quit with an error message. Is there a stability issue with OpenOCD?
3165 No, this is not a stability issue concerning OpenOCD. Most users have solved
3166 this issue by simply using a self-powered USB hub, which they connect their
3167 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3168 supply stable enough for the Amontec JTAGkey to be operated.
3170 @b{Laptops running on battery have this problem too...}
3172 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3173 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3174 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3175 What does that mean and what might be the reason for this?
3177 First of all, the reason might be the USB power supply. Try using a self-powered
3178 hub instead of a direct connection to your computer. Secondly, the error code 4
3179 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3180 chip ran into some sort of error - this points us to a USB problem.
3182 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3183 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3184 What does that mean and what might be the reason for this?
3186 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3187 has closed the connection to OpenOCD. This might be a GDB issue.
3189 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3190 are described, there is a parameter for specifying the clock frequency
3191 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3192 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3193 specified in kilohertz. However, I do have a quartz crystal of a
3194 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3195 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3198 No. The clock frequency specified here must be given as an integral number.
3199 However, this clock frequency is used by the In-Application-Programming (IAP)
3200 routines of the LPC2000 family only, which seems to be very tolerant concerning
3201 the given clock frequency, so a slight difference between the specified clock
3202 frequency and the actual clock frequency will not cause any trouble.
3204 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3206 Well, yes and no. Commands can be given in arbitrary order, yet the
3207 devices listed for the JTAG scan chain must be given in the right
3208 order (jtag newdevice), with the device closest to the TDO-Pin being
3209 listed first. In general, whenever objects of the same type exist
3210 which require an index number, then these objects must be given in the
3211 right order (jtag newtap, targets and flash banks - a target
3212 references a jtag newtap and a flash bank references a target).
3214 You can use the ``scan_chain'' command to verify and display the tap order.
3216 @item @b{JTAG Tap Order} JTAG Tap Order - Command Order
3218 Many newer devices have multiple JTAG taps. For example: ST
3219 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3220 ``cortexM3'' tap. Example: The STM32 reference manual, Document ID:
3221 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3222 connected to the Boundary Scan Tap, which then connects to the
3223 CortexM3 Tap, which then connects to the TDO pin.
3225 Thus, the proper order for the STM32 chip is: (1) The CortexM3, then
3226 (2) The Boundary Scan Tap. If your board includes an additional JTAG
3227 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3228 place it before or after the stm32 chip in the chain. For example:
3231 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3232 @item STM32 BS TDO (output) -> STM32 CortexM3 TDI (input)
3233 @item STM32 CortexM3 TDO (output) -> SM32 TDO Pin
3234 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3235 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3238 The ``jtag device'' commands would thus be in the order shown below. Note
3241 @item jtag newtap Xilinx tap -irlen ...
3242 @item jtag newtap stm32 cpu -irlen ...
3243 @item jtag newtap stm32 bs -irlen ...
3244 @item # Create the debug target and say where it is
3245 @item target create stm32.cpu -chain-position stm32.cpu ...
3249 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3250 log file, I can see these error messages: Error: arm7_9_common.c:561
3251 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3257 @node TCL Crash Course
3258 @chapter TCL Crash Course
3261 Not everyone knows TCL - this is not intended to be a replacement for
3262 learning TCL, the intent of this chapter is to give you some idea of
3263 how the TCL Scripts work.
3265 This chapter is written with two audiences in mind. (1) OpenOCD users
3266 who need to understand a bit more of how JIM-Tcl works so they can do
3267 something useful, and (2) those that want to add a new command to
3270 @section TCL Rule #1
3271 There is a famous joke, it goes like this:
3273 @item Rule #1: The wife is aways correct
3274 @item Rule #2: If you think otherwise, See Rule #1
3277 The TCL equal is this:
3280 @item Rule #1: Everything is a string
3281 @item Rule #2: If you think otherwise, See Rule #1
3284 As in the famous joke, the consiquences of Rule #1 are profound. Once
3285 you understand Rule #1, you will understand TCL.
3287 @section TCL Rule #1b
3288 There is a second pair of rules.
3290 @item Rule #1: Control flow does not exist. Only commands
3291 @* For example: the classic FOR loop or IF statement is not a control
3292 flow item, they are commands, there is no such thing as control flow
3294 @item Rule #2: If you think otherwise, See Rule #1
3295 @* Actually what happens is this: There are commands that by
3296 convention, act like control flow key words in other languages. One of
3297 those commands is the word ``for'', another command is ``if''.
3300 @section Per Rule #1 - All Results are strings
3301 Every TCL command results in a string. The word ``result'' is used
3302 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
3303 Everything is a string}
3305 @section TCL Quoting Operators
3306 In life of a TCL script, there are two important periods of time, the
3307 difference is subtle.
3310 @item Evaluation Time
3313 The two key items here are how ``quoted things'' work in TCL. TCL has
3314 three primary quoting constructs, the [square-brackets] the
3315 @{curly-braces@} and ``double-quotes''
3317 By now you should know $VARIABLES always start with a $DOLLAR
3318 sign. BTW, to set a variable, you actually use the command ``set'', as
3319 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
3320 = 1'' statement, but without the equal sign.
3323 @item @b{[square-brackets]}
3324 @* @b{[square-brackets]} are command subsitution. It operates much
3325 like Unix Shell `back-ticks`. The result of a [square-bracket]
3326 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
3327 string}. These two statments are roughly identical.
3331 echo "The Date is: $X"
3334 puts "The Date is: $X"
3336 @item @b{``double-quoted-things''}
3337 @* @b{``double-quoted-things''} are just simply quoted
3338 text. $VARIABLES and [square-brackets] are expanded in place - the
3339 result however is exactly 1 string. @i{Remember Rule #1 - Everything
3343 puts "It is now \"[date]\", $x is in 1 hour"
3345 @item @b{@{Curly-Braces@}}
3346 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
3347 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
3348 'single-quote' operators in BASH shell scripts, with the added
3349 feature: @{curly-braces@} nest, single quotes can not. @{@{@{this is
3350 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
3351 28/nov/2008, Jim/OpenOCD does not have a date command.
3354 @section Consiquences of Rule 1/2/3/4
3356 The consiquences of Rule 1 is profound.
3358 @subsection Tokenizing & Execution.
3360 Of course, whitespace, blank lines and #comment lines are handled in
3363 As a script is parsed, each (multi) line in the script file is
3364 tokenized and according to the quoting rules. After tokenizing, that
3365 line is immedatly executed.
3367 Multi line statements end with one or more ``still-open''
3368 @{curly-braces@} which - eventually - a few lines later closes.
3370 @subsection Command Execution
3372 Remember earlier: There is no such thing as ``control flow''
3373 statements in TCL. Instead there are COMMANDS that simpily act like
3374 control flow operators.
3376 Commands are executed like this:
3379 @item Parse the next line into (argc) and (argv[]).
3380 @item Look up (argv[0]) in a table and call its function.
3381 @item Repeat until End Of File.
3384 It sort of works like this:
3387 ReadAndParse( &argc, &argv );
3389 cmdPtr = LookupCommand( argv[0] );
3391 (*cmdPtr->Execute)( argc, argv );
3395 When the command ``proc'' is parsed (which creates a procedure
3396 function) it gets 3 parameters on the command line. @b{1} the name of
3397 the proc (function), @b{2} the list of parameters, and @b{3} the body
3398 of the function. Not the choice of words: LIST and BODY. The PROC
3399 command stores these items in a table somewhere so it can be found by
3402 @subsection The FOR Command
3404 The most interesting command to look at is the FOR command. In TCL,
3405 the FOR command is normally implimented in C. Remember, FOR is a
3406 command just like any other command.
3408 When the ascii text containing the FOR command is parsed, the parser
3409 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
3413 @item The ascii text 'for'
3414 @item The start text
3415 @item The test expression
3420 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
3421 Remember @i{Rule #1 - Everything is a string.} The key point is this:
3422 Often many of those parameters are in @{curly-braces@} - thus the
3423 variables inside are not expanded or replaced until later.
3425 Remember that every TCL command looks like the classic ``main( argc,
3426 argv )'' function in C. In JimTCL - they actually look like this:
3430 MyCommand( Jim_Interp *interp,
3432 Jim_Obj * const *argvs );
3435 Real TCL is nearly identical. Although the newer versions have
3436 introduced a byte-code parser and intepreter, but at the core, it
3437 still operates in the same basic way.
3439 @subsection FOR Command Implimentation
3441 To understand TCL it is perhaps most helpful to see the FOR
3442 command. Remember, it is a COMMAND not a control flow structure.
3444 In TCL there are two underying C helper functions.
3446 Remember Rule #1 - You are a string.
3448 The @b{first} helper parses and executes commands found in an ascii
3449 string. Commands can be seperated by semi-colons, or newlines. While
3450 parsing, variables are expanded per the quoting rules
3452 The @b{second} helper evaluates an ascii string as a numerical
3453 expression and returns a value.
3455 Here is an example of how the @b{FOR} command could be
3456 implimented. The pseudo code below does not show error handling.
3458 void Execute_AsciiString( void *interp, const char *string );
3460 int Evaluate_AsciiExpression( void *interp, const char *string );
3463 MyForCommand( void *interp,
3468 SetResult( interp, "WRONG number of parameters");
3472 // argv[0] = the ascii string just like C
3474 // Execute the start statement.
3475 Execute_AsciiString( interp, argv[1] );
3479 i = Evaluate_AsciiExpression(interp, argv[2]);
3484 Execute_AsciiString( interp, argv[3] );
3486 // Execute the LOOP part
3487 Execute_AsciiString( interp, argv[4] );
3491 SetResult( interp, "" );
3496 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
3497 in the same basic way.
3499 @section OpenOCD TCL Usage
3501 @subsection source and find commands
3502 @b{Where:} In many configuration files
3503 @* Example: @b{ source [find FILENAME] }
3504 @*Remember the parsing rules
3506 @item The FIND command is in square brackets.
3507 @* The FIND command is executed with the parameter FILENAME. It should
3508 find the full path to the named file. The RESULT is a string, which is
3509 subsituted on the orginal command line.
3510 @item The command source is executed with the resulting filename.
3511 @* SOURCE reads a file and executes as a script.
3513 @subsection format command
3514 @b{Where:} Generally occurs in numerous places.
3515 @* TCL no command like @b{printf()}, intead it has @b{format}, which is really more like
3521 puts [format "The answer: %d" [expr $x * $y]]
3524 @item The SET command creates 2 variables, X and Y.
3525 @item The double [nested] EXPR command performs math
3526 @* The EXPR command produces numerical result as a string.
3528 @item The format command is executed, producing a single string
3529 @* Refer to Rule #1.
3530 @item The PUTS command outputs the text.
3532 @subsection Body Or Inlined Text
3533 @b{Where:} Various TARGET scripts.
3536 proc someproc @{@} @{
3537 ... multiple lines of stuff ...
3539 $_TARGETNAME configure -event FOO someproc
3540 #2 Good - no variables
3541 $_TARGETNAME confgure -event foo "this ; that;"
3542 #3 Good Curly Braces
3543 $_TARGETNAME configure -event FOO @{
3546 #4 DANGER DANGER DANGER
3547 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
3550 @item The $_TARGETNAME is an OpenOCD variable convention.
3551 @*@b{$_TARGETNAME} represents the last target created, the value changes
3552 each time a new target is created. Remember the parsing rules. When
3553 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
3554 the name of the target which happens to be a TARGET (object)
3556 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
3557 @*There are 4 examples:
3559 @item The TCLBODY is a simple string that happens to be a proc name
3560 @item The TCLBODY is several simple commands semi-colon seperated
3561 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
3562 @item The TCLBODY is a string with variables that get expanded.
3565 In the end, when the target event FOO occurs the TCLBODY is
3566 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
3567 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
3569 Remember the parsing rules. In case #3, @{curly-braces@} mean the
3570 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
3571 and the text is evaluated. In case #4, they are replaced before the
3572 ``Target Object Command'' is executed. This occurs at the same time
3573 $_TARGETNAME is replaced. In case #4 the date will never
3574 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
3575 Jim/OpenOCD does not have a date command@}
3577 @subsection Global Variables
3578 @b{Where:} You might discover this when writing your own procs @* In
3579 simple terms: Inside a PROC, if you need to access a global variable
3580 you must say so. Also see ``upvar''. Example:
3582 proc myproc @{ @} @{
3583 set y 0 #Local variable Y
3584 global x #Global variable X
3585 puts [format "X=%d, Y=%d" $x $y]
3588 @section Other Tcl Hacks
3589 @b{Dynamic Variable Creation}
3591 # Dynamically create a bunch of variables.
3592 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
3594 set vn [format "BIT%d" $x]
3598 set $vn [expr (1 << $x)]
3601 @b{Dynamic Proc/Command Creation}
3603 # One "X" function - 5 uart functions.
3604 foreach who @{A B C D E@}
3605 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
3609 @node Target library
3610 @chapter Target library
3611 @cindex Target library
3613 OpenOCD comes with a target configuration script library. These scripts can be
3614 used as-is or serve as a starting point.
3616 The target library is published together with the OpenOCD executable and
3617 the path to the target library is in the OpenOCD script search path.
3618 Similarly there are example scripts for configuring the JTAG interface.
3620 The command line below uses the example parport configuration scripts
3621 that ship with OpenOCD, then configures the str710.cfg target and
3622 finally issues the init and reset command. The communication speed
3623 is set to 10kHz for reset and 8MHz for post reset.
3627 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
3631 To list the target scripts available:
3634 $ ls /usr/local/lib/openocd/target
3636 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
3637 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
3638 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
3639 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
3647 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
3648 @comment case issue with ``Index.html'' and ``index.html''
3649 @comment Occurs when creating ``--html --no-split'' output
3650 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
3651 @unnumbered OpenOCD Index