1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
8 @title Open On-Chip Debugger (openocd)
10 @vskip 0pt plus 1filll
15 @node Top, About, , (dir)
18 The Manual always document the latest version of OpenOCD available from SVN.
21 * About:: About Openocd.
23 * Building:: Building Openocd
24 * Running:: Running Openocd
25 * Configuration:: Openocd Configuration.
26 * Commands:: Openocd Commands
27 * Sample Scripts:: Sample Target Scripts
28 * FAQ:: Frequently Asked Questions
29 * License:: GNU Free Documentation License
37 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
38 and boundary-scan testing for embedded target devices. The targets are interfaced
39 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
40 connection types in the future.
42 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
43 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
44 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
45 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
47 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
48 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
49 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
55 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
56 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
57 Others interested in improving the state of free and open debug and testing technology
58 are welcome to participate.
60 Other developers have contributed support for additional targets and flashes as well
61 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
65 @cindex building openocd
67 You can download the current SVN version with SVN client of your choice from the
68 following repositories:
70 (@uref{svn://svn.berlios.de/openocd/trunk}
74 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
76 Using the SVN command line client, you could use the following command to fetch the
77 latest version (make sure there is no (non-svn) directory called "openocd" in the
81 svn checkout svn://svn.berlios.de/openocd/trunk
84 Building the OpenOCD requires a recent version of the GNU autotools.
85 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
86 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
87 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
88 paths, resulting in obscure dependency errors (This is an observation I've gathered
89 from the logs of one user - correct me if I'm wrong).
91 You further need the appropriate driver files, if you want to build support for
92 a FTDI FT2232 based interface:
94 @item @b{ftdi2232} libftdi ((@uref{http://www.intra2net.com/opensource/ftdi/})
95 @item @b{ftd2xx} libftd2xx ((@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
96 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
97 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
100 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
101 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
103 In general, the D2XX driver provides superior performance (several times as fast),
104 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
105 a kernel module, only a user space library.
107 To build OpenOCD (on both Linux and Cygwin), use the following commands:
111 Bootstrap generates the configure script, and prepares building on your system.
115 Configure generates the Makefiles used to build OpenOCD
119 Make builds the OpenOCD, and places the final executable in ./src/
121 The configure script takes several options, specifying which JTAG interfaces
128 --enable-parport_ppdev
130 --enable-amtjtagaccel
132 --enable-ft2232_ftd2xx
133 @footnote{Using the latest D2XX drivers from FTDI and following their installation
134 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
137 --enable-ft2232_libftdi
139 --with-ftd2xx=/path/to/d2xx/
142 If you want to access the parallel port using the PPDEV interface you have to specify
143 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
144 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
145 (see (@uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
147 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
148 absolute path containing no spaces.
150 Linux users should copy the various parts of the D2XX package to the appropriate
151 locations, i.e. /usr/include, /usr/lib.
155 @cindex running openocd
156 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
157 Run with @option{--help} or @option{-h} to view the available command line arguments.
159 It reads its configuration by default from the file openocd.cfg located in the current
160 working directory. This may be overwritten with the @option{-f <configfile>} command line
163 To enable debug output (when reporting problems or working on OpenOCD itself), use
164 the @option{-d} command line switch. This sets the debug_level to "3", outputting
165 the most information, including debug messages. The default setting is "2", outputting
166 only informational messages, warnings and errors. You can also change this setting
167 from within a telnet or gdb session (@option{debug_level <n>}).
169 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
172 @chapter Configuration
173 @cindex configuration
174 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
175 by default from the file openocd.cfg in the current directory. A different configuration
176 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
178 The configuration file is used to specify on which ports the daemon listens for new
179 connections, the JTAG interface used to connect to the target, the layout of the JTAG
180 chain, the targets that should be debugged, and connected flashes.
182 @section Daemon configuration
185 @item @b{telnet_port} <@var{number}>
187 Port on which to listen for incoming telnet connections
188 @item @b{gdb_port} <@var{number}>
190 First port on which to listen for incoming GDB connections. The GDB port for the
191 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
192 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
193 @cindex daemon_startup
194 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
195 if it should just attach to the target.
198 @section JTAG interface configuration
201 @item @b{interface} <@var{name}>
203 Use the interface driver <@var{name}> to connect to the target. Currently supported
207 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
211 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
216 FTDI FT2232 based devices using either the open-source libftdi or the binary only
217 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
218 platform. The libftdi uses libusb, and should be portable to all systems that provide
223 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
228 @item @b{jtag_speed} <@var{number}>
230 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
231 speed. The actual effect of this option depends on the JTAG interface used.
233 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
235 The configuration of the reset signals available on the JTAG interface AND the target.
236 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
237 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
238 @samp{srst_only} or @samp{trst_and_srst}.
239 [@var{combination}] is an optional value specifying broken reset signal implementations.
240 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
241 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
242 that the system is reset together with the test logic (only hypothetical, I haven't
243 seen hardware with such a bug, and can be worked around).
245 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
246 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
247 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
248 (default) and @samp{srst_push_pull} for the system reset. These values only affect
249 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
251 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
253 Describes the devices that form the JTAG daisy chain, with the first device being
254 the one closest to TDO. The parameters are the length of the instruction register
255 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
256 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
257 The IDCODE instruction will in future be used to query devices for their JTAG
258 identification code. This line is the same for all ARM7 and ARM9 devices.
259 Other devices, like CPLDs, require different parameters. An example configuration
260 line for a Xilinx XC9500 CPLD would look like this:
262 jtag_device 8 0x01 0x0e3 0xfe
264 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
265 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
266 The IDCODE instruction is 0xfe.
268 @item @b{jtag_nsrst_delay} <@var{ms}>
269 @cindex jtag_nsrst_delay
270 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
271 starting new JTAG operations.
272 @item @b{jtag_ntrst_delay} <@var{ms}>
273 @cindex jtag_ntrst_delay
274 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
275 starting new JTAG operations.
277 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
278 or on-chip features) keep a reset line asserted for some time after the external reset
282 @section parport options
285 @item @b{parport_port} <@var{number}>
287 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
288 the @file{/dev/parport} device
290 When using PPDEV to access the parallel port, use the number of the parallel port:
291 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
292 you may encounter a problem.
293 @item @b{parport_cable} <@var{name}>
294 @cindex parport_cable
295 The layout of the parallel port cable used to connect to the target.
296 Currently supported cables are
300 Original Wiggler layout, also supported by several clones, such
301 as the Olimex ARM-JTAG
302 @item old_amt_wiggler
303 @cindex old_amt_wiggler
304 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
305 version available from the website uses the original Wiggler layout ('@var{wiggler}')
308 Describes the connection of the Amontec Chameleon's CPLD when operated in
309 configuration mode. This is only used to program the Chameleon itself, not
313 Xilinx Parallel cable III.
316 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
317 This is also the layout used by the HollyGates design
318 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
323 @item @b{parport_write_on_exit} <@var{on|off}>
324 @cindex parport_write_on_exit
325 This will configure the parallel driver to write a known value to the parallel
326 interface on exiting openocd
329 @section amt_jtagaccel options
331 @item @b{parport_port} <@var{number}>
333 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
334 @file{/dev/parport} device
336 @section ft2232 options
339 @item @b{ft2232_device_desc} <@var{description}>
340 @cindex ft2232_device_desc
341 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
342 default value is used. This setting is only valid if compiled with FTD2XX support.
343 @item @b{ft2232_layout} <@var{name}>
344 @cindex ft2232_layout
345 The layout of the FT2232 GPIO signals used to control output-enables and reset
346 signals. Valid layouts are
349 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
351 Amontec JTAGkey and JTAGkey-tiny
357 American Microsystems M5960
359 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
360 SRST signals on external connector
364 Hitex STM32 Performance Stick
367 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
368 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
369 default values are used. This command is not available on Windows.
370 @item @b{ft2232_latency} <@var{ms}>
371 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
372 ft2232_read() fails to return the expected number of bytes. This can be caused by
373 USB communication delays and has proved hard to reproduce and debug. Setting the
374 FT2232 latency timer to a larger value increases delays for short USB packages but it
375 also reduces the risk of timeouts before receiving the expected number of bytes.
376 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
379 @section ep93xx options
380 @cindex ep93xx options
381 Currently, there are no options available for the ep93xx interface.
384 @section Target configuration
387 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
390 Defines a target that should be debugged. Currently supported types are:
403 If you want to use a target board that is not on this list, see Adding a new
406 Endianess may be @option{little} or @option{big}.
408 The reset_mode specifies what should happen to the target when a reset occurs:
412 Immediately request a target halt after reset. This allows targets to be debugged
413 from the very first instruction. This is only possible with targets and JTAG
414 interfaces that correctly implement the reset signals.
417 Similar to @option{reset_halt}, but executes the script file defined to handle the
418 'reset' event for the target. Like @option{reset_halt} this only works with
419 correct reset implementations.
422 Simply let the target run after a reset.
425 Let the target run for some time (default: 1s), and then request halt.
428 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
429 to run for some time, then halted, and the @option{reset} event script is executed.
432 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
433 completely independent (like the LPC2000 series), or where the JTAG interface is
434 unavailable for some time during startup (like the STR7 series), you can't use
435 @option{reset_halt} or @option{reset_init}.
437 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
438 @cindex target_script
439 Event is either @var{reset} or @var{post_halt} or @var{pre_resume}.
440 TODO: describe exact semantic of events
441 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
442 @cindex run_and_halt_time
443 The amount of time the debugger should wait after releasing reset before it asserts
444 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
446 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
447 <@var{backup}|@var{nobackup}>
449 Specifies a working area for the debugger to use. This may be used to speed-up
450 downloads to target memory and flash operations, or to perform otherwise unavailable
451 operations (some coprocessor operations on ARM7/9 systems, for example). The last
452 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
453 a working_area that doesn't need to be backed up, as that slows down operation.
456 @subsection arm7tdmi options
457 @cindex arm7tdmi options
458 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
459 The arm7tdmi target definition requires at least one additional argument, specifying
460 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
461 The optional [@var{variant}] parameter has been removed in recent versions.
462 The correct feature set is determined at runtime.
464 @subsection arm720t options
465 @cindex arm720t options
466 ARM720t options are similar to ARM7TDMI options.
468 @subsection arm9tdmi options
469 @cindex arm9tdmi options
470 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
471 @option{arm920t}, @option{arm922t} and @option{arm940t}.
472 This enables the hardware single-stepping support found on these cores.
474 @subsection arm920t options
475 @cindex arm920t options
476 ARM920t options are similar to ARM9TDMI options.
478 @subsection arm966e options
479 @cindex arm966e options
480 ARM966e options are similar to ARM9TDMI options.
482 @subsection xscale options
483 @cindex xscale options
484 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
485 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
487 @section Flash configuration
488 @cindex Flash configuration
491 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
492 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
494 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
495 and <@var{bus_width}> bytes using the selected flash <driver>.
497 @item @b{flash autoerase} <@option{on}|@option{off}>
498 @cindex flash autoerase
499 auto erase flash banks prior to writing. Currently only works when using
500 @option{flash write_image} command. Default is @option{off}.
503 @subsection lpc2000 options
504 @cindex lpc2000 options
506 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
507 <@var{clock}> [@var{calc_checksum}]
508 LPC flashes don't require the chip and bus width to be specified. Additional
509 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
510 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
511 of the target this flash belongs to (first is 0), the frequency at which the core
512 is currently running (in kHz - must be an integral number), and the optional keyword
513 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
516 @subsection cfi options
519 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
521 CFI flashes require the number of the target they're connected to as an additional
522 argument. The CFI driver makes use of a working area (specified for the target)
523 to significantly speed up operation.
525 @subsection at91sam7 options
526 @cindex at91sam7 options
528 @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
529 AT91SAM7 flashes only require the target#, all other values are looked up after
530 reading the chip-id and type.
532 @subsection str7 options
535 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
536 variant can be either STR71x, STR73x or STR75x.
538 @subsection str9 options
541 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
542 The str9 needs the flash controller to be configured prior to Flash programming, eg.
544 str9x flash_config 0 4 2 0 0x80000
546 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
548 @subsection str9 options (str9xpec driver)
550 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
551 Before using the flash commands the turbo mode will need enabling using str9xpec
552 @option{enable_turbo} <@var{num>.}
554 Only use this driver for locking/unlocking the device or configuring the option bytes.
555 Use the standard str9 driver for programming.
557 @subsection stellaris (LM3Sxxx) options
558 @cindex stellaris (LM3Sxxx) options
560 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
561 stellaris flash plugin only require the target#.
563 @subsection stm32x options
564 @cindex stm32x options
566 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
567 stm32x flash plugin only require the target#.
573 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
574 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
575 is available from both the telnet interface and a GDB session. To issue commands to the
576 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
577 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
583 @item @b{sleep} <@var{msec}>
585 Wait for n milliseconds before resuming. Useful in connection with script files
586 (@var{script} command and @var{target_script} configuration).
590 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
592 @item @b{debug_level} [@var{n}]
594 Display or adjust debug level to n<0-3>
596 @item @b{log_output} <@var{file}>
598 Redirect logging to <file> (default: stderr)
600 @item @b{script} <@var{file}>
602 Execute commands from <file>
606 @subsection Target state handling
608 @item @b{poll} [@option{on}|@option{off}]
610 Poll the target for its current state. If the target is in debug mode, architecture
611 specific information about the current state are printed. An optional parameter
612 allows continuous polling to be enabled and disabled.
616 Send a halt request to the target. The debugger signals the debug request,
617 and waits for the target to enter debug mode.
619 @item @b{resume} [@var{address}]
621 Resume the target at its current code position, or at an optional address.
623 @item @b{step} [@var{address}]
625 Single-step the target at its current code position, or at an optional address.
627 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
628 |@option{run_and_init}]
630 Do a hard-reset. The optional parameter specifies what should happen after the reset.
631 This optional parameter overwrites the setting specified in the configuration file,
632 making the new behaviour the default for the @option{reset} command.
639 Immediately halt the target (works only with certain configurations).
642 Immediately halt the target, and execute the reset script (works only with certain
645 @cindex reset run_and_halt
646 Let the target run for a certain amount of time, then request a halt.
648 @cindex reset run_and_init
649 Let the target run for a certain amount of time, then request a halt. Execute the
650 reset script once the target entered debug mode.
654 @subsection Memory access commands
655 These commands allow accesses of a specific size to the memory system:
657 @item @b{mdw} <@var{addr}> [@var{count}]
660 @item @b{mdh} <@var{addr}> [@var{count}]
662 display memory half-words
663 @item @b{mdb} <@var{addr}> [@var{count}]
666 @item @b{mww} <@var{addr}> <@var{value}>
669 @item @b{mwh} <@var{addr}> <@var{value}>
671 write memory half-word
672 @item @b{mwb} <@var{addr}> <@var{value}>
676 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
678 Load image <@var{file}> to target memory at <@var{address}>
679 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
681 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
682 (binary) <@var{file}>.
683 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
685 Verify <@var{file}> to target memory starting at <@var{address}>.
686 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
688 Load binary <@var{file}> to target memory at <@var{address}>
689 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
691 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
692 (binary) <@var{file}>.
695 @subsection Flash commands
696 @cindex Flash commands
698 @item @b{flash banks}
700 List configured flash banks
701 @item @b{flash info} <@var{num}>
703 Print info about flash bank <@option{num}>
704 @item @b{flash probe} <@var{num}>
706 Identify the flash, or validate the parameters of the configured flash. Operation
707 depends on the flash type.
708 @item @b{flash erase_check} <@var{num}>
709 @cindex flash erase_check
710 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
711 updates the erase state information displayed by @option{flash info}. That means you have
712 to issue an @option{erase_check} command after erasing or programming the device to get
714 @item @b{flash protect_check} <@var{num}>
715 @cindex flash protect_check
716 Check protection state of sectors in flash bank <num>.
717 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}>
719 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
720 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
721 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
723 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
725 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
726 bytes from the beginning of the bank. This command was replaced by the new command
727 @option{flash write_binary} using the same syntax.
728 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
729 @cindex flash write_binary
730 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
731 <@option{offset}> bytes from the beginning of the bank.
732 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
733 @cindex flash write_image
734 Write the image <@var{file}> to the current target's flash bank(s). A relocation
735 [@var{offset}] can be specified and the file [@var{type}] can be specified
736 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
737 (ELF file) or @option{s19} (Motorola s19).
738 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
739 @cindex flash protect
740 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
741 <@var{last}> of @option{flash bank} <@var{num}>.
742 @item @b{flash auto_erase} <@var{on}|@var{off}>
743 @cindex flash auto_erase
744 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
745 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
749 @section Target Specific Commands
750 @cindex Target Specific Commands
752 @subsection AT91SAM7 specific commands
753 @cindex AT91SAM7 specific commands
754 The flash configuration is deduced from the chip identification register. The flash
755 controller handles erases automatically on a page (128/265 byte) basis so erase is
756 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
757 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
758 that can be erased separatly.Only an EraseAll command is supported by the controller
759 for each flash plane and this is called with
761 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
762 bulk erase flash planes first_plane to last_plane.
763 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
764 @cindex at91sam7 gpnvm
765 set or clear a gpnvm bit for the processor
768 @subsection STR9 specific commands
769 @cindex STR9 specific commands
770 These are flash specific commands when using the str9xpec driver.
772 @item @b{str9xpec enable_turbo} <@var{num}>
773 @cindex str9xpec enable_turbo
774 enable turbo mode, simply this will remove the str9 from the chain and talk
775 directly to the embedded flash controller.
776 @item @b{str9xpec disable_turbo} <@var{num}>
777 @cindex str9xpec disable_turbo
778 restore the str9 into jtag chain.
779 @item @b{str9xpec lock} <@var{num}>
780 @cindex str9xpec lock
781 lock str9 device. The str9 will only respond to an unlock command that will
783 @item @b{str9xpec unlock} <@var{num}>
784 @cindex str9xpec unlock
786 @item @b{str9xpec options_read} <@var{num}>
787 @cindex str9xpec options_read
788 read str9 option bytes.
789 @item @b{str9xpec options_write} <@var{num}>
790 @cindex str9xpec options_write
791 write str9 option bytes.
794 @subsection STR9 configuration
795 @cindex STR9 configuration
797 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
798 <@var{BBADR}> <@var{NBBADR}>
799 @cindex str9x flash_config
800 Configure str9 flash controller.
802 eg. str9x flash_config 0 4 2 0 0x80000
804 BBSR - Boot Bank Size register
805 NBBSR - Non Boot Bank Size register
806 BBADR - Boot Bank Start Address register
807 NBBADR - Boot Bank Start Address register
811 @subsection STR9 option byte configuration
812 @cindex STR9 option byte configuration
814 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
815 @cindex str9xpec options_cmap
816 configure str9 boot bank.
817 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
818 @cindex str9xpec options_lvdthd
819 configure str9 lvd threshold.
820 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
821 @cindex str9xpec options_lvdsel
822 configure str9 lvd source.
823 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
824 @cindex str9xpec options_lvdwarn
825 configure str9 lvd reset warning source.
828 @subsection STM32x specific commands
829 @cindex STM32x specific commands
831 These are flash specific commands when using the stm32x driver.
833 @item @b{stm32x lock} <@var{num}>
836 @item @b{stm32x unlock} <@var{num}>
837 @cindex stm32x unlock
839 @item @b{stm32x options_read} <@var{num}>
840 @cindex stm32x options_read
841 read stm32 option bytes.
842 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
843 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
844 @cindex stm32x options_write
845 write stm32 option bytes.
846 @item @b{stm32x mass_erase} <@var{num}>
847 @cindex stm32x mass_erase
848 mass erase flash memory.
852 @section Arcitecture Specific Commands
853 @cindex Arcitecture Specific Commands
855 @subsection ARMV4/5 specific commands
856 @cindex ARMV4/5 specific commands
858 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
859 or Intel XScale (XScale isn't supported yet).
861 @item @b{armv4_5 reg}
863 Display a list of all banked core registers, fetching the current value from every
864 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
866 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
867 @cindex armv4_5 core_mode
868 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
869 The target is resumed in the currently set @option{core_mode}.
872 @subsection ARM7/9 specific commands
873 @cindex ARM7/9 specific commands
875 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
876 ARM920t or ARM926EJ-S.
878 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
879 @cindex arm7_9 sw_bkpts
880 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
881 one of the watchpoint registers to implement software breakpoints. Disabling
882 SW Bkpts frees that register again.
883 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
884 @cindex arm7_9 force_hw_bkpts
885 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
886 breakpoints are turned into hardware breakpoints.
887 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
889 Enable use of the DBGRQ bit to force entry into debug mode. This should be
890 safe for all but ARM7TDMI--S cores (like Philips LPC).
891 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
892 @cindex arm7_9 fast_writes [DEPRECATED]
893 See @option{arm7_9 fast_memory_access} instead.
894 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
895 @cindex arm7_9 fast_memory_access
896 Allow the OpenOCD to read and write memory without checking completion of
897 the operation. This provides a huge speed increase, especially with USB JTAG
898 cables (FT2232), but might be unsafe if used with targets running at a very low
899 speed, like the 32kHz startup clock of an AT91RM9200.
900 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
901 @cindex arm7_9 dcc_downloads
902 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
903 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
904 unsafe, especially with targets running at a very low speed. This command was introduced
905 with OpenOCD rev. 60.
908 @subsection ARM920T specific commands
909 @cindex ARM920T specific commands
912 @item @b{arm920t cache_info}
913 @cindex arm920t cache_info
914 Print information about the caches found. This allows you to see if your target
915 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
916 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
917 @cindex arm920t md<bhw>_phys
918 Display memory at physical address addr.
919 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
920 @cindex arm920t mw<bhw>_phys
921 Write memory at physical address addr.
922 @item @b{arm920t read_cache} <@var{filename}>
923 @cindex arm920t read_cache
924 Dump the content of ICache and DCache to a file.
925 @item @b{arm920t read_mmu} <@var{filename}>
926 @cindex arm920t read_mmu
927 Dump the content of the ITLB and DTLB to a file.
928 @item @b{arm920t virt2phys} <@var{VA}>
929 @cindex arm920t virt2phys
930 Translate a virtual address to a physical address.
934 @section Debug commands
935 @cindex Debug commands
936 The following commands give direct access to the core, and are most likely
937 only useful while debugging the OpenOCD.
939 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
940 @cindex arm7_9 write_xpsr
941 Immediately write either the current program status register (CPSR) or the saved
942 program status register (SPSR), without changing the register cache (as displayed
943 by the @option{reg} and @option{armv4_5 reg} commands).
944 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
945 <@var{0=cpsr},@var{1=spsr}>
946 @cindex arm7_9 write_xpsr_im8
947 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
948 operation (similar to @option{write_xpsr}).
949 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
950 @cindex arm7_9 write_core_reg
951 Write a core register, without changing the register cache (as displayed by the
952 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
953 encoding of the [M4:M0] bits of the PSR.
957 @section JTAG commands
958 @cindex JTAG commands
962 Print current scan chain configuration.
965 Toggle reset lines <@var{trst}> <@var{srst}>.
966 @item @b{endstate} <@var{tap_state}>
968 Finish JTAG operations in <@var{tap_state}>.
969 @item @b{runtest} <@var{num_cycles}>
971 Move to Run-Test/Idle, and execute <@var{num_cycles}>
972 @item @b{statemove} [@var{tap_state}]
974 Move to current endstate or [@var{tap_state}]
977 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
980 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
981 @item @b{verify_ircapture}
982 @cindex verify_ircapture
983 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
986 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
989 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
993 @chapter Sample Scripts
996 This page will collect some script examples for different CPUs.
998 The configuration script can be divided in the following section:
1000 @item deamon configuration
1002 @item jtag scan chain
1003 @item target configuration
1004 @item flash configuration
1007 Detailed information about each section can be found at OpenOCD configuration
1009 @section OMAP5912 Flash Debug
1010 @cindex OMAP5912 Flash Debug
1011 The following two scripts was used with an wiggler PP and and a TI OMAP5912
1012 dual core processor (@uref{http://www.ti.com}) on a OMAP5912 OSK board
1013 @uref{(http://www.spectrumdigital.com}).
1014 @subsection Openocd config
1016 #daemon configuration
1023 parport_cable wiggler
1026 #use combined on interfaces or targets that can't set TRST/SRST separately
1027 reset_config trst_and_srst
1030 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1031 jtag_device 38 0x0 0x0 0x0
1032 jtag_device 4 0x1 0x0 0xe
1033 jtag_device 8 0x0 0x0 0x0
1035 #target configuration
1036 daemon_startup reset
1038 #target <type> <endianness> <reset mode> <chainpos> <variant>
1039 target arm926ejs little run_and_init 1 arm926ejs
1040 target_script 0 reset omap5912_osk.init
1041 run_and_halt_time 0 30
1043 # omap5912 lcd frame buffer as working area
1044 working_area 0 0x20000000 0x3e800 nobackup
1046 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1047 flash bank cfi 0x00000000 0x1000000 2 2 0
1050 @subsection Openocd init
1062 mww 0xfffec808 0x000000f5
1063 mww 0xfffec808 0x000000a0
1065 mww 0xfffeb048 0x0000aaaa
1067 mww 0xfffeb048 0x00005555
1076 @section STR71x Script
1077 @cindex STR71x Script
1078 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1080 #daemon configuration
1086 ft2232_device_desc "Amontec JTAGkey A"
1087 ft2232_layout jtagkey
1088 ft2232_vid_pid 0x0403 0xcff8
1091 #use combined on interfaces or targets that can't set TRST/SRST separately
1092 reset_config trst_and_srst srst_pulls_trst
1095 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1096 jtag_device 4 0x1 0xf 0xe
1098 #target configuration
1099 daemon_startup reset
1101 #target <type> <startup mode>
1102 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1103 target arm7tdmi little run_and_halt 0 arm7tdmi
1104 run_and_halt_time 0 30
1106 working_area 0 0x2000C000 0x4000 nobackup
1108 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1109 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1112 @section STR750 Script
1113 @cindex STR750 Script
1114 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1116 #daemon configuration
1122 ft2232_device_desc "Amontec JTAGkey A"
1123 ft2232_layout jtagkey
1124 ft2232_vid_pid 0x0403 0xcff8
1127 #use combined on interfaces or targets that can't set TRST/SRST separately
1128 #reset_config trst_and_srst srst_pulls_trst
1129 reset_config trst_and_srst srst_pulls_trst
1132 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1133 jtag_device 4 0x1 0xf 0xe
1135 #jtag nTRST and nSRST delay
1136 jtag_nsrst_delay 500
1137 jtag_ntrst_delay 500
1139 #target configuration
1140 daemon_startup reset
1142 #target <type> <startup mode>
1143 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1144 target arm7tdmi little run_and_halt 0 arm7tdmi
1145 run_and_halt_time 0 30
1147 working_area 0 0x40000000 0x4000 nobackup
1149 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1150 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1153 @section STR912 Script
1154 @cindex STR912 Script
1155 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1157 #daemon configuration
1163 ft2232_device_desc "Amontec JTAGkey A"
1164 ft2232_layout jtagkey
1167 #use combined on interfaces or targets that can't set TRST/SRST separately
1168 reset_config trst_and_srst
1171 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1172 jtag_device 8 0x1 0x1 0xfe
1173 jtag_device 4 0x1 0xf 0xe
1174 jtag_device 5 0x1 0x1 0x1e
1176 #target configuration
1177 daemon_startup reset
1179 #target <type> <startup mode>
1180 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1181 target arm966e little reset_halt 1 arm966e
1182 run_and_halt_time 0 30
1184 working_area 0 0x50000000 16384 nobackup
1186 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1187 flash bank str9x 0x00000000 0x00080000 0 0 0
1190 @section STR912 comstick
1191 @cindex STR912 comstick Script
1192 The following script was used with a Hitex STR9 Comstick:
1194 #daemon configuration
1200 ft2232_device_desc "STR9-comStick A"
1201 ft2232_layout comstick
1204 jtag_nsrst_delay 100
1205 jtag_ntrst_delay 100
1207 #use combined on interfaces or targets that can't set TRST/SRST separately
1208 reset_config trst_and_srst
1211 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1212 jtag_device 8 0x1 0x1 0xfe
1213 jtag_device 4 0x1 0xf 0xe
1214 jtag_device 5 0x1 0x1 0x1e
1216 #target configuration
1217 daemon_startup reset
1219 #target <type> <startup mode>
1220 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1221 target arm966e little reset_halt 1 arm966e
1222 run_and_halt_time 0 30
1224 working_area 0 0x50000000 16384 nobackup
1226 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1227 flash bank str9x 0x00000000 0x00080000 0 0 0
1230 @section STM32x Script
1231 @cindex STM32x Script
1232 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1234 #daemon configuration
1240 ft2232_device_desc "Amontec JTAGkey A"
1241 ft2232_layout jtagkey
1244 jtag_nsrst_delay 100
1245 jtag_ntrst_delay 100
1247 #use combined on interfaces or targets that can't set TRST/SRST separately
1248 reset_config trst_and_srst
1251 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1252 jtag_device 4 0x1 0xf 0xe
1253 jtag_device 5 0x1 0x1 0x1e
1255 #target configuration
1256 daemon_startup reset
1258 #target <type> <startup mode>
1259 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1260 target cortex_m3 little run_and_halt 0
1261 run_and_halt_time 0 30
1263 working_area 0 0x20000000 16384 nobackup
1265 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1266 flash bank stm32x 0x08000000 0x00010000 0 0 0
1269 @section STM32x Performance Stick
1270 @cindex STM32x Performance Stick Script
1271 The following script was used with the Hitex STM32 Performance Stick
1273 #daemon configuration
1279 ft2232_device_desc "STM32-PerformanceStick A"
1280 ft2232_layout stm32stick
1283 jtag_nsrst_delay 100
1284 jtag_ntrst_delay 100
1286 #use combined on interfaces or targets that can't set TRST/SRST separately
1287 reset_config trst_and_srst
1290 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1291 jtag_device 4 0x1 0xf 0xe
1292 jtag_device 5 0x1 0x1 0x1e
1293 jtag_device 4 0x1 0xf 0xe
1295 #target configuration
1296 daemon_startup reset
1298 #target <type> <startup mode>
1299 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1300 target cortex_m3 little run_and_halt 0
1301 run_and_halt_time 0 30
1303 working_area 0 0x20000000 16384 nobackup
1305 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1306 flash bank stm32x 0x08000000 0x00010000 0 0 0
1309 @section LPC2294 Script
1310 @cindex LPC2294 Script
1311 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1313 #daemon configuration
1319 ft2232_device_desc "Amontec JTAGkey A"
1320 ft2232_layout jtagkey
1321 ft2232_vid_pid 0x0403 0xcff8
1324 #use combined on interfaces or targets that can't set TRST/SRST separately
1325 reset_config trst_and_srst srst_pulls_trst
1328 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1329 jtag_device 4 0x1 0xf 0xe
1331 #target configuration
1332 daemon_startup reset
1334 #target <type> <startup mode>
1335 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1336 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1337 run_and_halt_time 0 30
1339 working_area 0 0x40000000 0x40000 nobackup
1341 #flash configuration
1342 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1345 @section AT91R40008 Script
1346 @cindex AT91R40008 Script
1347 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1349 #daemon configuration
1355 ft2232_device_desc "Amontec JTAGkey A"
1356 ft2232_layout jtagkey
1357 ft2232_vid_pid 0x0403 0xcff8
1359 jtag_nsrst_delay 200
1360 jtag_ntrst_delay 200
1362 #use combined on interfaces or targets that can't set TRST/SRST separately
1363 reset_config srst_only srst_pulls_trst
1366 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1367 jtag_device 4 0x1 0xf 0xe
1369 #target configuration
1370 daemon_startup reset
1372 #target <type> <startup mode>
1373 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1374 target arm7tdmi little run_and_halt 0 arm7tdmi
1375 run_and_halt_time 0 30
1378 @section LPC2129 Script
1379 @cindex LPC2129 Script
1380 The following script was used with an wiggler PP and a LPC-2129 cpu:
1382 #daemon configuration
1389 parport_cable wiggler
1392 #use combined on interfaces or targets that can't set TRST/SRST separately
1393 reset_config trst_and_srst srst_pulls_trst
1396 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1397 jtag_device 4 0x1 0xf 0xe
1399 #target configuration
1400 daemon_startup reset
1402 #target <type> <startup mode>
1403 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1404 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1405 run_and_halt_time 0 30
1407 working_area 0 0x00000000 0x400000 nobackup
1409 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1410 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1413 @section AT91SAM7s Script
1414 @cindex AT91SAM7s Script
1415 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1417 #daemon configuration
1423 ft2232_device_desc "Olimex OpenOCD JTAG A"
1424 ft2232_layout olimex-jtag
1425 ft2232_vid_pid 0x15BA 0x0003
1427 jtag_nsrst_delay 200
1428 jtag_ntrst_delay 200
1430 #use combined on interfaces or targets that can't set TRST/SRST separately
1431 reset_config srst_only srst_pulls_trst
1434 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1435 jtag_device 4 0x1 0xf 0xe
1437 #target configuration
1438 daemon_startup reset
1440 #target <type> <startup mode>
1441 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1442 target arm7tdmi little run_and_halt 0 arm7tdmi
1443 run_and_halt_time 0 30
1445 # flash-options AT91
1446 working_area 0 0x00200000 0x4000 nobackup
1447 flash bank at91sam7 0 0 0 0 0
1450 # erase command (telnet-interface) for complete flash:
1451 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1452 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1453 # set/clear NVM-Bits:
1454 # at91sam7 gpnvm <num> <bit> <set|clear>
1455 # disable locking from SAM-BA:
1456 # flash protect 0 0 1 off
1459 @section XSCALE IXP42x Script
1460 @cindex XSCALE IXP42x Script
1461 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1463 #daemon configuration
1469 ft2232_device_desc "Amontec JTAGkey A"
1470 ft2232_layout jtagkey
1471 ft2232_vid_pid 0x0403 0xcff8
1473 jtag_nsrst_delay 200
1474 jtag_ntrst_delay 200
1476 #use combined on interfaces or targets that can't set TRST/SRST separately
1477 reset_config srst_only srst_pulls_trst
1480 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1481 jtag_device 7 0x1 0x7f 0x7e
1483 #target configuration
1484 daemon_startup reset
1486 #target <type> <startup mode>
1487 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1488 target xscale big run_and_halt 0 IXP42x
1489 run_and_halt_time 0 30
1492 @section Cirrus Logic EP9301 Script
1493 @cindex Cirrus Logic EP9301 Script
1494 The following script was used with FT2232 based JTAG interfaces and a
1495 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1497 #daemon configuration
1505 #ft2232_device_desc "Olimex OpenOCD JTAG"
1506 #ft2232_layout olimex-jtag
1507 #ft2232_vid_pid 0x15ba 0x0003
1509 #Amontec JTAGkey (and JTAGkey-Tiny)
1510 #Serial is only necessary if more than one JTAGkey is connected
1511 ft2232_device_desc "Amontec JTAGkey A"
1512 #ft2232_serial AMTJKV31
1513 #ft2232_serial T1P3S2W8
1514 ft2232_layout jtagkey
1515 ft2232_vid_pid 0x0403 0xcff8
1517 #wiggler/parallel port interface
1520 #parport_cable wiggler
1523 reset_config trst_and_srst
1526 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1527 jtag_device 4 0x1 0xf 0xe
1529 jtag_nsrst_delay 100
1530 jtag_ntrst_delay 100
1532 #target configuration
1533 daemon_startup attach
1535 #target <type> <endianess> <reset mode>
1536 target arm920t little reset_halt 0
1537 working_area 0 0x80014000 0x1000 backup
1539 #flash configuration
1540 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1541 flash bank cfi 0x60000000 0x1000000 2 2 0
1544 @section Hilscher netX 100 / 500 Script
1545 @cindex Hilscher netX 100 / 500 Script
1546 The following script was used with an Amontec JTAGkey and a Hilscher
1549 #daemon configuration
1555 ft2232_device_desc "Amontec JTAGkey A"
1556 ft2232_layout jtagkey
1557 ft2232_vid_pid 0x0403 0xcff8
1560 #use combined on interfaces or targets that can't set TRST/SRST separately
1561 reset_config trst_and_srst
1564 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1565 jtag_device 4 0x1 0xf 0xe
1567 jtag_nsrst_delay 100
1568 jtag_ntrst_delay 100
1570 #target configuration
1571 daemon_startup reset
1573 #target <type> <endianness> <startup mode> <chainpos> <variant>
1574 target arm926ejs little run_and_halt 0 arm926ejs
1575 run_and_halt_time 0 500
1578 @section Marvell/Intel PXA270 Script
1579 @cindex Marvell/Intel PXA270 Script
1581 # config for Intel PXA270
1582 # not, as of 2007-06-22, openocd only works with the
1583 # libftd2xx library from ftdi. libftdi does not work.
1589 ft2232_layout olimex-jtag
1590 ft2232_vid_pid 0x15BA 0x0003
1591 ft2232_device_desc "Olimex OpenOCD JTAG"
1593 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1594 # the rest of the needed delays are built into the openocd program
1595 jtag_nsrst_delay 260
1596 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1597 # the rest of the needed delays are built into the openocd program
1600 #use combined on interfaces or targets that can't set TRST/SRST separately
1601 reset_config trst_and_srst separate
1604 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1605 jtag_device 7 0x1 0x7f 0x7e
1607 #target configuration
1608 daemon_startup reset
1610 target xscale little reset_halt 0 pxa27x
1612 # maps to PXA internal RAM. If you are using a PXA255
1613 # you must initialize SDRAM or leave this option off
1614 working_area 0 0x5c000000 0x10000 nobackup
1616 run_and_halt_time 0 30
1618 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1619 # works for P30 flash
1620 flash bank cfi 0x00000000 0x1000000 2 4 0
1627 @item OpenOCD complains about a missing cygwin1.dll
1629 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1630 claims to come with all the necessary dlls. When using Cygwin, try launching
1631 the OpenOCD from the Cygwin shell.
1633 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1634 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1635 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1637 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1638 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1639 software breakpoints consume one of the two available hardware breakpoints,
1640 and are therefor disabled by default. If your code is running from RAM, you
1641 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1642 your code resides in Flash, you can't use software breakpoints, but you can force
1643 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1645 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1646 and works sometimes fine.
1648 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1649 clock at the time you're programming the flash. If you've specified the crystal's
1650 frequency, make sure the PLL is disabled, if you've specified the full core speed
1651 (e.g. 60MHz), make sure the PLL is enabled.
1653 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1654 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1655 out while waiting for end of scan, rtck was disabled".
1657 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1658 settings in your PC Bios (ECP, EPP, and different versions of those).
1660 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1661 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1662 memory read caused data abort".
1664 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1665 beyond the last valid frame. It might be possible to prevent this by setting up
1666 a proper "initial" stack frame, if you happen to know what exactly has to
1667 be done, feel free to add this here.
1669 @item I get the following message in the OpenOCD console (or log file):
1670 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1672 This warning doesn't indicate any serious problem, as long as you don't want to
1673 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1674 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1675 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1676 independently. With this setup, it's not possible to halt the core right out of
1677 reset, everything else should work fine.
1679 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1680 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1681 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1682 quit with an error message. Is there a stability issue with OpenOCD?
1684 No, this is not a stability issue concering OpenOCD. Most users have solved
1685 this issue by simply using a self-powered USB Hub, which they connect their
1686 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1687 supply stable enough for the Amontec JTAGkey to be operated.
1689 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1690 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1691 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1692 What does that mean and what might be the reason for this?
1694 First of all, the reason might be the USB power supply. Try using a self-powered
1695 hub instead of a direct connection to your computer. Secondly, the error code 4
1696 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1697 Chip ran into some sort of error - this points us to a USB problem.
1699 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1700 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1701 What does that mean and what might be the reason for this?
1703 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1704 has closed the connection to OpenOCD. This might be a GDB issue.
1706 @item In the configuration file in the section where flash device configurations
1707 are described, there is a parameter for specifying the clock frequency for
1708 LPC2000 internal flash devices (e.g.
1709 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1710 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1711 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1712 Is it possible to specify real numbers for the clock frequency?
1714 No. The clock frequency specified here must be given as an integral number.
1715 However, this clock frequency is used by the In-Application-Programming (IAP)
1716 routines of the LPC2000 family only, which seems to be very tolerant concerning
1717 the given clock frequency, so a slight difference between the specified clock
1718 frequency and the actual clock frequency will not cause any trouble.
1720 @item Do I have to keep a specific order for the commands in the configuration file?
1722 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1723 listed for the JTAG scan chain must be given in the right order (jtag_device),
1724 with the device closest to the TDO-Pin being listed first. In general,
1725 whenever objects of the same type exist which require an index number, then
1726 these objects must be given in the right order (jtag_devices, targets and flash
1727 banks - a target references a jtag_device and a flash bank references a target).
1729 @item Sometimes my debugging session terminates with an error. When I look into the
1730 log file, I can see these error messages: Error: arm7_9_common.c:561
1731 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP