1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
116 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
117 A @dfn{TAP} is a ``Test Access Port'', a module which processes
118 special instructions and data. TAPs are daisy-chained within and
119 between chips and boards.
121 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
122 based, parallel port based, and other standalone boxes that run
123 OpenOCD internally. @xref{JTAG Hardware Dongles}.
125 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
126 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
127 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
128 debugged via the GDB protocol.
130 @b{Flash Programing:} Flash writing is supported for external CFI
131 compatible NOR flashes (Intel and AMD/Spansion command set) and several
132 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
133 STM32x). Preliminary support for various NAND flash controllers
134 (LPC3180, Orion, S3C24xx, more) controller is included.
136 @section OpenOCD Web Site
138 The OpenOCD web site provides the latest public news from the community:
140 @uref{http://openocd.berlios.de/web/}
142 @section Latest User's Guide:
144 The user's guide you are now reading may not be the latest one
145 available. A version for more recent code may be available.
146 Its HTML form is published irregularly at:
148 @uref{http://openocd.berlios.de/doc/html/index.html}
150 PDF form is likewise published at:
152 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
154 @section OpenOCD User's Forum
156 There is an OpenOCD forum (phpBB) hosted by SparkFun:
158 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
162 @chapter OpenOCD Developer Resources
165 If you are interested in improving the state of OpenOCD's debugging and
166 testing support, new contributions will be welcome. Motivated developers
167 can produce new target, flash or interface drivers, improve the
168 documentation, as well as more conventional bug fixes and enhancements.
170 The resources in this chapter are available for developers wishing to explore
171 or expand the OpenOCD source code.
173 @section OpenOCD GIT Repository
175 During the 0.3.x release cycle, OpenOCD switched from Subversion to
176 a GIT repository hosted at SourceForge. The repository URL is:
178 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
180 You may prefer to use a mirror and the HTTP protocol:
182 @uref{http://repo.or.cz/r/openocd.git}
184 With standard GIT tools, use @command{git clone} to initialize
185 a local repository, and @command{git pull} to update it.
186 There are also gitweb pages letting you browse the repository
187 with a web browser, or download arbitrary snapshots without
188 needing a GIT client:
190 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
192 @uref{http://repo.or.cz/w/openocd.git}
194 The @file{README} file contains the instructions for building the project
195 from the repository or a snapshot.
197 Developers that want to contribute patches to the OpenOCD system are
198 @b{strongly} encouraged to work against mainline.
199 Patches created against older versions may require additional
200 work from their submitter in order to be updated for newer releases.
202 @section Doxygen Developer Manual
204 During the 0.2.x release cycle, the OpenOCD project began
205 providing a Doxygen reference manual. This document contains more
206 technical information about the software internals, development
207 processes, and similar documentation:
209 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
211 This document is a work-in-progress, but contributions would be welcome
212 to fill in the gaps. All of the source files are provided in-tree,
213 listed in the Doxyfile configuration in the top of the source tree.
215 @section OpenOCD Developer Mailing List
217 The OpenOCD Developer Mailing List provides the primary means of
218 communication between developers:
220 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
222 Discuss and submit patches to this list.
223 The @file{PATCHES} file contains basic information about how
227 @node JTAG Hardware Dongles
228 @chapter JTAG Hardware Dongles
237 Defined: @b{dongle}: A small device that plugins into a computer and serves as
238 an adapter .... [snip]
240 In the OpenOCD case, this generally refers to @b{a small adapater} one
241 attaches to your computer via USB or the Parallel Printer Port. The
242 execption being the Zylin ZY1000 which is a small box you attach via
243 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
244 require any drivers to be installed on the developer PC. It also has
245 a built in web interface. It supports RTCK/RCLK or adaptive clocking
246 and has a built in relay to power cycle targets remotely.
249 @section Choosing a Dongle
251 There are several things you should keep in mind when choosing a dongle.
254 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
255 Does your dongle support it? You might need a level converter.
256 @item @b{Pinout} What pinout does your target board use?
257 Does your dongle support it? You may be able to use jumper
258 wires, or an "octopus" connector, to convert pinouts.
259 @item @b{Connection} Does your computer have the USB, printer, or
260 Ethernet port needed?
261 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
264 @section Stand alone Systems
266 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
267 dongle, but a standalone box. The ZY1000 has the advantage that it does
268 not require any drivers installed on the developer PC. It also has
269 a built in web interface. It supports RTCK/RCLK or adaptive clocking
270 and has a built in relay to power cycle targets remotely.
272 @section USB FT2232 Based
274 There are many USB JTAG dongles on the market, many of them are based
275 on a chip from ``Future Technology Devices International'' (FTDI)
276 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
277 See: @url{http://www.ftdichip.com} for more information.
278 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
279 chips are starting to become available in JTAG adapters.
283 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
285 @* See: @url{http://www.amontec.com/jtagkey.shtml}
287 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
289 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
291 @* See: @url{http://www.signalyzer.com}
292 @item @b{evb_lm3s811}
293 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
294 @item @b{luminary_icdi}
295 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
296 @item @b{olimex-jtag}
297 @* See: @url{http://www.olimex.com}
299 @* See: @url{http://www.tincantools.com}
300 @item @b{turtelizer2}
302 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
303 @url{http://www.ethernut.de}
305 @* Link: @url{http://www.hitex.com/index.php?id=383}
307 @* Link @url{http://www.hitex.com/stm32-stick}
308 @item @b{axm0432_jtag}
309 @* Axiom AXM-0432 Link @url{http://www.axman.com}
311 @* Link @url{http://www.hitex.com/index.php?id=cortino}
314 @section USB JLINK based
315 There are several OEM versions of the Segger @b{JLINK} adapter. It is
316 an example of a micro controller based JTAG adapter, it uses an
317 AT91SAM764 internally.
320 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
321 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
322 @item @b{SEGGER JLINK}
323 @* Link: @url{http://www.segger.com/jlink.html}
325 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
328 @section USB RLINK based
329 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
332 @item @b{Raisonance RLink}
333 @* Link: @url{http://www.raisonance.com/products/RLink.php}
334 @item @b{STM32 Primer}
335 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
336 @item @b{STM32 Primer2}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
343 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
345 @item @b{USB - Presto}
346 @* Link: @url{http://tools.asix.net/prg_presto.htm}
348 @item @b{Versaloon-Link}
349 @* Link: @url{http://www.simonqian.com/en/Versaloon}
351 @item @b{ARM-JTAG-EW}
352 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
355 @section IBM PC Parallel Printer Port Based
357 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
358 and the MacGraigor Wiggler. There are many clones and variations of
361 Note that parallel ports are becoming much less common, so if you
362 have the choice you should probably avoid these adapters in favor
367 @item @b{Wiggler} - There are many clones of this.
368 @* Link: @url{http://www.macraigor.com/wiggler.htm}
370 @item @b{DLC5} - From XILINX - There are many clones of this
371 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
372 produced, PDF schematics are easily found and it is easy to make.
374 @item @b{Amontec - JTAG Accelerator}
375 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
378 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
381 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
382 Improved parallel-port wiggler-style JTAG adapter}
384 @item @b{Wiggler_ntrst_inverted}
385 @* Yet another variation - See the source code, src/jtag/parport.c
387 @item @b{old_amt_wiggler}
388 @* Unknown - probably not on the market today
391 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
394 @* Link: @url{http://www.amontec.com/chameleon.shtml}
400 @* ispDownload from Lattice Semiconductor
401 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
404 @* From ST Microsystems;
405 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
406 FlashLINK JTAG programing cable for PSD and uPSD}
414 @* An EP93xx based Linux machine using the GPIO pins directly.
417 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
422 @chapter About JIM-Tcl
426 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
427 This programming language provides a simple and extensible
430 All commands presented in this Guide are extensions to JIM-Tcl.
431 You can use them as simple commands, without needing to learn
432 much of anything about Tcl.
433 Alternatively, can write Tcl programs with them.
435 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
438 @item @b{JIM vs. Tcl}
439 @* JIM-TCL is a stripped down version of the well known Tcl language,
440 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
441 fewer features. JIM-Tcl is a single .C file and a single .H file and
442 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
443 4.2 MB .zip file containing 1540 files.
445 @item @b{Missing Features}
446 @* Our practice has been: Add/clone the real Tcl feature if/when
447 needed. We welcome JIM Tcl improvements, not bloat.
450 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
451 command interpreter today is a mixture of (newer)
452 JIM-Tcl commands, and (older) the orginal command interpreter.
455 @* At the OpenOCD telnet command line (or via the GDB mon command) one
456 can type a Tcl for() loop, set variables, etc.
457 Some of the commands documented in this guide are implemented
458 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
460 @item @b{Historical Note}
461 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
463 @item @b{Need a crash course in Tcl?}
464 @*@xref{Tcl Crash Course}.
469 @cindex command line options
471 @cindex directory search
473 The @option{--help} option shows:
477 --help | -h display this help
478 --version | -v display OpenOCD version
479 --file | -f use configuration file <name>
480 --search | -s dir to search for config files and scripts
481 --debug | -d set debug level <0-3>
482 --log_output | -l redirect log output to file <name>
483 --command | -c run <command>
484 --pipe | -p use pipes when talking to gdb
487 By default OpenOCD reads the file configuration file @file{openocd.cfg}
488 in the current directory. To specify a different (or multiple)
489 configuration file, you can use the ``-f'' option. For example:
492 openocd -f config1.cfg -f config2.cfg -f config3.cfg
495 OpenOCD starts by processing the configuration commands provided
496 on the command line or in @file{openocd.cfg}.
497 @xref{Configuration Stage}.
498 At the end of the configuration stage it verifies the JTAG scan
499 chain defined using those commands; your configuration should
500 ensure that this always succeeds.
501 Normally, OpenOCD then starts running as a daemon.
502 Alternatively, commands may be used to terminate the configuration
503 stage early, perform work (such as updating some flash memory),
504 and then shut down without acting as a daemon.
506 Once OpenOCD starts running as a daemon, it waits for connections from
507 clients (Telnet, GDB, Other) and processes the commands issued through
510 If you are having problems, you can enable internal debug messages via
513 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
514 @option{-c} command line switch.
516 To enable debug output (when reporting problems or working on OpenOCD
517 itself), use the @option{-d} command line switch. This sets the
518 @option{debug_level} to "3", outputting the most information,
519 including debug messages. The default setting is "2", outputting only
520 informational messages, warnings and errors. You can also change this
521 setting from within a telnet or gdb session using @command{debug_level
522 <n>} (@pxref{debug_level}).
524 You can redirect all output from the daemon to a file using the
525 @option{-l <logfile>} switch.
527 Search paths for config/script files can be added to OpenOCD by using
528 the @option{-s <search>} switch. The current directory and the OpenOCD
529 target library is in the search path by default.
531 For details on the @option{-p} option. @xref{Connecting to GDB}.
533 Note! OpenOCD will launch the GDB & telnet server even if it can not
534 establish a connection with the target. In general, it is possible for
535 the JTAG controller to be unresponsive until the target is set up
536 correctly via e.g. GDB monitor commands in a GDB init script.
538 @node OpenOCD Project Setup
539 @chapter OpenOCD Project Setup
541 To use OpenOCD with your development projects, you need to do more than
542 just connecting the JTAG adapter hardware (dongle) to your development board
543 and then starting the OpenOCD server.
544 You also need to configure that server so that it knows
545 about that adapter and board, and helps your work.
547 @section Hooking up the JTAG Adapter
549 Today's most common case is a dongle with a JTAG cable on one side
550 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
551 and a USB cable on the other.
552 Instead of USB, some cables use Ethernet;
553 older ones may use a PC parallel port, or even a serial port.
556 @item @emph{Start with power to your target board turned off},
557 and nothing connected to your JTAG adapter.
558 If you're particularly paranoid, unplug power to the board.
559 It's important to have the ground signal properly set up,
560 unless you are using a JTAG adapter which provides
561 galvanic isolation between the target board and the
564 @item @emph{Be sure it's the right kind of JTAG connector.}
565 If your dongle has a 20-pin ARM connector, you need some kind
566 of adapter (or octopus, see below) to hook it up to
567 boards using 14-pin or 10-pin connectors ... or to 20-pin
568 connectors which don't use ARM's pinout.
570 In the same vein, make sure the voltage levels are compatible.
571 Not all JTAG adapters have the level shifters needed to work
572 with 1.2 Volt boards.
574 @item @emph{Be certain the cable is properly oriented} or you might
575 damage your board. In most cases there are only two possible
576 ways to connect the cable.
577 Connect the JTAG cable from your adapter to the board.
578 Be sure it's firmly connected.
580 In the best case, the connector is keyed to physically
581 prevent you from inserting it wrong.
582 This is most often done using a slot on the board's male connector
583 housing, which must match a key on the JTAG cable's female connector.
584 If there's no housing, then you must look carefully and
585 make sure pin 1 on the cable hooks up to pin 1 on the board.
586 Ribbon cables are frequently all grey except for a wire on one
587 edge, which is red. The red wire is pin 1.
589 Sometimes dongles provide cables where one end is an ``octopus'' of
590 color coded single-wire connectors, instead of a connector block.
591 These are great when converting from one JTAG pinout to another,
592 but are tedious to set up.
593 Use these with connector pinout diagrams to help you match up the
594 adapter signals to the right board pins.
596 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
597 A USB, parallel, or serial port connector will go to the host which
598 you are using to run OpenOCD.
599 For Ethernet, consult the documentation and your network administrator.
601 For USB based JTAG adapters you have an easy sanity check at this point:
602 does the host operating system see the JTAG adapter?
604 @item @emph{Connect the adapter's power supply, if needed.}
605 This step is primarily for non-USB adapters,
606 but sometimes USB adapters need extra power.
608 @item @emph{Power up the target board.}
609 Unless you just let the magic smoke escape,
610 you're now ready to set up the OpenOCD server
611 so you can use JTAG to work with that board.
615 Talk with the OpenOCD server using
616 telnet (@code{telnet localhost 4444} on many systems) or GDB.
617 @xref{GDB and OpenOCD}.
619 @section Project Directory
621 There are many ways you can configure OpenOCD and start it up.
623 A simple way to organize them all involves keeping a
624 single directory for your work with a given board.
625 When you start OpenOCD from that directory,
626 it searches there first for configuration files, scripts,
627 and for code you upload to the target board.
628 It is also the natural place to write files,
629 such as log files and data you download from the board.
631 @section Configuration Basics
633 There are two basic ways of configuring OpenOCD, and
634 a variety of ways you can mix them.
635 Think of the difference as just being how you start the server:
638 @item Many @option{-f file} or @option{-c command} options on the command line
639 @item No options, but a @dfn{user config file}
640 in the current directory named @file{openocd.cfg}
643 Here is an example @file{openocd.cfg} file for a setup
644 using a Signalyzer FT2232-based JTAG adapter to talk to
645 a board with an Atmel AT91SAM7X256 microcontroller:
648 source [find interface/signalyzer.cfg]
650 # GDB can also flash my flash!
651 gdb_memory_map enable
652 gdb_flash_program enable
654 source [find target/sam7x256.cfg]
657 Here is the command line equivalent of that configuration:
660 openocd -f interface/signalyzer.cfg \
661 -c "gdb_memory_map enable" \
662 -c "gdb_flash_program enable" \
663 -f target/sam7x256.cfg
666 You could wrap such long command lines in shell scripts,
667 each supporting a different development task.
668 One might re-flash the board with a specific firmware version.
669 Another might set up a particular debugging or run-time environment.
672 At this writing (October 2009) the command line method has
673 problems with how it treats variables.
674 For example, after @option{-c "set VAR value"}, or doing the
675 same in a script, the variable @var{VAR} will have no value
676 that can be tested in a later script.
679 Here we will focus on the simpler solution: one user config
680 file, including basic configuration plus any TCL procedures
681 to simplify your work.
683 @section User Config Files
684 @cindex config file, user
685 @cindex user config file
686 @cindex config file, overview
688 A user configuration file ties together all the parts of a project
690 One of the following will match your situation best:
693 @item Ideally almost everything comes from configuration files
694 provided by someone else.
695 For example, OpenOCD distributes a @file{scripts} directory
696 (probably in @file{/usr/share/openocd/scripts} on Linux).
697 Board and tool vendors can provide these too, as can individual
698 user sites; the @option{-s} command line option lets you say
699 where to find these files. (@xref{Running}.)
700 The AT91SAM7X256 example above works this way.
702 Three main types of non-user configuration file each have their
703 own subdirectory in the @file{scripts} directory:
706 @item @b{interface} -- one for each kind of JTAG adapter/dongle
707 @item @b{board} -- one for each different board
708 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
711 Best case: include just two files, and they handle everything else.
712 The first is an interface config file.
713 The second is board-specific, and it sets up the JTAG TAPs and
714 their GDB targets (by deferring to some @file{target.cfg} file),
715 declares all flash memory, and leaves you nothing to do except
719 source [find interface/olimex-jtag-tiny.cfg]
720 source [find board/csb337.cfg]
723 Boards with a single microcontroller often won't need more
724 than the target config file, as in the AT91SAM7X256 example.
725 That's because there is no external memory (flash, DDR RAM), and
726 the board differences are encapsulated by application code.
728 @item You can often reuse some standard config files but
729 need to write a few new ones, probably a @file{board.cfg} file.
730 You will be using commands described later in this User's Guide,
731 and working with the guidelines in the next chapter.
733 For example, there may be configuration files for your JTAG adapter
734 and target chip, but you need a new board-specific config file
735 giving access to your particular flash chips.
736 Or you might need to write another target chip configuration file
737 for a new chip built around the Cortex M3 core.
740 When you write new configuration files, please submit
741 them for inclusion in the next OpenOCD release.
742 For example, a @file{board/newboard.cfg} file will help the
743 next users of that board, and a @file{target/newcpu.cfg}
744 will help support users of any board using that chip.
748 You may may need to write some C code.
749 It may be as simple as a supporting a new ft2232 or parport
750 based dongle; a bit more involved, like a NAND or NOR flash
751 controller driver; or a big piece of work like supporting
752 a new chip architecture.
755 Reuse the existing config files when you can.
756 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
757 You may find a board configuration that's a good example to follow.
759 When you write config files, separate the reusable parts
760 (things every user of that interface, chip, or board needs)
761 from ones specific to your environment and debugging approach.
765 For example, a @code{gdb-attach} event handler that invokes
766 the @command{reset init} command will interfere with debugging
767 early boot code, which performs some of the same actions
768 that the @code{reset-init} event handler does.
771 Likewise, the @command{arm9tdmi vector_catch} command (or
773 its siblings @command{xscale vector_catch}
774 and @command{cortex_m3 vector_catch}) can be a timesaver
775 during some debug sessions, but don't make everyone use that either.
776 Keep those kinds of debugging aids in your user config file,
777 along with messaging and tracing setup.
778 (@xref{Software Debug Messages and Tracing}.)
781 You might need to override some defaults.
782 For example, you might need to move, shrink, or back up the target's
783 work area if your application needs much SRAM.
786 TCP/IP port configuration is another example of something which
787 is environment-specific, and should only appear in
788 a user config file. @xref{TCP/IP Ports}.
791 @section Project-Specific Utilities
793 A few project-specific utility
794 routines may well speed up your work.
795 Write them, and keep them in your project's user config file.
797 For example, if you are making a boot loader work on a
798 board, it's nice to be able to debug the ``after it's
799 loaded to RAM'' parts separately from the finicky early
800 code which sets up the DDR RAM controller and clocks.
801 A script like this one, or a more GDB-aware sibling,
805 proc ramboot @{ @} @{
806 # Reset, running the target's "reset-init" scripts
807 # to initialize clocks and the DDR RAM controller.
808 # Leave the CPU halted.
811 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
812 load_image u-boot.bin 0x20000000
819 Then once that code is working you will need to make it
820 boot from NOR flash; a different utility would help.
821 Alternatively, some developers write to flash using GDB.
822 (You might use a similar script if you're working with a flash
823 based microcontroller application instead of a boot loader.)
826 proc newboot @{ @} @{
827 # Reset, leaving the CPU halted. The "reset-init" event
828 # proc gives faster access to the CPU and to NOR flash;
829 # "reset halt" would be slower.
832 # Write standard version of U-Boot into the first two
833 # sectors of NOR flash ... the standard version should
834 # do the same lowlevel init as "reset-init".
835 flash protect 0 0 1 off
836 flash erase_sector 0 0 1
837 flash write_bank 0 u-boot.bin 0x0
838 flash protect 0 0 1 on
840 # Reboot from scratch using that new boot loader.
845 You may need more complicated utility procedures when booting
847 That often involves an extra bootloader stage,
848 running from on-chip SRAM to perform DDR RAM setup so it can load
849 the main bootloader code (which won't fit into that SRAM).
851 Other helper scripts might be used to write production system images,
852 involving considerably more than just a three stage bootloader.
854 @section Target Software Changes
856 Sometimes you may want to make some small changes to the software
857 you're developing, to help make JTAG debugging work better.
858 For example, in C or assembly language code you might
859 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
860 handling issues like:
864 @item @b{ARM Wait-For-Interrupt}...
865 Many ARM chips synchronize the JTAG clock using the core clock.
866 Low power states which stop that core clock thus prevent JTAG access.
867 Idle loops in tasking environments often enter those low power states
868 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
870 You may want to @emph{disable that instruction} in source code,
871 or otherwise prevent using that state,
872 to ensure you can get JTAG access at any time.
873 For example, the OpenOCD @command{halt} command may not
874 work for an idle processor otherwise.
876 @item @b{Delay after reset}...
877 Not all chips have good support for debugger access
878 right after reset; many LPC2xxx chips have issues here.
879 Similarly, applications that reconfigure pins used for
880 JTAG access as they start will also block debugger access.
882 To work with boards like this, @emph{enable a short delay loop}
883 the first thing after reset, before "real" startup activities.
884 For example, one second's delay is usually more than enough
885 time for a JTAG debugger to attach, so that
886 early code execution can be debugged
887 or firmware can be replaced.
889 @item @b{Debug Communications Channel (DCC)}...
890 Some processors include mechanisms to send messages over JTAG.
891 Many ARM cores support these, as do some cores from other vendors.
892 (OpenOCD may be able to use this DCC internally, speeding up some
893 operations like writing to memory.)
895 Your application may want to deliver various debugging messages
896 over JTAG, by @emph{linking with a small library of code}
897 provided with OpenOCD and using the utilities there to send
898 various kinds of message.
899 @xref{Software Debug Messages and Tracing}.
903 @node Config File Guidelines
904 @chapter Config File Guidelines
906 This chapter is aimed at any user who needs to write a config file,
907 including developers and integrators of OpenOCD and any user who
908 needs to get a new board working smoothly.
909 It provides guidelines for creating those files.
911 You should find the following directories under @t{$(INSTALLDIR)/scripts},
912 with files including the ones listed here.
913 Use them as-is where you can; or as models for new files.
916 @item @file{interface} ...
917 think JTAG Dongle. Files that configure JTAG adapters go here.
920 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
921 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
922 at91rm9200.cfg jlink.cfg parport.cfg
923 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
924 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
925 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
926 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
927 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
928 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
929 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
930 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
933 @item @file{board} ...
934 think Circuit Board, PWA, PCB, they go by many names. Board files
935 contain initialization items that are specific to a board.
936 They reuse target configuration files, since the same
937 microprocessor chips are used on many boards,
938 but support for external parts varies widely. For
939 example, the SDRAM initialization sequence for the board, or the type
940 of external flash and what address it uses. Any initialization
941 sequence to enable that external flash or SDRAM should be found in the
942 board file. Boards may also contain multiple targets: two CPUs; or
946 arm_evaluator7t.cfg keil_mcb1700.cfg
947 at91rm9200-dk.cfg keil_mcb2140.cfg
948 at91sam9g20-ek.cfg linksys_nslu2.cfg
949 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
950 atmel_at91sam9260-ek.cfg mini2440.cfg
951 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
952 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
953 csb337.cfg olimex_sam7_ex256.cfg
954 csb732.cfg olimex_sam9_l9260.cfg
955 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
956 dm355evm.cfg omap2420_h4.cfg
957 dm365evm.cfg osk5912.cfg
958 dm6446evm.cfg pic-p32mx.cfg
959 eir.cfg propox_mmnet1001.cfg
960 ek-lm3s1968.cfg pxa255_sst.cfg
961 ek-lm3s3748.cfg sheevaplug.cfg
962 ek-lm3s811.cfg stm3210e_eval.cfg
963 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
964 hammer.cfg str910-eval.cfg
965 hitex_lpc2929.cfg telo.cfg
966 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
967 hitex_str9-comstick.cfg topas910.cfg
968 iar_str912_sk.cfg topasa900.cfg
969 imx27ads.cfg unknown_at91sam9260.cfg
970 imx27lnst.cfg x300t.cfg
971 imx31pdk.cfg zy1000.cfg
974 @item @file{target} ...
975 think chip. The ``target'' directory represents the JTAG TAPs
977 which OpenOCD should control, not a board. Two common types of targets
978 are ARM chips and FPGA or CPLD chips.
979 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
980 the target config file defines all of them.
983 aduc702x.cfg imx27.cfg pxa255.cfg
984 ar71xx.cfg imx31.cfg pxa270.cfg
985 at91eb40a.cfg imx35.cfg readme.txt
986 at91r40008.cfg is5114.cfg sam7se512.cfg
987 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
988 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
989 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
990 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
991 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
992 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
993 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
994 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
995 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
996 at91sam9260.cfg lpc2129.cfg stm32.cfg
997 c100.cfg lpc2148.cfg str710.cfg
998 c100config.tcl lpc2294.cfg str730.cfg
999 c100helper.tcl lpc2378.cfg str750.cfg
1000 c100regs.tcl lpc2478.cfg str912.cfg
1001 cs351x.cfg lpc2900.cfg telo.cfg
1002 davinci.cfg mega128.cfg ti_dm355.cfg
1003 dragonite.cfg netx500.cfg ti_dm365.cfg
1004 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1005 feroceon.cfg omap3530.cfg tmpa900.cfg
1006 icepick.cfg omap5912.cfg tmpa910.cfg
1007 imx21.cfg pic32mx.cfg xba_revA3.cfg
1010 @item @emph{more} ... browse for other library files which may be useful.
1011 For example, there are various generic and CPU-specific utilities.
1014 The @file{openocd.cfg} user config
1015 file may override features in any of the above files by
1016 setting variables before sourcing the target file, or by adding
1017 commands specific to their situation.
1019 @section Interface Config Files
1021 The user config file
1022 should be able to source one of these files with a command like this:
1025 source [find interface/FOOBAR.cfg]
1028 A preconfigured interface file should exist for every interface in use
1029 today, that said, perhaps some interfaces have only been used by the
1030 sole developer who created it.
1032 A separate chapter gives information about how to set these up.
1033 @xref{Interface - Dongle Configuration}.
1034 Read the OpenOCD source code if you have a new kind of hardware interface
1035 and need to provide a driver for it.
1037 @section Board Config Files
1038 @cindex config file, board
1039 @cindex board config file
1041 The user config file
1042 should be able to source one of these files with a command like this:
1045 source [find board/FOOBAR.cfg]
1048 The point of a board config file is to package everything
1049 about a given board that user config files need to know.
1050 In summary the board files should contain (if present)
1053 @item One or more @command{source [target/...cfg]} statements
1054 @item NOR flash configuration (@pxref{NOR Configuration})
1055 @item NAND flash configuration (@pxref{NAND Configuration})
1056 @item Target @code{reset} handlers for SDRAM and I/O configuration
1057 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1058 @item All things that are not ``inside a chip''
1061 Generic things inside target chips belong in target config files,
1062 not board config files. So for example a @code{reset-init} event
1063 handler should know board-specific oscillator and PLL parameters,
1064 which it passes to target-specific utility code.
1066 The most complex task of a board config file is creating such a
1067 @code{reset-init} event handler.
1068 Define those handlers last, after you verify the rest of the board
1069 configuration works.
1071 @subsection Communication Between Config files
1073 In addition to target-specific utility code, another way that
1074 board and target config files communicate is by following a
1075 convention on how to use certain variables.
1077 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1078 Thus the rule we follow in OpenOCD is this: Variables that begin with
1079 a leading underscore are temporary in nature, and can be modified and
1080 used at will within a target configuration file.
1082 Complex board config files can do the things like this,
1083 for a board with three chips:
1086 # Chip #1: PXA270 for network side, big endian
1087 set CHIPNAME network
1089 source [find target/pxa270.cfg]
1090 # on return: _TARGETNAME = network.cpu
1091 # other commands can refer to the "network.cpu" target.
1092 $_TARGETNAME configure .... events for this CPU..
1094 # Chip #2: PXA270 for video side, little endian
1097 source [find target/pxa270.cfg]
1098 # on return: _TARGETNAME = video.cpu
1099 # other commands can refer to the "video.cpu" target.
1100 $_TARGETNAME configure .... events for this CPU..
1102 # Chip #3: Xilinx FPGA for glue logic
1105 source [find target/spartan3.cfg]
1108 That example is oversimplified because it doesn't show any flash memory,
1109 or the @code{reset-init} event handlers to initialize external DRAM
1110 or (assuming it needs it) load a configuration into the FPGA.
1111 Such features are usually needed for low-level work with many boards,
1112 where ``low level'' implies that the board initialization software may
1113 not be working. (That's a common reason to need JTAG tools. Another
1114 is to enable working with microcontroller-based systems, which often
1115 have no debugging support except a JTAG connector.)
1117 Target config files may also export utility functions to board and user
1118 config files. Such functions should use name prefixes, to help avoid
1121 Board files could also accept input variables from user config files.
1122 For example, there might be a @code{J4_JUMPER} setting used to identify
1123 what kind of flash memory a development board is using, or how to set
1124 up other clocks and peripherals.
1126 @subsection Variable Naming Convention
1127 @cindex variable names
1129 Most boards have only one instance of a chip.
1130 However, it should be easy to create a board with more than
1131 one such chip (as shown above).
1132 Accordingly, we encourage these conventions for naming
1133 variables associated with different @file{target.cfg} files,
1134 to promote consistency and
1135 so that board files can override target defaults.
1137 Inputs to target config files include:
1140 @item @code{CHIPNAME} ...
1141 This gives a name to the overall chip, and is used as part of
1142 tap identifier dotted names.
1143 While the default is normally provided by the chip manufacturer,
1144 board files may need to distinguish between instances of a chip.
1145 @item @code{ENDIAN} ...
1146 By default @option{little} - although chips may hard-wire @option{big}.
1147 Chips that can't change endianness don't need to use this variable.
1148 @item @code{CPUTAPID} ...
1149 When OpenOCD examines the JTAG chain, it can be told verify the
1150 chips against the JTAG IDCODE register.
1151 The target file will hold one or more defaults, but sometimes the
1152 chip in a board will use a different ID (perhaps a newer revision).
1155 Outputs from target config files include:
1158 @item @code{_TARGETNAME} ...
1159 By convention, this variable is created by the target configuration
1160 script. The board configuration file may make use of this variable to
1161 configure things like a ``reset init'' script, or other things
1162 specific to that board and that target.
1163 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1164 @code{_TARGETNAME1}, ... etc.
1167 @subsection The reset-init Event Handler
1168 @cindex event, reset-init
1169 @cindex reset-init handler
1171 Board config files run in the OpenOCD configuration stage;
1172 they can't use TAPs or targets, since they haven't been
1174 This means you can't write memory or access chip registers;
1175 you can't even verify that a flash chip is present.
1176 That's done later in event handlers, of which the target @code{reset-init}
1177 handler is one of the most important.
1179 Except on microcontrollers, the basic job of @code{reset-init} event
1180 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1181 Microcontrollers rarely use boot loaders; they run right out of their
1182 on-chip flash and SRAM memory. But they may want to use one of these
1183 handlers too, if just for developer convenience.
1186 Because this is so very board-specific, and chip-specific, no examples
1188 Instead, look at the board config files distributed with OpenOCD.
1189 If you have a boot loader, its source code may also be useful.
1192 Some of this code could probably be shared between different boards.
1193 For example, setting up a DRAM controller often doesn't differ by
1194 much except the bus width (16 bits or 32?) and memory timings, so a
1195 reusable TCL procedure loaded by the @file{target.cfg} file might take
1196 those as parameters.
1197 Similarly with oscillator, PLL, and clock setup;
1198 and disabling the watchdog.
1199 Structure the code cleanly, and provide comments to help
1200 the next developer doing such work.
1201 (@emph{You might be that next person} trying to reuse init code!)
1203 The last thing normally done in a @code{reset-init} handler is probing
1204 whatever flash memory was configured. For most chips that needs to be
1205 done while the associated target is halted, either because JTAG memory
1206 access uses the CPU or to prevent conflicting CPU access.
1208 @subsection JTAG Clock Rate
1210 Before your @code{reset-init} handler has set up
1211 the PLLs and clocking, you may need to run with
1212 a low JTAG clock rate.
1214 Then you'd increase that rate after your handler has
1215 made it possible to use the faster JTAG clock.
1216 When the initial low speed is board-specific, for example
1217 because it depends on a board-specific oscillator speed, then
1218 you should probably set it up in the board config file;
1219 if it's target-specific, it belongs in the target config file.
1221 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1222 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1223 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1224 Consult chip documentation to determine the peak JTAG clock rate,
1225 which might be less than that.
1228 On most ARMs, JTAG clock detection is coupled to the core clock, so
1229 software using a @option{wait for interrupt} operation blocks JTAG access.
1230 Adaptive clocking provides a partial workaround, but a more complete
1231 solution just avoids using that instruction with JTAG debuggers.
1234 If the board supports adaptive clocking, use the @command{jtag_rclk}
1235 command, in case your board is used with JTAG adapter which
1236 also supports it. Otherwise use @command{jtag_khz}.
1237 Set the slow rate at the beginning of the reset sequence,
1238 and the faster rate as soon as the clocks are at full speed.
1240 @section Target Config Files
1241 @cindex config file, target
1242 @cindex target config file
1244 Board config files communicate with target config files using
1245 naming conventions as described above, and may source one or
1246 more target config files like this:
1249 source [find target/FOOBAR.cfg]
1252 The point of a target config file is to package everything
1253 about a given chip that board config files need to know.
1254 In summary the target files should contain
1258 @item Add TAPs to the scan chain
1259 @item Add CPU targets (includes GDB support)
1260 @item CPU/Chip/CPU-Core specific features
1264 As a rule of thumb, a target file sets up only one chip.
1265 For a microcontroller, that will often include a single TAP,
1266 which is a CPU needing a GDB target, and its on-chip flash.
1268 More complex chips may include multiple TAPs, and the target
1269 config file may need to define them all before OpenOCD
1270 can talk to the chip.
1271 For example, some phone chips have JTAG scan chains that include
1272 an ARM core for operating system use, a DSP,
1273 another ARM core embedded in an image processing engine,
1274 and other processing engines.
1276 @subsection Default Value Boiler Plate Code
1278 All target configuration files should start with code like this,
1279 letting board config files express environment-specific
1280 differences in how things should be set up.
1283 # Boards may override chip names, perhaps based on role,
1284 # but the default should match what the vendor uses
1285 if @{ [info exists CHIPNAME] @} @{
1286 set _CHIPNAME $CHIPNAME
1288 set _CHIPNAME sam7x256
1291 # ONLY use ENDIAN with targets that can change it.
1292 if @{ [info exists ENDIAN] @} @{
1298 # TAP identifiers may change as chips mature, for example with
1299 # new revision fields (the "3" here). Pick a good default; you
1300 # can pass several such identifiers to the "jtag newtap" command.
1301 if @{ [info exists CPUTAPID ] @} @{
1302 set _CPUTAPID $CPUTAPID
1304 set _CPUTAPID 0x3f0f0f0f
1307 @c but 0x3f0f0f0f is for an str73x part ...
1309 @emph{Remember:} Board config files may include multiple target
1310 config files, or the same target file multiple times
1311 (changing at least @code{CHIPNAME}).
1313 Likewise, the target configuration file should define
1314 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1315 use it later on when defining debug targets:
1318 set _TARGETNAME $_CHIPNAME.cpu
1319 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1322 @subsection Adding TAPs to the Scan Chain
1323 After the ``defaults'' are set up,
1324 add the TAPs on each chip to the JTAG scan chain.
1325 @xref{TAP Declaration}, and the naming convention
1328 In the simplest case the chip has only one TAP,
1329 probably for a CPU or FPGA.
1330 The config file for the Atmel AT91SAM7X256
1331 looks (in part) like this:
1334 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1335 -expected-id $_CPUTAPID
1338 A board with two such at91sam7 chips would be able
1339 to source such a config file twice, with different
1340 values for @code{CHIPNAME}, so
1341 it adds a different TAP each time.
1343 If there are nonzero @option{-expected-id} values,
1344 OpenOCD attempts to verify the actual tap id against those values.
1345 It will issue error messages if there is mismatch, which
1346 can help to pinpoint problems in OpenOCD configurations.
1349 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1350 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1351 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1352 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1353 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1356 There are more complex examples too, with chips that have
1357 multiple TAPs. Ones worth looking at include:
1360 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1361 plus a JRC to enable them
1362 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1363 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1364 is not currently used)
1367 @subsection Add CPU targets
1369 After adding a TAP for a CPU, you should set it up so that
1370 GDB and other commands can use it.
1371 @xref{CPU Configuration}.
1372 For the at91sam7 example above, the command can look like this;
1373 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1374 to little endian, and this chip doesn't support changing that.
1377 set _TARGETNAME $_CHIPNAME.cpu
1378 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1381 Work areas are small RAM areas associated with CPU targets.
1382 They are used by OpenOCD to speed up downloads,
1383 and to download small snippets of code to program flash chips.
1384 If the chip includes a form of ``on-chip-ram'' - and many do - define
1385 a work area if you can.
1386 Again using the at91sam7 as an example, this can look like:
1389 $_TARGETNAME configure -work-area-phys 0x00200000 \
1390 -work-area-size 0x4000 -work-area-backup 0
1393 @subsection Chip Reset Setup
1395 As a rule, you should put the @command{reset_config} command
1396 into the board file. Most things you think you know about a
1397 chip can be tweaked by the board.
1399 Some chips have specific ways the TRST and SRST signals are
1400 managed. In the unusual case that these are @emph{chip specific}
1401 and can never be changed by board wiring, they could go here.
1403 Some chips need special attention during reset handling if
1404 they're going to be used with JTAG.
1405 An example might be needing to send some commands right
1406 after the target's TAP has been reset, providing a
1407 @code{reset-deassert-post} event handler that writes a chip
1408 register to report that JTAG debugging is being done.
1410 JTAG clocking constraints often change during reset, and in
1411 some cases target config files (rather than board config files)
1412 are the right places to handle some of those issues.
1413 For example, immediately after reset most chips run using a
1414 slower clock than they will use later.
1415 That means that after reset (and potentially, as OpenOCD
1416 first starts up) they must use a slower JTAG clock rate
1417 than they will use later.
1420 @quotation Important
1421 When you are debugging code that runs right after chip
1422 reset, getting these issues right is critical.
1423 In particular, if you see intermittent failures when
1424 OpenOCD verifies the scan chain after reset,
1425 look at how you are setting up JTAG clocking.
1428 @subsection ARM Core Specific Hacks
1430 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1431 special high speed download features - enable it.
1433 If present, the MMU, the MPU and the CACHE should be disabled.
1435 Some ARM cores are equipped with trace support, which permits
1436 examination of the instruction and data bus activity. Trace
1437 activity is controlled through an ``Embedded Trace Module'' (ETM)
1438 on one of the core's scan chains. The ETM emits voluminous data
1439 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1440 If you are using an external trace port,
1441 configure it in your board config file.
1442 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1443 configure it in your target config file.
1446 etm config $_TARGETNAME 16 normal full etb
1447 etb config $_TARGETNAME $_CHIPNAME.etb
1450 @subsection Internal Flash Configuration
1452 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1454 @b{Never ever} in the ``target configuration file'' define any type of
1455 flash that is external to the chip. (For example a BOOT flash on
1456 Chip Select 0.) Such flash information goes in a board file - not
1457 the TARGET (chip) file.
1461 @item at91sam7x256 - has 256K flash YES enable it.
1462 @item str912 - has flash internal YES enable it.
1463 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1464 @item pxa270 - again - CS0 flash - it goes in the board file.
1467 @node Daemon Configuration
1468 @chapter Daemon Configuration
1469 @cindex initialization
1470 The commands here are commonly found in the openocd.cfg file and are
1471 used to specify what TCP/IP ports are used, and how GDB should be
1474 @anchor{Configuration Stage}
1475 @section Configuration Stage
1476 @cindex configuration stage
1477 @cindex config command
1479 When the OpenOCD server process starts up, it enters a
1480 @emph{configuration stage} which is the only time that
1481 certain commands, @emph{configuration commands}, may be issued.
1482 In this manual, the definition of a configuration command is
1483 presented as a @emph{Config Command}, not as a @emph{Command}
1484 which may be issued interactively.
1486 Those configuration commands include declaration of TAPs,
1488 the interface used for JTAG communication,
1489 and other basic setup.
1490 The server must leave the configuration stage before it
1491 may access or activate TAPs.
1492 After it leaves this stage, configuration commands may no
1495 The first thing OpenOCD does after leaving the configuration
1496 stage is to verify that it can talk to the scan chain
1497 (list of TAPs) which has been configured.
1498 It will warn if it doesn't find TAPs it expects to find,
1499 or finds TAPs that aren't supposed to be there.
1500 You should see no errors at this point.
1501 If you see errors, resolve them by correcting the
1502 commands you used to configure the server.
1503 Common errors include using an initial JTAG speed that's too
1504 fast, and not providing the right IDCODE values for the TAPs
1507 @deffn {Config Command} init
1508 This command terminates the configuration stage and
1509 enters the normal command mode. This can be useful to add commands to
1510 the startup scripts and commands such as resetting the target,
1511 programming flash, etc. To reset the CPU upon startup, add "init" and
1512 "reset" at the end of the config script or at the end of the OpenOCD
1513 command line using the @option{-c} command line switch.
1515 If this command does not appear in any startup/configuration file
1516 OpenOCD executes the command for you after processing all
1517 configuration files and/or command line options.
1519 @b{NOTE:} This command normally occurs at or near the end of your
1520 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1521 targets ready. For example: If your openocd.cfg file needs to
1522 read/write memory on your target, @command{init} must occur before
1523 the memory read/write commands. This includes @command{nand probe}.
1526 @anchor{TCP/IP Ports}
1527 @section TCP/IP Ports
1532 The OpenOCD server accepts remote commands in several syntaxes.
1533 Each syntax uses a different TCP/IP port, which you may specify
1534 only during configuration (before those ports are opened).
1536 For reasons including security, you may wish to prevent remote
1537 access using one or more of these ports.
1538 In such cases, just specify the relevant port number as zero.
1539 If you disable all access through TCP/IP, you will need to
1540 use the command line @option{-pipe} option.
1542 @deffn {Command} gdb_port (number)
1544 Specify or query the first port used for incoming GDB connections.
1545 The GDB port for the
1546 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1547 When not specified during the configuration stage,
1548 the port @var{number} defaults to 3333.
1549 When specified as zero, this port is not activated.
1552 @deffn {Command} tcl_port (number)
1553 Specify or query the port used for a simplified RPC
1554 connection that can be used by clients to issue TCL commands and get the
1555 output from the Tcl engine.
1556 Intended as a machine interface.
1557 When not specified during the configuration stage,
1558 the port @var{number} defaults to 6666.
1559 When specified as zero, this port is not activated.
1562 @deffn {Command} telnet_port (number)
1563 Specify or query the
1564 port on which to listen for incoming telnet connections.
1565 This port is intended for interaction with one human through TCL commands.
1566 When not specified during the configuration stage,
1567 the port @var{number} defaults to 4444.
1568 When specified as zero, this port is not activated.
1571 @anchor{GDB Configuration}
1572 @section GDB Configuration
1574 @cindex GDB configuration
1575 You can reconfigure some GDB behaviors if needed.
1576 The ones listed here are static and global.
1577 @xref{Target Configuration}, about configuring individual targets.
1578 @xref{Target Events}, about configuring target-specific event handling.
1580 @anchor{gdb_breakpoint_override}
1581 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1582 Force breakpoint type for gdb @command{break} commands.
1583 This option supports GDB GUIs which don't
1584 distinguish hard versus soft breakpoints, if the default OpenOCD and
1585 GDB behaviour is not sufficient. GDB normally uses hardware
1586 breakpoints if the memory map has been set up for flash regions.
1589 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1590 Configures what OpenOCD will do when GDB detaches from the daemon.
1591 Default behaviour is @option{resume}.
1594 @anchor{gdb_flash_program}
1595 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1596 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1597 vFlash packet is received.
1598 The default behaviour is @option{enable}.
1601 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1602 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1603 requested. GDB will then know when to set hardware breakpoints, and program flash
1604 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1605 for flash programming to work.
1606 Default behaviour is @option{enable}.
1607 @xref{gdb_flash_program}.
1610 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1611 Specifies whether data aborts cause an error to be reported
1612 by GDB memory read packets.
1613 The default behaviour is @option{disable};
1614 use @option{enable} see these errors reported.
1617 @anchor{Event Polling}
1618 @section Event Polling
1620 Hardware debuggers are parts of asynchronous systems,
1621 where significant events can happen at any time.
1622 The OpenOCD server needs to detect some of these events,
1623 so it can report them to through TCL command line
1626 Examples of such events include:
1629 @item One of the targets can stop running ... maybe it triggers
1630 a code breakpoint or data watchpoint, or halts itself.
1631 @item Messages may be sent over ``debug message'' channels ... many
1632 targets support such messages sent over JTAG,
1633 for receipt by the person debugging or tools.
1634 @item Loss of power ... some adapters can detect these events.
1635 @item Resets not issued through JTAG ... such reset sources
1636 can include button presses or other system hardware, sometimes
1637 including the target itself (perhaps through a watchdog).
1638 @item Debug instrumentation sometimes supports event triggering
1639 such as ``trace buffer full'' (so it can quickly be emptied)
1640 or other signals (to correlate with code behavior).
1643 None of those events are signaled through standard JTAG signals.
1644 However, most conventions for JTAG connectors include voltage
1645 level and system reset (SRST) signal detection.
1646 Some connectors also include instrumentation signals, which
1647 can imply events when those signals are inputs.
1649 In general, OpenOCD needs to periodically check for those events,
1650 either by looking at the status of signals on the JTAG connector
1651 or by sending synchronous ``tell me your status'' JTAG requests
1652 to the various active targets.
1653 There is a command to manage and monitor that polling,
1654 which is normally done in the background.
1656 @deffn Command poll [@option{on}|@option{off}]
1657 Poll the current target for its current state.
1658 (Also, @pxref{target curstate}.)
1659 If that target is in debug mode, architecture
1660 specific information about the current state is printed.
1661 An optional parameter
1662 allows background polling to be enabled and disabled.
1664 You could use this from the TCL command shell, or
1665 from GDB using @command{monitor poll} command.
1668 background polling: on
1669 target state: halted
1670 target halted in ARM state due to debug-request, \
1671 current mode: Supervisor
1672 cpsr: 0x800000d3 pc: 0x11081bfc
1673 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1678 @node Interface - Dongle Configuration
1679 @chapter Interface - Dongle Configuration
1680 @cindex config file, interface
1681 @cindex interface config file
1683 JTAG Adapters/Interfaces/Dongles are normally configured
1684 through commands in an interface configuration
1685 file which is sourced by your @file{openocd.cfg} file, or
1686 through a command line @option{-f interface/....cfg} option.
1689 source [find interface/olimex-jtag-tiny.cfg]
1693 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1694 A few cases are so simple that you only need to say what driver to use:
1701 Most adapters need a bit more configuration than that.
1704 @section Interface Configuration
1706 The interface command tells OpenOCD what type of JTAG dongle you are
1707 using. Depending on the type of dongle, you may need to have one or
1708 more additional commands.
1710 @deffn {Config Command} {interface} name
1711 Use the interface driver @var{name} to connect to the
1715 @deffn Command {interface_list}
1716 List the interface drivers that have been built into
1717 the running copy of OpenOCD.
1720 @deffn Command {jtag interface}
1721 Returns the name of the interface driver being used.
1724 @section Interface Drivers
1726 Each of the interface drivers listed here must be explicitly
1727 enabled when OpenOCD is configured, in order to be made
1728 available at run time.
1730 @deffn {Interface Driver} {amt_jtagaccel}
1731 Amontec Chameleon in its JTAG Accelerator configuration,
1732 connected to a PC's EPP mode parallel port.
1733 This defines some driver-specific commands:
1735 @deffn {Config Command} {parport_port} number
1736 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1737 the number of the @file{/dev/parport} device.
1740 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1741 Displays status of RTCK option.
1742 Optionally sets that option first.
1746 @deffn {Interface Driver} {arm-jtag-ew}
1747 Olimex ARM-JTAG-EW USB adapter
1748 This has one driver-specific command:
1750 @deffn Command {armjtagew_info}
1755 @deffn {Interface Driver} {at91rm9200}
1756 Supports bitbanged JTAG from the local system,
1757 presuming that system is an Atmel AT91rm9200
1758 and a specific set of GPIOs is used.
1759 @c command: at91rm9200_device NAME
1760 @c chooses among list of bit configs ... only one option
1763 @deffn {Interface Driver} {dummy}
1764 A dummy software-only driver for debugging.
1767 @deffn {Interface Driver} {ep93xx}
1768 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1771 @deffn {Interface Driver} {ft2232}
1772 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1773 These interfaces have several commands, used to configure the driver
1774 before initializing the JTAG scan chain:
1776 @deffn {Config Command} {ft2232_device_desc} description
1777 Provides the USB device description (the @emph{iProduct string})
1778 of the FTDI FT2232 device. If not
1779 specified, the FTDI default value is used. This setting is only valid
1780 if compiled with FTD2XX support.
1783 @deffn {Config Command} {ft2232_serial} serial-number
1784 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1785 in case the vendor provides unique IDs and more than one FT2232 device
1786 is connected to the host.
1787 If not specified, serial numbers are not considered.
1788 (Note that USB serial numbers can be arbitrary Unicode strings,
1789 and are not restricted to containing only decimal digits.)
1792 @deffn {Config Command} {ft2232_layout} name
1793 Each vendor's FT2232 device can use different GPIO signals
1794 to control output-enables, reset signals, and LEDs.
1795 Currently valid layout @var{name} values include:
1797 @item @b{axm0432_jtag} Axiom AXM-0432
1798 @item @b{comstick} Hitex STR9 comstick
1799 @item @b{cortino} Hitex Cortino JTAG interface
1800 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1801 either for the local Cortex-M3 (SRST only)
1802 or in a passthrough mode (neither SRST nor TRST)
1803 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1804 @item @b{flyswatter} Tin Can Tools Flyswatter
1805 @item @b{icebear} ICEbear JTAG adapter from Section 5
1806 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1807 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1808 @item @b{m5960} American Microsystems M5960
1809 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1810 @item @b{oocdlink} OOCDLink
1811 @c oocdlink ~= jtagkey_prototype_v1
1812 @item @b{sheevaplug} Marvell Sheevaplug development kit
1813 @item @b{signalyzer} Xverve Signalyzer
1814 @item @b{stm32stick} Hitex STM32 Performance Stick
1815 @item @b{turtelizer2} egnite Software turtelizer2
1816 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1820 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1821 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1822 default values are used.
1823 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1825 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1829 @deffn {Config Command} {ft2232_latency} ms
1830 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1831 ft2232_read() fails to return the expected number of bytes. This can be caused by
1832 USB communication delays and has proved hard to reproduce and debug. Setting the
1833 FT2232 latency timer to a larger value increases delays for short USB packets but it
1834 also reduces the risk of timeouts before receiving the expected number of bytes.
1835 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1838 For example, the interface config file for a
1839 Turtelizer JTAG Adapter looks something like this:
1843 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1844 ft2232_layout turtelizer2
1845 ft2232_vid_pid 0x0403 0xbdc8
1849 @deffn {Interface Driver} {gw16012}
1850 Gateworks GW16012 JTAG programmer.
1851 This has one driver-specific command:
1853 @deffn {Config Command} {parport_port} number
1854 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1855 the number of the @file{/dev/parport} device.
1859 @deffn {Interface Driver} {jlink}
1860 Segger jlink USB adapter
1861 @c command: jlink_info
1863 @c command: jlink_hw_jtag (2|3)
1864 @c sets version 2 or 3
1867 @deffn {Interface Driver} {parport}
1868 Supports PC parallel port bit-banging cables:
1869 Wigglers, PLD download cable, and more.
1870 These interfaces have several commands, used to configure the driver
1871 before initializing the JTAG scan chain:
1873 @deffn {Config Command} {parport_cable} name
1874 The layout of the parallel port cable used to connect to the target.
1875 Currently valid cable @var{name} values include:
1878 @item @b{altium} Altium Universal JTAG cable.
1879 @item @b{arm-jtag} Same as original wiggler except SRST and
1880 TRST connections reversed and TRST is also inverted.
1881 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1882 in configuration mode. This is only used to
1883 program the Chameleon itself, not a connected target.
1884 @item @b{dlc5} The Xilinx Parallel cable III.
1885 @item @b{flashlink} The ST Parallel cable.
1886 @item @b{lattice} Lattice ispDOWNLOAD Cable
1887 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1889 Amontec's Chameleon Programmer. The new version available from
1890 the website uses the original Wiggler layout ('@var{wiggler}')
1891 @item @b{triton} The parallel port adapter found on the
1892 ``Karo Triton 1 Development Board''.
1893 This is also the layout used by the HollyGates design
1894 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1895 @item @b{wiggler} The original Wiggler layout, also supported by
1896 several clones, such as the Olimex ARM-JTAG
1897 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1898 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1902 @deffn {Config Command} {parport_port} number
1903 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1904 the @file{/dev/parport} device
1906 When using PPDEV to access the parallel port, use the number of the parallel port:
1907 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1908 you may encounter a problem.
1911 @deffn {Config Command} {parport_write_on_exit} (on|off)
1912 This will configure the parallel driver to write a known
1913 cable-specific value to the parallel interface on exiting OpenOCD
1916 For example, the interface configuration file for a
1917 classic ``Wiggler'' cable might look something like this:
1922 parport_cable wiggler
1926 @deffn {Interface Driver} {presto}
1927 ASIX PRESTO USB JTAG programmer.
1928 @c command: presto_serial str
1929 @c sets serial number
1932 @deffn {Interface Driver} {rlink}
1933 Raisonance RLink USB adapter
1936 @deffn {Interface Driver} {usbprog}
1937 usbprog is a freely programmable USB adapter.
1940 @deffn {Interface Driver} {vsllink}
1941 vsllink is part of Versaloon which is a versatile USB programmer.
1944 This defines quite a few driver-specific commands,
1945 which are not currently documented here.
1949 @deffn {Interface Driver} {ZY1000}
1950 This is the Zylin ZY1000 JTAG debugger.
1953 This defines some driver-specific commands,
1954 which are not currently documented here.
1957 @deffn Command power [@option{on}|@option{off}]
1958 Turn power switch to target on/off.
1959 No arguments: print status.
1966 JTAG clock setup is part of system setup.
1967 It @emph{does not belong with interface setup} since any interface
1968 only knows a few of the constraints for the JTAG clock speed.
1969 Sometimes the JTAG speed is
1970 changed during the target initialization process: (1) slow at
1971 reset, (2) program the CPU clocks, (3) run fast.
1972 Both the "slow" and "fast" clock rates are functions of the
1973 oscillators used, the chip, the board design, and sometimes
1974 power management software that may be active.
1976 The speed used during reset, and the scan chain verification which
1977 follows reset, can be adjusted using a @code{reset-start}
1978 target event handler.
1979 It can then be reconfigured to a faster speed by a
1980 @code{reset-init} target event handler after it reprograms those
1981 CPU clocks, or manually (if something else, such as a boot loader,
1982 sets up those clocks).
1983 @xref{Target Events}.
1984 When the initial low JTAG speed is a chip characteristic, perhaps
1985 because of a required oscillator speed, provide such a handler
1986 in the target config file.
1987 When that speed is a function of a board-specific characteristic
1988 such as which speed oscillator is used, it belongs in the board
1989 config file instead.
1990 In both cases it's safest to also set the initial JTAG clock rate
1991 to that same slow speed, so that OpenOCD never starts up using a
1992 clock speed that's faster than the scan chain can support.
1996 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1999 If your system supports adaptive clocking (RTCK), configuring
2000 JTAG to use that is probably the most robust approach.
2001 However, it introduces delays to synchronize clocks; so it
2002 may not be the fastest solution.
2004 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2005 instead of @command{jtag_khz}.
2007 @deffn {Command} jtag_khz max_speed_kHz
2008 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2009 JTAG interfaces usually support a limited number of
2010 speeds. The speed actually used won't be faster
2011 than the speed specified.
2013 Chip data sheets generally include a top JTAG clock rate.
2014 The actual rate is often a function of a CPU core clock,
2015 and is normally less than that peak rate.
2016 For example, most ARM cores accept at most one sixth of the CPU clock.
2018 Speed 0 (khz) selects RTCK method.
2020 If your system uses RTCK, you won't need to change the
2021 JTAG clocking after setup.
2022 Not all interfaces, boards, or targets support ``rtck''.
2023 If the interface device can not
2024 support it, an error is returned when you try to use RTCK.
2027 @defun jtag_rclk fallback_speed_kHz
2028 @cindex adaptive clocking
2030 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2031 If that fails (maybe the interface, board, or target doesn't
2032 support it), falls back to the specified frequency.
2034 # Fall back to 3mhz if RTCK is not supported
2039 @node Reset Configuration
2040 @chapter Reset Configuration
2041 @cindex Reset Configuration
2043 Every system configuration may require a different reset
2044 configuration. This can also be quite confusing.
2045 Resets also interact with @var{reset-init} event handlers,
2046 which do things like setting up clocks and DRAM, and
2047 JTAG clock rates. (@xref{JTAG Speed}.)
2048 They can also interact with JTAG routers.
2049 Please see the various board files for examples.
2052 To maintainers and integrators:
2053 Reset configuration touches several things at once.
2054 Normally the board configuration file
2055 should define it and assume that the JTAG adapter supports
2056 everything that's wired up to the board's JTAG connector.
2058 However, the target configuration file could also make note
2059 of something the silicon vendor has done inside the chip,
2060 which will be true for most (or all) boards using that chip.
2061 And when the JTAG adapter doesn't support everything, the
2062 user configuration file will need to override parts of
2063 the reset configuration provided by other files.
2066 @section Types of Reset
2068 There are many kinds of reset possible through JTAG, but
2069 they may not all work with a given board and adapter.
2070 That's part of why reset configuration can be error prone.
2074 @emph{System Reset} ... the @emph{SRST} hardware signal
2075 resets all chips connected to the JTAG adapter, such as processors,
2076 power management chips, and I/O controllers. Normally resets triggered
2077 with this signal behave exactly like pressing a RESET button.
2079 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2080 just the TAP controllers connected to the JTAG adapter.
2081 Such resets should not be visible to the rest of the system; resetting a
2082 device's the TAP controller just puts that controller into a known state.
2084 @emph{Emulation Reset} ... many devices can be reset through JTAG
2085 commands. These resets are often distinguishable from system
2086 resets, either explicitly (a "reset reason" register says so)
2087 or implicitly (not all parts of the chip get reset).
2089 @emph{Other Resets} ... system-on-chip devices often support
2090 several other types of reset.
2091 You may need to arrange that a watchdog timer stops
2092 while debugging, preventing a watchdog reset.
2093 There may be individual module resets.
2096 In the best case, OpenOCD can hold SRST, then reset
2097 the TAPs via TRST and send commands through JTAG to halt the
2098 CPU at the reset vector before the 1st instruction is executed.
2099 Then when it finally releases the SRST signal, the system is
2100 halted under debugger control before any code has executed.
2101 This is the behavior required to support the @command{reset halt}
2102 and @command{reset init} commands; after @command{reset init} a
2103 board-specific script might do things like setting up DRAM.
2104 (@xref{Reset Command}.)
2106 @anchor{SRST and TRST Issues}
2107 @section SRST and TRST Issues
2109 Because SRST and TRST are hardware signals, they can have a
2110 variety of system-specific constraints. Some of the most
2115 @item @emph{Signal not available} ... Some boards don't wire
2116 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2117 support such signals even if they are wired up.
2118 Use the @command{reset_config} @var{signals} options to say
2119 when either of those signals is not connected.
2120 When SRST is not available, your code might not be able to rely
2121 on controllers having been fully reset during code startup.
2122 Missing TRST is not a problem, since JTAG level resets can
2123 be triggered using with TMS signaling.
2125 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2126 adapter will connect SRST to TRST, instead of keeping them separate.
2127 Use the @command{reset_config} @var{combination} options to say
2128 when those signals aren't properly independent.
2130 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2131 delay circuit, reset supervisor, or on-chip features can extend
2132 the effect of a JTAG adapter's reset for some time after the adapter
2133 stops issuing the reset. For example, there may be chip or board
2134 requirements that all reset pulses last for at least a
2135 certain amount of time; and reset buttons commonly have
2136 hardware debouncing.
2137 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2138 commands to say when extra delays are needed.
2140 @item @emph{Drive type} ... Reset lines often have a pullup
2141 resistor, letting the JTAG interface treat them as open-drain
2142 signals. But that's not a requirement, so the adapter may need
2143 to use push/pull output drivers.
2144 Also, with weak pullups it may be advisable to drive
2145 signals to both levels (push/pull) to minimize rise times.
2146 Use the @command{reset_config} @var{trst_type} and
2147 @var{srst_type} parameters to say how to drive reset signals.
2149 @item @emph{Special initialization} ... Targets sometimes need
2150 special JTAG initialization sequences to handle chip-specific
2151 issues (not limited to errata).
2152 For example, certain JTAG commands might need to be issued while
2153 the system as a whole is in a reset state (SRST active)
2154 but the JTAG scan chain is usable (TRST inactive).
2155 (@xref{JTAG Commands}, where the @command{jtag_reset}
2156 command is presented.)
2159 There can also be other issues.
2160 Some devices don't fully conform to the JTAG specifications.
2161 Trivial system-specific differences are common, such as
2162 SRST and TRST using slightly different names.
2163 There are also vendors who distribute key JTAG documentation for
2164 their chips only to developers who have signed a Non-Disclosure
2167 Sometimes there are chip-specific extensions like a requirement to use
2168 the normally-optional TRST signal (precluding use of JTAG adapters which
2169 don't pass TRST through), or needing extra steps to complete a TAP reset.
2171 In short, SRST and especially TRST handling may be very finicky,
2172 needing to cope with both architecture and board specific constraints.
2174 @section Commands for Handling Resets
2176 @deffn {Command} jtag_nsrst_delay milliseconds
2177 How long (in milliseconds) OpenOCD should wait after deasserting
2178 nSRST (active-low system reset) before starting new JTAG operations.
2179 When a board has a reset button connected to SRST line it will
2180 probably have hardware debouncing, implying you should use this.
2183 @deffn {Command} jtag_ntrst_delay milliseconds
2184 How long (in milliseconds) OpenOCD should wait after deasserting
2185 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2188 @deffn {Command} reset_config mode_flag ...
2189 This command displays or modifies the reset configuration
2190 of your combination of JTAG board and target in target
2191 configuration scripts.
2193 Information earlier in this section describes the kind of problems
2194 the command is intended to address (@pxref{SRST and TRST Issues}).
2195 As a rule this command belongs only in board config files,
2196 describing issues like @emph{board doesn't connect TRST};
2197 or in user config files, addressing limitations derived
2198 from a particular combination of interface and board.
2199 (An unlikely example would be using a TRST-only adapter
2200 with a board that only wires up SRST.)
2202 The @var{mode_flag} options can be specified in any order, but only one
2203 of each type -- @var{signals}, @var{combination},
2206 and @var{srst_type} -- may be specified at a time.
2207 If you don't provide a new value for a given type, its previous
2208 value (perhaps the default) is unchanged.
2209 For example, this means that you don't need to say anything at all about
2210 TRST just to declare that if the JTAG adapter should want to drive SRST,
2211 it must explicitly be driven high (@option{srst_push_pull}).
2215 @var{signals} can specify which of the reset signals are connected.
2216 For example, If the JTAG interface provides SRST, but the board doesn't
2217 connect that signal properly, then OpenOCD can't use it.
2218 Possible values are @option{none} (the default), @option{trst_only},
2219 @option{srst_only} and @option{trst_and_srst}.
2222 If your board provides SRST and/or TRST through the JTAG connector,
2223 you must declare that or else those signals will not be used.
2227 The @var{combination} is an optional value specifying broken reset
2228 signal implementations.
2229 The default behaviour if no option given is @option{separate},
2230 indicating everything behaves normally.
2231 @option{srst_pulls_trst} states that the
2232 test logic is reset together with the reset of the system (e.g. Philips
2233 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2234 the system is reset together with the test logic (only hypothetical, I
2235 haven't seen hardware with such a bug, and can be worked around).
2236 @option{combined} implies both @option{srst_pulls_trst} and
2237 @option{trst_pulls_srst}.
2240 The @var{gates} tokens control flags that describe some cases where
2241 JTAG may be unvailable during reset.
2242 @option{srst_gates_jtag} (default)
2243 indicates that asserting SRST gates the
2244 JTAG clock. This means that no communication can happen on JTAG
2245 while SRST is asserted.
2246 Its converse is @option{srst_nogate}, indicating that JTAG commands
2247 can safely be issued while SRST is active.
2250 The optional @var{trst_type} and @var{srst_type} parameters allow the
2251 driver mode of each reset line to be specified. These values only affect
2252 JTAG interfaces with support for different driver modes, like the Amontec
2253 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2254 relevant signal (TRST or SRST) is not connected.
2258 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2259 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2260 Most boards connect this signal to a pulldown, so the JTAG TAPs
2261 never leave reset unless they are hooked up to a JTAG adapter.
2264 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2265 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2266 Most boards connect this signal to a pullup, and allow the
2267 signal to be pulled low by various events including system
2268 powerup and pressing a reset button.
2273 @node TAP Declaration
2274 @chapter TAP Declaration
2275 @cindex TAP declaration
2276 @cindex TAP configuration
2278 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2279 TAPs serve many roles, including:
2282 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2283 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2284 Others do it indirectly, making a CPU do it.
2285 @item @b{Program Download} Using the same CPU support GDB uses,
2286 you can initialize a DRAM controller, download code to DRAM, and then
2287 start running that code.
2288 @item @b{Boundary Scan} Most chips support boundary scan, which
2289 helps test for board assembly problems like solder bridges
2290 and missing connections
2293 OpenOCD must know about the active TAPs on your board(s).
2294 Setting up the TAPs is the core task of your configuration files.
2295 Once those TAPs are set up, you can pass their names to code
2296 which sets up CPUs and exports them as GDB targets,
2297 probes flash memory, performs low-level JTAG operations, and more.
2299 @section Scan Chains
2302 TAPs are part of a hardware @dfn{scan chain},
2303 which is daisy chain of TAPs.
2304 They also need to be added to
2305 OpenOCD's software mirror of that hardware list,
2306 giving each member a name and associating other data with it.
2307 Simple scan chains, with a single TAP, are common in
2308 systems with a single microcontroller or microprocessor.
2309 More complex chips may have several TAPs internally.
2310 Very complex scan chains might have a dozen or more TAPs:
2311 several in one chip, more in the next, and connecting
2312 to other boards with their own chips and TAPs.
2314 You can display the list with the @command{scan_chain} command.
2315 (Don't confuse this with the list displayed by the @command{targets}
2316 command, presented in the next chapter.
2317 That only displays TAPs for CPUs which are configured as
2319 Here's what the scan chain might look like for a chip more than one TAP:
2322 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2323 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2324 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2325 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2326 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2329 Unfortunately those TAPs can't always be autoconfigured,
2330 because not all devices provide good support for that.
2331 JTAG doesn't require supporting IDCODE instructions, and
2332 chips with JTAG routers may not link TAPs into the chain
2333 until they are told to do so.
2335 The configuration mechanism currently supported by OpenOCD
2336 requires explicit configuration of all TAP devices using
2337 @command{jtag newtap} commands, as detailed later in this chapter.
2338 A command like this would declare one tap and name it @code{chip1.cpu}:
2341 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2344 Each target configuration file lists the TAPs provided
2346 Board configuration files combine all the targets on a board,
2348 Note that @emph{the order in which TAPs are declared is very important.}
2349 It must match the order in the JTAG scan chain, both inside
2350 a single chip and between them.
2351 @xref{FAQ TAP Order}.
2353 For example, the ST Microsystems STR912 chip has
2354 three separate TAPs@footnote{See the ST
2355 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2356 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2357 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2358 To configure those taps, @file{target/str912.cfg}
2359 includes commands something like this:
2362 jtag newtap str912 flash ... params ...
2363 jtag newtap str912 cpu ... params ...
2364 jtag newtap str912 bs ... params ...
2367 Actual config files use a variable instead of literals like
2368 @option{str912}, to support more than one chip of each type.
2369 @xref{Config File Guidelines}.
2371 @deffn Command {jtag names}
2372 Returns the names of all current TAPs in the scan chain.
2373 Use @command{jtag cget} or @command{jtag tapisenabled}
2374 to examine attributes and state of each TAP.
2376 foreach t [jtag names] @{
2377 puts [format "TAP: %s\n" $t]
2382 @deffn Command {scan_chain}
2383 Displays the TAPs in the scan chain configuration,
2385 The set of TAPs listed by this command is fixed by
2386 exiting the OpenOCD configuration stage,
2387 but systems with a JTAG router can
2388 enable or disable TAPs dynamically.
2389 In addition to the enable/disable status, the contents of
2390 each TAP's instruction register can also change.
2393 @c FIXME! "jtag cget" should be able to return all TAP
2394 @c attributes, like "$target_name cget" does for targets.
2396 @c Probably want "jtag eventlist", and a "tap-reset" event
2397 @c (on entry to RESET state).
2402 When TAP objects are declared with @command{jtag newtap},
2403 a @dfn{dotted.name} is created for the TAP, combining the
2404 name of a module (usually a chip) and a label for the TAP.
2405 For example: @code{xilinx.tap}, @code{str912.flash},
2406 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2407 Many other commands use that dotted.name to manipulate or
2408 refer to the TAP. For example, CPU configuration uses the
2409 name, as does declaration of NAND or NOR flash banks.
2411 The components of a dotted name should follow ``C'' symbol
2412 name rules: start with an alphabetic character, then numbers
2413 and underscores are OK; while others (including dots!) are not.
2416 In older code, JTAG TAPs were numbered from 0..N.
2417 This feature is still present.
2418 However its use is highly discouraged, and
2419 should not be relied on; it will be removed by mid-2010.
2420 Update all of your scripts to use TAP names rather than numbers,
2421 by paying attention to the runtime warnings they trigger.
2422 Using TAP numbers in target configuration scripts prevents
2423 reusing those scripts on boards with multiple targets.
2426 @section TAP Declaration Commands
2428 @c shouldn't this be(come) a {Config Command}?
2429 @anchor{jtag newtap}
2430 @deffn Command {jtag newtap} chipname tapname configparams...
2431 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2432 and configured according to the various @var{configparams}.
2434 The @var{chipname} is a symbolic name for the chip.
2435 Conventionally target config files use @code{$_CHIPNAME},
2436 defaulting to the model name given by the chip vendor but
2439 @cindex TAP naming convention
2440 The @var{tapname} reflects the role of that TAP,
2441 and should follow this convention:
2444 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2445 @item @code{cpu} -- The main CPU of the chip, alternatively
2446 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2447 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2448 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2449 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2450 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2451 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2452 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2454 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2455 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2456 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2457 a JTAG TAP; that TAP should be named @code{sdma}.
2460 Every TAP requires at least the following @var{configparams}:
2463 @item @code{-irlen} @var{NUMBER}
2464 @*The length in bits of the
2465 instruction register, such as 4 or 5 bits.
2468 A TAP may also provide optional @var{configparams}:
2471 @item @code{-disable} (or @code{-enable})
2472 @*Use the @code{-disable} parameter to flag a TAP which is not
2473 linked in to the scan chain after a reset using either TRST
2474 or the JTAG state machine's @sc{reset} state.
2475 You may use @code{-enable} to highlight the default state
2476 (the TAP is linked in).
2477 @xref{Enabling and Disabling TAPs}.
2478 @item @code{-expected-id} @var{number}
2479 @*A non-zero @var{number} represents a 32-bit IDCODE
2480 which you expect to find when the scan chain is examined.
2481 These codes are not required by all JTAG devices.
2482 @emph{Repeat the option} as many times as required if more than one
2483 ID code could appear (for example, multiple versions).
2484 Specify @var{number} as zero to suppress warnings about IDCODE
2485 values that were found but not included in the list.
2486 @item @code{-ircapture} @var{NUMBER}
2487 @*The bit pattern loaded by the TAP into the JTAG shift register
2488 on entry to the @sc{ircapture} state, such as 0x01.
2489 JTAG requires the two LSBs of this value to be 01.
2490 By default, @code{-ircapture} and @code{-irmask} are set
2491 up to verify that two-bit value; but you may provide
2492 additional bits, if you know them.
2493 @item @code{-irmask} @var{NUMBER}
2494 @*A mask used with @code{-ircapture}
2495 to verify that instruction scans work correctly.
2496 Such scans are not used by OpenOCD except to verify that
2497 there seems to be no problems with JTAG scan chain operations.
2501 @section Other TAP commands
2503 @c @deffn Command {jtag arp_init-reset}
2504 @c ... more or less "toggle TRST ... and SRST too, what the heck"
2506 @deffn Command {jtag cget} dotted.name @option{-event} name
2507 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2508 At this writing this TAP attribute
2509 mechanism is used only for event handling.
2510 (It is not a direct analogue of the @code{cget}/@code{configure}
2511 mechanism for debugger targets.)
2512 See the next section for information about the available events.
2514 The @code{configure} subcommand assigns an event handler,
2515 a TCL string which is evaluated when the event is triggered.
2516 The @code{cget} subcommand returns that handler.
2524 OpenOCD includes two event mechanisms.
2525 The one presented here applies to all JTAG TAPs.
2526 The other applies to debugger targets,
2527 which are associated with certain TAPs.
2529 The TAP events currently defined are:
2532 @item @b{post-reset}
2533 @* The TAP has just completed a JTAG reset.
2534 The tap may still be in the JTAG @sc{reset} state.
2535 Handlers for these events might perform initialization sequences
2536 such as issuing TCK cycles, TMS sequences to ensure
2537 exit from the ARM SWD mode, and more.
2539 Because the scan chain has not yet been verified, handlers for these events
2540 @emph{should not issue commands which scan the JTAG IR or DR registers}
2541 of any particular target.
2542 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2544 @* The scan chain has been reset and verified.
2545 This handler may enable TAPs as needed.
2546 @item @b{tap-disable}
2547 @* The TAP needs to be disabled. This handler should
2548 implement @command{jtag tapdisable}
2549 by issuing the relevant JTAG commands.
2550 @item @b{tap-enable}
2551 @* The TAP needs to be enabled. This handler should
2552 implement @command{jtag tapenable}
2553 by issuing the relevant JTAG commands.
2556 If you need some action after each JTAG reset, which isn't actually
2557 specific to any TAP (since you can't yet trust the scan chain's
2558 contents to be accurate), you might:
2561 jtag configure CHIP.jrc -event post-reset @{
2562 echo "JTAG Reset done"
2563 ... non-scan jtag operations to be done after reset
2568 @anchor{Enabling and Disabling TAPs}
2569 @section Enabling and Disabling TAPs
2570 @cindex JTAG Route Controller
2573 In some systems, a @dfn{JTAG Route Controller} (JRC)
2574 is used to enable and/or disable specific JTAG TAPs.
2575 Many ARM based chips from Texas Instruments include
2576 an ``ICEpick'' module, which is a JRC.
2577 Such chips include DaVinci and OMAP3 processors.
2579 A given TAP may not be visible until the JRC has been
2580 told to link it into the scan chain; and if the JRC
2581 has been told to unlink that TAP, it will no longer
2583 Such routers address problems that JTAG ``bypass mode''
2587 @item The scan chain can only go as fast as its slowest TAP.
2588 @item Having many TAPs slows instruction scans, since all
2589 TAPs receive new instructions.
2590 @item TAPs in the scan chain must be powered up, which wastes
2591 power and prevents debugging some power management mechanisms.
2594 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2595 as implied by the existence of JTAG routers.
2596 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2597 does include a kind of JTAG router functionality.
2599 @c (a) currently the event handlers don't seem to be able to
2600 @c fail in a way that could lead to no-change-of-state.
2602 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2603 shown below, and is implemented using TAP event handlers.
2604 So for example, when defining a TAP for a CPU connected to
2605 a JTAG router, your @file{target.cfg} file
2606 should define TAP event handlers using
2607 code that looks something like this:
2610 jtag configure CHIP.cpu -event tap-enable @{
2611 ... jtag operations using CHIP.jrc
2613 jtag configure CHIP.cpu -event tap-disable @{
2614 ... jtag operations using CHIP.jrc
2618 Then you might want that CPU's TAP enabled almost all the time:
2621 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2624 Note how that particular setup event handler declaration
2625 uses quotes to evaluate @code{$CHIP} when the event is configured.
2626 Using brackets @{ @} would cause it to be evaluated later,
2627 at runtime, when it might have a different value.
2629 @deffn Command {jtag tapdisable} dotted.name
2630 If necessary, disables the tap
2631 by sending it a @option{tap-disable} event.
2632 Returns the string "1" if the tap
2633 specified by @var{dotted.name} is enabled,
2634 and "0" if it is disabled.
2637 @deffn Command {jtag tapenable} dotted.name
2638 If necessary, enables the tap
2639 by sending it a @option{tap-enable} event.
2640 Returns the string "1" if the tap
2641 specified by @var{dotted.name} is enabled,
2642 and "0" if it is disabled.
2645 @deffn Command {jtag tapisenabled} dotted.name
2646 Returns the string "1" if the tap
2647 specified by @var{dotted.name} is enabled,
2648 and "0" if it is disabled.
2651 Humans will find the @command{scan_chain} command more helpful
2652 for querying the state of the JTAG taps.
2656 @node CPU Configuration
2657 @chapter CPU Configuration
2660 This chapter discusses how to set up GDB debug targets for CPUs.
2661 You can also access these targets without GDB
2662 (@pxref{Architecture and Core Commands},
2663 and @ref{Target State handling}) and
2664 through various kinds of NAND and NOR flash commands.
2665 If you have multiple CPUs you can have multiple such targets.
2667 We'll start by looking at how to examine the targets you have,
2668 then look at how to add one more target and how to configure it.
2670 @section Target List
2671 @cindex target, current
2672 @cindex target, list
2674 All targets that have been set up are part of a list,
2675 where each member has a name.
2676 That name should normally be the same as the TAP name.
2677 You can display the list with the @command{targets}
2679 This display often has only one CPU; here's what it might
2680 look like with more than one:
2682 TargetName Type Endian TapName State
2683 -- ------------------ ---------- ------ ------------------ ------------
2684 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2685 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2688 One member of that list is the @dfn{current target}, which
2689 is implicitly referenced by many commands.
2690 It's the one marked with a @code{*} near the target name.
2691 In particular, memory addresses often refer to the address
2692 space seen by that current target.
2693 Commands like @command{mdw} (memory display words)
2694 and @command{flash erase_address} (erase NOR flash blocks)
2695 are examples; and there are many more.
2697 Several commands let you examine the list of targets:
2699 @deffn Command {target count}
2700 @emph{Note: target numbers are deprecated; don't use them.
2701 They will be removed shortly after August 2010, including this command.
2702 Iterate target using @command{target names}, not by counting.}
2704 Returns the number of targets, @math{N}.
2705 The highest numbered target is @math{N - 1}.
2707 set c [target count]
2708 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2709 # Assuming you have created this function
2710 print_target_details $x
2715 @deffn Command {target current}
2716 Returns the name of the current target.
2719 @deffn Command {target names}
2720 Lists the names of all current targets in the list.
2722 foreach t [target names] @{
2723 puts [format "Target: %s\n" $t]
2728 @deffn Command {target number} number
2729 @emph{Note: target numbers are deprecated; don't use them.
2730 They will be removed shortly after August 2010, including this command.}
2732 The list of targets is numbered starting at zero.
2733 This command returns the name of the target at index @var{number}.
2735 set thename [target number $x]
2736 puts [format "Target %d is: %s\n" $x $thename]
2740 @c yep, "target list" would have been better.
2741 @c plus maybe "target setdefault".
2743 @deffn Command targets [name]
2744 @emph{Note: the name of this command is plural. Other target
2745 command names are singular.}
2747 With no parameter, this command displays a table of all known
2748 targets in a user friendly form.
2750 With a parameter, this command sets the current target to
2751 the given target with the given @var{name}; this is
2752 only relevant on boards which have more than one target.
2755 @section Target CPU Types and Variants
2760 Each target has a @dfn{CPU type}, as shown in the output of
2761 the @command{targets} command. You need to specify that type
2762 when calling @command{target create}.
2763 The CPU type indicates more than just the instruction set.
2764 It also indicates how that instruction set is implemented,
2765 what kind of debug support it integrates,
2766 whether it has an MMU (and if so, what kind),
2767 what core-specific commands may be available
2768 (@pxref{Architecture and Core Commands}),
2771 For some CPU types, OpenOCD also defines @dfn{variants} which
2772 indicate differences that affect their handling.
2773 For example, a particular implementation bug might need to be
2774 worked around in some chip versions.
2776 It's easy to see what target types are supported,
2777 since there's a command to list them.
2778 However, there is currently no way to list what target variants
2779 are supported (other than by reading the OpenOCD source code).
2781 @anchor{target types}
2782 @deffn Command {target types}
2783 Lists all supported target types.
2784 At this writing, the supported CPU types and variants are:
2787 @item @code{arm11} -- this is a generation of ARMv6 cores
2788 @item @code{arm720t} -- this is an ARMv4 core
2789 @item @code{arm7tdmi} -- this is an ARMv4 core
2790 @item @code{arm920t} -- this is an ARMv5 core
2791 @item @code{arm926ejs} -- this is an ARMv5 core
2792 @item @code{arm966e} -- this is an ARMv5 core
2793 @item @code{arm9tdmi} -- this is an ARMv4 core
2794 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2795 (Support for this is preliminary and incomplete.)
2796 @item @code{cortex_a8} -- this is an ARMv7 core
2797 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2798 compact Thumb2 instruction set. It supports one variant:
2800 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2801 This will cause OpenOCD to use a software reset rather than asserting
2802 SRST, to avoid a issue with clearing the debug registers.
2803 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2804 be detected and the normal reset behaviour used.
2806 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2807 @item @code{feroceon} -- resembles arm926
2808 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2810 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2811 provide a functional SRST line on the EJTAG connector. This causes
2812 OpenOCD to instead use an EJTAG software reset command to reset the
2814 You still need to enable @option{srst} on the @command{reset_config}
2815 command to enable OpenOCD hardware reset functionality.
2817 @item @code{xscale} -- this is actually an architecture,
2818 not a CPU type. It is based on the ARMv5 architecture.
2819 There are several variants defined:
2821 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2822 @code{pxa27x} ... instruction register length is 7 bits
2823 @item @code{pxa250}, @code{pxa255},
2824 @code{pxa26x} ... instruction register length is 5 bits
2829 To avoid being confused by the variety of ARM based cores, remember
2830 this key point: @emph{ARM is a technology licencing company}.
2831 (See: @url{http://www.arm.com}.)
2832 The CPU name used by OpenOCD will reflect the CPU design that was
2833 licenced, not a vendor brand which incorporates that design.
2834 Name prefixes like arm7, arm9, arm11, and cortex
2835 reflect design generations;
2836 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2837 reflect an architecture version implemented by a CPU design.
2839 @anchor{Target Configuration}
2840 @section Target Configuration
2842 Before creating a ``target'', you must have added its TAP to the scan chain.
2843 When you've added that TAP, you will have a @code{dotted.name}
2844 which is used to set up the CPU support.
2845 The chip-specific configuration file will normally configure its CPU(s)
2846 right after it adds all of the chip's TAPs to the scan chain.
2848 Although you can set up a target in one step, it's often clearer if you
2849 use shorter commands and do it in two steps: create it, then configure
2851 All operations on the target after it's created will use a new
2852 command, created as part of target creation.
2854 The two main things to configure after target creation are
2855 a work area, which usually has target-specific defaults even
2856 if the board setup code overrides them later;
2857 and event handlers (@pxref{Target Events}), which tend
2858 to be much more board-specific.
2859 The key steps you use might look something like this
2862 target create MyTarget cortex_m3 -chain-position mychip.cpu
2863 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2864 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2865 $MyTarget configure -event reset-init @{ myboard_reinit @}
2868 You should specify a working area if you can; typically it uses some
2870 Such a working area can speed up many things, including bulk
2871 writes to target memory;
2872 flash operations like checking to see if memory needs to be erased;
2873 GDB memory checksumming;
2877 On more complex chips, the work area can become
2878 inaccessible when application code
2879 (such as an operating system)
2880 enables or disables the MMU.
2881 For example, the particular MMU context used to acess the virtual
2882 address will probably matter ... and that context might not have
2883 easy access to other addresses needed.
2884 At this writing, OpenOCD doesn't have much MMU intelligence.
2887 It's often very useful to define a @code{reset-init} event handler.
2888 For systems that are normally used with a boot loader,
2889 common tasks include updating clocks and initializing memory
2891 That may be needed to let you write the boot loader into flash,
2892 in order to ``de-brick'' your board; or to load programs into
2893 external DDR memory without having run the boot loader.
2895 @deffn Command {target create} target_name type configparams...
2896 This command creates a GDB debug target that refers to a specific JTAG tap.
2897 It enters that target into a list, and creates a new
2898 command (@command{@var{target_name}}) which is used for various
2899 purposes including additional configuration.
2902 @item @var{target_name} ... is the name of the debug target.
2903 By convention this should be the same as the @emph{dotted.name}
2904 of the TAP associated with this target, which must be specified here
2905 using the @code{-chain-position @var{dotted.name}} configparam.
2907 This name is also used to create the target object command,
2908 referred to here as @command{$target_name},
2909 and in other places the target needs to be identified.
2910 @item @var{type} ... specifies the target type. @xref{target types}.
2911 @item @var{configparams} ... all parameters accepted by
2912 @command{$target_name configure} are permitted.
2913 If the target is big-endian, set it here with @code{-endian big}.
2914 If the variant matters, set it here with @code{-variant}.
2916 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2920 @deffn Command {$target_name configure} configparams...
2921 The options accepted by this command may also be
2922 specified as parameters to @command{target create}.
2923 Their values can later be queried one at a time by
2924 using the @command{$target_name cget} command.
2926 @emph{Warning:} changing some of these after setup is dangerous.
2927 For example, moving a target from one TAP to another;
2928 and changing its endianness or variant.
2932 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2933 used to access this target.
2935 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2936 whether the CPU uses big or little endian conventions
2938 @item @code{-event} @var{event_name} @var{event_body} --
2939 @xref{Target Events}.
2940 Note that this updates a list of named event handlers.
2941 Calling this twice with two different event names assigns
2942 two different handlers, but calling it twice with the
2943 same event name assigns only one handler.
2945 @item @code{-variant} @var{name} -- specifies a variant of the target,
2946 which OpenOCD needs to know about.
2948 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2949 whether the work area gets backed up; by default,
2950 @emph{it is not backed up.}
2951 When possible, use a working_area that doesn't need to be backed up,
2952 since performing a backup slows down operations.
2953 For example, the beginning of an SRAM block is likely to
2954 be used by most build systems, but the end is often unused.
2956 @item @code{-work-area-size} @var{size} -- specify/set the work area
2958 @item @code{-work-area-phys} @var{address} -- set the work area
2959 base @var{address} to be used when no MMU is active.
2961 @item @code{-work-area-virt} @var{address} -- set the work area
2962 base @var{address} to be used when an MMU is active.
2967 @section Other $target_name Commands
2968 @cindex object command
2970 The Tcl/Tk language has the concept of object commands,
2971 and OpenOCD adopts that same model for targets.
2973 A good Tk example is a on screen button.
2974 Once a button is created a button
2975 has a name (a path in Tk terms) and that name is useable as a first
2976 class command. For example in Tk, one can create a button and later
2977 configure it like this:
2981 button .foobar -background red -command @{ foo @}
2983 .foobar configure -foreground blue
2985 set x [.foobar cget -background]
2987 puts [format "The button is %s" $x]
2990 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2991 button, and its object commands are invoked the same way.
2994 str912.cpu mww 0x1234 0x42
2995 omap3530.cpu mww 0x5555 123
2998 The commands supported by OpenOCD target objects are:
3000 @deffn Command {$target_name arp_examine}
3001 @deffnx Command {$target_name arp_halt}
3002 @deffnx Command {$target_name arp_poll}
3003 @deffnx Command {$target_name arp_reset}
3004 @deffnx Command {$target_name arp_waitstate}
3005 Internal OpenOCD scripts (most notably @file{startup.tcl})
3006 use these to deal with specific reset cases.
3007 They are not otherwise documented here.
3010 @deffn Command {$target_name array2mem} arrayname width address count
3011 @deffnx Command {$target_name mem2array} arrayname width address count
3012 These provide an efficient script-oriented interface to memory.
3013 The @code{array2mem} primitive writes bytes, halfwords, or words;
3014 while @code{mem2array} reads them.
3015 In both cases, the TCL side uses an array, and
3016 the target side uses raw memory.
3018 The efficiency comes from enabling the use of
3019 bulk JTAG data transfer operations.
3020 The script orientation comes from working with data
3021 values that are packaged for use by TCL scripts;
3022 @command{mdw} type primitives only print data they retrieve,
3023 and neither store nor return those values.
3026 @item @var{arrayname} ... is the name of an array variable
3027 @item @var{width} ... is 8/16/32 - indicating the memory access size
3028 @item @var{address} ... is the target memory address
3029 @item @var{count} ... is the number of elements to process
3033 @deffn Command {$target_name cget} queryparm
3034 Each configuration parameter accepted by
3035 @command{$target_name configure}
3036 can be individually queried, to return its current value.
3037 The @var{queryparm} is a parameter name
3038 accepted by that command, such as @code{-work-area-phys}.
3039 There are a few special cases:
3042 @item @code{-event} @var{event_name} -- returns the handler for the
3043 event named @var{event_name}.
3044 This is a special case because setting a handler requires
3046 @item @code{-type} -- returns the target type.
3047 This is a special case because this is set using
3048 @command{target create} and can't be changed
3049 using @command{$target_name configure}.
3052 For example, if you wanted to summarize information about
3053 all the targets you might use something like this:
3056 foreach name [target names] @{
3057 set y [$name cget -endian]
3058 set z [$name cget -type]
3059 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3065 @anchor{target curstate}
3066 @deffn Command {$target_name curstate}
3067 Displays the current target state:
3068 @code{debug-running},
3071 @code{running}, or @code{unknown}.
3072 (Also, @pxref{Event Polling}.)
3075 @deffn Command {$target_name eventlist}
3076 Displays a table listing all event handlers
3077 currently associated with this target.
3078 @xref{Target Events}.
3081 @deffn Command {$target_name invoke-event} event_name
3082 Invokes the handler for the event named @var{event_name}.
3083 (This is primarily intended for use by OpenOCD framework
3084 code, for example by the reset code in @file{startup.tcl}.)
3087 @deffn Command {$target_name mdw} addr [count]
3088 @deffnx Command {$target_name mdh} addr [count]
3089 @deffnx Command {$target_name mdb} addr [count]
3090 Display contents of address @var{addr}, as
3091 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3092 or 8-bit bytes (@command{mdb}).
3093 If @var{count} is specified, displays that many units.
3094 (If you want to manipulate the data instead of displaying it,
3095 see the @code{mem2array} primitives.)
3098 @deffn Command {$target_name mww} addr word
3099 @deffnx Command {$target_name mwh} addr halfword
3100 @deffnx Command {$target_name mwb} addr byte
3101 Writes the specified @var{word} (32 bits),
3102 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3103 at the specified address @var{addr}.
3106 @anchor{Target Events}
3107 @section Target Events
3108 @cindex target events
3110 At various times, certain things can happen, or you want them to happen.
3113 @item What should happen when GDB connects? Should your target reset?
3114 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3115 @item During reset, do you need to write to certain memory locations
3116 to set up system clocks or
3117 to reconfigure the SDRAM?
3120 All of the above items can be addressed by target event handlers.
3121 These are set up by @command{$target_name configure -event} or
3122 @command{target create ... -event}.
3124 The programmer's model matches the @code{-command} option used in Tcl/Tk
3125 buttons and events. The two examples below act the same, but one creates
3126 and invokes a small procedure while the other inlines it.
3129 proc my_attach_proc @{ @} @{
3133 mychip.cpu configure -event gdb-attach my_attach_proc
3134 mychip.cpu configure -event gdb-attach @{
3140 The following target events are defined:
3143 @item @b{debug-halted}
3144 @* The target has halted for debug reasons (i.e.: breakpoint)
3145 @item @b{debug-resumed}
3146 @* The target has resumed (i.e.: gdb said run)
3147 @item @b{early-halted}
3148 @* Occurs early in the halt process
3150 @item @b{examine-end}
3151 @* Currently not used (goal: when JTAG examine completes)
3152 @item @b{examine-start}
3153 @* Currently not used (goal: when JTAG examine starts)
3155 @item @b{gdb-attach}
3156 @* When GDB connects
3157 @item @b{gdb-detach}
3158 @* When GDB disconnects
3160 @* When the target has halted and GDB is not doing anything (see early halt)
3161 @item @b{gdb-flash-erase-start}
3162 @* Before the GDB flash process tries to erase the flash
3163 @item @b{gdb-flash-erase-end}
3164 @* After the GDB flash process has finished erasing the flash
3165 @item @b{gdb-flash-write-start}
3166 @* Before GDB writes to the flash
3167 @item @b{gdb-flash-write-end}
3168 @* After GDB writes to the flash
3170 @* Before the target steps, gdb is trying to start/resume the target
3172 @* The target has halted
3174 @item @b{old-gdb_program_config}
3175 @* DO NOT USE THIS: Used internally
3176 @item @b{old-pre_resume}
3177 @* DO NOT USE THIS: Used internally
3179 @item @b{reset-assert-pre}
3180 @* Issued as part of @command{reset} processing
3181 after SRST and/or TRST were activated and deactivated,
3182 but before SRST alone is re-asserted on the tap.
3183 @item @b{reset-assert-post}
3184 @* Issued as part of @command{reset} processing
3185 when SRST is asserted on the tap.
3186 @item @b{reset-deassert-pre}
3187 @* Issued as part of @command{reset} processing
3188 when SRST is about to be released on the tap.
3189 @item @b{reset-deassert-post}
3190 @* Issued as part of @command{reset} processing
3191 when SRST has been released on the tap.
3193 @* Issued as the final step in @command{reset} processing.
3195 @item @b{reset-halt-post}
3196 @* Currently not used
3197 @item @b{reset-halt-pre}
3198 @* Currently not used
3200 @item @b{reset-init}
3201 @* Used by @b{reset init} command for board-specific initialization.
3202 This event fires after @emph{reset-deassert-post}.
3204 This is where you would configure PLLs and clocking, set up DRAM so
3205 you can download programs that don't fit in on-chip SRAM, set up pin
3206 multiplexing, and so on.
3207 (You may be able to switch to a fast JTAG clock rate here, after
3208 the target clocks are fully set up.)
3209 @item @b{reset-start}
3210 @* Issued as part of @command{reset} processing
3211 before either SRST or TRST are activated.
3213 This is the most robust place to switch to a low JTAG clock rate, if
3214 SRST disables PLLs needed to use a fast clock.
3216 @item @b{reset-wait-pos}
3217 @* Currently not used
3218 @item @b{reset-wait-pre}
3219 @* Currently not used
3221 @item @b{resume-start}
3222 @* Before any target is resumed
3223 @item @b{resume-end}
3224 @* After all targets have resumed
3228 @* Target has resumed
3232 @node Flash Commands
3233 @chapter Flash Commands
3235 OpenOCD has different commands for NOR and NAND flash;
3236 the ``flash'' command works with NOR flash, while
3237 the ``nand'' command works with NAND flash.
3238 This partially reflects different hardware technologies:
3239 NOR flash usually supports direct CPU instruction and data bus access,
3240 while data from a NAND flash must be copied to memory before it can be
3241 used. (SPI flash must also be copied to memory before use.)
3242 However, the documentation also uses ``flash'' as a generic term;
3243 for example, ``Put flash configuration in board-specific files''.
3247 @item Configure via the command @command{flash bank}
3248 @* Do this in a board-specific configuration file,
3249 passing parameters as needed by the driver.
3250 @item Operate on the flash via @command{flash subcommand}
3251 @* Often commands to manipulate the flash are typed by a human, or run
3252 via a script in some automated way. Common tasks include writing a
3253 boot loader, operating system, or other data.
3255 @* Flashing via GDB requires the flash be configured via ``flash
3256 bank'', and the GDB flash features be enabled.
3257 @xref{GDB Configuration}.
3260 Many CPUs have the ablity to ``boot'' from the first flash bank.
3261 This means that misprogramming that bank can ``brick'' a system,
3262 so that it can't boot.
3263 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3264 board by (re)installing working boot firmware.
3266 @anchor{NOR Configuration}
3267 @section Flash Configuration Commands
3268 @cindex flash configuration
3270 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3271 Configures a flash bank which provides persistent storage
3272 for addresses from @math{base} to @math{base + size - 1}.
3273 These banks will often be visible to GDB through the target's memory map.
3274 In some cases, configuring a flash bank will activate extra commands;
3275 see the driver-specific documentation.
3278 @item @var{driver} ... identifies the controller driver
3279 associated with the flash bank being declared.
3280 This is usually @code{cfi} for external flash, or else
3281 the name of a microcontroller with embedded flash memory.
3282 @xref{Flash Driver List}.
3283 @item @var{base} ... Base address of the flash chip.
3284 @item @var{size} ... Size of the chip, in bytes.
3285 For some drivers, this value is detected from the hardware.
3286 @item @var{chip_width} ... Width of the flash chip, in bytes;
3287 ignored for most microcontroller drivers.
3288 @item @var{bus_width} ... Width of the data bus used to access the
3289 chip, in bytes; ignored for most microcontroller drivers.
3290 @item @var{target} ... Names the target used to issue
3291 commands to the flash controller.
3292 @comment Actually, it's currently a controller-specific parameter...
3293 @item @var{driver_options} ... drivers may support, or require,
3294 additional parameters. See the driver-specific documentation
3295 for more information.
3298 This command is not available after OpenOCD initialization has completed.
3299 Use it in board specific configuration files, not interactively.
3303 @comment the REAL name for this command is "ocd_flash_banks"
3304 @comment less confusing would be: "flash list" (like "nand list")
3305 @deffn Command {flash banks}
3306 Prints a one-line summary of each device declared
3307 using @command{flash bank}, numbered from zero.
3308 Note that this is the @emph{plural} form;
3309 the @emph{singular} form is a very different command.
3312 @deffn Command {flash probe} num
3313 Identify the flash, or validate the parameters of the configured flash. Operation
3314 depends on the flash type.
3315 The @var{num} parameter is a value shown by @command{flash banks}.
3316 Most flash commands will implicitly @emph{autoprobe} the bank;
3317 flash drivers can distinguish between probing and autoprobing,
3318 but most don't bother.
3321 @section Erasing, Reading, Writing to Flash
3322 @cindex flash erasing
3323 @cindex flash reading
3324 @cindex flash writing
3325 @cindex flash programming
3327 One feature distinguishing NOR flash from NAND or serial flash technologies
3328 is that for read access, it acts exactly like any other addressible memory.
3329 This means you can use normal memory read commands like @command{mdw} or
3330 @command{dump_image} with it, with no special @command{flash} subcommands.
3331 @xref{Memory access}, and @ref{Image access}.
3333 Write access works differently. Flash memory normally needs to be erased
3334 before it's written. Erasing a sector turns all of its bits to ones, and
3335 writing can turn ones into zeroes. This is why there are special commands
3336 for interactive erasing and writing, and why GDB needs to know which parts
3337 of the address space hold NOR flash memory.
3340 Most of these erase and write commands leverage the fact that NOR flash
3341 chips consume target address space. They implicitly refer to the current
3342 JTAG target, and map from an address in that target's address space
3343 back to a flash bank.
3344 @comment In May 2009, those mappings may fail if any bank associated
3345 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3346 A few commands use abstract addressing based on bank and sector numbers,
3347 and don't depend on searching the current target and its address space.
3348 Avoid confusing the two command models.
3351 Some flash chips implement software protection against accidental writes,
3352 since such buggy writes could in some cases ``brick'' a system.
3353 For such systems, erasing and writing may require sector protection to be
3355 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3356 and AT91SAM7 on-chip flash.
3357 @xref{flash protect}.
3359 @anchor{flash erase_sector}
3360 @deffn Command {flash erase_sector} num first last
3361 Erase sectors in bank @var{num}, starting at sector @var{first}
3362 up to and including @var{last}.
3363 Sector numbering starts at 0.
3364 Providing a @var{last} sector of @option{last}
3365 specifies "to the end of the flash bank".
3366 The @var{num} parameter is a value shown by @command{flash banks}.
3369 @deffn Command {flash erase_address} address length
3370 Erase sectors starting at @var{address} for @var{length} bytes.
3371 The flash bank to use is inferred from the @var{address}, and
3372 the specified length must stay within that bank.
3373 As a special case, when @var{length} is zero and @var{address} is
3374 the start of the bank, the whole flash is erased.
3377 @deffn Command {flash fillw} address word length
3378 @deffnx Command {flash fillh} address halfword length
3379 @deffnx Command {flash fillb} address byte length
3380 Fills flash memory with the specified @var{word} (32 bits),
3381 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3382 starting at @var{address} and continuing
3383 for @var{length} units (word/halfword/byte).
3384 No erasure is done before writing; when needed, that must be done
3385 before issuing this command.
3386 Writes are done in blocks of up to 1024 bytes, and each write is
3387 verified by reading back the data and comparing it to what was written.
3388 The flash bank to use is inferred from the @var{address} of
3389 each block, and the specified length must stay within that bank.
3391 @comment no current checks for errors if fill blocks touch multiple banks!
3393 @anchor{flash write_bank}
3394 @deffn Command {flash write_bank} num filename offset
3395 Write the binary @file{filename} to flash bank @var{num},
3396 starting at @var{offset} bytes from the beginning of the bank.
3397 The @var{num} parameter is a value shown by @command{flash banks}.
3400 @anchor{flash write_image}
3401 @deffn Command {flash write_image} [erase] filename [offset] [type]
3402 Write the image @file{filename} to the current target's flash bank(s).
3403 A relocation @var{offset} may be specified, in which case it is added
3404 to the base address for each section in the image.
3405 The file [@var{type}] can be specified
3406 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3407 @option{elf} (ELF file), @option{s19} (Motorola s19).
3408 @option{mem}, or @option{builder}.
3409 The relevant flash sectors will be erased prior to programming
3410 if the @option{erase} parameter is given.
3411 The flash bank to use is inferred from the @var{address} of
3415 @section Other Flash commands
3416 @cindex flash protection
3418 @deffn Command {flash erase_check} num
3419 Check erase state of sectors in flash bank @var{num},
3420 and display that status.
3421 The @var{num} parameter is a value shown by @command{flash banks}.
3422 This is the only operation that
3423 updates the erase state information displayed by @option{flash info}. That means you have
3424 to issue a @command{flash erase_check} command after erasing or programming the device
3425 to get updated information.
3426 (Code execution may have invalidated any state records kept by OpenOCD.)
3429 @deffn Command {flash info} num
3430 Print info about flash bank @var{num}
3431 The @var{num} parameter is a value shown by @command{flash banks}.
3432 The information includes per-sector protect status.
3435 @anchor{flash protect}
3436 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3437 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3438 in flash bank @var{num}, starting at sector @var{first}
3439 and continuing up to and including @var{last}.
3440 Providing a @var{last} sector of @option{last}
3441 specifies "to the end of the flash bank".
3442 The @var{num} parameter is a value shown by @command{flash banks}.
3445 @deffn Command {flash protect_check} num
3446 Check protection state of sectors in flash bank @var{num}.
3447 The @var{num} parameter is a value shown by @command{flash banks}.
3448 @comment @option{flash erase_sector} using the same syntax.
3451 @anchor{Flash Driver List}
3452 @section Flash Drivers, Options, and Commands
3453 As noted above, the @command{flash bank} command requires a driver name,
3454 and allows driver-specific options and behaviors.
3455 Some drivers also activate driver-specific commands.
3457 @subsection External Flash
3459 @deffn {Flash Driver} cfi
3460 @cindex Common Flash Interface
3462 The ``Common Flash Interface'' (CFI) is the main standard for
3463 external NOR flash chips, each of which connects to a
3464 specific external chip select on the CPU.
3465 Frequently the first such chip is used to boot the system.
3466 Your board's @code{reset-init} handler might need to
3467 configure additional chip selects using other commands (like: @command{mww} to
3468 configure a bus and its timings) , or
3469 perhaps configure a GPIO pin that controls the ``write protect'' pin
3471 The CFI driver can use a target-specific working area to significantly
3474 The CFI driver can accept the following optional parameters, in any order:
3477 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3478 like AM29LV010 and similar types.
3479 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3482 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3483 wide on a sixteen bit bus:
3486 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3487 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3489 @c "cfi part_id" disabled
3492 @subsection Internal Flash (Microcontrollers)
3494 @deffn {Flash Driver} aduc702x
3495 The ADUC702x analog microcontrollers from Analog Devices
3496 include internal flash and use ARM7TDMI cores.
3497 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3498 The setup command only requires the @var{target} argument
3499 since all devices in this family have the same memory layout.
3502 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3506 @deffn {Flash Driver} at91sam3
3508 All members of the AT91SAM3 microcontroller family from
3509 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3510 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3511 that the driver was orginaly developed and tested using the
3512 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3513 the family was cribbed from the data sheet. @emph{Note to future
3514 readers/updaters: Please remove this worrysome comment after other
3515 chips are confirmed.}
3517 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3518 have one flash bank. In all cases the flash banks are at
3519 the following fixed locations:
3522 # Flash bank 0 - all chips
3523 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3524 # Flash bank 1 - only 256K chips
3525 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3528 Internally, the AT91SAM3 flash memory is organized as follows.
3529 Unlike the AT91SAM7 chips, these are not used as parameters
3530 to the @command{flash bank} command:
3533 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3534 @item @emph{Bank Size:} 128K/64K Per flash bank
3535 @item @emph{Sectors:} 16 or 8 per bank
3536 @item @emph{SectorSize:} 8K Per Sector
3537 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3540 The AT91SAM3 driver adds some additional commands:
3542 @deffn Command {at91sam3 gpnvm}
3543 @deffnx Command {at91sam3 gpnvm clear} number
3544 @deffnx Command {at91sam3 gpnvm set} number
3545 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3546 With no parameters, @command{show} or @command{show all},
3547 shows the status of all GPNVM bits.
3548 With @command{show} @var{number}, displays that bit.
3550 With @command{set} @var{number} or @command{clear} @var{number},
3551 modifies that GPNVM bit.
3554 @deffn Command {at91sam3 info}
3555 This command attempts to display information about the AT91SAM3
3556 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3557 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3558 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3559 various clock configuration registers and attempts to display how it
3560 believes the chip is configured. By default, the SLOWCLK is assumed to
3561 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3564 @deffn Command {at91sam3 slowclk} [value]
3565 This command shows/sets the slow clock frequency used in the
3566 @command{at91sam3 info} command calculations above.
3570 @deffn {Flash Driver} at91sam7
3571 All members of the AT91SAM7 microcontroller family from Atmel include
3572 internal flash and use ARM7TDMI cores. The driver automatically
3573 recognizes a number of these chips using the chip identification
3574 register, and autoconfigures itself.
3577 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3580 For chips which are not recognized by the controller driver, you must
3581 provide additional parameters in the following order:
3584 @item @var{chip_model} ... label used with @command{flash info}
3586 @item @var{sectors_per_bank}
3587 @item @var{pages_per_sector}
3588 @item @var{pages_size}
3589 @item @var{num_nvm_bits}
3590 @item @var{freq_khz} ... required if an external clock is provided,
3591 optional (but recommended) when the oscillator frequency is known
3594 It is recommended that you provide zeroes for all of those values
3595 except the clock frequency, so that everything except that frequency
3596 will be autoconfigured.
3597 Knowing the frequency helps ensure correct timings for flash access.
3599 The flash controller handles erases automatically on a page (128/256 byte)
3600 basis, so explicit erase commands are not necessary for flash programming.
3601 However, there is an ``EraseAll`` command that can erase an entire flash
3602 plane (of up to 256KB), and it will be used automatically when you issue
3603 @command{flash erase_sector} or @command{flash erase_address} commands.
3605 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3606 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3607 bit for the processor. Each processor has a number of such bits,
3608 used for controlling features such as brownout detection (so they
3609 are not truly general purpose).
3611 This assumes that the first flash bank (number 0) is associated with
3612 the appropriate at91sam7 target.
3617 @deffn {Flash Driver} avr
3618 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3619 @emph{The current implementation is incomplete.}
3620 @comment - defines mass_erase ... pointless given flash_erase_address
3623 @deffn {Flash Driver} ecosflash
3624 @emph{No idea what this is...}
3625 The @var{ecosflash} driver defines one mandatory parameter,
3626 the name of a modules of target code which is downloaded
3630 @deffn {Flash Driver} lpc2000
3631 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3632 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3635 There are LPC2000 devices which are not supported by the @var{lpc2000}
3637 The LPC2888 is supported by the @var{lpc288x} driver.
3638 The LPC29xx family is supported by the @var{lpc2900} driver.
3641 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3642 which must appear in the following order:
3645 @item @var{variant} ... required, may be
3646 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3647 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3648 or @var{lpc1700} (LPC175x and LPC176x)
3649 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3650 at which the core is running
3651 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3652 telling the driver to calculate a valid checksum for the exception vector table.
3655 LPC flashes don't require the chip and bus width to be specified.
3658 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3659 lpc2000_v2 14765 calc_checksum
3662 @deffn {Command} {lpc2000 part_id} bank
3663 Displays the four byte part identifier associated with
3664 the specified flash @var{bank}.
3668 @deffn {Flash Driver} lpc288x
3669 The LPC2888 microcontroller from NXP needs slightly different flash
3670 support from its lpc2000 siblings.
3671 The @var{lpc288x} driver defines one mandatory parameter,
3672 the programming clock rate in Hz.
3673 LPC flashes don't require the chip and bus width to be specified.
3676 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3680 @deffn {Flash Driver} lpc2900
3681 This driver supports the LPC29xx ARM968E based microcontroller family
3684 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3685 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3686 sector layout are auto-configured by the driver.
3687 The driver has one additional mandatory parameter: The CPU clock rate
3688 (in kHz) at the time the flash operations will take place. Most of the time this
3689 will not be the crystal frequency, but a higher PLL frequency. The
3690 @code{reset-init} event handler in the board script is usually the place where
3693 The driver rejects flashless devices (currently the LPC2930).
3695 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3696 It must be handled much more like NAND flash memory, and will therefore be
3697 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3699 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3700 sector needs to be erased or programmed, it is automatically unprotected.
3701 What is shown as protection status in the @code{flash info} command, is
3702 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3703 sector from ever being erased or programmed again. As this is an irreversible
3704 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3705 and not by the standard @code{flash protect} command.
3707 Example for a 125 MHz clock frequency:
3709 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3712 Some @code{lpc2900}-specific commands are defined. In the following command list,
3713 the @var{bank} parameter is the bank number as obtained by the
3714 @code{flash banks} command.
3716 @deffn Command {lpc2900 signature} bank
3717 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3718 content. This is a hardware feature of the flash block, hence the calculation is
3719 very fast. You may use this to verify the content of a programmed device against
3724 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3728 @deffn Command {lpc2900 read_custom} bank filename
3729 Reads the 912 bytes of customer information from the flash index sector, and
3730 saves it to a file in binary format.
3733 lpc2900 read_custom 0 /path_to/customer_info.bin
3737 The index sector of the flash is a @emph{write-only} sector. It cannot be
3738 erased! In order to guard against unintentional write access, all following
3739 commands need to be preceeded by a successful call to the @code{password}
3742 @deffn Command {lpc2900 password} bank password
3743 You need to use this command right before each of the following commands:
3744 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3745 @code{lpc2900 secure_jtag}.
3747 The password string is fixed to "I_know_what_I_am_doing".
3750 lpc2900 password 0 I_know_what_I_am_doing
3751 Potentially dangerous operation allowed in next command!
3755 @deffn Command {lpc2900 write_custom} bank filename type
3756 Writes the content of the file into the customer info space of the flash index
3757 sector. The filetype can be specified with the @var{type} field. Possible values
3758 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3759 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3760 contain a single section, and the contained data length must be exactly
3762 @quotation Attention
3763 This cannot be reverted! Be careful!
3767 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3771 @deffn Command {lpc2900 secure_sector} bank first last
3772 Secures the sector range from @var{first} to @var{last} (including) against
3773 further program and erase operations. The sector security will be effective
3774 after the next power cycle.
3775 @quotation Attention
3776 This cannot be reverted! Be careful!
3778 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3781 lpc2900 secure_sector 0 1 1
3783 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3784 # 0: 0x00000000 (0x2000 8kB) not protected
3785 # 1: 0x00002000 (0x2000 8kB) protected
3786 # 2: 0x00004000 (0x2000 8kB) not protected
3790 @deffn Command {lpc2900 secure_jtag} bank
3791 Irreversibly disable the JTAG port. The new JTAG security setting will be
3792 effective after the next power cycle.
3793 @quotation Attention
3794 This cannot be reverted! Be careful!
3798 lpc2900 secure_jtag 0
3803 @deffn {Flash Driver} ocl
3804 @emph{No idea what this is, other than using some arm7/arm9 core.}
3807 flash bank ocl 0 0 0 0 $_TARGETNAME
3811 @deffn {Flash Driver} pic32mx
3812 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3813 and integrate flash memory.
3814 @emph{The current implementation is incomplete.}
3817 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3820 @comment numerous *disabled* commands are defined:
3821 @comment - chip_erase ... pointless given flash_erase_address
3822 @comment - lock, unlock ... pointless given protect on/off (yes?)
3823 @comment - pgm_word ... shouldn't bank be deduced from address??
3824 Some pic32mx-specific commands are defined:
3825 @deffn Command {pic32mx pgm_word} address value bank
3826 Programs the specified 32-bit @var{value} at the given @var{address}
3827 in the specified chip @var{bank}.
3831 @deffn {Flash Driver} stellaris
3832 All members of the Stellaris LM3Sxxx microcontroller family from
3834 include internal flash and use ARM Cortex M3 cores.
3835 The driver automatically recognizes a number of these chips using
3836 the chip identification register, and autoconfigures itself.
3837 @footnote{Currently there is a @command{stellaris mass_erase} command.
3838 That seems pointless since the same effect can be had using the
3839 standard @command{flash erase_address} command.}
3842 flash bank stellaris 0 0 0 0 $_TARGETNAME
3846 @deffn {Flash Driver} stm32x
3847 All members of the STM32 microcontroller family from ST Microelectronics
3848 include internal flash and use ARM Cortex M3 cores.
3849 The driver automatically recognizes a number of these chips using
3850 the chip identification register, and autoconfigures itself.
3853 flash bank stm32x 0 0 0 0 $_TARGETNAME
3856 Some stm32x-specific commands
3857 @footnote{Currently there is a @command{stm32x mass_erase} command.
3858 That seems pointless since the same effect can be had using the
3859 standard @command{flash erase_address} command.}
3862 @deffn Command {stm32x lock} num
3863 Locks the entire stm32 device.
3864 The @var{num} parameter is a value shown by @command{flash banks}.
3867 @deffn Command {stm32x unlock} num
3868 Unlocks the entire stm32 device.
3869 The @var{num} parameter is a value shown by @command{flash banks}.
3872 @deffn Command {stm32x options_read} num
3873 Read and display the stm32 option bytes written by
3874 the @command{stm32x options_write} command.
3875 The @var{num} parameter is a value shown by @command{flash banks}.
3878 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3879 Writes the stm32 option byte with the specified values.
3880 The @var{num} parameter is a value shown by @command{flash banks}.
3884 @deffn {Flash Driver} str7x
3885 All members of the STR7 microcontroller family from ST Microelectronics
3886 include internal flash and use ARM7TDMI cores.
3887 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3888 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3891 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3894 @deffn Command {str7x disable_jtag} bank
3895 Activate the Debug/Readout protection mechanism
3896 for the specified flash bank.
3900 @deffn {Flash Driver} str9x
3901 Most members of the STR9 microcontroller family from ST Microelectronics
3902 include internal flash and use ARM966E cores.
3903 The str9 needs the flash controller to be configured using
3904 the @command{str9x flash_config} command prior to Flash programming.
3907 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3908 str9x flash_config 0 4 2 0 0x80000
3911 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3912 Configures the str9 flash controller.
3913 The @var{num} parameter is a value shown by @command{flash banks}.
3916 @item @var{bbsr} - Boot Bank Size register
3917 @item @var{nbbsr} - Non Boot Bank Size register
3918 @item @var{bbadr} - Boot Bank Start Address register
3919 @item @var{nbbadr} - Boot Bank Start Address register
3925 @deffn {Flash Driver} tms470
3926 Most members of the TMS470 microcontroller family from Texas Instruments
3927 include internal flash and use ARM7TDMI cores.
3928 This driver doesn't require the chip and bus width to be specified.
3930 Some tms470-specific commands are defined:
3932 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3933 Saves programming keys in a register, to enable flash erase and write commands.
3936 @deffn Command {tms470 osc_mhz} clock_mhz
3937 Reports the clock speed, which is used to calculate timings.
3940 @deffn Command {tms470 plldis} (0|1)
3941 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3946 @subsection str9xpec driver
3949 Here is some background info to help
3950 you better understand how this driver works. OpenOCD has two flash drivers for
3954 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3955 flash programming as it is faster than the @option{str9xpec} driver.
3957 Direct programming @option{str9xpec} using the flash controller. This is an
3958 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3959 core does not need to be running to program using this flash driver. Typical use
3960 for this driver is locking/unlocking the target and programming the option bytes.
3963 Before we run any commands using the @option{str9xpec} driver we must first disable
3964 the str9 core. This example assumes the @option{str9xpec} driver has been
3965 configured for flash bank 0.
3967 # assert srst, we do not want core running
3968 # while accessing str9xpec flash driver
3970 # turn off target polling
3973 str9xpec enable_turbo 0
3975 str9xpec options_read 0
3976 # re-enable str9 core
3977 str9xpec disable_turbo 0
3981 The above example will read the str9 option bytes.
3982 When performing a unlock remember that you will not be able to halt the str9 - it
3983 has been locked. Halting the core is not required for the @option{str9xpec} driver
3984 as mentioned above, just issue the commands above manually or from a telnet prompt.
3986 @deffn {Flash Driver} str9xpec
3987 Only use this driver for locking/unlocking the device or configuring the option bytes.
3988 Use the standard str9 driver for programming.
3989 Before using the flash commands the turbo mode must be enabled using the
3990 @command{str9xpec enable_turbo} command.
3992 Several str9xpec-specific commands are defined:
3994 @deffn Command {str9xpec disable_turbo} num
3995 Restore the str9 into JTAG chain.
3998 @deffn Command {str9xpec enable_turbo} num
3999 Enable turbo mode, will simply remove the str9 from the chain and talk
4000 directly to the embedded flash controller.
4003 @deffn Command {str9xpec lock} num
4004 Lock str9 device. The str9 will only respond to an unlock command that will
4008 @deffn Command {str9xpec part_id} num
4009 Prints the part identifier for bank @var{num}.
4012 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4013 Configure str9 boot bank.
4016 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4017 Configure str9 lvd source.
4020 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4021 Configure str9 lvd threshold.
4024 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4025 Configure str9 lvd reset warning source.
4028 @deffn Command {str9xpec options_read} num
4029 Read str9 option bytes.
4032 @deffn Command {str9xpec options_write} num
4033 Write str9 option bytes.
4036 @deffn Command {str9xpec unlock} num
4045 @subsection mFlash Configuration
4046 @cindex mFlash Configuration
4048 @deffn {Config Command} {mflash bank} soc base RST_pin target
4049 Configures a mflash for @var{soc} host bank at
4051 The pin number format depends on the host GPIO naming convention.
4052 Currently, the mflash driver supports s3c2440 and pxa270.
4054 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4057 mflash bank s3c2440 0x10000000 1b 0
4060 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4063 mflash bank pxa270 0x08000000 43 0
4067 @subsection mFlash commands
4068 @cindex mFlash commands
4070 @deffn Command {mflash config pll} frequency
4071 Configure mflash PLL.
4072 The @var{frequency} is the mflash input frequency, in Hz.
4073 Issuing this command will erase mflash's whole internal nand and write new pll.
4074 After this command, mflash needs power-on-reset for normal operation.
4075 If pll was newly configured, storage and boot(optional) info also need to be update.
4078 @deffn Command {mflash config boot}
4079 Configure bootable option.
4080 If bootable option is set, mflash offer the first 8 sectors
4084 @deffn Command {mflash config storage}
4085 Configure storage information.
4086 For the normal storage operation, this information must be
4090 @deffn Command {mflash dump} num filename offset size
4091 Dump @var{size} bytes, starting at @var{offset} bytes from the
4092 beginning of the bank @var{num}, to the file named @var{filename}.
4095 @deffn Command {mflash probe}
4099 @deffn Command {mflash write} num filename offset
4100 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4101 @var{offset} bytes from the beginning of the bank.
4104 @node NAND Flash Commands
4105 @chapter NAND Flash Commands
4108 Compared to NOR or SPI flash, NAND devices are inexpensive
4109 and high density. Today's NAND chips, and multi-chip modules,
4110 commonly hold multiple GigaBytes of data.
4112 NAND chips consist of a number of ``erase blocks'' of a given
4113 size (such as 128 KBytes), each of which is divided into a
4114 number of pages (of perhaps 512 or 2048 bytes each). Each
4115 page of a NAND flash has an ``out of band'' (OOB) area to hold
4116 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4117 of OOB for every 512 bytes of page data.
4119 One key characteristic of NAND flash is that its error rate
4120 is higher than that of NOR flash. In normal operation, that
4121 ECC is used to correct and detect errors. However, NAND
4122 blocks can also wear out and become unusable; those blocks
4123 are then marked "bad". NAND chips are even shipped from the
4124 manufacturer with a few bad blocks. The highest density chips
4125 use a technology (MLC) that wears out more quickly, so ECC
4126 support is increasingly important as a way to detect blocks
4127 that have begun to fail, and help to preserve data integrity
4128 with techniques such as wear leveling.
4130 Software is used to manage the ECC. Some controllers don't
4131 support ECC directly; in those cases, software ECC is used.
4132 Other controllers speed up the ECC calculations with hardware.
4133 Single-bit error correction hardware is routine. Controllers
4134 geared for newer MLC chips may correct 4 or more errors for
4135 every 512 bytes of data.
4137 You will need to make sure that any data you write using
4138 OpenOCD includes the apppropriate kind of ECC. For example,
4139 that may mean passing the @code{oob_softecc} flag when
4140 writing NAND data, or ensuring that the correct hardware
4143 The basic steps for using NAND devices include:
4145 @item Declare via the command @command{nand device}
4146 @* Do this in a board-specific configuration file,
4147 passing parameters as needed by the controller.
4148 @item Configure each device using @command{nand probe}.
4149 @* Do this only after the associated target is set up,
4150 such as in its reset-init script or in procures defined
4151 to access that device.
4152 @item Operate on the flash via @command{nand subcommand}
4153 @* Often commands to manipulate the flash are typed by a human, or run
4154 via a script in some automated way. Common task include writing a
4155 boot loader, operating system, or other data needed to initialize or
4159 @b{NOTE:} At the time this text was written, the largest NAND
4160 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4161 This is because the variables used to hold offsets and lengths
4162 are only 32 bits wide.
4163 (Larger chips may work in some cases, unless an offset or length
4164 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4165 Some larger devices will work, since they are actually multi-chip
4166 modules with two smaller chips and individual chipselect lines.
4168 @anchor{NAND Configuration}
4169 @section NAND Configuration Commands
4170 @cindex NAND configuration
4172 NAND chips must be declared in configuration scripts,
4173 plus some additional configuration that's done after
4174 OpenOCD has initialized.
4176 @deffn {Config Command} {nand device} controller target [configparams...]
4177 Declares a NAND device, which can be read and written to
4178 after it has been configured through @command{nand probe}.
4179 In OpenOCD, devices are single chips; this is unlike some
4180 operating systems, which may manage multiple chips as if
4181 they were a single (larger) device.
4182 In some cases, configuring a device will activate extra
4183 commands; see the controller-specific documentation.
4185 @b{NOTE:} This command is not available after OpenOCD
4186 initialization has completed. Use it in board specific
4187 configuration files, not interactively.
4190 @item @var{controller} ... identifies the controller driver
4191 associated with the NAND device being declared.
4192 @xref{NAND Driver List}.
4193 @item @var{target} ... names the target used when issuing
4194 commands to the NAND controller.
4195 @comment Actually, it's currently a controller-specific parameter...
4196 @item @var{configparams} ... controllers may support, or require,
4197 additional parameters. See the controller-specific documentation
4198 for more information.
4202 @deffn Command {nand list}
4203 Prints a summary of each device declared
4204 using @command{nand device}, numbered from zero.
4205 Note that un-probed devices show no details.
4208 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4209 blocksize: 131072, blocks: 8192
4210 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4211 blocksize: 131072, blocks: 8192
4216 @deffn Command {nand probe} num
4217 Probes the specified device to determine key characteristics
4218 like its page and block sizes, and how many blocks it has.
4219 The @var{num} parameter is the value shown by @command{nand list}.
4220 You must (successfully) probe a device before you can use
4221 it with most other NAND commands.
4224 @section Erasing, Reading, Writing to NAND Flash
4226 @deffn Command {nand dump} num filename offset length [oob_option]
4227 @cindex NAND reading
4228 Reads binary data from the NAND device and writes it to the file,
4229 starting at the specified offset.
4230 The @var{num} parameter is the value shown by @command{nand list}.
4232 Use a complete path name for @var{filename}, so you don't depend
4233 on the directory used to start the OpenOCD server.
4235 The @var{offset} and @var{length} must be exact multiples of the
4236 device's page size. They describe a data region; the OOB data
4237 associated with each such page may also be accessed.
4239 @b{NOTE:} At the time this text was written, no error correction
4240 was done on the data that's read, unless raw access was disabled
4241 and the underlying NAND controller driver had a @code{read_page}
4242 method which handled that error correction.
4244 By default, only page data is saved to the specified file.
4245 Use an @var{oob_option} parameter to save OOB data:
4247 @item no oob_* parameter
4248 @*Output file holds only page data; OOB is discarded.
4249 @item @code{oob_raw}
4250 @*Output file interleaves page data and OOB data;
4251 the file will be longer than "length" by the size of the
4252 spare areas associated with each data page.
4253 Note that this kind of "raw" access is different from
4254 what's implied by @command{nand raw_access}, which just
4255 controls whether a hardware-aware access method is used.
4256 @item @code{oob_only}
4257 @*Output file has only raw OOB data, and will
4258 be smaller than "length" since it will contain only the
4259 spare areas associated with each data page.
4263 @deffn Command {nand erase} num [offset length]
4264 @cindex NAND erasing
4265 @cindex NAND programming
4266 Erases blocks on the specified NAND device, starting at the
4267 specified @var{offset} and continuing for @var{length} bytes.
4268 Both of those values must be exact multiples of the device's
4269 block size, and the region they specify must fit entirely in the chip.
4270 If those parameters are not specified,
4271 the whole NAND chip will be erased.
4272 The @var{num} parameter is the value shown by @command{nand list}.
4274 @b{NOTE:} This command will try to erase bad blocks, when told
4275 to do so, which will probably invalidate the manufacturer's bad
4277 For the remainder of the current server session, @command{nand info}
4278 will still report that the block ``is'' bad.
4281 @deffn Command {nand write} num filename offset [option...]
4282 @cindex NAND writing
4283 @cindex NAND programming
4284 Writes binary data from the file into the specified NAND device,
4285 starting at the specified offset. Those pages should already
4286 have been erased; you can't change zero bits to one bits.
4287 The @var{num} parameter is the value shown by @command{nand list}.
4289 Use a complete path name for @var{filename}, so you don't depend
4290 on the directory used to start the OpenOCD server.
4292 The @var{offset} must be an exact multiple of the device's page size.
4293 All data in the file will be written, assuming it doesn't run
4294 past the end of the device.
4295 Only full pages are written, and any extra space in the last
4296 page will be filled with 0xff bytes. (That includes OOB data,
4297 if that's being written.)
4299 @b{NOTE:} At the time this text was written, bad blocks are
4300 ignored. That is, this routine will not skip bad blocks,
4301 but will instead try to write them. This can cause problems.
4303 Provide at most one @var{option} parameter. With some
4304 NAND drivers, the meanings of these parameters may change
4305 if @command{nand raw_access} was used to disable hardware ECC.
4307 @item no oob_* parameter
4308 @*File has only page data, which is written.
4309 If raw acccess is in use, the OOB area will not be written.
4310 Otherwise, if the underlying NAND controller driver has
4311 a @code{write_page} routine, that routine may write the OOB
4312 with hardware-computed ECC data.
4313 @item @code{oob_only}
4314 @*File has only raw OOB data, which is written to the OOB area.
4315 Each page's data area stays untouched. @i{This can be a dangerous
4316 option}, since it can invalidate the ECC data.
4317 You may need to force raw access to use this mode.
4318 @item @code{oob_raw}
4319 @*File interleaves data and OOB data, both of which are written
4320 If raw access is enabled, the data is written first, then the
4322 Otherwise, if the underlying NAND controller driver has
4323 a @code{write_page} routine, that routine may modify the OOB
4324 before it's written, to include hardware-computed ECC data.
4325 @item @code{oob_softecc}
4326 @*File has only page data, which is written.
4327 The OOB area is filled with 0xff, except for a standard 1-bit
4328 software ECC code stored in conventional locations.
4329 You might need to force raw access to use this mode, to prevent
4330 the underlying driver from applying hardware ECC.
4331 @item @code{oob_softecc_kw}
4332 @*File has only page data, which is written.
4333 The OOB area is filled with 0xff, except for a 4-bit software ECC
4334 specific to the boot ROM in Marvell Kirkwood SoCs.
4335 You might need to force raw access to use this mode, to prevent
4336 the underlying driver from applying hardware ECC.
4340 @section Other NAND commands
4341 @cindex NAND other commands
4343 @deffn Command {nand check_bad_blocks} [offset length]
4344 Checks for manufacturer bad block markers on the specified NAND
4345 device. If no parameters are provided, checks the whole
4346 device; otherwise, starts at the specified @var{offset} and
4347 continues for @var{length} bytes.
4348 Both of those values must be exact multiples of the device's
4349 block size, and the region they specify must fit entirely in the chip.
4350 The @var{num} parameter is the value shown by @command{nand list}.
4352 @b{NOTE:} Before using this command you should force raw access
4353 with @command{nand raw_access enable} to ensure that the underlying
4354 driver will not try to apply hardware ECC.
4357 @deffn Command {nand info} num
4358 The @var{num} parameter is the value shown by @command{nand list}.
4359 This prints the one-line summary from "nand list", plus for
4360 devices which have been probed this also prints any known
4361 status for each block.
4364 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4365 Sets or clears an flag affecting how page I/O is done.
4366 The @var{num} parameter is the value shown by @command{nand list}.
4368 This flag is cleared (disabled) by default, but changing that
4369 value won't affect all NAND devices. The key factor is whether
4370 the underlying driver provides @code{read_page} or @code{write_page}
4371 methods. If it doesn't provide those methods, the setting of
4372 this flag is irrelevant; all access is effectively ``raw''.
4374 When those methods exist, they are normally used when reading
4375 data (@command{nand dump} or reading bad block markers) or
4376 writing it (@command{nand write}). However, enabling
4377 raw access (setting the flag) prevents use of those methods,
4378 bypassing hardware ECC logic.
4379 @i{This can be a dangerous option}, since writing blocks
4380 with the wrong ECC data can cause them to be marked as bad.
4383 @anchor{NAND Driver List}
4384 @section NAND Drivers, Options, and Commands
4385 As noted above, the @command{nand device} command allows
4386 driver-specific options and behaviors.
4387 Some controllers also activate controller-specific commands.
4389 @deffn {NAND Driver} davinci
4390 This driver handles the NAND controllers found on DaVinci family
4391 chips from Texas Instruments.
4392 It takes three extra parameters:
4393 address of the NAND chip;
4394 hardware ECC mode to use (@option{hwecc1},
4395 @option{hwecc4}, @option{hwecc4_infix});
4396 address of the AEMIF controller on this processor.
4398 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4400 All DaVinci processors support the single-bit ECC hardware,
4401 and newer ones also support the four-bit ECC hardware.
4402 The @code{write_page} and @code{read_page} methods are used
4403 to implement those ECC modes, unless they are disabled using
4404 the @command{nand raw_access} command.
4407 @deffn {NAND Driver} lpc3180
4408 These controllers require an extra @command{nand device}
4409 parameter: the clock rate used by the controller.
4410 @deffn Command {lpc3180 select} num [mlc|slc]
4411 Configures use of the MLC or SLC controller mode.
4412 MLC implies use of hardware ECC.
4413 The @var{num} parameter is the value shown by @command{nand list}.
4416 At this writing, this driver includes @code{write_page}
4417 and @code{read_page} methods. Using @command{nand raw_access}
4418 to disable those methods will prevent use of hardware ECC
4419 in the MLC controller mode, but won't change SLC behavior.
4421 @comment current lpc3180 code won't issue 5-byte address cycles
4423 @deffn {NAND Driver} orion
4424 These controllers require an extra @command{nand device}
4425 parameter: the address of the controller.
4427 nand device orion 0xd8000000
4429 These controllers don't define any specialized commands.
4430 At this writing, their drivers don't include @code{write_page}
4431 or @code{read_page} methods, so @command{nand raw_access} won't
4432 change any behavior.
4435 @deffn {NAND Driver} s3c2410
4436 @deffnx {NAND Driver} s3c2412
4437 @deffnx {NAND Driver} s3c2440
4438 @deffnx {NAND Driver} s3c2443
4439 These S3C24xx family controllers don't have any special
4440 @command{nand device} options, and don't define any
4441 specialized commands.
4442 At this writing, their drivers don't include @code{write_page}
4443 or @code{read_page} methods, so @command{nand raw_access} won't
4444 change any behavior.
4447 @node PLD/FPGA Commands
4448 @chapter PLD/FPGA Commands
4452 Programmable Logic Devices (PLDs) and the more flexible
4453 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4454 OpenOCD can support programming them.
4455 Although PLDs are generally restrictive (cells are less functional, and
4456 there are no special purpose cells for memory or computational tasks),
4457 they share the same OpenOCD infrastructure.
4458 Accordingly, both are called PLDs here.
4460 @section PLD/FPGA Configuration and Commands
4462 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4463 OpenOCD maintains a list of PLDs available for use in various commands.
4464 Also, each such PLD requires a driver.
4466 They are referenced by the number shown by the @command{pld devices} command,
4467 and new PLDs are defined by @command{pld device driver_name}.
4469 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4470 Defines a new PLD device, supported by driver @var{driver_name},
4471 using the TAP named @var{tap_name}.
4472 The driver may make use of any @var{driver_options} to configure its
4476 @deffn {Command} {pld devices}
4477 Lists the PLDs and their numbers.
4480 @deffn {Command} {pld load} num filename
4481 Loads the file @file{filename} into the PLD identified by @var{num}.
4482 The file format must be inferred by the driver.
4485 @section PLD/FPGA Drivers, Options, and Commands
4487 Drivers may support PLD-specific options to the @command{pld device}
4488 definition command, and may also define commands usable only with
4489 that particular type of PLD.
4491 @deffn {FPGA Driver} virtex2
4492 Virtex-II is a family of FPGAs sold by Xilinx.
4493 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4494 No driver-specific PLD definition options are used,
4495 and one driver-specific command is defined.
4497 @deffn {Command} {virtex2 read_stat} num
4498 Reads and displays the Virtex-II status register (STAT)
4503 @node General Commands
4504 @chapter General Commands
4507 The commands documented in this chapter here are common commands that
4508 you, as a human, may want to type and see the output of. Configuration type
4509 commands are documented elsewhere.
4513 @item @b{Source Of Commands}
4514 @* OpenOCD commands can occur in a configuration script (discussed
4515 elsewhere) or typed manually by a human or supplied programatically,
4516 or via one of several TCP/IP Ports.
4518 @item @b{From the human}
4519 @* A human should interact with the telnet interface (default port: 4444)
4520 or via GDB (default port 3333).
4522 To issue commands from within a GDB session, use the @option{monitor}
4523 command, e.g. use @option{monitor poll} to issue the @option{poll}
4524 command. All output is relayed through the GDB session.
4526 @item @b{Machine Interface}
4527 The Tcl interface's intent is to be a machine interface. The default Tcl
4532 @section Daemon Commands
4534 @deffn {Command} exit
4535 Exits the current telnet session.
4538 @c note EXTREMELY ANNOYING word wrap at column 75
4539 @c even when lines are e.g. 100+ columns ...
4540 @c coded in startup.tcl
4541 @deffn {Command} help [string]
4542 With no parameters, prints help text for all commands.
4543 Otherwise, prints each helptext containing @var{string}.
4544 Not every command provides helptext.
4547 @deffn Command sleep msec [@option{busy}]
4548 Wait for at least @var{msec} milliseconds before resuming.
4549 If @option{busy} is passed, busy-wait instead of sleeping.
4550 (This option is strongly discouraged.)
4551 Useful in connection with script files
4552 (@command{script} command and @command{target_name} configuration).
4555 @deffn Command shutdown
4556 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4559 @anchor{debug_level}
4560 @deffn Command debug_level [n]
4561 @cindex message level
4562 Display debug level.
4563 If @var{n} (from 0..3) is provided, then set it to that level.
4564 This affects the kind of messages sent to the server log.
4565 Level 0 is error messages only;
4566 level 1 adds warnings;
4567 level 2 adds informational messages;
4568 and level 3 adds debugging messages.
4569 The default is level 2, but that can be overridden on
4570 the command line along with the location of that log
4571 file (which is normally the server's standard output).
4575 @deffn Command fast (@option{enable}|@option{disable})
4577 Set default behaviour of OpenOCD to be "fast and dangerous".
4579 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4580 fast memory access, and DCC downloads. Those parameters may still be
4581 individually overridden.
4583 The target specific "dangerous" optimisation tweaking options may come and go
4584 as more robust and user friendly ways are found to ensure maximum throughput
4585 and robustness with a minimum of configuration.
4587 Typically the "fast enable" is specified first on the command line:
4590 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4594 @deffn Command echo message
4595 Logs a message at "user" priority.
4596 Output @var{message} to stdout.
4598 echo "Downloading kernel -- please wait"
4602 @deffn Command log_output [filename]
4603 Redirect logging to @var{filename};
4604 the initial log output channel is stderr.
4607 @anchor{Target State handling}
4608 @section Target State handling
4611 @cindex target initialization
4613 In this section ``target'' refers to a CPU configured as
4614 shown earlier (@pxref{CPU Configuration}).
4615 These commands, like many, implicitly refer to
4616 a current target which is used to perform the
4617 various operations. The current target may be changed
4618 by using @command{targets} command with the name of the
4619 target which should become current.
4621 @deffn Command reg [(number|name) [value]]
4622 Access a single register by @var{number} or by its @var{name}.
4624 @emph{With no arguments}:
4625 list all available registers for the current target,
4626 showing number, name, size, value, and cache status.
4628 @emph{With number/name}: display that register's value.
4630 @emph{With both number/name and value}: set register's value.
4632 Cores may have surprisingly many registers in their
4633 Debug and trace infrastructure:
4637 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4638 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4639 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4641 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4642 0x00000000 (dirty: 0, valid: 0)
4647 @deffn Command halt [ms]
4648 @deffnx Command wait_halt [ms]
4649 The @command{halt} command first sends a halt request to the target,
4650 which @command{wait_halt} doesn't.
4651 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4652 or 5 seconds if there is no parameter, for the target to halt
4653 (and enter debug mode).
4654 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4657 On ARM cores, software using the @emph{wait for interrupt} operation
4658 often blocks the JTAG access needed by a @command{halt} command.
4659 This is because that operation also puts the core into a low
4660 power mode by gating the core clock;
4661 but the core clock is needed to detect JTAG clock transitions.
4663 One partial workaround uses adaptive clocking: when the core is
4664 interrupted the operation completes, then JTAG clocks are accepted
4665 at least until the interrupt handler completes.
4666 However, this workaround is often unusable since the processor, board,
4667 and JTAG adapter must all support adaptive JTAG clocking.
4668 Also, it can't work until an interrupt is issued.
4670 A more complete workaround is to not use that operation while you
4671 work with a JTAG debugger.
4672 Tasking environments generaly have idle loops where the body is the
4673 @emph{wait for interrupt} operation.
4674 (On older cores, it is a coprocessor action;
4675 newer cores have a @option{wfi} instruction.)
4676 Such loops can just remove that operation, at the cost of higher
4677 power consumption (because the CPU is needlessly clocked).
4682 @deffn Command resume [address]
4683 Resume the target at its current code position,
4684 or the optional @var{address} if it is provided.
4685 OpenOCD will wait 5 seconds for the target to resume.
4688 @deffn Command step [address]
4689 Single-step the target at its current code position,
4690 or the optional @var{address} if it is provided.
4693 @anchor{Reset Command}
4694 @deffn Command reset
4695 @deffnx Command {reset run}
4696 @deffnx Command {reset halt}
4697 @deffnx Command {reset init}
4698 Perform as hard a reset as possible, using SRST if possible.
4699 @emph{All defined targets will be reset, and target
4700 events will fire during the reset sequence.}
4702 The optional parameter specifies what should
4703 happen after the reset.
4704 If there is no parameter, a @command{reset run} is executed.
4705 The other options will not work on all systems.
4706 @xref{Reset Configuration}.
4709 @item @b{run} Let the target run
4710 @item @b{halt} Immediately halt the target
4711 @item @b{init} Immediately halt the target, and execute the reset-init script
4715 @deffn Command soft_reset_halt
4716 Requesting target halt and executing a soft reset. This is often used
4717 when a target cannot be reset and halted. The target, after reset is
4718 released begins to execute code. OpenOCD attempts to stop the CPU and
4719 then sets the program counter back to the reset vector. Unfortunately
4720 the code that was executed may have left the hardware in an unknown
4724 @section I/O Utilities
4726 These commands are available when
4727 OpenOCD is built with @option{--enable-ioutil}.
4728 They are mainly useful on embedded targets,
4730 Hosts with operating systems have complementary tools.
4732 @emph{Note:} there are several more such commands.
4734 @deffn Command append_file filename [string]*
4735 Appends the @var{string} parameters to
4736 the text file @file{filename}.
4737 Each string except the last one is followed by one space.
4738 The last string is followed by a newline.
4741 @deffn Command cat filename
4742 Reads and displays the text file @file{filename}.
4745 @deffn Command cp src_filename dest_filename
4746 Copies contents from the file @file{src_filename}
4747 into @file{dest_filename}.
4751 @emph{No description provided.}
4755 @emph{No description provided.}
4759 @emph{No description provided.}
4762 @deffn Command meminfo
4763 Display available RAM memory on OpenOCD host.
4764 Used in OpenOCD regression testing scripts.
4768 @emph{No description provided.}
4772 @emph{No description provided.}
4775 @deffn Command rm filename
4776 @c "rm" has both normal and Jim-level versions??
4777 Unlinks the file @file{filename}.
4780 @deffn Command trunc filename
4781 Removes all data in the file @file{filename}.
4784 @anchor{Memory access}
4785 @section Memory access commands
4786 @cindex memory access
4788 These commands allow accesses of a specific size to the memory
4789 system. Often these are used to configure the current target in some
4790 special way. For example - one may need to write certain values to the
4791 SDRAM controller to enable SDRAM.
4794 @item Use the @command{targets} (plural) command
4795 to change the current target.
4796 @item In system level scripts these commands are deprecated.
4797 Please use their TARGET object siblings to avoid making assumptions
4798 about what TAP is the current target, or about MMU configuration.
4801 @deffn Command mdw addr [count]
4802 @deffnx Command mdh addr [count]
4803 @deffnx Command mdb addr [count]
4804 Display contents of address @var{addr}, as
4805 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4806 or 8-bit bytes (@command{mdb}).
4807 If @var{count} is specified, displays that many units.
4808 (If you want to manipulate the data instead of displaying it,
4809 see the @code{mem2array} primitives.)
4812 @deffn Command mww addr word
4813 @deffnx Command mwh addr halfword
4814 @deffnx Command mwb addr byte
4815 Writes the specified @var{word} (32 bits),
4816 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4817 at the specified address @var{addr}.
4821 @anchor{Image access}
4822 @section Image loading commands
4823 @cindex image loading
4824 @cindex image dumping
4827 @deffn Command {dump_image} filename address size
4828 Dump @var{size} bytes of target memory starting at @var{address} to the
4829 binary file named @var{filename}.
4832 @deffn Command {fast_load}
4833 Loads an image stored in memory by @command{fast_load_image} to the
4834 current target. Must be preceeded by fast_load_image.
4837 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4838 Normally you should be using @command{load_image} or GDB load. However, for
4839 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4840 host), storing the image in memory and uploading the image to the target
4841 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4842 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4843 memory, i.e. does not affect target. This approach is also useful when profiling
4844 target programming performance as I/O and target programming can easily be profiled
4849 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4850 Load image from file @var{filename} to target memory at @var{address}.
4851 The file format may optionally be specified
4852 (@option{bin}, @option{ihex}, or @option{elf})
4855 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4856 Displays image section sizes and addresses
4857 as if @var{filename} were loaded into target memory
4858 starting at @var{address} (defaults to zero).
4859 The file format may optionally be specified
4860 (@option{bin}, @option{ihex}, or @option{elf})
4863 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4864 Verify @var{filename} against target memory starting at @var{address}.
4865 The file format may optionally be specified
4866 (@option{bin}, @option{ihex}, or @option{elf})
4867 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4871 @section Breakpoint and Watchpoint commands
4875 CPUs often make debug modules accessible through JTAG, with
4876 hardware support for a handful of code breakpoints and data
4878 In addition, CPUs almost always support software breakpoints.
4880 @deffn Command {bp} [address len [@option{hw}]]
4881 With no parameters, lists all active breakpoints.
4882 Else sets a breakpoint on code execution starting
4883 at @var{address} for @var{length} bytes.
4884 This is a software breakpoint, unless @option{hw} is specified
4885 in which case it will be a hardware breakpoint.
4887 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4888 for similar mechanisms that do not consume hardware breakpoints.)
4891 @deffn Command {rbp} address
4892 Remove the breakpoint at @var{address}.
4895 @deffn Command {rwp} address
4896 Remove data watchpoint on @var{address}
4899 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4900 With no parameters, lists all active watchpoints.
4901 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4902 The watch point is an "access" watchpoint unless
4903 the @option{r} or @option{w} parameter is provided,
4904 defining it as respectively a read or write watchpoint.
4905 If a @var{value} is provided, that value is used when determining if
4906 the watchpoint should trigger. The value may be first be masked
4907 using @var{mask} to mark ``don't care'' fields.
4910 @section Misc Commands
4913 @deffn Command {profile} seconds filename
4914 Profiling samples the CPU's program counter as quickly as possible,
4915 which is useful for non-intrusive stochastic profiling.
4916 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4919 @deffn Command {version}
4920 Displays a string identifying the version of this OpenOCD server.
4923 @deffn Command {virt2phys} virtual_address
4924 Requests the current target to map the specified @var{virtual_address}
4925 to its corresponding physical address, and displays the result.
4928 @node Architecture and Core Commands
4929 @chapter Architecture and Core Commands
4930 @cindex Architecture Specific Commands
4931 @cindex Core Specific Commands
4933 Most CPUs have specialized JTAG operations to support debugging.
4934 OpenOCD packages most such operations in its standard command framework.
4935 Some of those operations don't fit well in that framework, so they are
4936 exposed here as architecture or implementation (core) specific commands.
4938 @anchor{ARM Hardware Tracing}
4939 @section ARM Hardware Tracing
4944 CPUs based on ARM cores may include standard tracing interfaces,
4945 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4946 address and data bus trace records to a ``Trace Port''.
4950 Development-oriented boards will sometimes provide a high speed
4951 trace connector for collecting that data, when the particular CPU
4952 supports such an interface.
4953 (The standard connector is a 38-pin Mictor, with both JTAG
4954 and trace port support.)
4955 Those trace connectors are supported by higher end JTAG adapters
4956 and some logic analyzer modules; frequently those modules can
4957 buffer several megabytes of trace data.
4958 Configuring an ETM coupled to such an external trace port belongs
4959 in the board-specific configuration file.
4961 If the CPU doesn't provide an external interface, it probably
4962 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4963 dedicated SRAM. 4KBytes is one common ETB size.
4964 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4965 (target) configuration file, since it works the same on all boards.
4968 ETM support in OpenOCD doesn't seem to be widely used yet.
4971 ETM support may be buggy, and at least some @command{etm config}
4972 parameters should be detected by asking the ETM for them.
4973 It seems like a GDB hookup should be possible,
4974 as well as triggering trace on specific events
4975 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4976 There should be GUI tools to manipulate saved trace data and help
4977 analyse it in conjunction with the source code.
4978 It's unclear how much of a common interface is shared
4979 with the current XScale trace support, or should be
4980 shared with eventual Nexus-style trace module support.
4981 At this writing (September 2009) only ARM7 and ARM9 support
4982 for ETM modules is available. The code should be able to
4983 work with some newer cores; but not all of them support
4984 this original style of JTAG access.
4987 @subsection ETM Configuration
4988 ETM setup is coupled with the trace port driver configuration.
4990 @deffn {Config Command} {etm config} target width mode clocking driver
4991 Declares the ETM associated with @var{target}, and associates it
4992 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4994 Several of the parameters must reflect the trace port configuration.
4995 The @var{width} must be either 4, 8, or 16.
4996 The @var{mode} must be @option{normal}, @option{multiplexted},
4997 or @option{demultiplexted}.
4998 The @var{clocking} must be @option{half} or @option{full}.
5001 You can see the ETM registers using the @command{reg} command.
5002 Not all possible registers are present in every ETM.
5003 Most of the registers are write-only, and are used to configure
5004 what CPU activities are traced.
5008 @deffn Command {etm info}
5009 Displays information about the current target's ETM.
5012 @deffn Command {etm status}
5013 Displays status of the current target's ETM and trace port driver:
5014 is the ETM idle, or is it collecting data?
5015 Did trace data overflow?
5019 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
5020 Displays what data that ETM will collect.
5021 If arguments are provided, first configures that data.
5022 When the configuration changes, tracing is stopped
5023 and any buffered trace data is invalidated.
5026 @item @var{type} ... describing how data accesses are traced,
5027 when they pass any ViewData filtering that that was set up.
5029 @option{none} (save nothing),
5030 @option{data} (save data),
5031 @option{address} (save addresses),
5032 @option{all} (save data and addresses)
5033 @item @var{context_id_bits} ... 0, 8, 16, or 32
5034 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
5035 cycle-accurate instruction tracing.
5036 Before ETMv3, enabling this causes much extra data to be recorded.
5037 @item @var{branch_output} ... @option{enable} or @option{disable}.
5038 Disable this unless you need to try reconstructing the instruction
5039 trace stream without an image of the code.
5043 @deffn Command {etm trigger_percent} [percent]
5044 This displays, or optionally changes, the trace port driver's
5045 behavior after the ETM's configured @emph{trigger} event fires.
5046 It controls how much more trace data is saved after the (single)
5047 trace trigger becomes active.
5050 @item The default corresponds to @emph{trace around} usage,
5051 recording 50 percent data before the event and the rest
5053 @item The minimum value of @var{percent} is 2 percent,
5054 recording almost exclusively data before the trigger.
5055 Such extreme @emph{trace before} usage can help figure out
5056 what caused that event to happen.
5057 @item The maximum value of @var{percent} is 100 percent,
5058 recording data almost exclusively after the event.
5059 This extreme @emph{trace after} usage might help sort out
5060 how the event caused trouble.
5062 @c REVISIT allow "break" too -- enter debug mode.
5065 @subsection ETM Trace Operation
5067 After setting up the ETM, you can use it to collect data.
5068 That data can be exported to files for later analysis.
5069 It can also be parsed with OpenOCD, for basic sanity checking.
5071 To configure what is being traced, you will need to write
5072 various trace registers using @command{reg ETM_*} commands.
5073 For the definitions of these registers, read ARM publication
5074 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
5075 Be aware that most of the relevant registers are write-only,
5076 and that ETM resources are limited. There are only a handful
5077 of address comparators, data comparators, counters, and so on.
5079 Examples of scenarios you might arrange to trace include:
5082 @item Code flow within a function, @emph{excluding} subroutines
5083 it calls. Use address range comparators to enable tracing
5084 for instruction access within that function's body.
5085 @item Code flow within a function, @emph{including} subroutines
5086 it calls. Use the sequencer and address comparators to activate
5087 tracing on an ``entered function'' state, then deactivate it by
5088 exiting that state when the function's exit code is invoked.
5089 @item Code flow starting at the fifth invocation of a function,
5090 combining one of the above models with a counter.
5091 @item CPU data accesses to the registers for a particular device,
5092 using address range comparators and the ViewData logic.
5093 @item Such data accesses only during IRQ handling, combining the above
5094 model with sequencer triggers which on entry and exit to the IRQ handler.
5095 @item @emph{... more}
5098 At this writing, September 2009, there are no Tcl utility
5099 procedures to help set up any common tracing scenarios.
5101 @deffn Command {etm analyze}
5102 Reads trace data into memory, if it wasn't already present.
5103 Decodes and prints the data that was collected.
5106 @deffn Command {etm dump} filename
5107 Stores the captured trace data in @file{filename}.
5110 @deffn Command {etm image} filename [base_address] [type]
5111 Opens an image file.
5114 @deffn Command {etm load} filename
5115 Loads captured trace data from @file{filename}.
5118 @deffn Command {etm start}
5119 Starts trace data collection.
5122 @deffn Command {etm stop}
5123 Stops trace data collection.
5126 @anchor{Trace Port Drivers}
5127 @subsection Trace Port Drivers
5129 To use an ETM trace port it must be associated with a driver.
5131 @deffn {Trace Port Driver} dummy
5132 Use the @option{dummy} driver if you are configuring an ETM that's
5133 not connected to anything (on-chip ETB or off-chip trace connector).
5134 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
5135 any trace data collection.}
5136 @deffn {Config Command} {etm_dummy config} target
5137 Associates the ETM for @var{target} with a dummy driver.
5141 @deffn {Trace Port Driver} etb
5142 Use the @option{etb} driver if you are configuring an ETM
5143 to use on-chip ETB memory.
5144 @deffn {Config Command} {etb config} target etb_tap
5145 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
5146 You can see the ETB registers using the @command{reg} command.
5150 @deffn {Trace Port Driver} oocd_trace
5151 This driver isn't available unless OpenOCD was explicitly configured
5152 with the @option{--enable-oocd_trace} option. You probably don't want
5153 to configure it unless you've built the appropriate prototype hardware;
5154 it's @emph{proof-of-concept} software.
5156 Use the @option{oocd_trace} driver if you are configuring an ETM that's
5157 connected to an off-chip trace connector.
5159 @deffn {Config Command} {oocd_trace config} target tty
5160 Associates the ETM for @var{target} with a trace driver which
5161 collects data through the serial port @var{tty}.
5164 @deffn Command {oocd_trace resync}
5165 Re-synchronizes with the capture clock.
5168 @deffn Command {oocd_trace status}
5169 Reports whether the capture clock is locked or not.
5174 @section ARMv4 and ARMv5 Architecture
5178 These commands are specific to ARM architecture v4 and v5,
5179 including all ARM7 or ARM9 systems and Intel XScale.
5180 They are available in addition to other core-specific
5181 commands that may be available.
5183 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
5184 Displays the core_state, optionally changing it to process
5185 either @option{arm} or @option{thumb} instructions.
5186 The target may later be resumed in the currently set core_state.
5187 (Processors may also support the Jazelle state, but
5188 that is not currently supported in OpenOCD.)
5191 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
5193 Disassembles @var{count} instructions starting at @var{address}.
5194 If @var{count} is not specified, a single instruction is disassembled.
5195 If @option{thumb} is specified, or the low bit of the address is set,
5196 Thumb (16-bit) instructions are used;
5197 else ARM (32-bit) instructions are used.
5198 (Processors may also support the Jazelle state, but
5199 those instructions are not currently understood by OpenOCD.)
5202 @deffn Command {armv4_5 reg}
5203 Display a table of all banked core registers, fetching the current value from every
5204 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
5208 @subsection ARM7 and ARM9 specific commands
5212 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5213 ARM9TDMI, ARM920T or ARM926EJ-S.
5214 They are available in addition to the ARMv4/5 commands,
5215 and any other core-specific commands that may be available.
5217 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5218 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5219 instead of breakpoints. This should be
5220 safe for all but ARM7TDMI--S cores (like Philips LPC).
5221 This feature is enabled by default on most ARM9 cores,
5222 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5225 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5227 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5228 amounts of memory. DCC downloads offer a huge speed increase, but might be
5229 unsafe, especially with targets running at very low speeds. This command was introduced
5230 with OpenOCD rev. 60, and requires a few bytes of working area.
5233 @anchor{arm7_9 fast_memory_access}
5234 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5235 Enable or disable memory writes and reads that don't check completion of
5236 the operation. This provides a huge speed increase, especially with USB JTAG
5237 cables (FT2232), but might be unsafe if used with targets running at very low
5238 speeds, like the 32kHz startup clock of an AT91RM9200.
5241 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
5242 @emph{This is intended for use while debugging OpenOCD; you probably
5245 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
5246 as used in the specified @var{mode}
5247 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
5248 the M4..M0 bits of the PSR).
5249 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
5250 Register 16 is the mode-specific SPSR,
5251 unless the specified mode is 0xffffffff (32-bit all-ones)
5252 in which case register 16 is the CPSR.
5253 The write goes directly to the CPU, bypassing the register cache.
5256 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
5257 @emph{This is intended for use while debugging OpenOCD; you probably
5260 If the second parameter is zero, writes @var{word} to the
5261 Current Program Status register (CPSR).
5262 Else writes @var{word} to the current mode's Saved PSR (SPSR).
5263 In both cases, this bypasses the register cache.
5266 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
5267 @emph{This is intended for use while debugging OpenOCD; you probably
5270 Writes eight bits to the CPSR or SPSR,
5271 first rotating them by @math{2*rotate} bits,
5272 and bypassing the register cache.
5273 This has lower JTAG overhead than writing the entire CPSR or SPSR
5274 with @command{arm7_9 write_xpsr}.
5277 @subsection ARM720T specific commands
5280 These commands are available to ARM720T based CPUs,
5281 which are implementations of the ARMv4T architecture
5282 based on the ARM7TDMI-S integer core.
5283 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
5285 @deffn Command {arm720t cp15} regnum [value]
5286 Display cp15 register @var{regnum};
5287 else if a @var{value} is provided, that value is written to that register.
5290 @deffn Command {arm720t mdw_phys} addr [count]
5291 @deffnx Command {arm720t mdh_phys} addr [count]
5292 @deffnx Command {arm720t mdb_phys} addr [count]
5293 Display contents of physical address @var{addr}, as
5294 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5295 or 8-bit bytes (@command{mdb_phys}).
5296 If @var{count} is specified, displays that many units.
5299 @deffn Command {arm720t mww_phys} addr word
5300 @deffnx Command {arm720t mwh_phys} addr halfword
5301 @deffnx Command {arm720t mwb_phys} addr byte
5302 Writes the specified @var{word} (32 bits),
5303 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5304 at the specified physical address @var{addr}.
5307 @deffn Command {arm720t virt2phys} va
5308 Translate a virtual address @var{va} to a physical address
5309 and display the result.
5312 @subsection ARM9 specific commands
5315 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5317 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5319 For historical reasons, one command shared by these cores starts
5320 with the @command{arm9tdmi} prefix.
5321 This is true even for ARM9E based processors, which implement the
5322 ARMv5TE architecture instead of ARMv4T.
5324 @c 9-june-2009: tried this on arm920t, it didn't work.
5325 @c no-params always lists nothing caught, and that's how it acts.
5327 @anchor{arm9tdmi vector_catch}
5328 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
5329 @cindex vector_catch
5330 Vector Catch hardware provides a sort of dedicated breakpoint
5331 for hardware events such as reset, interrupt, and abort.
5332 You can use this to conserve normal breakpoint resources,
5333 so long as you're not concerned with code that branches directly
5334 to those hardware vectors.
5336 This always finishes by listing the current configuration.
5337 If parameters are provided, it first reconfigures the
5338 vector catch hardware to intercept
5339 @option{all} of the hardware vectors,
5340 @option{none} of them,
5341 or a list with one or more of the following:
5342 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
5343 @option{irq} @option{fiq}.
5346 @subsection ARM920T specific commands
5349 These commands are available to ARM920T based CPUs,
5350 which are implementations of the ARMv4T architecture
5351 built using the ARM9TDMI integer core.
5352 They are available in addition to the ARMv4/5, ARM7/ARM9,
5353 and ARM9TDMI commands.
5355 @deffn Command {arm920t cache_info}
5356 Print information about the caches found. This allows to see whether your target
5357 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5360 @deffn Command {arm920t cp15} regnum [value]
5361 Display cp15 register @var{regnum};
5362 else if a @var{value} is provided, that value is written to that register.
5365 @deffn Command {arm920t cp15i} opcode [value [address]]
5366 Interpreted access using cp15 @var{opcode}.
5367 If no @var{value} is provided, the result is displayed.
5368 Else if that value is written using the specified @var{address},
5369 or using zero if no other address is not provided.
5372 @deffn Command {arm920t mdw_phys} addr [count]
5373 @deffnx Command {arm920t mdh_phys} addr [count]
5374 @deffnx Command {arm920t mdb_phys} addr [count]
5375 Display contents of physical address @var{addr}, as
5376 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5377 or 8-bit bytes (@command{mdb_phys}).
5378 If @var{count} is specified, displays that many units.
5381 @deffn Command {arm920t mww_phys} addr word
5382 @deffnx Command {arm920t mwh_phys} addr halfword
5383 @deffnx Command {arm920t mwb_phys} addr byte
5384 Writes the specified @var{word} (32 bits),
5385 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5386 at the specified physical address @var{addr}.
5389 @deffn Command {arm920t read_cache} filename
5390 Dump the content of ICache and DCache to a file named @file{filename}.
5393 @deffn Command {arm920t read_mmu} filename
5394 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5397 @deffn Command {arm920t virt2phys} va
5398 Translate a virtual address @var{va} to a physical address
5399 and display the result.
5402 @subsection ARM926ej-s specific commands
5405 These commands are available to ARM926ej-s based CPUs,
5406 which are implementations of the ARMv5TEJ architecture
5407 based on the ARM9EJ-S integer core.
5408 They are available in addition to the ARMv4/5, ARM7/ARM9,
5409 and ARM9TDMI commands.
5411 The Feroceon cores also support these commands, although
5412 they are not built from ARM926ej-s designs.
5414 @deffn Command {arm926ejs cache_info}
5415 Print information about the caches found.
5418 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5419 Accesses cp15 register @var{regnum} using
5420 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5421 If a @var{value} is provided, that value is written to that register.
5422 Else that register is read and displayed.
5425 @deffn Command {arm926ejs mdw_phys} addr [count]
5426 @deffnx Command {arm926ejs mdh_phys} addr [count]
5427 @deffnx Command {arm926ejs mdb_phys} addr [count]
5428 Display contents of physical address @var{addr}, as
5429 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5430 or 8-bit bytes (@command{mdb_phys}).
5431 If @var{count} is specified, displays that many units.
5434 @deffn Command {arm926ejs mww_phys} addr word
5435 @deffnx Command {arm926ejs mwh_phys} addr halfword
5436 @deffnx Command {arm926ejs mwb_phys} addr byte
5437 Writes the specified @var{word} (32 bits),
5438 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5439 at the specified physical address @var{addr}.
5442 @deffn Command {arm926ejs virt2phys} va
5443 Translate a virtual address @var{va} to a physical address
5444 and display the result.
5447 @subsection ARM966E specific commands
5450 These commands are available to ARM966 based CPUs,
5451 which are implementations of the ARMv5TE architecture.
5452 They are available in addition to the ARMv4/5, ARM7/ARM9,
5453 and ARM9TDMI commands.
5455 @deffn Command {arm966e cp15} regnum [value]
5456 Display cp15 register @var{regnum};
5457 else if a @var{value} is provided, that value is written to that register.
5460 @subsection XScale specific commands
5463 Some notes about the debug implementation on the XScale CPUs:
5465 The XScale CPU provides a special debug-only mini-instruction cache
5466 (mini-IC) in which exception vectors and target-resident debug handler
5467 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5468 must point vector 0 (the reset vector) to the entry of the debug
5469 handler. However, this means that the complete first cacheline in the
5470 mini-IC is marked valid, which makes the CPU fetch all exception
5471 handlers from the mini-IC, ignoring the code in RAM.
5473 OpenOCD currently does not sync the mini-IC entries with the RAM
5474 contents (which would fail anyway while the target is running), so
5475 the user must provide appropriate values using the @code{xscale
5476 vector_table} command.
5478 It is recommended to place a pc-relative indirect branch in the vector
5479 table, and put the branch destination somewhere in memory. Doing so
5480 makes sure the code in the vector table stays constant regardless of
5481 code layout in memory:
5484 ldr pc,[pc,#0x100-8]
5485 ldr pc,[pc,#0x100-8]
5486 ldr pc,[pc,#0x100-8]
5487 ldr pc,[pc,#0x100-8]
5488 ldr pc,[pc,#0x100-8]
5489 ldr pc,[pc,#0x100-8]
5490 ldr pc,[pc,#0x100-8]
5491 ldr pc,[pc,#0x100-8]
5493 .long real_reset_vector
5494 .long real_ui_handler
5495 .long real_swi_handler
5497 .long real_data_abort
5498 .long 0 /* unused */
5499 .long real_irq_handler
5500 .long real_fiq_handler
5503 The debug handler must be placed somewhere in the address space using
5504 the @code{xscale debug_handler} command. The allowed locations for the
5505 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5506 0xfffff800). The default value is 0xfe000800.
5509 These commands are available to XScale based CPUs,
5510 which are implementations of the ARMv5TE architecture.
5512 @deffn Command {xscale analyze_trace}
5513 Displays the contents of the trace buffer.
5516 @deffn Command {xscale cache_clean_address} address
5517 Changes the address used when cleaning the data cache.
5520 @deffn Command {xscale cache_info}
5521 Displays information about the CPU caches.
5524 @deffn Command {xscale cp15} regnum [value]
5525 Display cp15 register @var{regnum};
5526 else if a @var{value} is provided, that value is written to that register.
5529 @deffn Command {xscale debug_handler} target address
5530 Changes the address used for the specified target's debug handler.
5533 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5534 Enables or disable the CPU's data cache.
5537 @deffn Command {xscale dump_trace} filename
5538 Dumps the raw contents of the trace buffer to @file{filename}.
5541 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5542 Enables or disable the CPU's instruction cache.
5545 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5546 Enables or disable the CPU's memory management unit.
5549 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5550 Enables or disables the trace buffer,
5551 and controls how it is emptied.
5554 @deffn Command {xscale trace_image} filename [offset [type]]
5555 Opens a trace image from @file{filename}, optionally rebasing
5556 its segment addresses by @var{offset}.
5557 The image @var{type} may be one of
5558 @option{bin} (binary), @option{ihex} (Intel hex),
5559 @option{elf} (ELF file), @option{s19} (Motorola s19),
5560 @option{mem}, or @option{builder}.
5563 @anchor{xscale vector_catch}
5564 @deffn Command {xscale vector_catch} [mask]
5565 @cindex vector_catch
5566 Display a bitmask showing the hardware vectors to catch.
5567 If the optional parameter is provided, first set the bitmask to that value.
5569 The mask bits correspond with bit 16..23 in the DCSR:
5572 0x02 Trap Undefined Instructions
5573 0x04 Trap Software Interrupt
5574 0x08 Trap Prefetch Abort
5575 0x10 Trap Data Abort
5582 @anchor{xscale vector_table}
5583 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5584 @cindex vector_table
5586 Set an entry in the mini-IC vector table. There are two tables: one for
5587 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5588 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5589 points to the debug handler entry and can not be overwritten.
5590 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5592 Without arguments, the current settings are displayed.
5596 @section ARMv6 Architecture
5599 @subsection ARM11 specific commands
5602 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5603 Write @var{value} to a coprocessor @var{pX} register
5604 passing parameters @var{CRn},
5605 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5606 and the MCR instruction.
5607 (The difference beween this and the MCR2 instruction is
5608 one bit in the encoding, effecively a fifth parameter.)
5611 @deffn Command {arm11 memwrite burst} [value]
5612 Displays the value of the memwrite burst-enable flag,
5613 which is enabled by default.
5614 If @var{value} is defined, first assigns that.
5617 @deffn Command {arm11 memwrite error_fatal} [value]
5618 Displays the value of the memwrite error_fatal flag,
5619 which is enabled by default.
5620 If @var{value} is defined, first assigns that.
5623 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5624 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5625 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5626 and the MRC instruction.
5627 (The difference beween this and the MRC2 instruction is
5628 one bit in the encoding, effecively a fifth parameter.)
5629 Displays the result.
5632 @deffn Command {arm11 no_increment} [value]
5633 Displays the value of the flag controlling whether
5634 some read or write operations increment the pointer
5635 (the default behavior) or not (acting like a FIFO).
5636 If @var{value} is defined, first assigns that.
5639 @deffn Command {arm11 step_irq_enable} [value]
5640 Displays the value of the flag controlling whether
5641 IRQs are enabled during single stepping;
5642 they are disabled by default.
5643 If @var{value} is defined, first assigns that.
5646 @deffn Command {arm11 vcr} [value]
5647 @cindex vector_catch
5648 Displays the value of the @emph{Vector Catch Register (VCR)},
5649 coprocessor 14 register 7.
5650 If @var{value} is defined, first assigns that.
5652 Vector Catch hardware provides dedicated breakpoints
5653 for certain hardware events.
5654 The specific bit values are core-specific (as in fact is using
5655 coprocessor 14 register 7 itself) but all current ARM11
5656 cores @emph{except the ARM1176} use the same six bits.
5659 @section ARMv7 Architecture
5662 @subsection ARMv7 Debug Access Port (DAP) specific commands
5663 @cindex Debug Access Port
5665 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5666 included on cortex-m3 and cortex-a8 systems.
5667 They are available in addition to other core-specific commands that may be available.
5669 @deffn Command {dap info} [num]
5670 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5673 @deffn Command {dap apsel} [num]
5674 Select AP @var{num}, defaulting to 0.
5677 @deffn Command {dap apid} [num]
5678 Displays id register from AP @var{num},
5679 defaulting to the currently selected AP.
5682 @deffn Command {dap baseaddr} [num]
5683 Displays debug base address from AP @var{num},
5684 defaulting to the currently selected AP.
5687 @deffn Command {dap memaccess} [value]
5688 Displays the number of extra tck for mem-ap memory bus access [0-255].
5689 If @var{value} is defined, first assigns that.
5692 @subsection ARMv7-A specific commands
5695 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5697 Disassembles @var{count} instructions starting at @var{address}.
5698 If @var{count} is not specified, a single instruction is disassembled.
5699 If @option{thumb} is specified, or the low bit of the address is set,
5700 Thumb2 (mixed 16/32-bit) instructions are used;
5701 else ARM (32-bit) instructions are used.
5702 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5703 ThumbEE disassembly currently has no explicit support.
5704 (Processors may also support the Jazelle state, but
5705 those instructions are not currently understood by OpenOCD.)
5709 @subsection Cortex-M3 specific commands
5712 @deffn Command {cortex_m3 disassemble} address [count]
5714 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5715 If @var{count} is not specified, a single instruction is disassembled.
5718 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5719 Control masking (disabling) interrupts during target step/resume.
5722 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5723 @cindex vector_catch
5724 Vector Catch hardware provides dedicated breakpoints
5725 for certain hardware events.
5727 Parameters request interception of
5728 @option{all} of these hardware event vectors,
5729 @option{none} of them,
5730 or one or more of the following:
5731 @option{hard_err} for a HardFault exception;
5732 @option{mm_err} for a MemManage exception;
5733 @option{bus_err} for a BusFault exception;
5736 @option{chk_err}, or
5737 @option{nocp_err} for various UsageFault exceptions; or
5739 If NVIC setup code does not enable them,
5740 MemManage, BusFault, and UsageFault exceptions
5741 are mapped to HardFault.
5742 UsageFault checks for
5743 divide-by-zero and unaligned access
5744 must also be explicitly enabled.
5746 This finishes by listing the current vector catch configuration.
5749 @anchor{Software Debug Messages and Tracing}
5750 @section Software Debug Messages and Tracing
5751 @cindex Linux-ARM DCC support
5755 OpenOCD can process certain requests from target software. Currently
5756 @command{target_request debugmsgs}
5757 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5758 These messages are received as part of target polling, so
5759 you need to have @command{poll on} active to receive them.
5760 They are intrusive in that they will affect program execution
5761 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5763 See @file{libdcc} in the contrib dir for more details.
5764 In addition to sending strings, characters, and
5765 arrays of various size integers from the target,
5766 @file{libdcc} also exports a software trace point mechanism.
5767 The target being debugged may
5768 issue trace messages which include a 24-bit @dfn{trace point} number.
5769 Trace point support includes two distinct mechanisms,
5770 each supported by a command:
5773 @item @emph{History} ... A circular buffer of trace points
5774 can be set up, and then displayed at any time.
5775 This tracks where code has been, which can be invaluable in
5776 finding out how some fault was triggered.
5778 The buffer may overflow, since it collects records continuously.
5779 It may be useful to use some of the 24 bits to represent a
5780 particular event, and other bits to hold data.
5782 @item @emph{Counting} ... An array of counters can be set up,
5783 and then displayed at any time.
5784 This can help establish code coverage and identify hot spots.
5786 The array of counters is directly indexed by the trace point
5787 number, so trace points with higher numbers are not counted.
5790 Linux-ARM kernels have a ``Kernel low-level debugging
5791 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5792 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5793 deliver messages before a serial console can be activated.
5794 This is not the same format used by @file{libdcc}.
5795 Other software, such as the U-Boot boot loader, sometimes
5796 does the same thing.
5798 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5799 Displays current handling of target DCC message requests.
5800 These messages may be sent to the debugger while the target is running.
5801 The optional @option{enable} and @option{charmsg} parameters
5802 both enable the messages, while @option{disable} disables them.
5804 With @option{charmsg} the DCC words each contain one character,
5805 as used by Linux with CONFIG_DEBUG_ICEDCC;
5806 otherwise the libdcc format is used.
5809 @deffn Command {trace history} [@option{clear}|count]
5810 With no parameter, displays all the trace points that have triggered
5811 in the order they triggered.
5812 With the parameter @option{clear}, erases all current trace history records.
5813 With a @var{count} parameter, allocates space for that many
5817 @deffn Command {trace point} [@option{clear}|identifier]
5818 With no parameter, displays all trace point identifiers and how many times
5819 they have been triggered.
5820 With the parameter @option{clear}, erases all current trace point counters.
5821 With a numeric @var{identifier} parameter, creates a new a trace point counter
5822 and associates it with that identifier.
5824 @emph{Important:} The identifier and the trace point number
5825 are not related except by this command.
5826 These trace point numbers always start at zero (from server startup,
5827 or after @command{trace point clear}) and count up from there.
5832 @chapter JTAG Commands
5833 @cindex JTAG Commands
5834 Most general purpose JTAG commands have been presented earlier.
5835 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5836 Lower level JTAG commands, as presented here,
5837 may be needed to work with targets which require special
5838 attention during operations such as reset or initialization.
5840 To use these commands you will need to understand some
5841 of the basics of JTAG, including:
5844 @item A JTAG scan chain consists of a sequence of individual TAP
5845 devices such as a CPUs.
5846 @item Control operations involve moving each TAP through the same
5847 standard state machine (in parallel)
5848 using their shared TMS and clock signals.
5849 @item Data transfer involves shifting data through the chain of
5850 instruction or data registers of each TAP, writing new register values
5851 while the reading previous ones.
5852 @item Data register sizes are a function of the instruction active in
5853 a given TAP, while instruction register sizes are fixed for each TAP.
5854 All TAPs support a BYPASS instruction with a single bit data register.
5855 @item The way OpenOCD differentiates between TAP devices is by
5856 shifting different instructions into (and out of) their instruction
5860 @section Low Level JTAG Commands
5862 These commands are used by developers who need to access
5863 JTAG instruction or data registers, possibly controlling
5864 the order of TAP state transitions.
5865 If you're not debugging OpenOCD internals, or bringing up a
5866 new JTAG adapter or a new type of TAP device (like a CPU or
5867 JTAG router), you probably won't need to use these commands.
5869 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5870 Loads the data register of @var{tap} with a series of bit fields
5871 that specify the entire register.
5872 Each field is @var{numbits} bits long with
5873 a numeric @var{value} (hexadecimal encouraged).
5874 The return value holds the original value of each
5877 For example, a 38 bit number might be specified as one
5878 field of 32 bits then one of 6 bits.
5879 @emph{For portability, never pass fields which are more
5880 than 32 bits long. Many OpenOCD implementations do not
5881 support 64-bit (or larger) integer values.}
5883 All TAPs other than @var{tap} must be in BYPASS mode.
5884 The single bit in their data registers does not matter.
5886 When @var{tap_state} is specified, the JTAG state machine is left
5888 For example @sc{drpause} might be specified, so that more
5889 instructions can be issued before re-entering the @sc{run/idle} state.
5890 If the end state is not specified, the @sc{run/idle} state is entered.
5893 OpenOCD does not record information about data register lengths,
5894 so @emph{it is important that you get the bit field lengths right}.
5895 Remember that different JTAG instructions refer to different
5896 data registers, which may have different lengths.
5897 Moreover, those lengths may not be fixed;
5898 the SCAN_N instruction can change the length of
5899 the register accessed by the INTEST instruction
5900 (by connecting a different scan chain).
5904 @deffn Command {flush_count}
5905 Returns the number of times the JTAG queue has been flushed.
5906 This may be used for performance tuning.
5908 For example, flushing a queue over USB involves a
5909 minimum latency, often several milliseconds, which does
5910 not change with the amount of data which is written.
5911 You may be able to identify performance problems by finding
5912 tasks which waste bandwidth by flushing small transfers too often,
5913 instead of batching them into larger operations.
5916 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5917 For each @var{tap} listed, loads the instruction register
5918 with its associated numeric @var{instruction}.
5919 (The number of bits in that instruction may be displayed
5920 using the @command{scan_chain} command.)
5921 For other TAPs, a BYPASS instruction is loaded.
5923 When @var{tap_state} is specified, the JTAG state machine is left
5925 For example @sc{irpause} might be specified, so the data register
5926 can be loaded before re-entering the @sc{run/idle} state.
5927 If the end state is not specified, the @sc{run/idle} state is entered.
5930 OpenOCD currently supports only a single field for instruction
5931 register values, unlike data register values.
5932 For TAPs where the instruction register length is more than 32 bits,
5933 portable scripts currently must issue only BYPASS instructions.
5937 @deffn Command {jtag_reset} trst srst
5938 Set values of reset signals.
5939 The @var{trst} and @var{srst} parameter values may be
5940 @option{0}, indicating that reset is inactive (pulled or driven high),
5941 or @option{1}, indicating it is active (pulled or driven low).
5942 The @command{reset_config} command should already have been used
5943 to configure how the board and JTAG adapter treat these two
5944 signals, and to say if either signal is even present.
5945 @xref{Reset Configuration}.
5948 @deffn Command {runtest} @var{num_cycles}
5949 Move to the @sc{run/idle} state, and execute at least
5950 @var{num_cycles} of the JTAG clock (TCK).
5951 Instructions often need some time
5952 to execute before they take effect.
5955 @c tms_sequence (short|long)
5956 @c ... temporary, debug-only, probably gone before 0.2 ships
5958 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5959 Verify values captured during @sc{ircapture} and returned
5960 during IR scans. Default is enabled, but this can be
5961 overridden by @command{verify_jtag}.
5964 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5965 Enables verification of DR and IR scans, to help detect
5966 programming errors. For IR scans, @command{verify_ircapture}
5967 must also be enabled.
5971 @section TAP state names
5972 @cindex TAP state names
5974 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5975 and @command{irscan} commands are:
5978 @item @b{RESET} ... should act as if TRST were active
5979 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5982 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5984 @item @b{DRPAUSE} ... data register ready for update or more shifting
5989 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5991 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5996 Note that only six of those states are fully ``stable'' in the
5997 face of TMS fixed (low except for @sc{reset})
5998 and a free-running JTAG clock. For all the
5999 others, the next TCK transition changes to a new state.
6002 @item From @sc{drshift} and @sc{irshift}, clock transitions will
6003 produce side effects by changing register contents. The values
6004 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
6005 may not be as expected.
6006 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
6007 choices after @command{drscan} or @command{irscan} commands,
6008 since they are free of JTAG side effects.
6009 However, @sc{run/idle} may have side effects that appear at other
6010 levels, such as advancing the ARM9E-S instruction pipeline.
6011 Consult the documentation for the TAP(s) you are working with.
6014 @node Boundary Scan Commands
6015 @chapter Boundary Scan Commands
6017 One of the original purposes of JTAG was to support
6018 boundary scan based hardware testing.
6019 Although its primary focus is to support On-Chip Debugging,
6020 OpenOCD also includes some boundary scan commands.
6022 @section SVF: Serial Vector Format
6023 @cindex Serial Vector Format
6026 The Serial Vector Format, better known as @dfn{SVF}, is a
6027 way to represent JTAG test patterns in text files.
6028 OpenOCD supports running such test files.
6030 @deffn Command {svf} filename [@option{quiet}]
6031 This issues a JTAG reset (Test-Logic-Reset) and then
6032 runs the SVF script from @file{filename}.
6033 Unless the @option{quiet} option is specified,
6034 each command is logged before it is executed.
6037 @section XSVF: Xilinx Serial Vector Format
6038 @cindex Xilinx Serial Vector Format
6041 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
6042 binary representation of SVF which is optimized for use with
6044 OpenOCD supports running such test files.
6046 @quotation Important
6047 Not all XSVF commands are supported.
6050 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
6051 This issues a JTAG reset (Test-Logic-Reset) and then
6052 runs the XSVF script from @file{filename}.
6053 When a @var{tapname} is specified, the commands are directed at
6055 When @option{virt2} is specified, the @sc{xruntest} command counts
6056 are interpreted as TCK cycles instead of microseconds.
6057 Unless the @option{quiet} option is specified,
6058 messages are logged for comments and some retries.
6064 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
6065 be used to access files on PCs (either the developer's PC or some other PC).
6067 The way this works on the ZY1000 is to prefix a filename by
6068 "/tftp/ip/" and append the TFTP path on the TFTP
6069 server (tftpd). For example,
6072 load_image /tftp/10.0.0.96/c:\temp\abc.elf
6075 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
6076 if the file was hosted on the embedded host.
6078 In order to achieve decent performance, you must choose a TFTP server
6079 that supports a packet size bigger than the default packet size (512 bytes). There
6080 are numerous TFTP servers out there (free and commercial) and you will have to do
6081 a bit of googling to find something that fits your requirements.
6083 @node GDB and OpenOCD
6084 @chapter GDB and OpenOCD
6086 OpenOCD complies with the remote gdbserver protocol, and as such can be used
6087 to debug remote targets.
6089 @anchor{Connecting to GDB}
6090 @section Connecting to GDB
6091 @cindex Connecting to GDB
6092 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
6093 instance GDB 6.3 has a known bug that produces bogus memory access
6094 errors, which has since been fixed: look up 1836 in
6095 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
6097 OpenOCD can communicate with GDB in two ways:
6101 A socket (TCP/IP) connection is typically started as follows:
6103 target remote localhost:3333
6105 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
6107 A pipe connection is typically started as follows:
6109 target remote | openocd --pipe
6111 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
6112 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
6116 To list the available OpenOCD commands type @command{monitor help} on the
6119 OpenOCD supports the gdb @option{qSupported} packet, this enables information
6120 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
6121 packet size and the device's memory map.
6123 Previous versions of OpenOCD required the following GDB options to increase
6124 the packet size and speed up GDB communication:
6126 set remote memory-write-packet-size 1024
6127 set remote memory-write-packet-size fixed
6128 set remote memory-read-packet-size 1024
6129 set remote memory-read-packet-size fixed
6131 This is now handled in the @option{qSupported} PacketSize and should not be required.
6133 @section Programming using GDB
6134 @cindex Programming using GDB
6136 By default the target memory map is sent to GDB. This can be disabled by
6137 the following OpenOCD configuration option:
6139 gdb_memory_map disable
6141 For this to function correctly a valid flash configuration must also be set
6142 in OpenOCD. For faster performance you should also configure a valid
6145 Informing GDB of the memory map of the target will enable GDB to protect any
6146 flash areas of the target and use hardware breakpoints by default. This means
6147 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
6148 using a memory map. @xref{gdb_breakpoint_override}.
6150 To view the configured memory map in GDB, use the GDB command @option{info mem}
6151 All other unassigned addresses within GDB are treated as RAM.
6153 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
6154 This can be changed to the old behaviour by using the following GDB command
6156 set mem inaccessible-by-default off
6159 If @command{gdb_flash_program enable} is also used, GDB will be able to
6160 program any flash memory using the vFlash interface.
6162 GDB will look at the target memory map when a load command is given, if any
6163 areas to be programmed lie within the target flash area the vFlash packets
6166 If the target needs configuring before GDB programming, an event
6167 script can be executed:
6169 $_TARGETNAME configure -event EVENTNAME BODY
6172 To verify any flash programming the GDB command @option{compare-sections}
6175 @node Tcl Scripting API
6176 @chapter Tcl Scripting API
6177 @cindex Tcl Scripting API
6181 The commands are stateless. E.g. the telnet command line has a concept
6182 of currently active target, the Tcl API proc's take this sort of state
6183 information as an argument to each proc.
6185 There are three main types of return values: single value, name value
6186 pair list and lists.
6188 Name value pair. The proc 'foo' below returns a name/value pair
6194 > set foo(you) Oyvind
6195 > set foo(mouse) Micky
6196 > set foo(duck) Donald
6204 me Duane you Oyvind mouse Micky duck Donald
6206 Thus, to get the names of the associative array is easy:
6208 foreach { name value } [set foo] {
6209 puts "Name: $name, Value: $value"
6213 Lists returned must be relatively small. Otherwise a range
6214 should be passed in to the proc in question.
6216 @section Internal low-level Commands
6218 By low-level, the intent is a human would not directly use these commands.
6220 Low-level commands are (should be) prefixed with "ocd_", e.g.
6221 @command{ocd_flash_banks}
6222 is the low level API upon which @command{flash banks} is implemented.
6225 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6227 Read memory and return as a Tcl array for script processing
6228 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6230 Convert a Tcl array to memory locations and write the values
6231 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6233 Return information about the flash banks
6236 OpenOCD commands can consist of two words, e.g. "flash banks". The
6237 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6238 called "flash_banks".
6240 @section OpenOCD specific Global Variables
6244 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6245 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
6246 holds one of the following values:
6249 @item @b{winxx} Built using Microsoft Visual Studio
6250 @item @b{linux} Linux is the underlying operating sytem
6251 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6252 @item @b{cygwin} Running under Cygwin
6253 @item @b{mingw32} Running under MingW32
6254 @item @b{other} Unknown, none of the above.
6257 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6260 We should add support for a variable like Tcl variable
6261 @code{tcl_platform(platform)}, it should be called
6262 @code{jim_platform} (because it
6263 is jim, not real tcl).
6267 @chapter Deprecated/Removed Commands
6268 @cindex Deprecated/Removed Commands
6269 Certain OpenOCD commands have been deprecated or
6270 removed during the various revisions.
6272 Upgrade your scripts as soon as possible.
6273 These descriptions for old commands may be removed
6274 a year after the command itself was removed.
6275 This means that in January 2010 this chapter may
6276 become much shorter.
6279 @item @b{arm7_9 fast_writes}
6280 @cindex arm7_9 fast_writes
6281 @*Use @command{arm7_9 fast_memory_access} instead.
6282 @xref{arm7_9 fast_memory_access}.
6285 @*An buggy old command that would not really work since background polling would wipe out the global endstate
6286 @item @b{arm7_9 force_hw_bkpts}
6287 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
6288 for flash if the GDB memory map has been set up(default when flash is declared in
6289 target configuration). @xref{gdb_breakpoint_override}.
6290 @item @b{arm7_9 sw_bkpts}
6291 @*On by default. @xref{gdb_breakpoint_override}.
6292 @item @b{daemon_startup}
6293 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
6294 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
6295 and @option{target cortex_m3 little reset_halt 0}.
6296 @item @b{dump_binary}
6297 @*use @option{dump_image} command with same args. @xref{dump_image}.
6298 @item @b{flash erase}
6299 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
6300 @item @b{flash write}
6301 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6302 @item @b{flash write_binary}
6303 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6304 @item @b{flash auto_erase}
6305 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
6307 @item @b{jtag_device}
6308 @*use the @command{jtag newtap} command, converting from positional syntax
6309 to named prefixes, and naming the TAP.
6311 Note that if you try to use the old command, a message will tell you the
6312 right new command to use; and that the fourth parameter in the old syntax
6313 was never actually used.
6315 OLD: jtag_device 8 0x01 0xe3 0xfe
6316 NEW: jtag newtap CHIPNAME TAPNAME \
6317 -irlen 8 -ircapture 0x01 -irmask 0xe3
6320 @item @b{jtag_speed} value
6321 @*@xref{JTAG Speed}.
6322 Usually, a value of zero means maximum
6323 speed. The actual effect of this option depends on the JTAG interface used.
6325 @item wiggler: maximum speed / @var{number}
6326 @item ft2232: 6MHz / (@var{number}+1)
6327 @item amt jtagaccel: 8 / 2**@var{number}
6328 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
6329 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
6330 @comment end speed list.
6333 @item @b{load_binary}
6334 @*use @option{load_image} command with same args. @xref{load_image}.
6335 @item @b{run_and_halt_time}
6336 @*This command has been removed for simpler reset behaviour, it can be simulated with the
6343 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
6344 @*use the create subcommand of @option{target}.
6345 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
6346 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
6347 @item @b{working_area}
6348 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
6356 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6358 @cindex adaptive clocking
6361 In digital circuit design it is often refered to as ``clock
6362 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6363 operating at some speed, your target is operating at another. The two
6364 clocks are not synchronised, they are ``asynchronous''
6366 In order for the two to work together they must be synchronised. Otherwise
6367 the two systems will get out of sync with each other and nothing will
6368 work. There are 2 basic options:
6371 Use a special circuit.
6373 One clock must be some multiple slower than the other.
6376 @b{Does this really matter?} For some chips and some situations, this
6377 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6378 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6379 program/enable the oscillators and eventually the main clock. It is in
6380 those critical times you must slow the JTAG clock to sometimes 1 to
6383 Imagine debugging a 500MHz ARM926 hand held battery powered device
6384 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6387 @b{Solution #1 - A special circuit}
6389 In order to make use of this, your JTAG dongle must support the RTCK
6390 feature. Not all dongles support this - keep reading!
6392 The RTCK signal often found in some ARM chips is used to help with
6393 this problem. ARM has a good description of the problem described at
6394 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6395 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6396 work? / how does adaptive clocking work?''.
6398 The nice thing about adaptive clocking is that ``battery powered hand
6399 held device example'' - the adaptiveness works perfectly all the
6400 time. One can set a break point or halt the system in the deep power
6401 down code, slow step out until the system speeds up.
6403 Note that adaptive clocking may also need to work at the board level,
6404 when a board-level scan chain has multiple chips.
6405 Parallel clock voting schemes are good way to implement this,
6406 both within and between chips, and can easily be implemented
6408 It's not difficult to have logic fan a module's input TCK signal out
6409 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6410 back with the right polarity before changing the output RTCK signal.
6411 Texas Instruments makes some clock voting logic available
6412 for free (with no support) in VHDL form; see
6413 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6415 @b{Solution #2 - Always works - but may be slower}
6417 Often this is a perfectly acceptable solution.
6419 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6420 the target clock speed. But what that ``magic division'' is varies
6421 depending on the chips on your board.
6422 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6423 ARM11 cores use an 8:1 division.
6424 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6426 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6428 You can still debug the 'low power' situations - you just need to
6429 manually adjust the clock speed at every step. While painful and
6430 tedious, it is not always practical.
6432 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6433 have a special debug mode in your application that does a ``high power
6434 sleep''. If you are careful - 98% of your problems can be debugged
6437 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6438 operation in your idle loops even if you don't otherwise change the CPU
6440 That operation gates the CPU clock, and thus the JTAG clock; which
6441 prevents JTAG access. One consequence is not being able to @command{halt}
6442 cores which are executing that @emph{wait for interrupt} operation.
6444 To set the JTAG frequency use the command:
6452 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6454 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6455 around Windows filenames.
6468 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6470 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6471 claims to come with all the necessary DLLs. When using Cygwin, try launching
6472 OpenOCD from the Cygwin shell.
6474 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6475 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6476 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6478 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6479 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6480 software breakpoints consume one of the two available hardware breakpoints.
6482 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6484 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6485 clock at the time you're programming the flash. If you've specified the crystal's
6486 frequency, make sure the PLL is disabled. If you've specified the full core speed
6487 (e.g. 60MHz), make sure the PLL is enabled.
6489 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6490 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6491 out while waiting for end of scan, rtck was disabled".
6493 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6494 settings in your PC BIOS (ECP, EPP, and different versions of those).
6496 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6497 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6498 memory read caused data abort".
6500 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6501 beyond the last valid frame. It might be possible to prevent this by setting up
6502 a proper "initial" stack frame, if you happen to know what exactly has to
6503 be done, feel free to add this here.
6505 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6506 stack before calling main(). What GDB is doing is ``climbing'' the run
6507 time stack by reading various values on the stack using the standard
6508 call frame for the target. GDB keeps going - until one of 2 things
6509 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6510 stackframes have been processed. By pushing zeros on the stack, GDB
6513 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6514 your C code, do the same - artifically push some zeros onto the stack,
6515 remember to pop them off when the ISR is done.
6517 @b{Also note:} If you have a multi-threaded operating system, they
6518 often do not @b{in the intrest of saving memory} waste these few
6522 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6523 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6525 This warning doesn't indicate any serious problem, as long as you don't want to
6526 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6527 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6528 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6529 independently. With this setup, it's not possible to halt the core right out of
6530 reset, everything else should work fine.
6532 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6533 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6534 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6535 quit with an error message. Is there a stability issue with OpenOCD?
6537 No, this is not a stability issue concerning OpenOCD. Most users have solved
6538 this issue by simply using a self-powered USB hub, which they connect their
6539 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6540 supply stable enough for the Amontec JTAGkey to be operated.
6542 @b{Laptops running on battery have this problem too...}
6544 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6545 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6546 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6547 What does that mean and what might be the reason for this?
6549 First of all, the reason might be the USB power supply. Try using a self-powered
6550 hub instead of a direct connection to your computer. Secondly, the error code 4
6551 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6552 chip ran into some sort of error - this points us to a USB problem.
6554 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6555 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6556 What does that mean and what might be the reason for this?
6558 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6559 has closed the connection to OpenOCD. This might be a GDB issue.
6561 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6562 are described, there is a parameter for specifying the clock frequency
6563 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6564 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6565 specified in kilohertz. However, I do have a quartz crystal of a
6566 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6567 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6570 No. The clock frequency specified here must be given as an integral number.
6571 However, this clock frequency is used by the In-Application-Programming (IAP)
6572 routines of the LPC2000 family only, which seems to be very tolerant concerning
6573 the given clock frequency, so a slight difference between the specified clock
6574 frequency and the actual clock frequency will not cause any trouble.
6576 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6578 Well, yes and no. Commands can be given in arbitrary order, yet the
6579 devices listed for the JTAG scan chain must be given in the right
6580 order (jtag newdevice), with the device closest to the TDO-Pin being
6581 listed first. In general, whenever objects of the same type exist
6582 which require an index number, then these objects must be given in the
6583 right order (jtag newtap, targets and flash banks - a target
6584 references a jtag newtap and a flash bank references a target).
6586 You can use the ``scan_chain'' command to verify and display the tap order.
6588 Also, some commands can't execute until after @command{init} has been
6589 processed. Such commands include @command{nand probe} and everything
6590 else that needs to write to controller registers, perhaps for setting
6591 up DRAM and loading it with code.
6593 @anchor{FAQ TAP Order}
6594 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6597 Yes; whenever you have more than one, you must declare them in
6598 the same order used by the hardware.
6600 Many newer devices have multiple JTAG TAPs. For example: ST
6601 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6602 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6603 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6604 connected to the boundary scan TAP, which then connects to the
6605 Cortex-M3 TAP, which then connects to the TDO pin.
6607 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6608 (2) The boundary scan TAP. If your board includes an additional JTAG
6609 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6610 place it before or after the STM32 chip in the chain. For example:
6613 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6614 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6615 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6616 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6617 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6620 The ``jtag device'' commands would thus be in the order shown below. Note:
6623 @item jtag newtap Xilinx tap -irlen ...
6624 @item jtag newtap stm32 cpu -irlen ...
6625 @item jtag newtap stm32 bs -irlen ...
6626 @item # Create the debug target and say where it is
6627 @item target create stm32.cpu -chain-position stm32.cpu ...
6631 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6632 log file, I can see these error messages: Error: arm7_9_common.c:561
6633 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6639 @node Tcl Crash Course
6640 @chapter Tcl Crash Course
6643 Not everyone knows Tcl - this is not intended to be a replacement for
6644 learning Tcl, the intent of this chapter is to give you some idea of
6645 how the Tcl scripts work.
6647 This chapter is written with two audiences in mind. (1) OpenOCD users
6648 who need to understand a bit more of how JIM-Tcl works so they can do
6649 something useful, and (2) those that want to add a new command to
6652 @section Tcl Rule #1
6653 There is a famous joke, it goes like this:
6655 @item Rule #1: The wife is always correct
6656 @item Rule #2: If you think otherwise, See Rule #1
6659 The Tcl equal is this:
6662 @item Rule #1: Everything is a string
6663 @item Rule #2: If you think otherwise, See Rule #1
6666 As in the famous joke, the consequences of Rule #1 are profound. Once
6667 you understand Rule #1, you will understand Tcl.
6669 @section Tcl Rule #1b
6670 There is a second pair of rules.
6672 @item Rule #1: Control flow does not exist. Only commands
6673 @* For example: the classic FOR loop or IF statement is not a control
6674 flow item, they are commands, there is no such thing as control flow
6676 @item Rule #2: If you think otherwise, See Rule #1
6677 @* Actually what happens is this: There are commands that by
6678 convention, act like control flow key words in other languages. One of
6679 those commands is the word ``for'', another command is ``if''.
6682 @section Per Rule #1 - All Results are strings
6683 Every Tcl command results in a string. The word ``result'' is used
6684 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6685 Everything is a string}
6687 @section Tcl Quoting Operators
6688 In life of a Tcl script, there are two important periods of time, the
6689 difference is subtle.
6692 @item Evaluation Time
6695 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6696 three primary quoting constructs, the [square-brackets] the
6697 @{curly-braces@} and ``double-quotes''
6699 By now you should know $VARIABLES always start with a $DOLLAR
6700 sign. BTW: To set a variable, you actually use the command ``set'', as
6701 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6702 = 1'' statement, but without the equal sign.
6705 @item @b{[square-brackets]}
6706 @* @b{[square-brackets]} are command substitutions. It operates much
6707 like Unix Shell `back-ticks`. The result of a [square-bracket]
6708 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6709 string}. These two statements are roughly identical:
6713 echo "The Date is: $X"
6716 puts "The Date is: $X"
6718 @item @b{``double-quoted-things''}
6719 @* @b{``double-quoted-things''} are just simply quoted
6720 text. $VARIABLES and [square-brackets] are expanded in place - the
6721 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6725 puts "It is now \"[date]\", $x is in 1 hour"
6727 @item @b{@{Curly-Braces@}}
6728 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6729 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6730 'single-quote' operators in BASH shell scripts, with the added
6731 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6732 nested 3 times@}@}@} NOTE: [date] is a bad example;
6733 at this writing, Jim/OpenOCD does not have a date command.
6736 @section Consequences of Rule 1/2/3/4
6738 The consequences of Rule 1 are profound.
6740 @subsection Tokenisation & Execution.
6742 Of course, whitespace, blank lines and #comment lines are handled in
6745 As a script is parsed, each (multi) line in the script file is
6746 tokenised and according to the quoting rules. After tokenisation, that
6747 line is immedatly executed.
6749 Multi line statements end with one or more ``still-open''
6750 @{curly-braces@} which - eventually - closes a few lines later.
6752 @subsection Command Execution
6754 Remember earlier: There are no ``control flow''
6755 statements in Tcl. Instead there are COMMANDS that simply act like
6756 control flow operators.
6758 Commands are executed like this:
6761 @item Parse the next line into (argc) and (argv[]).
6762 @item Look up (argv[0]) in a table and call its function.
6763 @item Repeat until End Of File.
6766 It sort of works like this:
6769 ReadAndParse( &argc, &argv );
6771 cmdPtr = LookupCommand( argv[0] );
6773 (*cmdPtr->Execute)( argc, argv );
6777 When the command ``proc'' is parsed (which creates a procedure
6778 function) it gets 3 parameters on the command line. @b{1} the name of
6779 the proc (function), @b{2} the list of parameters, and @b{3} the body
6780 of the function. Not the choice of words: LIST and BODY. The PROC
6781 command stores these items in a table somewhere so it can be found by
6784 @subsection The FOR command
6786 The most interesting command to look at is the FOR command. In Tcl,
6787 the FOR command is normally implemented in C. Remember, FOR is a
6788 command just like any other command.
6790 When the ascii text containing the FOR command is parsed, the parser
6791 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6795 @item The ascii text 'for'
6796 @item The start text
6797 @item The test expression
6802 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6803 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6804 Often many of those parameters are in @{curly-braces@} - thus the
6805 variables inside are not expanded or replaced until later.
6807 Remember that every Tcl command looks like the classic ``main( argc,
6808 argv )'' function in C. In JimTCL - they actually look like this:
6812 MyCommand( Jim_Interp *interp,
6814 Jim_Obj * const *argvs );
6817 Real Tcl is nearly identical. Although the newer versions have
6818 introduced a byte-code parser and intepreter, but at the core, it
6819 still operates in the same basic way.
6821 @subsection FOR command implementation
6823 To understand Tcl it is perhaps most helpful to see the FOR
6824 command. Remember, it is a COMMAND not a control flow structure.
6826 In Tcl there are two underlying C helper functions.
6828 Remember Rule #1 - You are a string.
6830 The @b{first} helper parses and executes commands found in an ascii
6831 string. Commands can be seperated by semicolons, or newlines. While
6832 parsing, variables are expanded via the quoting rules.
6834 The @b{second} helper evaluates an ascii string as a numerical
6835 expression and returns a value.
6837 Here is an example of how the @b{FOR} command could be
6838 implemented. The pseudo code below does not show error handling.
6840 void Execute_AsciiString( void *interp, const char *string );
6842 int Evaluate_AsciiExpression( void *interp, const char *string );
6845 MyForCommand( void *interp,
6850 SetResult( interp, "WRONG number of parameters");
6854 // argv[0] = the ascii string just like C
6856 // Execute the start statement.
6857 Execute_AsciiString( interp, argv[1] );
6861 i = Evaluate_AsciiExpression(interp, argv[2]);
6866 Execute_AsciiString( interp, argv[3] );
6868 // Execute the LOOP part
6869 Execute_AsciiString( interp, argv[4] );
6873 SetResult( interp, "" );
6878 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6879 in the same basic way.
6881 @section OpenOCD Tcl Usage
6883 @subsection source and find commands
6884 @b{Where:} In many configuration files
6885 @* Example: @b{ source [find FILENAME] }
6886 @*Remember the parsing rules
6888 @item The FIND command is in square brackets.
6889 @* The FIND command is executed with the parameter FILENAME. It should
6890 find the full path to the named file. The RESULT is a string, which is
6891 substituted on the orginal command line.
6892 @item The command source is executed with the resulting filename.
6893 @* SOURCE reads a file and executes as a script.
6895 @subsection format command
6896 @b{Where:} Generally occurs in numerous places.
6897 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6903 puts [format "The answer: %d" [expr $x * $y]]
6906 @item The SET command creates 2 variables, X and Y.
6907 @item The double [nested] EXPR command performs math
6908 @* The EXPR command produces numerical result as a string.
6910 @item The format command is executed, producing a single string
6911 @* Refer to Rule #1.
6912 @item The PUTS command outputs the text.
6914 @subsection Body or Inlined Text
6915 @b{Where:} Various TARGET scripts.
6918 proc someproc @{@} @{
6919 ... multiple lines of stuff ...
6921 $_TARGETNAME configure -event FOO someproc
6922 #2 Good - no variables
6923 $_TARGETNAME confgure -event foo "this ; that;"
6924 #3 Good Curly Braces
6925 $_TARGETNAME configure -event FOO @{
6928 #4 DANGER DANGER DANGER
6929 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6932 @item The $_TARGETNAME is an OpenOCD variable convention.
6933 @*@b{$_TARGETNAME} represents the last target created, the value changes
6934 each time a new target is created. Remember the parsing rules. When
6935 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6936 the name of the target which happens to be a TARGET (object)
6938 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6939 @*There are 4 examples:
6941 @item The TCLBODY is a simple string that happens to be a proc name
6942 @item The TCLBODY is several simple commands seperated by semicolons
6943 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6944 @item The TCLBODY is a string with variables that get expanded.
6947 In the end, when the target event FOO occurs the TCLBODY is
6948 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6949 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6951 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6952 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6953 and the text is evaluated. In case #4, they are replaced before the
6954 ``Target Object Command'' is executed. This occurs at the same time
6955 $_TARGETNAME is replaced. In case #4 the date will never
6956 change. @{BTW: [date] is a bad example; at this writing,
6957 Jim/OpenOCD does not have a date command@}
6959 @subsection Global Variables
6960 @b{Where:} You might discover this when writing your own procs @* In
6961 simple terms: Inside a PROC, if you need to access a global variable
6962 you must say so. See also ``upvar''. Example:
6964 proc myproc @{ @} @{
6965 set y 0 #Local variable Y
6966 global x #Global variable X
6967 puts [format "X=%d, Y=%d" $x $y]
6970 @section Other Tcl Hacks
6971 @b{Dynamic variable creation}
6973 # Dynamically create a bunch of variables.
6974 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6976 set vn [format "BIT%d" $x]
6980 set $vn [expr (1 << $x)]
6983 @b{Dynamic proc/command creation}
6985 # One "X" function - 5 uart functions.
6986 foreach who @{A B C D E@}
6987 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6993 @node OpenOCD Concept Index
6994 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6995 @comment case issue with ``Index.html'' and ``index.html''
6996 @comment Occurs when creating ``--html --no-split'' output
6997 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6998 @unnumbered OpenOCD Concept Index
7002 @node Command and Driver Index
7003 @unnumbered Command and Driver Index