1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
8 @title Open On-Chip Debugger (openocd)
10 @vskip 0pt plus 1filll
15 @node Top, About, , (dir)
18 The Manual always document the latest version of OpenOCD available from SVN.
21 * About:: About Openocd.
23 * Building:: Building Openocd
24 * Running:: Running Openocd
25 * Configuration:: Openocd Configuration.
26 * Commands:: Openocd Commands
27 * Sample Scripts:: Sample Target Scripts
28 * FAQ:: Frequently Asked Questions
29 * License:: GNU Free Documentation License
37 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
38 and boundary-scan testing for embedded target devices. The targets are interfaced
39 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
40 connection types in the future.
42 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
43 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
44 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
45 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
47 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
48 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
49 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
55 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
56 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
57 Others interested in improving the state of free and open debug and testing technology
58 are welcome to participate.
60 Other developers have contributed support for additional targets and flashes as well
61 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
65 @cindex building openocd
67 You can download the current SVN version with SVN client of your choice from the
68 following repositories:
70 (@uref{svn://svn.berlios.de/openocd/trunk}
74 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
76 Using the SVN command line client, you could use the following command to fetch the
77 latest version (make sure there is no (non-svn) directory called "openocd" in the
81 svn checkout svn://svn.berlios.de/openocd/trunk
84 Building the OpenOCD requires a recent version of the GNU autotools.
85 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
86 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
87 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
88 paths, resulting in obscure dependency errors (This is an observation I've gathered
89 from the logs of one user - correct me if I'm wrong).
91 You further need the appropriate driver files, if you want to build support for
92 a FTDI FT2232 based interface:
94 @item @b{ftdi2232} libftdi ((@uref{http://www.intra2net.com/opensource/ftdi/})
95 @item @b{ftd2xx} libftd2xx ((@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
96 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
97 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
100 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
101 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
103 In general, the D2XX driver provides superior performance (several times as fast),
104 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
105 a kernel module, only a user space library.
107 To build OpenOCD (on both Linux and Cygwin), use the following commands:
111 Bootstrap generates the configure script, and prepares building on your system.
115 Configure generates the Makefiles used to build OpenOCD
119 Make builds the OpenOCD, and places the final executable in ./src/
121 The configure script takes several options, specifying which JTAG interfaces
128 --enable-parport_ppdev
130 --enable-amtjtagaccel
132 --enable-ft2232_ftd2xx
133 @footnote{Using the latest D2XX drivers from FTDI and following their installation
134 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
137 --enable-ft2232_libftdi
139 --with-ftd2xx=/path/to/d2xx/
142 If you want to access the parallel port using the PPDEV interface you have to specify
143 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
144 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
145 (see (@uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
147 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
148 absolute path containing no spaces.
150 Linux users should copy the various parts of the D2XX package to the appropriate
151 locations, i.e. /usr/include, /usr/lib.
155 @cindex running openocd
156 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
157 Run with @option{--help} or @option{-h} to view the available command line arguments.
159 It reads its configuration by default from the file openocd.cfg located in the current
160 working directory. This may be overwritten with the @option{-f <configfile>} command line
163 To enable debug output (when reporting problems or working on OpenOCD itself), use
164 the @option{-d} command line switch. This sets the debug_level to "3", outputting
165 the most information, including debug messages. The default setting is "2", outputting
166 only informational messages, warnings and errors. You can also change this setting
167 from within a telnet or gdb session (@option{debug_level <n>}).
169 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
172 @chapter Configuration
173 @cindex configuration
174 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
175 by default from the file openocd.cfg in the current directory. A different configuration
176 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
178 The configuration file is used to specify on which ports the daemon listens for new
179 connections, the JTAG interface used to connect to the target, the layout of the JTAG
180 chain, the targets that should be debugged, and connected flashes.
182 @section Daemon configuration
185 @item @b{telnet_port} <@var{number}>
187 Port on which to listen for incoming telnet connections
188 @item @b{gdb_port} <@var{number}>
190 First port on which to listen for incoming GDB connections. The GDB port for the
191 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
192 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
193 @cindex daemon_startup
194 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
195 if it should just attach to the target.
198 @section JTAG interface configuration
201 @item @b{interface} <@var{name}>
203 Use the interface driver <@var{name}> to connect to the target. Currently supported
207 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
211 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
216 FTDI FT2232 based devices using either the open-source libftdi or the binary only
217 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
218 platform. The libftdi uses libusb, and should be portable to all systems that provide
223 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
228 @item @b{jtag_speed} <@var{number}>
230 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
231 speed. The actual effect of this option depends on the JTAG interface used.
233 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
235 The configuration of the reset signals available on the JTAG interface AND the target.
236 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
237 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
238 @samp{srst_only} or @samp{trst_and_srst}.
239 [@var{combination}] is an optional value specifying broken reset signal implementations.
240 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
241 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
242 that the system is reset together with the test logic (only hypothetical, I haven't
243 seen hardware with such a bug, and can be worked around).
245 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
246 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
247 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
248 (default) and @samp{srst_push_pull} for the system reset. These values only affect
249 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
251 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
253 Describes the devices that form the JTAG daisy chain, with the first device being
254 the one closest to TDO. The parameters are the length of the instruction register
255 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
256 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
257 The IDCODE instruction will in future be used to query devices for their JTAG
258 identification code. This line is the same for all ARM7 and ARM9 devices.
259 Other devices, like CPLDs, require different parameters. An example configuration
260 line for a Xilinx XC9500 CPLD would look like this:
262 jtag_device 8 0x01 0x0e3 0xfe
264 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
265 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
266 The IDCODE instruction is 0xfe.
268 @item @b{jtag_nsrst_delay} <@var{ms}>
269 @cindex jtag_nsrst_delay
270 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
271 starting new JTAG operations.
272 @item @b{jtag_ntrst_delay} <@var{ms}>
273 @cindex jtag_ntrst_delay
274 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
275 starting new JTAG operations.
277 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
278 or on-chip features) keep a reset line asserted for some time after the external reset
282 @section parport options
285 @item @b{parport_port} <@var{number}>
287 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
288 the @file{/dev/parport} device
290 When using PPDEV to access the parallel port, use the number of the parallel port:
291 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
292 you may encounter a problem.
293 @item @b{parport_cable} <@var{name}>
294 @cindex parport_cable
295 The layout of the parallel port cable used to connect to the target.
296 Currently supported cables are
300 Original Wiggler layout, also supported by several clones, such
301 as the Olimex ARM-JTAG
302 @item old_amt_wiggler
303 @cindex old_amt_wiggler
304 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
305 version available from the website uses the original Wiggler layout ('@var{wiggler}')
308 Describes the connection of the Amontec Chameleon's CPLD when operated in
309 configuration mode. This is only used to program the Chameleon itself, not
313 Xilinx Parallel cable III.
316 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
317 This is also the layout used by the HollyGates design
318 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
325 @section amt_jtagaccel options
327 @item @b{parport_port} <@var{number}>
329 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
330 @file{/dev/parport} device
332 @section ft2232 options
335 @item @b{ft2232_device_desc} <@var{description}>
336 @cindex ft2232_device_desc
337 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
338 default value is used. This setting is only valid if compiled with FTD2XX support.
339 @item @b{ft2232_layout} <@var{name}>
340 @cindex ft2232_layout
341 The layout of the FT2232 GPIO signals used to control output-enables and reset
342 signals. Valid layouts are
345 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
347 Amontec JTAGkey and JTAGkey-tiny
353 American Microsystems M5960
355 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
356 SRST signals on external connector
361 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
362 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
363 default values are used. This command is not available on Windows.
364 @item @b{ft2232_latency} <@var{ms}>
365 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
366 ft2232_read() fails to return the expected number of bytes. This can be caused by
367 USB communication delays and has proved hard to reproduce and debug. Setting the
368 FT2232 latency timer to a larger value increases delays for short USB packages but it
369 also reduces the risk of timeouts before receiving the expected number of bytes.
370 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
373 @section ep93xx options
374 @cindex ep93xx options
375 Currently, there are no options available for the ep93xx interface.
378 @section Target configuration
381 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
384 Defines a target that should be debugged. Currently supported types are:
397 If you want to use a target board that is not on this list, see Adding a new
400 Endianess may be @option{little} or @option{big}.
402 The reset_mode specifies what should happen to the target when a reset occurs:
406 Immediately request a target halt after reset. This allows targets to be debugged
407 from the very first instruction. This is only possible with targets and JTAG
408 interfaces that correctly implement the reset signals.
411 Similar to @option{reset_halt}, but executes the script file defined to handle the
412 'reset' event for the target. Like @option{reset_halt} this only works with
413 correct reset implementations.
416 Simply let the target run after a reset.
419 Let the target run for some time (default: 1s), and then request halt.
422 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
423 to run for some time, then halted, and the @option{reset} event script is executed.
426 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
427 completely independent (like the LPC2000 series), or where the JTAG interface is
428 unavailable for some time during startup (like the STR7 series), you can't use
429 @option{reset_halt} or @option{reset_init}.
431 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
432 @cindex target_script
433 Event is either @var{reset} or @var{post_halt} or @var{pre_resume}.
434 TODO: describe exact semantic of events
435 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
436 @cindex run_and_halt_time
437 The amount of time the debugger should wait after releasing reset before it asserts
438 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
440 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
441 <@var{backup}|@var{nobackup}>
443 Specifies a working area for the debugger to use. This may be used to speed-up
444 downloads to target memory and flash operations, or to perform otherwise unavailable
445 operations (some coprocessor operations on ARM7/9 systems, for example). The last
446 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
447 a working_area that doesn't need to be backed up, as that slows down operation.
450 @subsection arm7tdmi options
451 @cindex arm7tdmi options
452 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
453 The arm7tdmi target definition requires at least one additional argument, specifying
454 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
455 The optional [@var{variant}] parameter has been removed in recent versions.
456 The correct feature set is determined at runtime.
458 @subsection arm720t options
459 @cindex arm720t options
460 ARM720t options are similar to ARM7TDMI options.
462 @subsection arm9tdmi options
463 @cindex arm9tdmi options
464 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
465 @option{arm920t}, @option{arm922t} and @option{arm940t}.
466 This enables the hardware single-stepping support found on these cores.
468 @subsection arm920t options
469 @cindex arm920t options
470 ARM920t options are similar to ARM9TDMI options.
472 @subsection arm966e options
473 @cindex arm966e options
474 ARM966e options are similar to ARM9TDMI options.
476 @subsection xscale options
477 @cindex xscale options
478 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
479 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
481 @section Flash configuration
482 @cindex Flash configuration
485 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
486 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
488 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
489 and <@var{bus_width}> bytes using the selected flash <driver>.
491 @item @b{flash autoerase} <@option{on}|@option{off}>
492 @cindex flash autoerase
493 auto erase flash banks prior to writing. Currently only works when using
494 @option{flash write_image} command. Default is @option{off}.
497 @subsection lpc2000 options
498 @cindex lpc2000 options
500 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
501 <@var{clock}> [@var{calc_checksum}]
502 LPC flashes don't require the chip and bus width to be specified. Additional
503 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
504 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
505 of the target this flash belongs to (first is 0), the frequency at which the core
506 is currently running (in kHz - must be an integral number), and the optional keyword
507 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
510 @subsection cfi options
513 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
515 CFI flashes require the number of the target they're connected to as an additional
516 argument. The CFI driver makes use of a working area (specified for the target)
517 to significantly speed up operation.
519 @subsection at91sam7 options
520 @cindex at91sam7 options
522 @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
523 AT91SAM7 flashes only require the target#, all other values are looked up after
524 reading the chip-id and type.
526 @subsection str7 options
529 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
530 variant can be either STR71x, STR73x or STR75x.
532 @subsection str9 options
535 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
536 The str9 needs the flash controller to be configured prior to Flash programming, eg.
538 str9x flash_config 0 4 2 0 0x80000
540 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
542 @subsection str9 options (str9xpec driver)
544 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
545 Before using the flash commands the turbo mode will need enabling using str9xpec
546 @option{enable_turbo} <@var{num>.}
548 Only use this driver for locking/unlocking the device or configuring the option bytes.
549 Use the standard str9 driver for programming.
551 @subsection stellaris (LM3Sxxx) options
552 @cindex stellaris (LM3Sxxx) options
554 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
555 stellaris flash plugin only require the target#.
557 @subsection stm32x options
558 @cindex stm32x options
560 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
561 stm32x flash plugin only require the target#.
567 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
568 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
569 is available from both the telnet interface and a GDB session. To issue commands to the
570 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
571 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
577 @item @b{sleep} <@var{msec}>
579 Wait for n milliseconds before resuming. Useful in connection with script files
580 (@var{script} command and @var{target_script} configuration).
584 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
586 @item @b{debug_level} [@var{n}]
588 Display or adjust debug level to n<0-3>
590 @item @b{log_output} <@var{file}>
592 Redirect logging to <file> (default: stderr)
594 @item @b{script} <@var{file}>
596 Execute commands from <file>
600 @subsection Target state handling
602 @item @b{poll} [@option{on}|@option{off}]
604 Poll the target for its current state. If the target is in debug mode, architecture
605 specific information about the current state are printed. An optional parameter
606 allows continuous polling to be enabled and disabled.
610 Send a halt request to the target. The debugger signals the debug request,
611 and waits for the target to enter debug mode.
613 @item @b{resume} [@var{address}]
615 Resume the target at its current code position, or at an optional address.
617 @item @b{step} [@var{address}]
619 Single-step the target at its current code position, or at an optional address.
621 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
622 |@option{run_and_init}]
624 Do a hard-reset. The optional parameter specifies what should happen after the reset.
625 This optional parameter overwrites the setting specified in the configuration file,
626 making the new behaviour the default for the @option{reset} command.
633 Immediately halt the target (works only with certain configurations).
636 Immediately halt the target, and execute the reset script (works only with certain
639 @cindex reset run_and_halt
640 Let the target run for a certain amount of time, then request a halt.
642 @cindex reset run_and_init
643 Let the target run for a certain amount of time, then request a halt. Execute the
644 reset script once the target entered debug mode.
648 @subsection Memory access commands
649 These commands allow accesses of a specific size to the memory system:
651 @item @b{mdw} <@var{addr}> [@var{count}]
654 @item @b{mdh} <@var{addr}> [@var{count}]
656 display memory half-words
657 @item @b{mdb} <@var{addr}> [@var{count}]
660 @item @b{mww} <@var{addr}> <@var{value}>
663 @item @b{mwh} <@var{addr}> <@var{value}>
665 write memory half-word
666 @item @b{mwb} <@var{addr}> <@var{value}>
670 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
672 Load image <@var{file}> to target memory at <@var{address}>
673 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
675 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
676 (binary) <@var{file}>.
677 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
679 Verify <@var{file}> to target memory starting at <@var{address}>.
680 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
682 Load binary <@var{file}> to target memory at <@var{address}>
683 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
685 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
686 (binary) <@var{file}>.
689 @subsection Flash commands
690 @cindex Flash commands
692 @item @b{flash banks}
694 List configured flash banks
695 @item @b{flash info} <@var{num}>
697 Print info about flash bank <@option{num}>
698 @item @b{flash probe} <@var{num}>
700 Identify the flash, or validate the parameters of the configured flash. Operation
701 depends on the flash type.
702 @item @b{flash erase_check} <@var{num}>
703 @cindex flash erase_check
704 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
705 updates the erase state information displayed by @option{flash info}. That means you have
706 to issue an @option{erase_check} command after erasing or programming the device to get
708 @item @b{flash protect_check} <@var{num}>
709 @cindex flash protect_check
710 Check protection state of sectors in flash bank <num>.
711 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}>
713 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
714 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
715 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
717 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
719 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
720 bytes from the beginning of the bank. This command was replaced by the new command
721 @option{flash write_binary} using the same syntax.
722 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
723 @cindex flash write_binary
724 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
725 <@option{offset}> bytes from the beginning of the bank.
726 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
727 @cindex flash write_image
728 Write the image <@var{file}> to the current target's flash bank(s). A relocation
729 [@var{offset}] can be specified and the file [@var{type}] can be specified
730 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
731 (ELF file) or @option{s19} (Motorola s19).
732 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
733 @cindex flash protect
734 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
735 <@var{last}> of @option{flash bank} <@var{num}>.
736 @item @b{flash auto_erase} <@var{on}|@var{off}>
737 @cindex flash auto_erase
738 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
739 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
743 @section Target Specific Commands
744 @cindex Target Specific Commands
746 @subsection AT91SAM7 specific commands
747 @cindex AT91SAM7 specific commands
748 The flash configuration is deduced from the chip identification register. The flash
749 controller handles erases automatically on a page (128/265 byte) basis so erase is
750 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
751 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
752 that can be erased separatly.Only an EraseAll command is supported by the controller
753 for each flash plane and this is called with
755 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
756 bulk erase flash planes first_plane to last_plane.
757 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
758 @cindex at91sam7 gpnvm
759 set or clear a gpnvm bit for the processor
762 @subsection STR9 specific commands
763 @cindex STR9 specific commands
764 These are flash specific commands when using the str9xpec driver.
766 @item @b{str9xpec enable_turbo} <@var{num}>
767 @cindex str9xpec enable_turbo
768 enable turbo mode, simply this will remove the str9 from the chain and talk
769 directly to the embedded flash controller.
770 @item @b{str9xpec disable_turbo} <@var{num}>
771 @cindex str9xpec disable_turbo
772 restore the str9 into jtag chain.
773 @item @b{str9xpec lock} <@var{num}>
774 @cindex str9xpec lock
775 lock str9 device. The str9 will only respond to an unlock command that will
777 @item @b{str9xpec unlock} <@var{num}>
778 @cindex str9xpec unlock
780 @item @b{str9xpec options_read} <@var{num}>
781 @cindex str9xpec options_read
782 read str9 option bytes.
783 @item @b{str9xpec options_write} <@var{num}>
784 @cindex str9xpec options_write
785 write str9 option bytes.
788 @subsection STR9 configuration
789 @cindex STR9 configuration
791 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
792 <@var{BBADR}> <@var{NBBADR}>
793 @cindex str9x flash_config
794 Configure str9 flash controller.
796 eg. str9x flash_config 0 4 2 0 0x80000
798 BBSR - Boot Bank Size register
799 NBBSR - Non Boot Bank Size register
800 BBADR - Boot Bank Start Address register
801 NBBADR - Boot Bank Start Address register
805 @subsection STR9 option byte configuration
806 @cindex STR9 option byte configuration
808 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
809 @cindex str9xpec options_cmap
810 configure str9 boot bank.
811 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
812 @cindex str9xpec options_lvdthd
813 configure str9 lvd threshold.
814 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
815 @cindex str9xpec options_lvdsel
816 configure str9 lvd source.
817 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
818 @cindex str9xpec options_lvdwarn
819 configure str9 lvd reset warning source.
822 @subsection STM32x specific commands
823 @cindex STM32x specific commands
825 These are flash specific commands when using the stm32x driver.
827 @item @b{stm32x lock} <@var{num}>
830 @item @b{stm32x unlock} <@var{num}>
831 @cindex stm32x unlock
833 @item @b{stm32x options_read} <@var{num}>
834 @cindex stm32x options_read
835 read stm32 option bytes.
836 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
837 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
838 @cindex stm32x options_write
839 write stm32 option bytes.
840 @item @b{stm32x mass_erase} <@var{num}>
841 @cindex stm32x mass_erase
842 mass erase flash memory.
846 @section Arcitecture Specific Commands
847 @cindex Arcitecture Specific Commands
849 @subsection ARMV4/5 specific commands
850 @cindex ARMV4/5 specific commands
852 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
853 or Intel XScale (XScale isn't supported yet).
855 @item @b{armv4_5 reg}
857 Display a list of all banked core registers, fetching the current value from every
858 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
860 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
861 @cindex armv4_5 core_mode
862 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
863 The target is resumed in the currently set @option{core_mode}.
866 @subsection ARM7/9 specific commands
867 @cindex ARM7/9 specific commands
869 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
870 ARM920t or ARM926EJ-S.
872 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
873 @cindex arm7_9 sw_bkpts
874 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
875 one of the watchpoint registers to implement software breakpoints. Disabling
876 SW Bkpts frees that register again.
877 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
878 @cindex arm7_9 force_hw_bkpts
879 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
880 breakpoints are turned into hardware breakpoints.
881 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
883 Enable use of the DBGRQ bit to force entry into debug mode. This should be
884 safe for all but ARM7TDMI--S cores (like Philips LPC).
885 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
886 @cindex arm7_9 fast_writes [DEPRECATED]
887 See @option{arm7_9 fast_memory_access} instead.
888 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
889 @cindex arm7_9 fast_memory_access
890 Allow the OpenOCD to read and write memory without checking completion of
891 the operation. This provides a huge speed increase, especially with USB JTAG
892 cables (FT2232), but might be unsafe if used with targets running at a very low
893 speed, like the 32kHz startup clock of an AT91RM9200.
894 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
895 @cindex arm7_9 dcc_downloads
896 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
897 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
898 unsafe, especially with targets running at a very low speed. This command was introduced
899 with OpenOCD rev. 60.
902 @subsection ARM920T specific commands
903 @cindex ARM920T specific commands
906 @item @b{arm920t cache_info}
907 @cindex arm920t cache_info
908 Print information about the caches found. This allows you to see if your target
909 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
910 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
911 @cindex arm920t md<bhw>_phys
912 Display memory at physical address addr.
913 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
914 @cindex arm920t mw<bhw>_phys
915 Write memory at physical address addr.
916 @item @b{arm920t read_cache} <@var{filename}>
917 @cindex arm920t read_cache
918 Dump the content of ICache and DCache to a file.
919 @item @b{arm920t read_mmu} <@var{filename}>
920 @cindex arm920t read_mmu
921 Dump the content of the ITLB and DTLB to a file.
922 @item @b{arm920t virt2phys} <@var{VA}>
923 @cindex arm920t virt2phys
924 Translate a virtual address to a physical address.
928 @section Debug commands
929 @cindex Debug commands
930 The following commands give direct access to the core, and are most likely
931 only useful while debugging the OpenOCD.
933 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
934 @cindex arm7_9 write_xpsr
935 Immediately write either the current program status register (CPSR) or the saved
936 program status register (SPSR), without changing the register cache (as displayed
937 by the @option{reg} and @option{armv4_5 reg} commands).
938 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
939 <@var{0=cpsr},@var{1=spsr}>
940 @cindex arm7_9 write_xpsr_im8
941 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
942 operation (similar to @option{write_xpsr}).
943 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
944 @cindex arm7_9 write_core_reg
945 Write a core register, without changing the register cache (as displayed by the
946 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
947 encoding of the [M4:M0] bits of the PSR.
951 @section JTAG commands
952 @cindex JTAG commands
956 Print current scan chain configuration.
959 Toggle reset lines <@var{trst}> <@var{srst}>.
960 @item @b{endstate} <@var{tap_state}>
962 Finish JTAG operations in <@var{tap_state}>.
963 @item @b{runtest} <@var{num_cycles}>
965 Move to Run-Test/Idle, and execute <@var{num_cycles}>
966 @item @b{statemove} [@var{tap_state}]
968 Move to current endstate or [@var{tap_state}]
971 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
974 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
975 @item @b{verify_ircapture}
976 @cindex verify_ircapture
977 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
980 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
983 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
987 @chapter Sample Scripts
990 This page will collect some script examples for different CPUs.
992 The configuration script can be divided in the following section:
994 @item deamon configuration
996 @item jtag scan chain
997 @item target configuration
998 @item flash configuration
1001 Detailed information about each section can be found at OpenOCD configuration
1003 @section OMAP5912 Flash Debug
1004 @cindex OMAP5912 Flash Debug
1005 The following two scripts was used with an wiggler PP and and a TI OMAP5912
1006 dual core processor (@uref{http://www.ti.com}) on a OMAP5912 OSK board
1007 @uref{(http://www.spectrumdigital.com}).
1008 @subsection Openocd config
1010 #daemon configuration
1017 parport_cable wiggler
1020 #use combined on interfaces or targets that can't set TRST/SRST separately
1021 reset_config trst_and_srst
1024 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1025 jtag_device 38 0x0 0x0 0x0
1026 jtag_device 4 0x1 0x0 0xe
1027 jtag_device 8 0x0 0x0 0x0
1029 #target configuration
1030 daemon_startup reset
1032 #target <type> <endianness> <reset mode> <chainpos> <variant>
1033 target arm926ejs little run_and_init 1 arm926ejs
1034 target_script 0 reset omap5912_osk.init
1035 run_and_halt_time 0 30
1037 # omap5912 lcd frame buffer as working area
1038 working_area 0 0x20000000 0x3e800 nobackup
1040 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1041 flash bank cfi 0x00000000 0x1000000 2 2 0
1044 @subsection Openocd init
1056 mww 0xfffec808 0x000000f5
1057 mww 0xfffec808 0x000000a0
1059 mww 0xfffeb048 0x0000aaaa
1061 mww 0xfffeb048 0x00005555
1070 @section STR71x Script
1071 @cindex STR71x Script
1072 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1074 #daemon configuration
1080 ft2232_device_desc "Amontec JTAGkey A"
1081 ft2232_layout jtagkey
1082 ft2232_vid_pid 0x0403 0xcff8
1085 #use combined on interfaces or targets that can't set TRST/SRST separately
1086 reset_config trst_and_srst srst_pulls_trst
1089 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1090 jtag_device 4 0x1 0xf 0xe
1092 #target configuration
1093 daemon_startup reset
1095 #target <type> <startup mode>
1096 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1097 target arm7tdmi little run_and_halt 0 arm7tdmi
1098 run_and_halt_time 0 30
1100 working_area 0 0x2000C000 0x4000 nobackup
1102 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1103 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1106 @section STR750 Script
1107 @cindex STR750 Script
1108 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1110 #daemon configuration
1116 ft2232_device_desc "Amontec JTAGkey A"
1117 ft2232_layout jtagkey
1118 ft2232_vid_pid 0x0403 0xcff8
1121 #use combined on interfaces or targets that can't set TRST/SRST separately
1122 #reset_config trst_and_srst srst_pulls_trst
1123 reset_config trst_and_srst srst_pulls_trst
1126 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1127 jtag_device 4 0x1 0xf 0xe
1129 #jtag nTRST and nSRST delay
1130 jtag_nsrst_delay 500
1131 jtag_ntrst_delay 500
1133 #target configuration
1134 daemon_startup reset
1136 #target <type> <startup mode>
1137 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1138 target arm7tdmi little run_and_halt 0 arm7tdmi
1139 run_and_halt_time 0 30
1141 working_area 0 0x40000000 0x4000 nobackup
1143 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1144 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1147 @section STR912 Script
1148 @cindex STR912 Script
1149 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1151 #daemon configuration
1157 ft2232_device_desc "Amontec JTAGkey A"
1158 ft2232_layout jtagkey
1161 #use combined on interfaces or targets that can't set TRST/SRST separately
1162 reset_config trst_and_srst
1165 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1166 jtag_device 8 0x1 0x1 0xfe
1167 jtag_device 4 0x1 0xf 0xe
1168 jtag_device 5 0x1 0x1 0x1e
1170 #target configuration
1171 daemon_startup reset
1173 #target <type> <startup mode>
1174 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1175 target arm966e little reset_halt 1 arm966e
1176 run_and_halt_time 0 30
1178 working_area 0 0x50000000 16384 nobackup
1180 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1181 flash bank str9x 0x00000000 0x00080000 0 0 0
1184 @section STM32x Script
1185 @cindex STM32x Script
1186 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1188 #daemon configuration
1194 ft2232_device_desc "Amontec JTAGkey A"
1195 ft2232_layout jtagkey
1198 #use combined on interfaces or targets that can't set TRST/SRST separately
1199 reset_config trst_and_srst
1202 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1203 jtag_device 4 0x1 0xf 0xe
1204 jtag_device 5 0x1 0x1 0x1e
1206 #target configuration
1207 daemon_startup reset
1209 #target <type> <startup mode>
1210 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1211 target cortex_m3 little run_and_halt 0
1212 run_and_halt_time 0 30
1214 working_area 0 0x20000000 16384 nobackup
1216 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1217 flash bank stm32x 0x08000000 0x00010000 0 0 0
1220 @section LPC2294 Script
1221 @cindex LPC2294 Script
1222 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1224 #daemon configuration
1230 ft2232_device_desc "Amontec JTAGkey A"
1231 ft2232_layout jtagkey
1232 ft2232_vid_pid 0x0403 0xcff8
1235 #use combined on interfaces or targets that can't set TRST/SRST separately
1236 reset_config trst_and_srst srst_pulls_trst
1239 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1240 jtag_device 4 0x1 0xf 0xe
1242 #target configuration
1243 daemon_startup reset
1245 #target <type> <startup mode>
1246 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1247 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1248 run_and_halt_time 0 30
1250 working_area 0 0x40000000 0x40000 nobackup
1252 #flash configuration
1253 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1256 @section AT91R40008 Script
1257 @cindex AT91R40008 Script
1258 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1260 #daemon configuration
1266 ft2232_device_desc "Amontec JTAGkey A"
1267 ft2232_layout jtagkey
1268 ft2232_vid_pid 0x0403 0xcff8
1270 jtag_nsrst_delay 200
1271 jtag_ntrst_delay 200
1273 #use combined on interfaces or targets that can't set TRST/SRST separately
1274 reset_config srst_only srst_pulls_trst
1277 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1278 jtag_device 4 0x1 0xf 0xe
1280 #target configuration
1281 daemon_startup reset
1283 #target <type> <startup mode>
1284 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1285 target arm7tdmi little run_and_halt 0 arm7tdmi
1286 run_and_halt_time 0 30
1289 @section LPC2129 Script
1290 @cindex LPC2129 Script
1291 The following script was used with an wiggler PP and a LPC-2129 cpu:
1293 #daemon configuration
1300 parport_cable wiggler
1303 #use combined on interfaces or targets that can't set TRST/SRST separately
1304 reset_config trst_and_srst srst_pulls_trst
1307 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1308 jtag_device 4 0x1 0xf 0xe
1310 #target configuration
1311 daemon_startup reset
1313 #target <type> <startup mode>
1314 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1315 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1316 run_and_halt_time 0 30
1318 working_area 0 0x00000000 0x400000 nobackup
1320 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1321 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1324 @section AT91SAM7s Script
1325 @cindex AT91SAM7s Script
1326 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1328 #daemon configuration
1334 ft2232_device_desc "Olimex OpenOCD JTAG A"
1335 ft2232_layout olimex-jtag
1336 ft2232_vid_pid 0x15BA 0x0003
1338 jtag_nsrst_delay 200
1339 jtag_ntrst_delay 200
1341 #use combined on interfaces or targets that can't set TRST/SRST separately
1342 reset_config srst_only srst_pulls_trst
1345 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1346 jtag_device 4 0x1 0xf 0xe
1348 #target configuration
1349 daemon_startup reset
1351 #target <type> <startup mode>
1352 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1353 target arm7tdmi little run_and_halt 0 arm7tdmi
1354 run_and_halt_time 0 30
1356 # flash-options AT91
1357 working_area 0 0x00200000 0x4000 nobackup
1358 flash bank at91sam7 0 0 0 0 0
1361 # erase command (telnet-interface) for complete flash:
1362 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1363 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1364 # set/clear NVM-Bits:
1365 # at91sam7 gpnvm <num> <bit> <set|clear>
1366 # disable locking from SAM-BA:
1367 # flash protect 0 0 1 off
1370 @section XSCALE IXP42x Script
1371 @cindex XSCALE IXP42x Script
1372 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1374 #daemon configuration
1380 ft2232_device_desc "Amontec JTAGkey A"
1381 ft2232_layout jtagkey
1382 ft2232_vid_pid 0x0403 0xcff8
1384 jtag_nsrst_delay 200
1385 jtag_ntrst_delay 200
1387 #use combined on interfaces or targets that can't set TRST/SRST separately
1388 reset_config srst_only srst_pulls_trst
1391 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1392 jtag_device 7 0x1 0x7f 0x7e
1394 #target configuration
1395 daemon_startup reset
1397 #target <type> <startup mode>
1398 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1399 target xscale big run_and_halt 0 IXP42x
1400 run_and_halt_time 0 30
1403 @section Cirrus Logic EP9301 Script
1404 @cindex Cirrus Logic EP9301 Script
1405 The following script was used with FT2232 based JTAG interfaces and a
1406 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1408 #daemon configuration
1416 #ft2232_device_desc "Olimex OpenOCD JTAG"
1417 #ft2232_layout olimex-jtag
1418 #ft2232_vid_pid 0x15ba 0x0003
1420 #Amontec JTAGkey (and JTAGkey-Tiny)
1421 #Serial is only necessary if more than one JTAGkey is connected
1422 ft2232_device_desc "Amontec JTAGkey A"
1423 #ft2232_serial AMTJKV31
1424 #ft2232_serial T1P3S2W8
1425 ft2232_layout jtagkey
1426 ft2232_vid_pid 0x0403 0xcff8
1428 #wiggler/parallel port interface
1431 #parport_cable wiggler
1434 reset_config trst_and_srst
1437 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1438 jtag_device 4 0x1 0xf 0xe
1440 jtag_nsrst_delay 100
1441 jtag_ntrst_delay 100
1443 #target configuration
1444 daemon_startup attach
1446 #target <type> <endianess> <reset mode>
1447 target arm920t little reset_halt 0
1448 working_area 0 0x80014000 0x1000 backup
1450 #flash configuration
1451 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1452 flash bank cfi 0x60000000 0x1000000 2 2 0
1455 @section Hilscher netX 100 / 500 Script
1456 @cindex Hilscher netX 100 / 500 Script
1457 The following script was used with an Amontec JTAGkey and a Hilscher
1460 #daemon configuration
1466 ft2232_device_desc "Amontec JTAGkey A"
1467 ft2232_layout jtagkey
1468 ft2232_vid_pid 0x0403 0xcff8
1471 #use combined on interfaces or targets that can't set TRST/SRST separately
1472 reset_config trst_and_srst
1475 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1476 jtag_device 4 0x1 0xf 0xe
1478 jtag_nsrst_delay 100
1479 jtag_ntrst_delay 100
1481 #target configuration
1482 daemon_startup reset
1484 #target <type> <endianness> <startup mode> <chainpos> <variant>
1485 target arm926ejs little run_and_halt 0 arm926ejs
1486 run_and_halt_time 0 500
1489 @section Marvell/Intel PXA270 Script
1490 @cindex Marvell/Intel PXA270 Script
1492 # config for Intel PXA270
1493 # not, as of 2007-06-22, openocd only works with the
1494 # libftd2xx library from ftdi. libftdi does not work.
1500 ft2232_layout olimex-jtag
1501 ft2232_vid_pid 0x15BA 0x0003
1502 ft2232_device_desc "Olimex OpenOCD JTAG"
1504 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1505 # the rest of the needed delays are built into the openocd program
1506 jtag_nsrst_delay 260
1507 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1508 # the rest of the needed delays are built into the openocd program
1511 #use combined on interfaces or targets that can't set TRST/SRST separately
1512 reset_config trst_and_srst separate
1515 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1516 jtag_device 7 0x1 0x7f 0x7e
1518 #target configuration
1519 daemon_startup reset
1521 target xscale little reset_halt 0 pxa27x
1523 # maps to PXA internal RAM. If you are using a PXA255
1524 # you must initialize SDRAM or leave this option off
1525 working_area 0 0x5c000000 0x10000 nobackup
1527 run_and_halt_time 0 30
1529 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1530 # works for P30 flash
1531 flash bank cfi 0x00000000 0x1000000 2 4 0
1538 @item OpenOCD complains about a missing cygwin1.dll
1540 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1541 claims to come with all the necessary dlls. When using Cygwin, try launching
1542 the OpenOCD from the Cygwin shell.
1544 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1545 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1546 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1548 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1549 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1550 software breakpoints consume one of the two available hardware breakpoints,
1551 and are therefor disabled by default. If your code is running from RAM, you
1552 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1553 your code resides in Flash, you can't use software breakpoints, but you can force
1554 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1556 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1557 and works sometimes fine.
1559 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1560 clock at the time you're programming the flash. If you've specified the crystal's
1561 frequency, make sure the PLL is disabled, if you've specified the full core speed
1562 (e.g. 60MHz), make sure the PLL is enabled.
1564 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1565 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1566 out while waiting for end of scan, rtck was disabled".
1568 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1569 settings in your PC Bios (ECP, EPP, and different versions of those).
1571 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1572 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1573 memory read caused data abort".
1575 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1576 beyond the last valid frame. It might be possible to prevent this by setting up
1577 a proper "initial" stack frame, if you happen to know what exactly has to
1578 be done, feel free to add this here.
1580 @item I get the following message in the OpenOCD console (or log file):
1581 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1583 This warning doesn't indicate any serious problem, as long as you don't want to
1584 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1585 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1586 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1587 independently. With this setup, it's not possible to halt the core right out of
1588 reset, everything else should work fine.
1590 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1591 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1592 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1593 quit with an error message. Is there a stability issue with OpenOCD?
1595 No, this is not a stability issue concering OpenOCD. Most users have solved
1596 this issue by simply using a self-powered USB Hub, which they connect their
1597 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1598 supply stable enough for the Amontec JTAGkey to be operated.
1600 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1601 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1602 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1603 What does that mean and what might be the reason for this?
1605 First of all, the reason might be the USB power supply. Try using a self-powered
1606 hub instead of a direct connection to your computer. Secondly, the error code 4
1607 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1608 Chip ran into some sort of error - this points us to a USB problem.
1610 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1611 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1612 What does that mean and what might be the reason for this?
1614 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1615 has closed the connection to OpenOCD. This might be a GDB issue.
1617 @item In the configuration file in the section where flash device configurations
1618 are described, there is a parameter for specifying the clock frequency for
1619 LPC2000 internal flash devices (e.g.
1620 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1621 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1622 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1623 Is it possible to specify real numbers for the clock frequency?
1625 No. The clock frequency specified here must be given as an integral number.
1626 However, this clock frequency is used by the In-Application-Programming (IAP)
1627 routines of the LPC2000 family only, which seems to be very tolerant concerning
1628 the given clock frequency, so a slight difference between the specified clock
1629 frequency and the actual clock frequency will not cause any trouble.
1631 @item Do I have to keep a specific order for the commands in the configuration file?
1633 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1634 listed for the JTAG scan chain must be given in the right order (jtag_device),
1635 with the device closest to the TDO-Pin being listed first. In general,
1636 whenever objects of the same type exist which require an index number, then
1637 these objects must be given in the right order (jtag_devices, targets and flash
1638 banks - a target references a jtag_device and a flash bank references a target).
1640 @item Sometimes my debugging session terminates with an error. When I look into the
1641 log file, I can see these error messages: Error: arm7_9_common.c:561
1642 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP