doc/manual/primer/jtag.txt

   1 /** @page primerjtag OpenOCD JTAG Primer
   2
   3 JTAG is unnecessarily confusing, because JTAG is often confused with
   4 boundary scan, which is just one of its possible functions.
   5
   6 JTAG is simply a communication interface designed to allow communication
   7 to functions contained on devices, for the designed purposes of
   8 initialisation, programming, testing, debugging, and anything else you
   9 want to use it for (as a chip designer).
  10
  11 Think of JTAG as I2C for testing.  It doesn't define what it can do,
  12 just a logical interface that allows a uniform channel for communication.
  13
  14 See @par
  15         http://en.wikipedia.org/wiki/Joint_Test_Action_Group
  16
  17 and @par
  18         http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-state-machine-large.png
  19
  20 The first page (among other things) shows a logical representation
  21 describing how multiple devices are wired up using JTAG.  JTAG does not
  22 specify, data rates or interface levels (3.3V/1.8V, etc) each device can
  23 support different data rates/interface logic levels.  How to wire them
  24 in a compatible way is an exercise for an engineer.
  25
  26 Basically TMS controls which shift register is placed on the device,
  27 between TDI and TDO.  The second diagram shows the state transitions on
  28 TMS which will select different shift registers.
  29
  30 The first thing you need to do is reset the state machine, because when
  31 you connect to a chip you do not know what state the controller is in,you need
  32 to clock TMS as 1, at least 7 times.  This will put you into "Test Logic
  33 Reset" State.  Knowing this, you can, once reset, then track what each
  34 transition on TMS will do, and hence know what state the JTAG state
  35 machine is in.
  36
  37 There are 2 "types" of shift registers.  The Instruction shift register
  38 and the data shift register.  The sizes of these are undefined, and can
  39 change from chip to chip.  The Instruction register is used to select
  40 which Data register/data register function is used, and the data
  41 register is used to read data from that function or write data to it.
  42
  43 Each of the states control what happens to either the data register or
  44 instruction register.
  45
  46 For example, one of the data registers will be known as "bypass" this is
  47 (usually) a single bit which has no function and is used to bypass the
  48 chip.  Assume we have 3 identical chips, wired up like the picture
  49 and each has a 3 bit instruction register, and there are 2 known
  50 instructions (110 = bypass, 010 = some other function) if we want to use
  51 "some other function", on the second chip in the line, and not change
  52 the other chips we would do the following transitions.
  53
  54 From Test Logic Reset, TMS goes:
  55
  56   0 1 1 0 0
  57
  58 which puts every chip in the chain into the "Shift IR state"
  59 Then (while holding TMS as 0) TDI goes:
  60
  61   0 1 1  0 1 0  0 1 1
  62
  63 which puts the following values in the instruction shift register for
  64 each chip [110] [010] [110]
  65
  66 The order is reversed, because we shift out the least significant bit
  67 first.  Then we transition TMS:
  68
  69   1 1 1 1 0 0
  70
  71 which puts us in the "Shift DR state".
  72
  73 Now when we clock data onto TDI (again while holding TMS to 0) , the
  74 data shifts through the data registers, and because of the instruction
  75 registers we selected (some other function has 8 bits in its data
  76 register), our total data register in the chain looks like this:
  77
  78   0 00000000 0
  79
  80 The first and last bit are in the "bypassed" chips, so values read from
  81 them are irrelevant and data written to them is ignored.  But we need to
  82 write bits for those registers, because they are in the chain.
  83
  84 If we wanted to write 0xF5 to the data register we would clock out of
  85 TDI (holding TMS to 0):
  86
  87   0 1 0 1 0 1 1 1 1 0
  88
  89 Again, we are clocking the least-significant bit first.  Then we would
  90 clock TMS:
  91
  92   1 1 0
  93
  94 which updates the selected data register with the value 0xF5 and returns
  95 us to run test idle.
  96
  97 If we needed to read the data register before over-writing it with F5,
  98 no sweat, that's already done, because the TDI/TDO are set up as a
  99 circular shift register, so if you write enough bits to fill the shift
 100 register, you will receive the "captured" contents of the data registers
 101 simultaneously on TDO.
 102
 103 That's JTAG in a nutshell.  On top of this, you need to get specs for
 104 target chips and work out what the various instruction registers/data
 105 registers do, so you can actually do something useful.  That's where it
 106 gets interesting.  But in and of itself, JTAG is actually very simple.
 107
 108 @section primerjtag More Reading
 109
 110 The following link goes to an HTML (or PDF) introduction to JTAG,
 111 written by one of the original members of the JTAG committee: @par
 112 http://www.asset-intertech.com/products/boundscan.htm
 113
 114 A separate primer contains information about @subpage primerjtagbs for
 115 developers that want to extend OpenOCD for such purposes.
 116
 117  */
 118 /** @page primerjtagbs JTAG Boundary Scan Primer
 119
 120 The following page provides an introduction on JTAG that focuses on its
 121 boundary scan capabilities: @par
 122 http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html
 123
 124 OpenOCD does not presently have clear means of using JTAG for boundary
 125 scan testing purposes; however, some developers have explored the
 126 possibilities.  The page contains information that may be useful to
 127 those wishing to implement boundary scan capabilities in OpenOCD.
 128
 129 @section primerbsdl The BSDL Language
 130
 131 For more information on the Boundary Scan Description Language (BSDL),
 132 the following page provides a good introduction: @par
 133 http://www.radio-electronics.com/info/t_and_m/boundaryscan/bsdl.php
 134
 135 @section primerbsdlvendors Vendor BSDL Files
 136
 137 NXP LPC: @par
 138 http://www.standardics.nxp.com/support/models/lpc2000/
 139
 140 Freescale PowerPC: @par
 141 http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCBSDLFLS
 142
 143 Freescale i.MX1 (too old): @par
 144 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX1&nodeId=0162468rH311432973ZrDR&fpsp=1&tab=Design_Tools_Tab
 145
 146 Renesas R32C/117: @par
 147 http://sg.renesas.com/fmwk.jsp?cnt=r32c116_7_8_root.jsp&fp=/products/mpumcu/m16c_family/r32c100_series/r32c116_7_8_group/
 148 - The device page does not come with BSDL file; you have to register to
 149   download them. @par
 150   http://www.corelis.com/support/BSDL.htm
 151
 152 TI links theirs right off the generic page for each chip;
 153 this may be the case for other vendors as well.  For example:
 154
 155 - DaVinci DM355 -- http://www.ti.com/litv/zip/sprm262b
 156 - DaVinci DM6446
 157   - 2.1 silicon -- http://www.ti.com/litv/zip/sprm325a
 158   - older silicon -- http://www.ti.com/litv/zip/sprm203
 159 - OMAP 3530
 160   - CBB package -- http://www.ti.com/litv/zip/sprm315b
 161     - 515 ball s-PGBA, POP, 0.4mm pitch
 162   - CUS package -- http://www.ti.com/litv/zip/sprm314a
 163     - 515 ball s-PGBA, POP, 0.5mm pitch
 164   - CBC package -- http://www.ti.com/litv/zip/sprm346
 165     - 423 ball s-PGBA, 0.65mm pitch
 166
 167 Many other files are available in the "Semiconductor Manufacturer's BSDL
 168 files" section of the following site: @par
 169 http://www.freelabs.com/~whitis/electronics/jtag/
 170
 171  */
 172 /** @file
 173 This file contains the @ref primerjtag and @ref primerjtagbs page.
 174  */