01494b86e9714c198fef9448f0a625d324ae836b
[openocd.git] / contrib / loaders / flash / stm32x.S
1 /***************************************************************************
2  *   Copyright (C) 2010 by Spencer Oliver                                  *
3  *   spen@spen-soft.co.uk                                                  *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20
21         .text
22         .syntax unified
23         .cpu cortex-m3
24         .thumb
25         .thumb_func
26         .global write
27
28 /*
29         r0 - source address
30         r1 - target address
31         r2 - count (halfword-16bit)
32         r3 - sector offet in : result out
33         r4 - flash base
34 */
35
36 #define STM32_FLASH_CR_OFFSET   0x10                    /* offset of CR register in FLASH struct */
37 #define STM32_FLASH_SR_OFFSET   0x0c                    /* offset of CR register in FLASH struct */
38
39 write:
40         ldr             r4, STM32_FLASH_BASE
41         add             r4, r3                                                          /* add offset 0x00 for sector 0 : 0x40 for sector 1 */
42 write_half_word:
43         movs    r3, #0x01
44         str             r3, [r4, #STM32_FLASH_CR_OFFSET]        /* PG (bit0) == 1 => flash programming enabled */
45         ldrh    r3, [r0], #0x02                                         /* read one half-word from src, increment ptr */
46         strh    r3, [r1], #0x02                                         /* write one half-word from src, increment ptr */
47 busy:
48         ldr     r3, [r4, #STM32_FLASH_SR_OFFSET]
49         tst     r3, #0x01                                                       /* BSY (bit0) == 1 => operation in progress */
50         beq     busy                                                            /* wait more... */
51         tst             r3, #0x14                                                       /* PGERR (bit2) == 1 or WRPRTERR (bit4) == 1 => error */
52         bne             exit                                                            /* fail... */
53         subs    r2, r2, #0x01                                           /* decrement counter */
54         bne             write_half_word                                         /* write next half-word if anything left */
55 exit:
56         bkpt    #0x00
57
58 STM32_FLASH_BASE: .word 0x40022000                              /* base address of FLASH struct */