stm32f1x: fix bug in flash loader and restrict instruction set to armv6-m
[openocd.git] / contrib / loaders / flash / stm32f1x.S
1 /***************************************************************************
2  *   Copyright (C) 2011 by Andreas Fritiofson                              *
3  *   andreas.fritiofson@gmail.com                                          *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
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19  ***************************************************************************/
20
21         .text
22         .syntax unified
23         .cpu cortex-m0
24         .thumb
25         .thumb_func
26         .global write
27
28         /* Params:
29          * r0 - flash base (in), status (out)
30          * r1 - count (halfword-16bit)
31          * r2 - workarea start
32          * r3 - workarea end
33          * r4 - target address
34          * Clobbered:
35          * r5 - rp
36          * r6 - wp, tmp
37          * r7 - tmp
38          */
39
40 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
41 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
42
43 wait_fifo:
44         ldr     r6, [r2, #0]    /* read wp */
45         cmp     r6, #0                  /* abort if wp == 0 */
46         beq     exit
47         ldr     r5, [r2, #4]    /* read rp */
48         cmp     r5, r6                  /* wait until rp != wp */
49         beq     wait_fifo
50         movs    r6, #1                  /* set PG flag to enable flash programming */
51         str     r6, [r0, #STM32_FLASH_CR_OFFSET]
52         ldrh    r6, [r5]        /* "*target_address++ = *rp++" */
53         strh    r6, [r4]
54         adds    r5, #2
55         adds    r4, #2
56 busy:
57         ldr     r6, [r0, #STM32_FLASH_SR_OFFSET]        /* wait until BSY flag is reset */
58         movs    r7, #1
59         tst     r6, r7
60         bne     busy
61         movs    r7, #0x14               /* check the error bits */
62         tst     r6, r7
63         bne     error
64         cmp     r5, r3                  /* wrap rp at end of buffer */
65         bcc     no_wrap
66         mov     r5, r2
67         adds    r5, #8
68 no_wrap:
69         str     r5, [r2, #4]    /* store rp */
70         subs    r1, r1, #1              /* decrement halfword count */
71         cmp     r1, #0
72         beq     exit            /* loop if not done */
73         b       wait_fifo
74 error:
75         movs    r0, #0
76         str     r0, [r2, #4]    /* set rp = 0 on error */
77 exit:
78         mov             r0, r6                  /* return status in r0 */
79         bkpt    #0