1 /***************************************************************************
2 * Copyright (C) 2010 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2011 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2015 Uwe Bonnes *
9 * bon@elektron.ikp.physik.tu-darmstadt.de *
11 * Copyright (C) 2018 Andreas Bolsch *
12 * andreas.bolsch@mni.thm.de *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc. *
27 ***************************************************************************/
36 * r0 = workarea start, status (out)
37 * r1 = workarea end + 1
39 * r3 = count (64bit words)
40 * r4 = flash status register
41 * r5 = flash control register
44 * r6/7 - temp (64-bit)
47 #include "../../../../src/flash/nor/stm32l4x.h"
53 mov r8, r3 /* copy dword count */
55 ldr r6, [r0, #0] /* read wp */
56 cmp r6, #0 /* if wp == 0, */
57 beq exit /* then abort */
58 ldr r3, [r0, #4] /* read rp */
59 subs r6, r6, r3 /* number of bytes available for read in r6 */
60 bpl fifo_stat /* if not wrapped around, skip */
61 adds r6, r6, r1 /* add end of buffer */
62 subs r6, r6, r0 /* sub start of buffer */
64 cmp r6, #8 /* wait until at least one dword available */
67 movs r6, #FLASH_PG /* flash program enable */
68 str r6, [r5] /* write to FLASH_CR, start operation */
69 ldmia r3!, {r6, r7} /* read one dword from src, increment ptr */
70 stmia r2!, {r6, r7} /* write one dword to dst, increment ptr */
72 ldr r7, =FLASH_BSY /* FLASH_BSY mask */
74 ldr r6, [r4] /* get FLASH_SR register */
75 tst r6, r7 /* BSY == 1 => operation in progress */
76 bne busy /* if still set, wait more ... */
77 movs r7, #FLASH_ERROR /* all error bits */
78 tst r6, r7 /* check for any error bit */
79 bne error /* fail ... */
81 cmp r3, r1 /* rp at end of buffer? */
82 bcc upd_rp /* if no, then skip */
83 subs r3, r3, r1 /* sub end of buffer */
84 adds r3, r3, r0 /* add start of buffer */
85 adds r3, r3, #8 /* skip wp and rp */
87 str r3, [r0, #4] /* store rp */
88 mov r7, r8 /* get dword count */
89 subs r7, r7, #1 /* decrement dword count */
90 mov r8, r7 /* save dword count */
91 beq exit /* exit if done */
98 str r3, [r0, #4] /* set rp = 0 on error */
100 mov r0, r6 /* return status in r0 */
101 movs r6, #0 /* flash program disable */
102 str r6, [r5] /* write to FLASH_CR */
103 movs r6, #FLASH_ERROR /* all error bits */
104 str r6, [r4] /* write to FLASH_CR to clear errors */