jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / contrib / loaders / flash / cortex-m0.S
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4 * Copyright (C) 2014 by Angus Gratton *
5 * Derived from stm32f1x.S:
6 * Copyright (C) 2011 by Andreas Fritiofson *
7 * andreas.fritiofson@gmail.com *
8 * Copyright (C) 2013 by Roman Dmitrienko *
9 * me@iamroman.org *
10 ***************************************************************************/
11 .text
12 .syntax unified
13 .cpu cortex-m0
14 .thumb
15 .thumb_func
16
17 /* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
18 * very generic (CPU blocks during flash writes), so this is actually
19 * just a generic word-oriented copy routine for Cortex-M0 (also
20 * suitable for Cortex-M0+/M3/M4.)
21 *
22 * To assemble:
23 * arm-none-eabi-gcc -c cortex-m0.S
24 *
25 * To disassemble:
26 * arm-none-eabi-objdump -o cortex-m0.o
27 *
28 * Thanks to Jens Bauer for providing advice on some of the tweaks.
29 */
30
31 /* Params:
32 * r0 - byte count (in)
33 * r1 - workarea start
34 * r2 - workarea end
35 * r3 - target address
36 * Clobbered:
37 * r4 - rp
38 * r5 - wp, tmp
39 */
40
41 wait_fifo:
42 ldr r5, [r1, #0] /* read wp */
43 cmp r5, #0 /* abort if wp == 0 */
44 beq exit
45 ldr r4, [r1, #4] /* read rp */
46 cmp r4, r5 /* wait until rp != wp */
47 beq wait_fifo
48
49 ldmia r4!, {r5} /* "*target_address++ = *rp++" */
50 stmia r3!, {r5}
51
52 cmp r4, r2 /* wrap rp at end of work area buffer */
53 bcc no_wrap
54 mov r4, r1
55 adds r4, #8 /* skip rp,wp at start of work area */
56 no_wrap:
57 str r4, [r1, #4] /* write back rp */
58 subs r0, #4 /* decrement byte count */
59 bne wait_fifo /* loop if not done */
60 exit:
61 bkpt #0

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