65d64da7eb5d6a55adfd2d831f508f49c421f44f
[openocd.git] / contrib / loaders / flash / armv4_5_cfi_span_8.s
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2010 Spencer Oliver *
5 * spen@spen-soft.co.uk *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 .text
24 .arm
25 .arch armv4
26
27 .section .init
28
29 /* input parameters - */
30 /* R0 = source address */
31 /* R1 = destination address */
32 /* R2 = number of writes */
33 /* R3 = flash write command */
34 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
35 /* output parameters - */
36 /* R5 = 0x80 ok 0x00 bad */
37 /* temp registers - */
38 /* R6 = value read from flash to test status */
39 /* R7 = holding register */
40 /* unlock registers - */
41 /* R8 = unlock1_addr */
42 /* R9 = unlock1_cmd */
43 /* R10 = unlock2_addr */
44 /* R11 = unlock2_cmd */
45
46 code:
47 ldrb r5, [r0], #1
48 strb r9, [r8]
49 strb r11, [r10]
50 strb r3, [r8]
51 strb r5, [r1]
52 nop
53 busy:
54 ldrb r6, [r1]
55 eor r7, r5, r6
56 ands r7, r4, r7
57 beq cont /* b if DQ7 == Data7 */
58 ands r6, r6, r4, lsr #2
59 beq busy /* b if DQ5 low */
60 ldrb r6, [r1]
61 eor r7, r5, r6
62 ands r7, r4, r7
63 beq cont /* b if DQ7 == Data7 */
64 mov r5, #0 /* 0x0 - return 0x00, error */
65 bne done
66 cont:
67 subs r2, r2, #1 /* 0x1 */
68 moveq r5, #128 /* 0x80 */
69 beq done
70 add r1, r1, #1 /* 0x1 */
71 b code
72 done:
73 b done
74
75 .end

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