From 393da819b14c62d267cf5ec86bc511c187e1af18 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 17 Oct 2023 19:04:00 -0700 Subject: [PATCH] aarch64: Use 64-bit reads/writes to access SCTLR_EL1 We were previously inadvertently clearing the top 32 bits of SCTLR_EL1 during read_memory/write_memory as a result of using 32-bit operations to access the register and because the fields used to temporarily store the register were 32-bit. Fix it. Change-Id: I657d7f949e1f7ab6bf90609e3f91cae09cade31a Signed-off-by: Peter Collingbourne Reviewed-on: https://review.openocd.org/c/openocd/+/7939 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/aarch64.c | 8 ++++---- src/target/aarch64.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/target/aarch64.c b/src/target/aarch64.c index db602435cf..1c056a015e 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg); + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg); if (retval != ERROR_OK) return retval; @@ -182,7 +182,7 @@ static int aarch64_mmu_modify(struct target *target, int enable) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg_curr); if (target_mode != ARM_MODE_ANY) @@ -1055,14 +1055,14 @@ static int aarch64_post_debug_entry(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg); + retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg); if (retval != ERROR_OK) return retval; if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY); - LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg); + LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg); aarch64->system_control_reg_curr = aarch64->system_control_reg; if (armv8->armv8_mmu.armv8_cache.info == -1) { diff --git a/src/target/aarch64.h b/src/target/aarch64.h index 2721fe747d..b265e82498 100644 --- a/src/target/aarch64.h +++ b/src/target/aarch64.h @@ -43,8 +43,8 @@ struct aarch64_common { struct armv8_common armv8_common; /* Context information */ - uint32_t system_control_reg; - uint32_t system_control_reg_curr; + uint64_t system_control_reg; + uint64_t system_control_reg_curr; /* Breakpoint register pairs */ int brp_num_context; -- 2.30.2