X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fti_dm355.cfg;h=2903e5d8f8405c088bbe71f2cf44ce6eee9f54bc;hb=85c03753371ed20edc5c03f36a2d2e11730d2239;hp=abfba10972e33993124f0e124bc72f2698560021;hpb=108028112fdf285cd74eaf50d6a353a09039bb7f;p=openocd.git

diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index abfba10972..2903e5d8f8 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -1,48 +1,57 @@
 #
-# Texas Instruments DaVinci family:  TMS320DM355
+# Texas Instruments DaVinci family: TMS320DM355
 #
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME dm355
-}
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
+   set _CHIPNAME dm355
 }
 
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
 #
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note:  when running without RTCK before the PLLs are set up, you
+# Also note: when running without RTCK before the PLLs are set up, you
 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
 #
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
    set _ETB_TAPID $ETB_TAPID
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
    set _CPU_TAPID $CPU_TAPID
 } else {
    set _CPU_TAPID 0x07926001
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b73b02f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
 
 ################
 
@@ -72,11 +81,11 @@ dict set dm355 uart2		0x01e06000
 source [find target/davinci.cfg]
 
 ################
-# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
 # and the ETB memory (4K) are other options, while trace is unused.
 set _TARGETNAME $_CHIPNAME.arm
 
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 
 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
 # and that the work area is used only with a kernel mmu context ...