X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32l.cfg;h=8e6a10e1f3c7adfe060a91152db4c5ab92c1dfe2;hb=d177ae04ff1efa4ffb8fc9d8beb16e36493093df;hp=eea082e65d80fbb78c69703a0ff3b6fedc124218;hpb=84043a95e1744884a9cd8132789c94e13b0312d2;p=openocd.git

diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg
index eea082e65d..8e6a10e1f3 100644
--- a/tcl/target/stm32l.cfg
+++ b/tcl/target/stm32l.cfg
@@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 
 proc stm32l_enable_HSI {} {
 	# Enable HSI as clock source