X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f2x.cfg;h=5022ef7dbd18dbe1c64197a32e1f8ce34398256d;hb=3427cf2b7e33240fc63c6398090dc7bcbf4f2d52;hp=a47b115d22bf9227f9f73df7937060e934b07130;hpb=ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3;p=openocd.git

diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index a47b115d22..5022ef7dbd 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -1,9 +1,14 @@
-# script for stm32f2xxx
+# script for stm32f2x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
-   set _CHIPNAME stm32f2xxx
+   set _CHIPNAME stm32f2x
 }
 
 if { [info exists ENDIAN] } {
@@ -26,10 +31,12 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-jtag_khz 1000
+adapter_khz 1000
 
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
+adapter_nsrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -39,7 +46,8 @@ if { [info exists CPUTAPID] } {
   # Section 32.6.3 - corresponds to Cortex-M3 r2p0
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
@@ -49,13 +57,19 @@ if { [info exists BSTAPID] } {
   # 
   set _BSTAPID 0x06411041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m reset_config sysresetreq