X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f1x.cfg;h=bd02e95b06057953cf4ba54f7ef46ba105f82a58;hb=751e2454bf076708d3e695833c4def460ab41d8b;hp=7d3f42f3b9762a5d29f82b6fbf6cfc47df72e0c3;hpb=b7d2cdc0d4fc319169c60362708a67e2ff626525;p=openocd.git

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 7d3f42f3b9..bd02e95b06 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -1,40 +1,41 @@
 # script for stm32f1x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME stm32f1x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 16kB
+# By default use 4kB (as found on some STM32F100s)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x4000
+   set _WORKAREASIZE 0x1000
 }
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0008
-  # Section 26.6.3
-   set _CPUTAPID 0x3ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
@@ -59,13 +60,15 @@ if { [info exists BSTAPID] } {
   set _BSTAPID8 0x06420041
   # VL line devices, Rev A
   set _BSTAPID9 0x06428041
-
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
 	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
 	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
 	-expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
 	-expected-id $_BSTAPID8 -expected-id $_BSTAPID9
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
@@ -76,6 +79,31 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}