X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=386242597cefd9b3a8ae3d59a455c67170458a62;hb=87bf0db12551daf6d1c34bd09a573c0b23d31df2;hp=7137621a43c87de0ed2daf7ac756286e65d1d26f;hpb=20a3b14828c5015647fa438e0cbee84685bcdf5f;p=openocd.git

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 7137621a43..386242597c 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -1,19 +1,19 @@
 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-#  This chip is now at end-of-life.  Final orders have been taken.
+# This chip is now at end-of-life.  Final orders have been taken.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME pxa255
+   set _CHIPNAME pxa255
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x69264013
@@ -28,8 +28,12 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
 
 # reset processing that works with PXA
 proc init_reset {mode} {