X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomapl138.cfg;h=d3e472c6d8c5519eaf7b0b66345c71d22804052c;hb=8fe2bed92c993242038c60273d1bb73f572e795e;hp=6e06a1934ea7badccdcc4d2879886abe50b993de;hpb=91305bfa7f550c96b967008c1512864cffdaa52a;p=openocd.git

diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 6e06a1934e..d3e472c6d8 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -1,16 +1,16 @@
 #
-# Texas Instruments DaVinci family:  OMAPL138
+# Texas Instruments DaVinci family: OMAPL138
 #
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME omapl138
+   set _CHIPNAME omapl138
 }
 
 source [find target/icepick.cfg]
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
    set _ETB_TAPID $ETB_TAPID
 } else {
    set _ETB_TAPID 0x2b900f0f
@@ -20,7 +20,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
    set _CPU_TAPID $CPU_TAPID
 } else {
    set _CPU_TAPID 0x07926001
@@ -30,7 +30,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 2"
 
 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b7d102f