X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=f9dcf7cbfe8a6fd47a03bdb0cc72823f1d9ce59c;hb=9c4d2946548f72d77f103b978ab30501d5953f04;hp=0e20852ca12d499bbd9b851d6b8078e9a75fef0f;hpb=d9ba56c295f057e716519a798bf9cdb4898c24f4;p=openocd.git

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 0e20852ca1..f9dcf7cbfe 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -62,8 +62,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick