X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=45f3c01ce59dd6493b39c69e11ef12e6adb1e97b;hb=4a26390eec5b969c07684ab5d4b7e957011d71bd;hp=3c7dd9cfe17c46046235501facee1231e808412f;hpb=7b3be0e21ec2065f77c1541b09e049b733361486;p=openocd.git

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 3c7dd9cfe1..45f3c01ce5 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -2,9 +2,9 @@
 #  http://focus.ti.com/docs/prod/folders/print/omap3530.html
 # Other OMAP3 chips remove DSP and/or the OpenGL support
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME omap3530
 }
 
@@ -34,22 +34,38 @@ if { [info exists JRC_TAPID ] } {
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID
 
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
 # GDB target:  Cortex-A8, using DAP
-target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
 
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
-     poll off
-     reset
-     sleep 500
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
-     jtag tapenable omap3530.dap
-     targets
+proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
      cortex_a8 dbginit
-     # Enable DBGU singal for OMAP353x
-     omap3.cpu mww 0x5401d030 0x00002000
-     poll on
+     # Enable DBGU signal for OMAP353x
+     $target mww 0x5401d030 0x00002000
 }
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+# REVISIT This assumes that SRST is unavailable, so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"