X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;h=d1734ddb11c854c0c0c9145e1cf24f175fb4c442;hb=40d9b241954d8b5ac0baa105a76eb2ded175d138;hp=9a813f5b94ee392b084220d64770d361ed629d07;hpb=2dfa5e9c844a5a3f8aaca146c874f13570b8f667;p=openocd.git

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 9a813f5b94..d1734ddb11 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,51 +1,73 @@
-# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+
+# LPC17xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
-	set  _CHIPNAME $CHIPNAME
+	set _CHIPNAME $CHIPNAME
 } else {
-	set  _CHIPNAME lpc1768
+	set _CHIPNAME lpc1768
 }
 
-if { [info exists ENDIAN] } {
-	set  _ENDIAN $ENDIAN
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+	set _CCLK $CCLK
 } else {
-	set  _ENDIAN little
+	set _CCLK 4000
 }
-
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
 	set _CPUTAPID 0x4ba00477
 }
 
 #delays on reset lines
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
-# LPC2000 & LPC1700 -> SRST causes TRST
-reset_config trst_and_srst srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
 
-# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
+# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
 
-$_TARGETNAME configure -event reset-init {
-	# Force target into ARM state
-	arm core_state arm
-	#do not remap 0x0000-0x0020 to anything but the flash
-#	mwb 0xE01FC040 0x01
-	mwb 0xE000ED08 0x00
-}
+# LPC1768 has 512kB of flash memory, managed by ROM code (including a
+# boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
+	lpc1700 $_CCLK calc_checksum
 
-# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
-# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 10
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
+$_TARGETNAME configure -event reset-init {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
 
-# 4MHz / 6 = 666kHz, so use 500
-jtag_khz 500
+	mww 0x400FC040 0x01
+}