X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;h=a436b30f69bbdee7b6bbb7257d909790eb0ece51;hb=adb8ec32dc7439aa3e34ab19f026e390ec129c10;hp=182fb89df498c2f90bd94c6e088ec8dbd052d38f;hpb=53b3d4dd53eebbf03f481dc59e4bc0259911864a;p=openocd.git

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 182fb89df4..a436b30f69 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,10 +1,8 @@
 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
-
-if { [info exists CHIPNAME] } {
-	set  _CHIPNAME $CHIPNAME
-} else {
-	set  _CHIPNAME lpc1768
-}
+set CHIPNAME lpc1768
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
 
 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
 # When board-specific code (reset-init handler or device firmware)
@@ -13,41 +11,7 @@ if { [info exists CHIPNAME] } {
 # (The ROM code doing those updates cares about core clock speed...)
 #
 # CCLK is the core clock frequency in KHz
-if { [info exists CCLK ] } {
-	set _CCLK $CCLK
-} else {
-	set _CCLK 4000
-}
-if { [info exists CPUTAPID ] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x4ba00477
-}
-
-#delays on reset lines
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# LPC2000 & LPC1700 -> SRST causes TRST
-reset_config srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
-
-# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
-# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
-
-# LPC1768 has 512kB of flash memory, managed by ROM code (including a
-# boot loader which verifies the flash exception table's checksum).
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
-	lpc1700 $_CCLK calc_checksum
+set CCLK 4000
 
-# JTAG clock should be CCLK/6 (unless using adaptive clocking)
-# CCLK is 4 MHz after reset, and until board-specific code (like
-# a reset-init handler) speeds it up.
-jtag_rclk [ expr 4000 / 6 ]
-$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6]  }
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];