X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx6.cfg;h=d7f0b90662296e73a03024c53f558e68ad015ff0;hb=d177ae04ff1efa4ffb8fc9d8beb16e36493093df;hp=707bab84cc85be57215e9edb533bb5b3b281a22d;hpb=0581ab7855422eea727892fb4aed7312c498c760;p=openocd.git

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index 707bab84cc..d7f0b90662 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -26,9 +26,11 @@ if { [info exists SJC_TAPID] } {
         set _SJC_TAPID 0x0191c01d
 }
 set _SJC_TAPID2 0x2191c01d
+set _SJC_TAPID3 0x2191e01d
 
 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2
+        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
+        -expected-id $_SJC_TAPID3
 
 # GDB target: Cortex-A9, using DAP, configuring only one core
 # Base addresses of cores:
@@ -37,7 +39,7 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
 # core 2  -  0x82154000
 # core 3  -  0x82156000
 set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x82150000
 
 # some TCK cycles are required to activate the DEBUG power domain
@@ -45,7 +47,7 @@ jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx6_dbginit {target} {
         # General Cortex A8/A9 debug initialisation
-        cortex_a8 dbginit
+        cortex_a dbginit
 }
 
 # Slow speed to be sure it will work