X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fdavinci.cfg;h=c14c98ea8eb8f0cd31694b95c7376b88e1aa1990;hb=fcf1301e5269fdf734946ccf03177511f2eda851;hp=e1eb48f598285991233780e37a4150110bc871c3;hpb=e996452089fd5ffba34094958e87d51c1fcf8619;p=openocd.git

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index e1eb48f598..c14c98ea8e 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
 	#
 
 	# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
-	arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+	arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
 
 	#
 	# Part II -- in case watchdog hasn't been set up
 	#
 
 	# TCR: disable, force internal clock source
-	arm926ejs mww_phys [expr $timer2_phys + 0x20] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x20] 0
 
 	# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
-	arm926ejs mww_phys [expr $timer2_phys + 0x24] 0
-	arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b
+	arm926ejs mww phys [expr $timer2_phys + 0x24] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
 
 	# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
 	# so watchdog triggers ASAP
-	arm926ejs mww_phys [expr $timer2_phys + 0x10] 0
-	arm926ejs mww_phys [expr $timer2_phys + 0x14] 0
-	arm926ejs mww_phys [expr $timer2_phys + 0x18] 0
-	arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x10] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x14] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x18] 0
+	arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
 
 	# WDTCR: put into pre-active state, then active
-	arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000
-	arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000
+	arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
+	arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
 
 	#
 	# Part III -- it's ready to rumble
 	#
 
 	# WDTCR: write invalid WDKEY to trigger reset
-	arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+	arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
 }