X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fat91sam9260_ext_RAM_ext_flash.cfg;h=034a3489007dfc739e997efaf87e9afe59e1bd9e;hb=b559b273b526b3077b3ca219eecc8df9f86efac0;hp=f10a021c8de68f01f19ed48d332e4de923feae31;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf;p=openocd.git

diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index f10a021c8d..034a348900 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -1,22 +1,22 @@
 
 
 
-jtag_khz 4
+adapter_khz 4
 
 
 ######################################
 # Target:    Atmel AT91SAM9260
 ######################################
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91sam9260
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -30,7 +30,7 @@ if { [info exists CPUTAPID ] } {
 reset_config trst_and_srst
 
 
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 
@@ -41,13 +41,13 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 # Target configuration
 ######################
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
 
 $_TARGETNAME invoke-event halted
 
 # Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
 
 scan_chain
 $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
@@ -55,13 +55,14 @@ $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
 
 # Flash configuration
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
 
 
 proc at91sam_init { } {
-	
+
 	# at reset chip runs at 32khz
-	jtag_khz 8
+	adapter_khz 8
 	halt
 	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
 	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
@@ -78,7 +79,7 @@ proc at91sam_init { } {
 	sleep 10                          # wait 10 ms
 
 	# Now run at anything fast... ie: 10mhz!
-	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
+	adapter_khz 10000                    # Increase JTAG Speed to 6 MHz
 	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
 
 	mww 0xffffec00 0x0a0a0a0a         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit