X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Fboard%2Fimx53loco.cfg;h=d4ec06079a6dbae266762f269f5c0755814ce855;hb=64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a;hp=e1bc44da3b3d4348c16aba6c6bc28815b67a7155;hpb=f855fdcf0d95ff9ba18a83f9a97d5368844d4f2c;p=openocd.git

diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index e1bc44da3b..d4ec06079a 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -70,7 +70,7 @@ proc init_l2cc { } {
 	set tR [arm mrc 15 0 1 0 1]
 	; #bic r0, r0, #0x2
 	; #mcr 15, 0, r0, c1, c0, 1
-	arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
 
 	; #/* reconfigure L2 cache aux control reg */
 	; #mov r0, #0xC0                   /* tag RAM */
@@ -140,7 +140,7 @@ proc init_clock { } {
 	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 
 	; # change uart clk parent to pll2
-	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
 
 	; # make sure change is effective
 	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@ -158,7 +158,7 @@ proc init_clock { } {
 	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 
 	; # make uart div=6
-	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
 
 	; # Restore the default values in the Gate registers
 	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@ -244,7 +244,7 @@ proc setup_pll { PLL_ADDR CLK } {
 	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 
 	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
-	while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
 }