X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Fboard%2Fcsb337.cfg;h=5e225f5f549de04f21d3dabe413cbe130d36ad26;hb=2076ba093d65f5d4a9069504aca09b9e1696bd02;hp=c2c47898be642d01be912f81544c0261b9034d2c;hpb=f1f54a0fc56b8025692b1ce60e0cc588c975e397;p=openocd.git

diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index c2c47898be..5e225f5f54 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -4,7 +4,8 @@
 source [find target/at91rm9200.cfg]
 
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
-flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 # ETM9 trace port connector present on this board, 16 data pins.
 if { [info exists ETM_DRIVER] } {
@@ -18,7 +19,7 @@ if { [info exists ETM_DRIVER] } {
 
 proc csb337_clk_init { } {
 	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
-	jtag_khz 8
+	adapter_khz 8
 
 	# CKGR_MOR:  start main oscillator (3.6864 MHz)
 	mww 0xfffffc20 0xff01
@@ -36,7 +37,7 @@ proc csb337_clk_init { } {
 	sleep 20
 
 	# CPU is in Normal Mode ... allows faster JTAG clock speed
-	jtag_khz 40000
+	adapter_khz 40000
 }
 
 proc csb337_nor_init { } {
@@ -112,3 +113,5 @@ proc csb337_reset_init { } {
 }
 
 $_TARGETNAME configure -event reset-init {csb337_reset_init}
+
+arm7_9 fast_memory_access enable