X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=59ee4d2a38b91d9e6b071c6082d1a772e4e0b2d2;hb=64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a;hp=03296c50e314287b868ed6c2515d82945d843bf7;hpb=f855fdcf0d95ff9ba18a83f9a97d5368844d4f2c;p=openocd.git

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 03296c50e3..59ee4d2a38 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } {
 	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
 
 	mww 0xfffffc20 0x00004001
-	while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
 
 	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
 	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
 
 	mww 0xfffffc28 0x202a3f01
-	while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
 
 	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00000101
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Now change PMC_MCKR register to select PLLA.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00001302
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Processor and master clocks are now operating and stable at maximum frequency possible:
 	#	-> MCLK = 132.096 MHz