X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.h;h=e480da9307ffc0594195d90fcae3316388f52e2b;hb=7cd2617384f4ac620c468343c1f2009fbfa2fc79;hp=936782cf3705f85cc7e943ab6b8aff25f96f6350;hpb=1e51cf049cfed3bc42a748d848210f8e4b472282;p=openocd.git

diff --git a/src/target/xscale.h b/src/target/xscale.h
index 936782cf37..e480da9307 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -23,7 +23,7 @@
 #ifndef XSCALE_H
 #define XSCALE_H
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "armv4_5_mmu.h"
 #include "trace.h"
 
@@ -37,6 +37,10 @@
 #define XSCALE_LDIC	0x07
 #define XSCALE_SELDCSR	0x09
 
+/* Possible CPU types */
+#define	XSCALE_IXP4XX_PXA2XX	0x0
+#define	XSCALE_PXA3XX		0x4
+
 enum xscale_debug_reason
 {
 	XSCALE_DBG_REASON_GENERIC,
@@ -63,25 +67,31 @@ struct xscale_trace_data
 	uint32_t chkpt0;
 	uint32_t chkpt1;
 	uint32_t last_instruction;
+	unsigned int num_checkpoints;
 	struct xscale_trace_data *next;
 };
 
+enum trace_mode
+{
+   XSCALE_TRACE_DISABLED,
+   XSCALE_TRACE_FILL,
+   XSCALE_TRACE_WRAP
+};
+
 struct xscale_trace
 {
-	trace_status_t capture_status;	/* current state of capture run */
-	struct image_s *image;					/* source for target opcodes */
+	struct image *image;					/* source for target opcodes */
 	struct xscale_trace_data *data;		/* linked list of collected trace data */
-	int buffer_enabled;				/* whether trace buffer is enabled */
-	int buffer_fill;				/* maximum number of trace runs to read (-1 for wrap-around) */
-	int pc_ok;
-	uint32_t current_pc;
-	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
+	int buffer_fill;				/* maximum number of trace runs to read */
+    int fill_counter;				/* running count during trace collection */
+    enum trace_mode mode;
+	enum arm_state core_state;	/* current core state (ARM, Thumb) */
 };
 
 struct xscale_common
 {
 	/* armv4/5 common stuff */
-	armv4_5_common_t armv4_5_common;
+	struct arm armv4_5_common;
 
 	int common_magic;
 
@@ -129,10 +139,13 @@ struct xscale_common
 	uint32_t cp15_control_reg;
 
 	int fast_memory_access;
+
+	/* CPU variant */
+	int xscale_variant;
 };
 
 static inline struct xscale_common *
-target_to_xscale(struct target_s *target)
+target_to_xscale(struct target *target)
 {
 	return container_of(target->arch_info, struct xscale_common,
 			armv4_5_common);
@@ -141,7 +154,7 @@ target_to_xscale(struct target_s *target)
 struct xscale_reg
 {
 	int dbg_handler_number;
-	target_t *target;
+	struct target *target;
 };
 
 enum
@@ -170,6 +183,6 @@ enum
 	XSCALE_TXRXCTRL,
 };
 
-#define ERROR_XSCALE_NO_TRACE_DATA	(-1500)
+#define ERROR_XSCALE_NO_TRACE_DATA	(-700)
 
 #endif /* XSCALE_H */