X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=fc71ea3347018a0ff2796cdede60bfcd6d62f7b0;hb=a42bea654ce1316dd521b1c9beffa8f829bf8be0;hp=816579ad8e0d44ee6452cb69bce7d31a59787b85;hpb=0529c14bfeb113ee37f4d961f9309102d57a1e39;p=openocd.git diff --git a/src/target/xscale.c b/src/target/xscale.c index 816579ad8e..fc71ea3347 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -37,6 +37,7 @@ #include "register.h" #include "image.h" #include "arm_opcodes.h" +#include "armv4_5.h" /* @@ -864,15 +865,8 @@ static int xscale_arch_state(struct target *target) return ERROR_INVALID_ARGUMENTS; } - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s" - "%s", - arm_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s", state[xscale->armv4_5_mmu.mmu_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled], @@ -1502,7 +1496,7 @@ static int xscale_assert_reset(struct target *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(target->tap, 0x7f); + xscale_jtag_set_instr(target->tap, ~0); jtag_execute_queue(); /* assert reset */ @@ -1911,7 +1905,13 @@ static int xscale_read_memory(struct target *target, uint32_t address, static int xscale_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /** \todo: provide a non-stub implementtion of this routine. */ + struct xscale_common *xscale = target_to_xscale(target); + + /* with MMU inactive, there are only physical addresses */ + if (!xscale->armv4_5_mmu.mmu_enabled) + return xscale_read_memory(target, address, size, count, buffer); + + /** \todo: provide a non-stub implementation of this routine. */ LOG_ERROR("%s: %s is not implemented. Disable MMU?", target_name(target), __func__); return ERROR_FAIL; @@ -1998,7 +1998,13 @@ static int xscale_write_memory(struct target *target, uint32_t address, static int xscale_write_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /** \todo: provide a non-stub implementtion of this routine. */ + struct xscale_common *xscale = target_to_xscale(target); + + /* with MMU inactive, there are only physical addresses */ + if (!xscale->armv4_5_mmu.mmu_enabled) + return xscale_read_memory(target, address, size, count, buffer); + + /** \todo: provide a non-stub implementation of this routine. */ LOG_ERROR("%s: %s is not implemented. Disable MMU?", target_name(target), __func__); return ERROR_FAIL; @@ -2976,6 +2982,9 @@ static int xscale_init_arch_info(struct target *target, xscale->dbr0_used = 0; xscale->dbr1_used = 0; + LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints", + target_name(target)); + xscale->arm_bkpt = ARMV5_BKPT(0x0); xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; @@ -3598,94 +3607,101 @@ COMMAND_HANDLER(xscale_handle_cp15) static const struct command_registration xscale_exec_command_handlers[] = { { .name = "cache_info", - .handler = &xscale_handle_cache_info_command, - .mode = COMMAND_EXEC, NULL, + .handler = xscale_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about CPU caches", }, - { .name = "mmu", - .handler = &xscale_handle_mmu_command, + .handler = xscale_handle_mmu_command, .mode = COMMAND_EXEC, - .usage = "[enable|disable]", .help = "enable or disable the MMU", + .usage = "['enable'|'disable']", }, { .name = "icache", - .handler = &xscale_handle_idcache_command, + .handler = xscale_handle_idcache_command, .mode = COMMAND_EXEC, - .usage = "[enable|disable]", - .help = "enable or disable the ICache", + .help = "display ICache state, optionally enabling or " + "disabling it", + .usage = "['enable'|'disable']", }, { .name = "dcache", - .handler = &xscale_handle_idcache_command, + .handler = xscale_handle_idcache_command, .mode = COMMAND_EXEC, - .usage = "[enable|disable]", - .help = "enable or disable the DCache", + .help = "display DCache state, optionally enabling or " + "disabling it", + .usage = "['enable'|'disable']", }, - { .name = "vector_catch", - .handler = &xscale_handle_vector_catch_command, + .handler = xscale_handle_vector_catch_command, .mode = COMMAND_EXEC, - .help = "mask of vectors that should be caught", - .usage = "[]", + .help = "set or display 8-bit mask of vectors " + "that should trigger debug entry", + .usage = "[mask]", }, { .name = "vector_table", - .handler = &xscale_handle_vector_table_command, + .handler = xscale_handle_vector_table_command, .mode = COMMAND_EXEC, - .usage = " ", - .help = "set static code for exception handler entry", + .help = "set vector table entry in mini-ICache, " + "or display current tables", + .usage = "[('high'|'low') index code]", }, - { .name = "trace_buffer", - .handler = &xscale_handle_trace_buffer_command, + .handler = xscale_handle_trace_buffer_command, .mode = COMMAND_EXEC, - .usage = " [fill [n]|wrap]", + .help = "display trace buffer status, enable or disable " + "tracing, and optionally reconfigure trace mode", + .usage = "['enable'|'disable' ['fill' number|'wrap']]", }, { .name = "dump_trace", - .handler = &xscale_handle_dump_trace_command, + .handler = xscale_handle_dump_trace_command, .mode = COMMAND_EXEC, - .help = "dump content of trace buffer to ", - .usage = "", + .help = "dump content of trace buffer to file", + .usage = "filename", }, { .name = "analyze_trace", - .handler = &xscale_handle_analyze_trace_buffer_command, + .handler = xscale_handle_analyze_trace_buffer_command, .mode = COMMAND_EXEC, .help = "analyze content of trace buffer", + .usage = "", }, { .name = "trace_image", - .handler = &xscale_handle_trace_image_command, - COMMAND_EXEC, - .help = "load image from [base address]", - .usage = " [address] [type]", + .handler = xscale_handle_trace_image_command, + .mode = COMMAND_EXEC, + .help = "load image from file to address (default 0)", + .usage = "filename [offset [filetype]]", }, - { .name = "cp15", - .handler = &xscale_handle_cp15, + .handler = xscale_handle_cp15, .mode = COMMAND_EXEC, - .help = "access coproc 15", - .usage = " [value]", + .help = "Read or write coprocessor 15 register.", + .usage = "register [value]", }, COMMAND_REGISTRATION_DONE }; static const struct command_registration xscale_any_command_handlers[] = { { .name = "debug_handler", - .handler = &xscale_handle_debug_handler_command, + .handler = xscale_handle_debug_handler_command, .mode = COMMAND_ANY, - .usage = "
", + .help = "Change address used for debug handler.", + .usage = "target address", }, { .name = "cache_clean_address", - .handler = &xscale_handle_cache_clean_address_command, + .handler = xscale_handle_cache_clean_address_command, .mode = COMMAND_ANY, + .help = "Change address used for cleaning data cache.", + .usage = "address", }, { .chain = xscale_exec_command_handlers, @@ -3722,6 +3738,7 @@ struct target_type xscale_target = .deassert_reset = xscale_deassert_reset, .soft_reset_halt = NULL, + /* REVISIT on some cores, allow exporting iwmmxt registers ... */ .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = xscale_read_memory,