X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Ftarget%2Fsam7x256.cfg;h=d7e11ff32dfde08252148250451793ff37072661;hb=e4218ebb8f7f5bf27578198e16ae5add99edeb75;hp=1d61b4ccf9609986646c5287bf3dcc6880315c6a;hpb=e2b6de3d66bae70cb08fea17f5b66ee875dbb636;p=openocd.git

diff --git a/src/target/target/sam7x256.cfg b/src/target/target/sam7x256.cfg
index 1d61b4ccf9..d7e11ff32d 100644
--- a/src/target/target/sam7x256.cfg
+++ b/src/target/target/sam7x256.cfg
@@ -5,17 +5,30 @@ reset_config srst_only srst_pulls_trst
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 jtag_device 4 0x1 0xf 0xe
 
-#target <type> <startup mode>
-#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
-target arm7tdmi little 0 arm7tdmi
+target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+[new_target_name] configure -event reset-init { 
+	# disable watchdog
+	mww 0xfffffd44 0x00008000	
+	# enable user reset
+	mww 0xfffffd08 0xa5000001	
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601	
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e 	
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007	
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100	
+	sleep 100
+}
 
-
-target_script 0 reset event/sam7x256_reset.script
-
-working_area 0 0x00200000 0x4000 nobackup
+[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 flash bank at91sam7 0 0 0 0 0
 
 # For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# openocd.texi